From 88a404a2d17701fcd980b4d1e26d0a1897c9137b Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Wed, 24 Sep 2025 12:24:26 +0200 Subject: [PATCH 1/6] microchipsw: add support for Microchip LAN969x switches Add a new microchipsw target aimed add supporting Microchip switch SoC-s. Start by supporting LAN969x SoC-s as the first subtarget. Signed-off-by: Robert Marko --- .github/labeler.yml | 6 + config/Config-images.in | 1 + target/linux/microchipsw/Makefile | 20 + target/linux/microchipsw/dts/lan969x.dtsi | 538 + target/linux/microchipsw/image/Makefile | 21 + .../linux/microchipsw/lan969x/config-default | 272 + target/linux/microchipsw/lan969x/target.mk | 8 + ...d-config-for-Microchip-SoC-platforms.patch | 74 + ...dd-support-for-Microchip-LAN969x-SoC.patch | 38 + ...-add-support-for-lan969x-SoC-pinctrl.patch | 348 + ...966x-make-clk_names-const-char-const.patch | 26 + ...x-prepare-driver-for-lan969x-support.patch | 151 + ...support-for-lan969x-SoC-clock-driver.patch | 70 + ...s-add-support-for-private-match-data.patch | 84 + ...5-serdes-add-constants-to-match-data.patch | 63 + ...s-add-constant-for-the-number-of-CMU.patch | 56 + ...-sparx5-serdes-add-ops-to-match-data.patch | 120 + ...s-add-function-for-getting-the-CMU-i.patch | 77 + ...s-add-indirection-layer-to-register-.patch | 1708 +++ ...s-add-support-for-branching-on-chip-.patch | 101 + ...es-add-support-for-lan969x-serdes-dr.patch | 175 + ...-make-it-selectable-for-ARCH_LAN969X.patch | 26 + ...-Make-it-selectable-for-ARCH_LAN969X.patch | 26 + ...make-it-selectable-for-ARCH_MICROCHI.patch | 27 + ...ake-it-selectable-for-ARCH_MICROCHIP.patch | 28 + ...-make-it-selectable-for-ARCH_MICROCH.patch | 29 + ...ake-it-selectable-for-ARCH_MICROCHIP.patch | 28 + ...ake-it-selectable-for-ARCH_MICROCHIP.patch | 28 + ...tmel-make-it-selectable-for-ARCH_MIC.patch | 28 + ...-make-it-selectable-for-ARCH_MICROCH.patch | 29 + ...5-add-support-for-private-match-data.patch | 135 + ...indirection-layer-to-register-macros.patch | 7398 +++++++++++++ ...t-sparx5-modify-SPX5_PORTS_ALL-macro.patch | 36 + ...d-sparx5-argument-to-a-few-functions.patch | 355 + ...t-sparx5-add-constants-to-match-data.patch | 88 + ...PX5_CONST-for-constants-which-alread.patch | 600 + ...PX5_CONST-for-constants-which-do-not.patch | 60 + ....13-net-sparx5-add-ops-to-match-data.patch | 227 + ...ut-chip-port-to-device-index-bit-fun.patch | 80 + ...ut-functions-for-getting-certain-arr.patch | 170 + ...ut-function-for-setting-the-port-mux.patch | 74 + ...3-net-sparx5-ops-out-PTP-IRQ-handler.patch | 56 + ...ut-function-for-DSM-calendar-calcula.patch | 137 + ...s_sparx5-macro-and-use-it-throughout.patch | 267 + ...ine-internal-ports-and-PGID-s-as-off.patch | 351 + ...upport-for-lan969x-targets-and-core-.patch | 169 + ...ge-spx5_wr-to-spx5_rmw-in-cal-update.patch | 48 + ...nge-frequency-calculation-for-SDLB-s.patch | 55 + ...parx5-context-pointer-to-a-few-funct.patch | 122 + ...x5-add-registers-required-by-lan969x.patch | 185 + ...t-lan969x-add-match-data-for-lan969x.patch | 216 + ...69x-add-register-diffs-to-match-data.patch | 365 + ...-lan969x-add-constants-to-match-data.patch | 54 + ...an969x-add-lan969x-ops-to-match-data.patch | 205 + ...net-lan969x-add-PTP-handler-function.patch | 180 + ...function-for-calculating-the-DSM-cal.patch | 359 + ...parx5-use-is_sparx5-macro-throughout.patch | 306 + ...x5-add-compatible-string-for-lan969x.patch | 38 + ...v6.13-net-sparx5-add-feature-support.patch | 130 + ...arx5-expose-some-sparx5-VCAP-symbols.patch | 116 + ...arx5-replace-SPX5_PORTS-with-n_ports.patch | 143 + ...add-new-VCAP-constants-to-match-data.patch | 97 + ...-execute-sparx5_vcap_init-on-lan969x.patch | 39 + ...x-add-autogenerated-VCAP-information.patch | 3916 +++++++ ...-lan969x-add-VCAP-configuration-data.patch | 166 + ...d-missing-lan969x-Kconfig-dependency.patch | 45 + ...cyclic-dependency-reported-by-depmod.patch | 9733 +++++++++++++++++ ...-the-use-of-spin_lock-in-PTP-handler.patch | 33 + ...5-fix-default-value-of-monitor-ports.patch | 42 + ...-net-sparx5-do-some-preparation-work.patch | 78 + ...x5-add-function-for-RGMII-port-check.patch | 82 + ...-sparx5-use-is_port_rgmii-throughout.patch | 115 + ...low-speed-configuration-when-port-is.patch | 40 + ...return-PCS-for-modes-that-require-it.patch | 40 + ...v6.14-net-sparx5-verify-RGMII-speeds.patch | 37 + ...6.14-net-lan969x-add-RGMII-registers.patch | 211 + ...net-lan969x-add-RGMII-implementation.patch | 320 + ...14-net-sparx5-enable-FDMA-on-lan969x.patch | 32 + ...sparx5-split-sparx5_fdma_-start-stop.patch | 135 + ...net-sparx5-activate-FDMA-tx-in-start.patch | 61 + ...parx5-ops-out-certain-FDMA-functions.patch | 146 + ...-net-lan969x-add-FDMA-implementation.patch | 609 ++ ...9x-Add-support-for-ethtool-pause-par.patch | 62 + ...quadspi-Add-support-for-sama7g5-QSPI.patch | 1175 ++ ...i-Factor-out-switching-to-Serial-Mem.patch | 181 + ...l-quadspi-Use-devm_-clock-management.patch | 131 + ...i-Update-to-current-device-naming-te.patch | 66 + ...l-quadspi-Fix-warning-in-doc-comment.patch | 34 + ...i-remove-references-to-runtime-PM-on.patch | 41 + ...i-Fix-printed-error-code-during-DMA-.patch | 49 + ...i-Fix-unbalanced-pm_runtime-by-using.patch | 62 + ...-dmaengine-Add-devm_dma_request_chan.patch | 81 + ...el-quadspi-Use-devm_dma_request_chan.patch | 122 + ...i-add-padcalib-2xgclk-and-dllon-capa.patch | 178 + ...i-add-support-for-SAM9X7-QSPI-contro.patch | 58 + ...uadspi-Add-support-for-sama7d65-QSPI.patch | 57 + ...9x-fix-flooding-configuration-on-bri.patch | 137 + ...-make-it-selectable-for-ARCH_LAN969X.patch | 26 + ...s-make-it-selectable-for-ARCH_LAN969.patch | 25 + ...-bindings-add-LAN969x-clock-bindings.patch | 40 + ...104-reset-sparx5-add-LAN969x-support.patch | 26 + ...ake-it-selectable-for-ARCH_MICROCHIP.patch | 24 + ...1-implement-quirk-SDCLK-stop-while-r.patch | 66 + ...-sdhci-of-at91-add-hw_reset-callback.patch | 58 + ...f-at91-add-compatible-to-sama7g5-SoC.patch | 73 + ...91-add-support-for-HS400-and-HS400ES.patch | 95 + ...dhci-of-at91-issue-IP-reset-at-probe.patch | 28 + ...1-perform-a-hardware-reset-at-probe-.patch | 28 + ...ci-of-at91-add-preset-for-HS400-mode.patch | 36 + ...1-disable-selectively-clocks-on-pm-r.patch | 66 + ...1-do-not-advertise-SDR104-mode-suppo.patch | 40 + ...sdhci-of-at91-avoid-division-by-zero.patch | 48 + ...-of-at91-add-sama7g5-required-quirks.patch | 24 + ...i-of-at91-add-soc-data-field-quirks2.patch | 50 + ...oduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch | 37 + ...18-mmc-mmc-sdhci-of-at91-add-LAN969x.patch | 33 + ...uadspi-Add-support-for-LAN969x-QSPI0.patch | 80 + ...-lan9662-otp-add-support-for-LAN969x.patch | 68 + ...ac-get-the-number-of-DMA-channels-fr.patch | 64 + 119 files changed, 36377 insertions(+) create mode 100644 target/linux/microchipsw/Makefile create mode 100644 target/linux/microchipsw/dts/lan969x.dtsi create mode 100644 target/linux/microchipsw/image/Makefile create mode 100644 target/linux/microchipsw/lan969x/config-default create mode 100644 target/linux/microchipsw/lan969x/target.mk create mode 100644 target/linux/microchipsw/patches-6.12/0001-v6.18-arm64-Add-config-for-Microchip-SoC-platforms.patch create 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target/linux/microchipsw/patches-6.12/0092-v6.18-net-sparx5-lan969x-fix-flooding-configuration-on-bri.patch create mode 100644 target/linux/microchipsw/patches-6.12/100-clk-lan966x-make-it-selectable-for-ARCH_LAN969X.patch create mode 100644 target/linux/microchipsw/patches-6.12/102-phy-sparx5-serdes-make-it-selectable-for-ARCH_LAN969.patch create mode 100644 target/linux/microchipsw/patches-6.12/103-include-dt-bindings-add-LAN969x-clock-bindings.patch create mode 100644 target/linux/microchipsw/patches-6.12/104-reset-sparx5-add-LAN969x-support.patch create mode 100644 target/linux/microchipsw/patches-6.12/105-hwmon-sparx5-make-it-selectable-for-ARCH_MICROCHIP.patch create mode 100644 target/linux/microchipsw/patches-6.12/106-mmc-sdhci-of-at91-implement-quirk-SDCLK-stop-while-r.patch create mode 100644 target/linux/microchipsw/patches-6.12/107-mmc-sdhci-of-at91-add-hw_reset-callback.patch create mode 100644 target/linux/microchipsw/patches-6.12/108-mmc-sdhci-of-at91-add-compatible-to-sama7g5-SoC.patch create mode 100644 target/linux/microchipsw/patches-6.12/109-mmc-sdhci-of-at91-add-support-for-HS400-and-HS400ES.patch create mode 100644 target/linux/microchipsw/patches-6.12/110-sdhci-sdhci-of-at91-issue-IP-reset-at-probe.patch create mode 100644 target/linux/microchipsw/patches-6.12/111-mmc-sdhci-of-at91-perform-a-hardware-reset-at-probe-.patch create mode 100644 target/linux/microchipsw/patches-6.12/112-mmc-sdhci-of-at91-add-preset-for-HS400-mode.patch create mode 100644 target/linux/microchipsw/patches-6.12/113-mmc-sdhci-of-at91-disable-selectively-clocks-on-pm-r.patch create mode 100644 target/linux/microchipsw/patches-6.12/114-mmc-sdhci-of-at91-do-not-advertise-SDR104-mode-suppo.patch create mode 100644 target/linux/microchipsw/patches-6.12/115-mmc-sdhci-of-at91-avoid-division-by-zero.patch create mode 100644 target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-sama7g5-required-quirks.patch create mode 100644 target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-soc-data-field-quirks2.patch create mode 100644 target/linux/microchipsw/patches-6.12/117-mmc-introduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch create mode 100644 target/linux/microchipsw/patches-6.12/118-mmc-mmc-sdhci-of-at91-add-LAN969x.patch create mode 100644 target/linux/microchipsw/patches-6.12/119-spi-atmel-quadspi-Add-support-for-LAN969x-QSPI0.patch create mode 100644 target/linux/microchipsw/patches-6.12/121-nvmem-lan9662-otp-add-support-for-LAN969x.patch create mode 100644 target/linux/microchipsw/patches-6.12/900-dmaengine-at_xdmac-get-the-number-of-DMA-channels-fr.patch diff --git a/.github/labeler.yml b/.github/labeler.yml index 89ac535595..182293d4f6 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml @@ -126,6 +126,12 @@ - "target/linux/mediatek/**" - "package/boot/arm-trusted-firmware-mediatek/**" - "package/boot/uboot-mediatek/**" +"target/microchipsw": +- changed-files: + - any-glob-to-any-file: + - "target/linux/microchipsw/**" + - "package/boot/arm-trusted-firmware-microchipsw/**" + - "package/boot/uboot-microchipsw/**" "target/mpc85xx": - changed-files: - any-glob-to-any-file: diff --git a/config/Config-images.in b/config/Config-images.in index 208c4838d1..9b04ddbeec 100644 --- a/config/Config-images.in +++ b/config/Config-images.in @@ -18,6 +18,7 @@ menu "Target Images" default TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_mpc85xx default TARGET_INITRAMFS_COMPRESSION_LZMA if TARGET_ramips default TARGET_INITRAMFS_COMPRESSION_ZSTD if TARGET_qualcommax + default TARGET_INITRAMFS_COMPRESSION_ZSTD if TARGET_microchipsw default TARGET_INITRAMFS_COMPRESSION_XZ if USES_SEPARATE_INITRAMFS default TARGET_INITRAMFS_COMPRESSION_NONE depends on TARGET_ROOTFS_INITRAMFS diff --git a/target/linux/microchipsw/Makefile b/target/linux/microchipsw/Makefile new file mode 100644 index 0000000000..c56bca568c --- /dev/null +++ b/target/linux/microchipsw/Makefile @@ -0,0 +1,20 @@ +include $(TOPDIR)/rules.mk + +ARCH:=aarch64 +BOARD:=microchipsw +BOARDNAME:=Microchip switches +FEATURES:=squashfs ramdisk fpu rtc emmc source-only +KERNELNAME:=Image +CPU_TYPE:=cortex-a53 +SUBTARGETS:=lan969x + +KERNEL_PATCHVER:=6.12 + +include $(INCLUDE_DIR)/target.mk +DEFAULT_PACKAGES += \ + kmod-gpio-button-hotplug \ + kmod-leds-gpio \ + uboot-envtools \ + ethtool-full + +$(eval $(call BuildTarget)) diff --git a/target/linux/microchipsw/dts/lan969x.dtsi b/target/linux/microchipsw/dts/lan969x.dtsi new file mode 100644 index 0000000000..db364c9d24 --- /dev/null +++ b/target/linux/microchipsw/dts/lan969x.dtsi @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. + */ + +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + model = "Microchip LAN969x"; + compatible = "microchip,lan969x"; + interrupt-parent = <&gic>; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + clocks { + fx100_clk: fx100-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <320000000>; + }; + + cpu_clk: cpu-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000000>; + }; + + ddr_clk: ddr-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + }; + + fabric_clk: fabric-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + next-level-cache = <&l2_0>; + }; + + l2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , /* Secure Phys IRQ */ + , /* Non-secure Phys IRQ */ + , /* Virt IRQ */ + ; /* Hyp IRQ */ + }; + + axi: axi { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usb: usb@300000 { + compatible = "microchip,lan9691-dwc3", "snps,dwc3"; + reg = <0x300000 0x80000>; + interrupts = ; + clocks = <&clks GCK_GATE_USB_DRD>, + <&clks GCK_ID_USB_REFCLK>; + clock-names = "bus_early", "ref"; + assigned-clocks = <&clks GCK_ID_USB_REFCLK>; + assigned-clock-rates = <60000000>; + maximum-speed = "high-speed"; + dr_mode = "host"; + status = "disabled"; + }; + + otp: otp@e0021000 { + compatible = "microchip,lan9691-otpc"; + reg = <0xe0021000 0x1000>; + }; + + flx0: flexcom@e0040000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0040000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM0>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0040000 0x800>; + status = "disabled"; + + usart0: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi0: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flx1: flexcom@e0044000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0044000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM1>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0044000 0x800>; + status = "disabled"; + + usart1: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi1: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(3)>, + <&dma AT91_XDMAC_DT_PERID(2)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + trng: rng@e0048000 { + compatible = "atmel,at91sam9g45-trng"; + reg = <0xe0048000 0x100>; + clocks = <&fabric_clk>; + status = "disabled"; + }; + + aes: crypto@e004c000 { + compatible = "atmel,at91sam9g46-aes"; + reg = <0xe004c000 0x100>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(12)>, + <&dma AT91_XDMAC_DT_PERID(13)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "aes_clk"; + status = "disabled"; + }; + + flx2: flexcom@e0060000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0060000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM2>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0060000 0x800>; + status = "disabled"; + + usart2: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(7)>, + <&dma AT91_XDMAC_DT_PERID(6)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + clocks = <&fabric_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flx3: flexcom@e0064000 { + compatible = "atmel,sama5d2-flexcom"; + reg = <0xe0064000 0x100>; + clocks = <&clks GCK_ID_FLEXCOM3>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0xe0064000 0x800>; + status = "disabled"; + + usart3: serial@200 { + compatible = "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "usart"; + atmel,fifo-size = <32>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + clock-names = "spi_clk"; + atmel,fifo-size = <32>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(9)>, + <&dma AT91_XDMAC_DT_PERID(8)>; + dma-names = "tx", "rx"; + clocks = <&fabric_clk>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + dma: dma-controller@e0068000 { + compatible = "microchip,sama7g5-dma"; + reg = <0xe0068000 0x1000>; + interrupts = ; + dma-channels = <16>; + #dma-cells = <1>; + clocks = <&fabric_clk>; + clock-names = "dma_clk"; + }; + + sha: crypto@e006c000 { + compatible = "atmel,at91sam9g46-sha"; + reg = <0xe006c000 0xec>; + interrupts = ; + dmas = <&dma AT91_XDMAC_DT_PERID(14)>; + dma-names = "tx"; + clocks = <&fabric_clk>; + clock-names = "sha_clk"; + status = "disabled"; + }; + + timer: timer@e008c000 { + compatible = "snps,dw-apb-timer"; + reg = <0xe008c000 0x400>; + clocks = <&fabric_clk>; + clock-names = "timer"; + interrupts = ; + status = "disabled"; + }; + + watchdog: watchdog@e0090000 { + compatible = "snps,dw-wdt"; + reg = <0xe0090000 0x1000>; + interrupts = ; + clocks = <&fabric_clk>; + }; + + cpu_ctrl: syscon@e00c0000 { + compatible = "microchip,lan966x-cpu-syscon", "syscon"; + reg = <0xe00c0000 0x350>; + }; + + switch: switch@e00c0000 { + compatible = "microchip,lan9691-switch"; + reg = <0xe00c0000 0x0010000>, + <0xe2010000 0x1410000>; + reg-names = "cpu", "devices"; + interrupt-names = "xtr", "fdma", "ptp"; + interrupts = , + , + ; + resets = <&reset 0>; + reset-names = "switch"; + status = "disabled"; + }; + + clks: clock-controller@e00c00b4 { + compatible = "microchip,lan9691-gck"; + #clock-cells = <1>; + clocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>; + clock-names = "cpu", "ddr", "sys"; + reg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>; + }; + + qspi0: spi@e0804000 { + compatible = "microchip,lan9691-qspi"; + reg = <0xe0804000 0x00000100>, + <0x20000000 0x08000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + clocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&clks GCK_ID_QSPI0>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sdmmc0: mmc@e0830000 { + compatible = "microchip,lan9691-sdhci"; + reg = <0xe0830000 0x00000300>; + interrupts = ; + clocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&clks GCK_ID_SDMMC0>; + assigned-clock-rates = <100000000>; + status = "disabled"; + }; + + sdmmc1: mmc@e0838000 { + compatible = "microchip,lan9691-sdhci"; + reg = <0xe0838000 0x00000300>; + interrupts = ; + clocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>; + clock-names = "hclock", "multclk"; + assigned-clocks = <&clks GCK_ID_SDMMC1>; + assigned-clock-rates = <45000000>; + status = "disabled"; + }; + + qspi2: spi@e0834000 { + compatible = "microchip,lan9691-qspi"; + reg = <0xe0834000 0x00000100>, + <0x30000000 0x04000000>; + reg-names = "qspi_base", "qspi_mmap"; + interrupts = ; + clocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>; + clock-names = "pclk", "gclk"; + assigned-clocks = <&clks GCK_ID_QSPI2>; + assigned-clock-rates = <100000000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + reset: reset-controller@e201000c { + compatible = "microchip,lan9691-switch-reset", "microchip,lan966x-switch-reset"; + reg = <0xe201000c 0x4>; + reg-names = "gcb"; + #reset-cells = <1>; + cpu-syscon = <&cpu_ctrl>; + }; + + gpio: pinctrl@e20100d4 { + compatible = "microchip,lan9691-pinctrl"; + reg = <0xe20100d4 0xd4>, + <0xe2010370 0xa8>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 66>; + interrupt-controller; + interrupts = ; + #interrupt-cells = <2>; + }; + + mdio0: mdio@e20101a8 { + compatible = "mscc,ocelot-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe20101a8 0x24>; + clocks = <&fx100_clk>; + status = "disabled"; + }; + + mdio1: mdio@e20101cc { + compatible = "mscc,ocelot-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xe20101cc 0x24>; + clocks = <&fx100_clk>; + status = "disabled"; + }; + + sgpio: gpio@e2010230 { + compatible = "microchip,sparx5-sgpio"; + reg = <0xe2010230 0x118>; + clocks = <&fx100_clk>; + resets = <&reset 0>; + reset-names = "switch"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + sgpio_in: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + sgpio_out: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + }; + }; + + tmon: hwmon@e2020100 { + compatible = "microchip,sparx5-temp"; + reg = <0xe2020100 0xc>; + clocks = <&fx100_clk>; + #thermal-sensor-cells = <0>; + }; + + serdes: serdes@e3410000 { + compatible = "microchip,lan9691-serdes"; + #phy-cells = <1>; + clocks = <&fabric_clk>; + reg = <0xe3410000 0x150000>; + }; + + gic: interrupt-controller@e8c11000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0xe8c11000 0x1000>, /* Distributor GICD_ */ + <0xe8c12000 0x2000>, /* CPU interface GICC_ */ + <0xe8c14000 0x2000>, /* Virt interface control */ + <0xe8c16000 0x2000>; /* Virt CPU interface */ + interrupts = ; + }; + }; +}; diff --git a/target/linux/microchipsw/image/Makefile b/target/linux/microchipsw/image/Makefile new file mode 100644 index 0000000000..4bee818578 --- /dev/null +++ b/target/linux/microchipsw/image/Makefile @@ -0,0 +1,21 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +define Device/Default + PROFILES := Default + KERNEL_LOADADDR := 0x60000000 + DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1))) + DEVICE_DTS_CONFIG := config-1 + DEVICE_DTS_DIR := ../dts + IMAGES := sysupgrade.bin + IMAGE/sysupgrade.bin = sysupgrade-tar | append-metadata + IMAGE/sysupgrade.bin/squashfs := +endef + +define Device/FitImage + KERNEL_SUFFIX := -uImage.itb + KERNEL = kernel-bin | libdeflate-gzip | fit gzip $$(KDIR)/image-$$(DEVICE_DTS).dtb + KERNEL_NAME := Image +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/microchipsw/lan969x/config-default b/target/linux/microchipsw/lan969x/config-default new file mode 100644 index 0000000000..fd4b7424e8 --- /dev/null +++ b/target/linux/microchipsw/lan969x/config-default @@ -0,0 +1,272 @@ +CONFIG_64BIT=y +CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y +CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y +CONFIG_ARCH_DEFAULT_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_FORCE_MAX_ORDER=10 +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_LAN969X=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y +CONFIG_ARCH_MICROCHIP=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_BITS_MAX=24 +CONFIG_ARCH_MMAP_RND_BITS_MIN=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 +CONFIG_ARCH_PKEY_BITS=3 +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANTS_EXECMEM_LATE=y +CONFIG_ARCH_WANTS_NO_INSTR=y +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_ARM64=y +CONFIG_ARM64_4K_PAGES=y +CONFIG_ARM64_ERRATUM_819472=y +CONFIG_ARM64_ERRATUM_824069=y +CONFIG_ARM64_ERRATUM_826319=y +CONFIG_ARM64_ERRATUM_827319=y +CONFIG_ARM64_ERRATUM_843419=y +CONFIG_ARM64_LD_HAS_FIX_ERRATUM_843419=y +CONFIG_ARM64_PA_BITS=48 +CONFIG_ARM64_PA_BITS_48=y +CONFIG_ARM64_PLATFORM_DEVICES=y +CONFIG_ARM64_TAGGED_ADDR_ABI=y +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +CONFIG_ARM64_WORKAROUND_CLEAN_CACHE=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_GIC=y +CONFIG_ARM_GIC_V3=y +CONFIG_ARM_GIC_V3_ITS=y +CONFIG_ARM_PSCI_FW=y +CONFIG_AT_XDMAC=y +CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y +CONFIG_CC_HAVE_SHADOW_CALL_STACK=y +CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_LAN966X=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +# CONFIG_COMPAT_32BIT_TIME is not set +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CPUMASK_OFFSTACK=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_RMAP=y +CONFIG_CRYPTO_DEV_ATMEL_AES=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_INFO=y +CONFIG_DMADEVICES=y +CONFIG_DMA_BOUNCE_UNALIGNED_KMALLOC=y +CONFIG_DMA_DIRECT_REMAP=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_NEED_SYNC=y +CONFIG_DMA_OF=y +CONFIG_DTC=y +CONFIG_DW_APB_TIMER=y +CONFIG_DW_APB_TIMER_OF=y +CONFIG_DW_WATCHDOG=y +CONFIG_EDAC_SUPPORT=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_FDMA=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FRAME_POINTER=y +CONFIG_FS_IOMAP=y +CONFIG_FUNCTION_ALIGNMENT=4 +CONFIG_FUNCTION_ALIGNMENT_4B=y +CONFIG_FWNODE_MDIO=y +CONFIG_FW_LOADER_PAGED_BUF=y +CONFIG_FW_LOADER_SYSFS=y +CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_DEVICES=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_CSUM=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IOREMAP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HWMON=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_ATMEL=y +CONFIG_HZ_PERIODIC=y +CONFIG_I2C=y +CONFIG_I2C_AT91=y +# CONFIG_I2C_AT91_SLAVE_EXPERIMENTAL is not set +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +CONFIG_INITRAMFS_SOURCE="" +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_MSI_LIB=y +CONFIG_IRQ_WORK=y +CONFIG_LAN969X_SWITCH=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LRU_GEN_WALKS_MMU=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +CONFIG_MDIO_I2C=y +CONFIG_MDIO_MSCC_MIIM=y +CONFIG_MFD_AT91_USART=y +CONFIG_MFD_ATMEL_FLEXCOM=y +CONFIG_MFD_CORE=y +CONFIG_MFD_SYSCON=y +CONFIG_MICREL_PHY=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_OF_AT91=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NLS=y +CONFIG_NO_IOPORT_MAP=y +CONFIG_NR_CPUS=512 +CONFIG_NVMEM=y +CONFIG_NVMEM_LAN9662_OTPC=y +CONFIG_NVMEM_LAYOUTS=y +CONFIG_NVMEM_SYSFS=y +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_PADATA=y +CONFIG_PAGE_POOL=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +CONFIG_PARTITION_PERCPU=y +CONFIG_PER_VMA_LOCK=y +CONFIG_PGTABLE_LEVELS=3 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_PHY_SPARX5_SERDES=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MICROCHIP_SGPIO=y +CONFIG_PINCTRL_OCELOT=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_SUPPLY=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_PWM=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RATIONAL=y +CONFIG_REGMAP=y +CONFIG_REGMAP_MMIO=y +CONFIG_RELOCATABLE=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_MCHP_SPARX5=y +CONFIG_RFS_ACCEL=y +CONFIG_RODATA_FULL_DEFAULT_ENABLED=y +CONFIG_RPS=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SENSORS_SPARX5=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_ATMEL=y +CONFIG_SERIAL_ATMEL_CONSOLE=y +CONFIG_SERIAL_ATMEL_PDC=y +CONFIG_SERIAL_ATMEL_TTYAT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SFP=y +CONFIG_SMP=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSE_IRQ=y +CONFIG_SPARX5_SWITCH=y +CONFIG_SPI=y +CONFIG_SPI_ATMEL=y +CONFIG_SPI_ATMEL_QUADSPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPLIT_PMD_PTLOCKS=y +CONFIG_SPLIT_PTE_PTLOCKS=y +CONFIG_SWIOTLB=y +CONFIG_SWPHY=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TOOLS_SUPPORT_RELR=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_UNMAP_KERNEL_AT_EL0=y +CONFIG_USB=y +CONFIG_USB_COMMON=y +CONFIG_USB_SUPPORT=y +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_VCAP=y +CONFIG_VDSO_GETRANDOM=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_SYSFS=y +CONFIG_XPS=y +CONFIG_ZONE_DMA32=y diff --git a/target/linux/microchipsw/lan969x/target.mk b/target/linux/microchipsw/lan969x/target.mk new file mode 100644 index 0000000000..dce697a82d --- /dev/null +++ b/target/linux/microchipsw/lan969x/target.mk @@ -0,0 +1,8 @@ +SUBTARGET:=lan969x +BOARDNAME:=Microchip LAN969x switches + +DEFAULT_PACKAGES += kmod-usb3 kmod-usb-dwc3 + +define Target/Description + Build firmware images for Microchip LAN969x switch based boards. +endef diff --git a/target/linux/microchipsw/patches-6.12/0001-v6.18-arm64-Add-config-for-Microchip-SoC-platforms.patch b/target/linux/microchipsw/patches-6.12/0001-v6.18-arm64-Add-config-for-Microchip-SoC-platforms.patch new file mode 100644 index 0000000000..7cdd3bd45f --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0001-v6.18-arm64-Add-config-for-Microchip-SoC-platforms.patch @@ -0,0 +1,74 @@ +From 83647d5b9b5b1f7315c908c8c35632cd46a47801 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 13 Aug 2025 19:44:37 +0200 +Subject: [PATCH 01/25] arm64: Add config for Microchip SoC platforms + +Currently, Microchip SparX-5 SoC is supported and it has its own symbol. + +However, this means that new Microchip platforms that share drivers need +to constantly keep updating depends on various drivers. + +So, to try and reduce this lets add ARCH_MICROCHIP symbol that drivers +could instead depend on. + +LAN969x is being worked on and it will be added under ARCH_MICROCHIP. + +Signed-off-by: Robert Marko +Acked-by: Daniel Machon +Signed-off-by: Nicolas Ferre +--- + arch/arm64/Kconfig.platforms | 36 ++++++++++++++++++++++-------------- + 1 file changed, 22 insertions(+), 14 deletions(-) + +--- a/arch/arm64/Kconfig.platforms ++++ b/arch/arm64/Kconfig.platforms +@@ -114,20 +114,6 @@ config ARCH_EXYNOS + help + This enables support for ARMv8 based Samsung Exynos SoC family. + +-config ARCH_SPARX5 +- bool "Microchip Sparx5 SoC family" +- select PINCTRL +- select DW_APB_TIMER_OF +- help +- This enables support for the Microchip Sparx5 ARMv8-based +- SoC family of TSN-capable gigabit switches. +- +- The SparX-5 Ethernet switch family provides a rich set of +- switching features such as advanced TCAM-based VLAN and QoS +- processing enabling delivery of differentiated services, and +- security through TCAM-based frame processing using versatile +- content aware processor (VCAP). +- + config ARCH_K3 + bool "Texas Instruments Inc. K3 multicore SoC architecture" + select PM_GENERIC_DOMAINS if PM +@@ -175,6 +161,28 @@ config ARCH_MESON + This enables support for the arm64 based Amlogic SoCs + such as the s905, S905X/D, S912, A113X/D or S905X/D2 + ++menu "Microchip SoC support" ++ ++config ARCH_MICROCHIP ++ bool ++ ++config ARCH_SPARX5 ++ bool "Microchip Sparx5 SoC family" ++ select PINCTRL ++ select DW_APB_TIMER_OF ++ select ARCH_MICROCHIP ++ help ++ This enables support for the Microchip Sparx5 ARMv8-based ++ SoC family of TSN-capable gigabit switches. ++ ++ The SparX-5 Ethernet switch family provides a rich set of ++ switching features such as advanced TCAM-based VLAN and QoS ++ processing enabling delivery of differentiated services, and ++ security through TCAM-based frame processing using versatile ++ content aware processor (VCAP). ++ ++endmenu ++ + config ARCH_MVEBU + bool "Marvell EBU SoC Family" + select ARMADA_AP806_SYSCON diff --git a/target/linux/microchipsw/patches-6.12/0002-v6.18-arm64-lan969x-Add-support-for-Microchip-LAN969x-SoC.patch b/target/linux/microchipsw/patches-6.12/0002-v6.18-arm64-lan969x-Add-support-for-Microchip-LAN969x-SoC.patch new file mode 100644 index 0000000000..727fcb65a0 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0002-v6.18-arm64-lan969x-Add-support-for-Microchip-LAN969x-SoC.patch @@ -0,0 +1,38 @@ +From 64016a564b81491c092ef03c7e11305650d8641a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 13 Aug 2025 19:44:39 +0200 +Subject: [PATCH 02/25] arm64: lan969x: Add support for Microchip LAN969x SoC + +This adds support for the Microchip LAN969x ARMv8-based SoC switch family. + +Signed-off-by: Robert Marko +Acked-by: Daniel Machon +Signed-off-by: Nicolas Ferre +--- + arch/arm64/Kconfig.platforms | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/arch/arm64/Kconfig.platforms ++++ b/arch/arm64/Kconfig.platforms +@@ -166,6 +166,21 @@ menu "Microchip SoC support" + config ARCH_MICROCHIP + bool + ++config ARCH_LAN969X ++ bool "Microchip LAN969X SoC family" ++ select PINCTRL ++ select DW_APB_TIMER_OF ++ select ARCH_MICROCHIP ++ help ++ This enables support for the Microchip LAN969X ARMv8-based ++ SoC family of TSN-capable gigabit switches. ++ ++ The LAN969X Ethernet switch family provides a rich set of ++ switching features such as advanced TCAM-based VLAN and QoS ++ processing enabling delivery of differentiated services, and ++ security through TCAM-based frame processing using versatile ++ content aware processor (VCAP). ++ + config ARCH_SPARX5 + bool "Microchip Sparx5 SoC family" + select PINCTRL diff --git a/target/linux/microchipsw/patches-6.12/0003-v6.13-pinctrl-ocelot-add-support-for-lan969x-SoC-pinctrl.patch b/target/linux/microchipsw/patches-6.12/0003-v6.13-pinctrl-ocelot-add-support-for-lan969x-SoC-pinctrl.patch new file mode 100644 index 0000000000..723bddfdf4 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0003-v6.13-pinctrl-ocelot-add-support-for-lan969x-SoC-pinctrl.patch @@ -0,0 +1,348 @@ +From bcf540500e1feb072cf7659f71a437a63f1735f9 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Tue, 17 Sep 2024 14:45:41 +0200 +Subject: [PATCH 03/25] pinctrl: ocelot: add support for lan969x SoC pinctrl + +This adds support for lan969x SoC pinctrl, reusing the existing ocelot +driver. There are 66 General Purpose I/O pins that are individually +configurable to multiple interfaces. + +Signed-off-by: Daniel Machon +Link: https://lore.kernel.org/20240917-lan969x-pinctrl-v2-2-ea02cbc56831@microchip.com +Signed-off-by: Linus Walleij +--- + drivers/pinctrl/pinctrl-ocelot.c | 203 +++++++++++++++++++++++++++++++ + 1 file changed, 203 insertions(+) + +--- a/drivers/pinctrl/pinctrl-ocelot.c ++++ b/drivers/pinctrl/pinctrl-ocelot.c +@@ -57,6 +57,8 @@ enum { + FUNC_CAN1, + FUNC_CLKMON, + FUNC_NONE, ++ FUNC_FAN, ++ FUNC_FC, + FUNC_FC0_a, + FUNC_FC0_b, + FUNC_FC0_c, +@@ -71,6 +73,7 @@ enum { + FUNC_FC4_a, + FUNC_FC4_b, + FUNC_FC4_c, ++ FUNC_FC_SHRD, + FUNC_FC_SHRD0, + FUNC_FC_SHRD1, + FUNC_FC_SHRD2, +@@ -92,6 +95,7 @@ enum { + FUNC_FC_SHRD18, + FUNC_FC_SHRD19, + FUNC_FC_SHRD20, ++ FUNC_FUSA, + FUNC_GPIO, + FUNC_IB_TRG_a, + FUNC_IB_TRG_b, +@@ -108,6 +112,8 @@ enum { + FUNC_IRQ1, + FUNC_IRQ1_IN, + FUNC_IRQ1_OUT, ++ FUNC_IRQ3, ++ FUNC_IRQ4, + FUNC_EXT_IRQ, + FUNC_MIIM, + FUNC_MIIM_a, +@@ -115,12 +121,14 @@ enum { + FUNC_MIIM_c, + FUNC_MIIM_Sa, + FUNC_MIIM_Sb, ++ FUNC_MIIM_IRQ, + FUNC_OB_TRG, + FUNC_OB_TRG_a, + FUNC_OB_TRG_b, + FUNC_PHY_LED, + FUNC_PCI_WAKE, + FUNC_MD, ++ FUNC_PCIE_PERST, + FUNC_PTP0, + FUNC_PTP1, + FUNC_PTP2, +@@ -152,6 +160,7 @@ enum { + FUNC_SGPIO_b, + FUNC_SI, + FUNC_SI2, ++ FUNC_SYNCE, + FUNC_TACHO, + FUNC_TACHO_a, + FUNC_TACHO_b, +@@ -170,6 +179,10 @@ enum { + FUNC_USB_S_a, + FUNC_USB_S_b, + FUNC_USB_S_c, ++ FUNC_USB_POWER, ++ FUNC_USB2PHY_RST, ++ FUNC_USB_OVER_DETECT, ++ FUNC_USB_ULPI, + FUNC_PLL_STAT, + FUNC_EMMC, + FUNC_EMMC_SD, +@@ -184,6 +197,8 @@ static const char *const ocelot_function + [FUNC_CAN1] = "can1", + [FUNC_CLKMON] = "clkmon", + [FUNC_NONE] = "none", ++ [FUNC_FAN] = "fan", ++ [FUNC_FC] = "fc", + [FUNC_FC0_a] = "fc0_a", + [FUNC_FC0_b] = "fc0_b", + [FUNC_FC0_c] = "fc0_c", +@@ -198,6 +213,7 @@ static const char *const ocelot_function + [FUNC_FC4_a] = "fc4_a", + [FUNC_FC4_b] = "fc4_b", + [FUNC_FC4_c] = "fc4_c", ++ [FUNC_FC_SHRD] = "fc_shrd", + [FUNC_FC_SHRD0] = "fc_shrd0", + [FUNC_FC_SHRD1] = "fc_shrd1", + [FUNC_FC_SHRD2] = "fc_shrd2", +@@ -219,6 +235,7 @@ static const char *const ocelot_function + [FUNC_FC_SHRD18] = "fc_shrd18", + [FUNC_FC_SHRD19] = "fc_shrd19", + [FUNC_FC_SHRD20] = "fc_shrd20", ++ [FUNC_FUSA] = "fusa", + [FUNC_GPIO] = "gpio", + [FUNC_IB_TRG_a] = "ib_trig_a", + [FUNC_IB_TRG_b] = "ib_trig_b", +@@ -235,6 +252,8 @@ static const char *const ocelot_function + [FUNC_IRQ1] = "irq1", + [FUNC_IRQ1_IN] = "irq1_in", + [FUNC_IRQ1_OUT] = "irq1_out", ++ [FUNC_IRQ3] = "irq3", ++ [FUNC_IRQ4] = "irq4", + [FUNC_EXT_IRQ] = "ext_irq", + [FUNC_MIIM] = "miim", + [FUNC_MIIM_a] = "miim_a", +@@ -242,8 +261,10 @@ static const char *const ocelot_function + [FUNC_MIIM_c] = "miim_c", + [FUNC_MIIM_Sa] = "miim_slave_a", + [FUNC_MIIM_Sb] = "miim_slave_b", ++ [FUNC_MIIM_IRQ] = "miim_irq", + [FUNC_PHY_LED] = "phy_led", + [FUNC_PCI_WAKE] = "pci_wake", ++ [FUNC_PCIE_PERST] = "pcie_perst", + [FUNC_MD] = "md", + [FUNC_OB_TRG] = "ob_trig", + [FUNC_OB_TRG_a] = "ob_trig_a", +@@ -279,6 +300,7 @@ static const char *const ocelot_function + [FUNC_SGPIO_b] = "sgpio_b", + [FUNC_SI] = "si", + [FUNC_SI2] = "si2", ++ [FUNC_SYNCE] = "synce", + [FUNC_TACHO] = "tacho", + [FUNC_TACHO_a] = "tacho_a", + [FUNC_TACHO_b] = "tacho_b", +@@ -294,6 +316,10 @@ static const char *const ocelot_function + [FUNC_USB_S_a] = "usb_slave_a", + [FUNC_USB_S_b] = "usb_slave_b", + [FUNC_USB_S_c] = "usb_slave_c", ++ [FUNC_USB_POWER] = "usb_power", ++ [FUNC_USB2PHY_RST] = "usb2phy_rst", ++ [FUNC_USB_OVER_DETECT] = "usb_over_detect", ++ [FUNC_USB_ULPI] = "usb_ulpi", + [FUNC_UART] = "uart", + [FUNC_UART2] = "uart2", + [FUNC_UART3] = "uart3", +@@ -1136,6 +1162,165 @@ static const struct pinctrl_pin_desc lan + LAN966X_PIN(77), + }; + ++#define LAN969X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ ++static struct ocelot_pin_caps lan969x_pin_##p = { \ ++ .pin = p, \ ++ .functions = { \ ++ FUNC_##f0, FUNC_##f1, FUNC_##f2, \ ++ FUNC_##f3 \ ++ }, \ ++ .a_functions = { \ ++ FUNC_##f4, FUNC_##f5, FUNC_##f6, \ ++ FUNC_##f7 \ ++ }, \ ++} ++ ++/* Pinmuxing table taken from data sheet */ ++/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ ++LAN969X_P(0, GPIO, IRQ0, FC_SHRD, PCIE_PERST, NONE, NONE, NONE, R); ++LAN969X_P(1, GPIO, IRQ1, FC_SHRD, USB_POWER, NONE, NONE, NONE, R); ++LAN969X_P(2, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); ++LAN969X_P(3, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); ++LAN969X_P(4, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R); ++LAN969X_P(5, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); ++LAN969X_P(6, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); ++LAN969X_P(7, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); ++LAN969X_P(8, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R); ++LAN969X_P(9, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); ++LAN969X_P(10, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); ++LAN969X_P(11, GPIO, MIIM_IRQ, MIIM_Sa, CLKMON, NONE, NONE, NONE, R); ++LAN969X_P(12, GPIO, IRQ3, FC_SHRD, USB2PHY_RST, NONE, NONE, NONE, R); ++LAN969X_P(13, GPIO, IRQ4, FC_SHRD, USB_OVER_DETECT, NONE, NONE, NONE, R); ++LAN969X_P(14, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); ++LAN969X_P(15, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); ++LAN969X_P(16, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R); ++LAN969X_P(17, GPIO, EMMC_SD, QSPI1, PTPSYNC_0, USB_POWER, NONE, NONE, R); ++LAN969X_P(18, GPIO, EMMC_SD, QSPI1, PTPSYNC_1, USB2PHY_RST, NONE, NONE, R); ++LAN969X_P(19, GPIO, EMMC_SD, QSPI1, PTPSYNC_2, USB_OVER_DETECT, NONE, NONE, R); ++LAN969X_P(20, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); ++LAN969X_P(21, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); ++LAN969X_P(22, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); ++LAN969X_P(23, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R); ++LAN969X_P(24, GPIO, EMMC_SD, NONE, NONE, NONE, NONE, NONE, R); ++LAN969X_P(25, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); ++LAN969X_P(26, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R); ++LAN969X_P(27, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); ++LAN969X_P(28, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R); ++LAN969X_P(29, GPIO, SYNCE, FC, MIIM_IRQ, QSPI1, NONE, NONE, R); ++LAN969X_P(30, GPIO, PTPSYNC_0, USB_ULPI, FC_SHRD, QSPI1, NONE, NONE, R); ++LAN969X_P(31, GPIO, PTPSYNC_1, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); ++LAN969X_P(32, GPIO, PTPSYNC_2, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); ++LAN969X_P(33, GPIO, SD, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R); ++LAN969X_P(34, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); ++LAN969X_P(35, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R); ++LAN969X_P(36, GPIO, SD, USB_ULPI, PCIE_PERST, FC_SHRD, NONE, NONE, R); ++LAN969X_P(37, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); ++LAN969X_P(38, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R); ++LAN969X_P(39, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); ++LAN969X_P(40, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R); ++LAN969X_P(41, GPIO, SD, USB_ULPI, MIIM_IRQ, NONE, NONE, NONE, R); ++LAN969X_P(42, GPIO, PTPSYNC_3, CAN1, NONE, NONE, NONE, NONE, R); ++LAN969X_P(43, GPIO, PTPSYNC_4, CAN1, NONE, NONE, NONE, NONE, R); ++LAN969X_P(44, GPIO, PTPSYNC_5, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(45, GPIO, PTPSYNC_6, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(46, GPIO, PTPSYNC_7, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(47, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(48, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(49, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(50, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(51, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(52, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(53, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R); ++LAN969X_P(54, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); ++LAN969X_P(55, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); ++LAN969X_P(56, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R); ++LAN969X_P(57, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_3, NONE, NONE, R); ++LAN969X_P(58, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_4, NONE, NONE, R); ++LAN969X_P(59, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_5, NONE, NONE, R); ++LAN969X_P(60, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_6, NONE, NONE, R); ++LAN969X_P(61, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); ++LAN969X_P(62, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R); ++LAN969X_P(63, GPIO, MIIM_IRQ, FC_SHRD, TWI, NONE, NONE, NONE, R); ++LAN969X_P(64, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); ++LAN969X_P(65, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); ++LAN969X_P(66, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R); ++ ++#define LAN969X_PIN(n) { \ ++ .number = n, \ ++ .name = "GPIO_"#n, \ ++ .drv_data = &lan969x_pin_##n \ ++} ++ ++static const struct pinctrl_pin_desc lan969x_pins[] = { ++ LAN969X_PIN(0), ++ LAN969X_PIN(1), ++ LAN969X_PIN(2), ++ LAN969X_PIN(3), ++ LAN969X_PIN(4), ++ LAN969X_PIN(5), ++ LAN969X_PIN(6), ++ LAN969X_PIN(7), ++ LAN969X_PIN(8), ++ LAN969X_PIN(9), ++ LAN969X_PIN(10), ++ LAN969X_PIN(11), ++ LAN969X_PIN(12), ++ LAN969X_PIN(13), ++ LAN969X_PIN(14), ++ LAN969X_PIN(15), ++ LAN969X_PIN(16), ++ LAN969X_PIN(17), ++ LAN969X_PIN(18), ++ LAN969X_PIN(19), ++ LAN969X_PIN(20), ++ LAN969X_PIN(21), ++ LAN969X_PIN(22), ++ LAN969X_PIN(23), ++ LAN969X_PIN(24), ++ LAN969X_PIN(25), ++ LAN969X_PIN(26), ++ LAN969X_PIN(27), ++ LAN969X_PIN(28), ++ LAN969X_PIN(29), ++ LAN969X_PIN(30), ++ LAN969X_PIN(31), ++ LAN969X_PIN(32), ++ LAN969X_PIN(33), ++ LAN969X_PIN(34), ++ LAN969X_PIN(35), ++ LAN969X_PIN(36), ++ LAN969X_PIN(37), ++ LAN969X_PIN(38), ++ LAN969X_PIN(39), ++ LAN969X_PIN(40), ++ LAN969X_PIN(41), ++ LAN969X_PIN(42), ++ LAN969X_PIN(43), ++ LAN969X_PIN(44), ++ LAN969X_PIN(45), ++ LAN969X_PIN(46), ++ LAN969X_PIN(47), ++ LAN969X_PIN(48), ++ LAN969X_PIN(49), ++ LAN969X_PIN(50), ++ LAN969X_PIN(51), ++ LAN969X_PIN(52), ++ LAN969X_PIN(53), ++ LAN969X_PIN(54), ++ LAN969X_PIN(55), ++ LAN969X_PIN(56), ++ LAN969X_PIN(57), ++ LAN969X_PIN(58), ++ LAN969X_PIN(59), ++ LAN969X_PIN(60), ++ LAN969X_PIN(61), ++ LAN969X_PIN(62), ++ LAN969X_PIN(63), ++ LAN969X_PIN(64), ++ LAN969X_PIN(65), ++ LAN969X_PIN(66), ++}; ++ + static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) + { + return ARRAY_SIZE(ocelot_function_names); +@@ -1682,6 +1867,23 @@ static struct ocelot_match_data lan966x_ + }, + }; + ++static struct ocelot_match_data lan969x_desc = { ++ .desc = { ++ .name = "lan969x-pinctrl", ++ .pins = lan969x_pins, ++ .npins = ARRAY_SIZE(lan969x_pins), ++ .pctlops = &ocelot_pctl_ops, ++ .pmxops = &lan966x_pmx_ops, ++ .confops = &ocelot_confops, ++ .owner = THIS_MODULE, ++ }, ++ .pincfg_data = { ++ .pd_bit = BIT(3), ++ .pu_bit = BIT(2), ++ .drive_bits = GENMASK(1, 0), ++ }, ++}; ++ + static int ocelot_create_group_func_map(struct device *dev, + struct ocelot_pinctrl *info) + { +@@ -2014,6 +2216,7 @@ static const struct of_device_id ocelot_ + { .compatible = "mscc,servalt-pinctrl", .data = &servalt_desc }, + { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, + { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, ++ { .compatible = "microchip,lan9691-pinctrl", .data = &lan969x_desc }, + {}, + }; + MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match); diff --git a/target/linux/microchipsw/patches-6.12/0004-v6.13-clk-lan966x-make-clk_names-const-char-const.patch b/target/linux/microchipsw/patches-6.12/0004-v6.13-clk-lan966x-make-clk_names-const-char-const.patch new file mode 100644 index 0000000000..f210904313 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0004-v6.13-clk-lan966x-make-clk_names-const-char-const.patch @@ -0,0 +1,26 @@ +From 60b15ad144394ef5da427160fd947af93affef72 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 16 Sep 2024 11:49:20 +0200 +Subject: [PATCH 04/25] clk: lan966x: make clk_names const char * const + +Change clk_names to const char * const to silence checkpatch in +subsequent patches. + +Signed-off-by: Daniel Machon +Link: https://lore.kernel.org/r/20240916-lan969x-clock-v1-2-0e150336074d@microchip.com +Signed-off-by: Claudiu Beznea +--- + drivers/clk/clk-lan966x.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/clk-lan966x.c ++++ b/drivers/clk/clk-lan966x.c +@@ -24,7 +24,7 @@ + + #define DIV_MAX 255 + +-static const char *clk_names[N_CLOCKS] = { ++static const char * const clk_names[N_CLOCKS] = { + "qspi0", "qspi1", "qspi2", "sdmmc0", + "pi", "mcan0", "mcan1", "flexcom0", + "flexcom1", "flexcom2", "flexcom3", diff --git a/target/linux/microchipsw/patches-6.12/0005-v6.13-clk-lan966x-prepare-driver-for-lan969x-support.patch b/target/linux/microchipsw/patches-6.12/0005-v6.13-clk-lan966x-prepare-driver-for-lan969x-support.patch new file mode 100644 index 0000000000..86c8504eff --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0005-v6.13-clk-lan966x-prepare-driver-for-lan969x-support.patch @@ -0,0 +1,151 @@ +From 471d54facf2a1ee5740839e7870873a3f5965911 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 16 Sep 2024 11:49:21 +0200 +Subject: [PATCH 05/25] clk: lan966x: prepare driver for lan969x support + +In preparation for lan969x support, add private match data for lan966x +and add variables for: peripheral clock names, clock gate names, number +of total clocks and number of generic clocks. Use the variables +throughout. + +Signed-off-by: Daniel Machon +Link: https://lore.kernel.org/r/20240916-lan969x-clock-v1-3-0e150336074d@microchip.com +[claudiu.beznea: in lan966x_clk_probe(): keep struct_size() arguments on + a single line] +Signed-off-by: Claudiu Beznea +--- + drivers/clk/clk-lan966x.c | 55 +++++++++++++++++++++++++++------------ + 1 file changed, 39 insertions(+), 16 deletions(-) + +--- a/drivers/clk/clk-lan966x.c ++++ b/drivers/clk/clk-lan966x.c +@@ -24,7 +24,7 @@ + + #define DIV_MAX 255 + +-static const char * const clk_names[N_CLOCKS] = { ++static const char * const lan966x_clk_names[] = { + "qspi0", "qspi1", "qspi2", "sdmmc0", + "pi", "mcan0", "mcan1", "flexcom0", + "flexcom1", "flexcom2", "flexcom3", +@@ -53,7 +53,7 @@ struct clk_gate_soc_desc { + int bit_idx; + }; + +-static const struct clk_gate_soc_desc clk_gate_desc[] = { ++static const struct clk_gate_soc_desc lan966x_clk_gate_desc[] = { + { "uhphs", 11 }, + { "udphs", 10 }, + { "mcramc", 9 }, +@@ -61,6 +61,22 @@ static const struct clk_gate_soc_desc cl + { } + }; + ++struct lan966x_match_data { ++ char *name; ++ const char * const *clk_name; ++ const struct clk_gate_soc_desc *clk_gate_desc; ++ u8 num_generic_clks; ++ u8 num_total_clks; ++}; ++ ++static struct lan966x_match_data lan966x_desc = { ++ .name = "lan966x", ++ .clk_name = lan966x_clk_names, ++ .clk_gate_desc = lan966x_clk_gate_desc, ++ .num_total_clks = 18, ++ .num_generic_clks = 14, ++}; ++ + static DEFINE_SPINLOCK(clk_gate_lock); + static void __iomem *base; + +@@ -186,24 +202,26 @@ static struct clk_hw *lan966x_gck_clk_re + }; + + static int lan966x_gate_clk_register(struct device *dev, ++ const struct lan966x_match_data *data, + struct clk_hw_onecell_data *hw_data, + void __iomem *gate_base) + { +- int i; ++ for (int i = data->num_generic_clks; i < data->num_total_clks; ++i) { ++ int idx = i - data->num_generic_clks; ++ const struct clk_gate_soc_desc *desc; + +- for (i = GCK_GATE_UHPHS; i < N_CLOCKS; ++i) { +- int idx = i - GCK_GATE_UHPHS; ++ desc = &data->clk_gate_desc[idx]; + + hw_data->hws[i] = +- devm_clk_hw_register_gate(dev, clk_gate_desc[idx].name, +- "lan966x", 0, gate_base, +- clk_gate_desc[idx].bit_idx, ++ devm_clk_hw_register_gate(dev, desc->name, ++ data->name, 0, gate_base, ++ desc->bit_idx, + 0, &clk_gate_lock); + + if (IS_ERR(hw_data->hws[i])) + return dev_err_probe(dev, PTR_ERR(hw_data->hws[i]), + "failed to register %s clock\n", +- clk_gate_desc[idx].name); ++ desc->name); + } + + return 0; +@@ -211,13 +229,18 @@ static int lan966x_gate_clk_register(str + + static int lan966x_clk_probe(struct platform_device *pdev) + { ++ const struct lan966x_match_data *data; + struct clk_hw_onecell_data *hw_data; + struct device *dev = &pdev->dev; + void __iomem *gate_base; + struct resource *res; + int i, ret; + +- hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, N_CLOCKS), ++ data = device_get_match_data(dev); ++ if (!data) ++ return -EINVAL; ++ ++ hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, data->num_total_clks), + GFP_KERNEL); + if (!hw_data) + return -ENOMEM; +@@ -228,10 +251,10 @@ static int lan966x_clk_probe(struct plat + + init.ops = &lan966x_gck_ops; + +- hw_data->num = GCK_GATE_UHPHS; ++ hw_data->num = data->num_generic_clks; + +- for (i = 0; i < GCK_GATE_UHPHS; i++) { +- init.name = clk_names[i]; ++ for (i = 0; i < data->num_generic_clks; i++) { ++ init.name = data->clk_name[i]; + hw_data->hws[i] = lan966x_gck_clk_register(dev, i); + if (IS_ERR(hw_data->hws[i])) { + dev_err(dev, "failed to register %s clock\n", +@@ -246,9 +269,9 @@ static int lan966x_clk_probe(struct plat + if (IS_ERR(gate_base)) + return PTR_ERR(gate_base); + +- hw_data->num = N_CLOCKS; ++ hw_data->num = data->num_total_clks; + +- ret = lan966x_gate_clk_register(dev, hw_data, gate_base); ++ ret = lan966x_gate_clk_register(dev, data, hw_data, gate_base); + if (ret) + return ret; + } +@@ -257,7 +280,7 @@ static int lan966x_clk_probe(struct plat + } + + static const struct of_device_id lan966x_clk_dt_ids[] = { +- { .compatible = "microchip,lan966x-gck", }, ++ { .compatible = "microchip,lan966x-gck", .data = &lan966x_desc }, + { } + }; + MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids); diff --git a/target/linux/microchipsw/patches-6.12/0006-v6.13-clk-lan966x-add-support-for-lan969x-SoC-clock-driver.patch b/target/linux/microchipsw/patches-6.12/0006-v6.13-clk-lan966x-add-support-for-lan969x-SoC-clock-driver.patch new file mode 100644 index 0000000000..be6188584f --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0006-v6.13-clk-lan966x-add-support-for-lan969x-SoC-clock-driver.patch @@ -0,0 +1,70 @@ +From 5b89e2d7ec7afd2e2d92f90f90f232e17d70cfc0 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 16 Sep 2024 11:49:22 +0200 +Subject: [PATCH 06/25] clk: lan966x: add support for lan969x SoC clock driver + +Add support for the lan969x SoC clock driver in the existing lan966x +driver. The lan969x clock controller contains 3 PLLs - cpu_clk, ddr_clk +and sys_clk (same as lan966x) which generates and supplies the clock to +various peripherals within the SoC. + +Signed-off-by: Daniel Machon +Link: https://lore.kernel.org/r/20240916-lan969x-clock-v1-4-0e150336074d@microchip.com +Signed-off-by: Claudiu Beznea +--- + drivers/clk/clk-lan966x.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/drivers/clk/clk-lan966x.c ++++ b/drivers/clk/clk-lan966x.c +@@ -31,6 +31,13 @@ static const char * const lan966x_clk_na + "flexcom4", "timer1", "usb_refclk", + }; + ++static const char * const lan969x_clk_names[] = { ++ "qspi0", "qspi2", "sdmmc0", "sdmmc1", ++ "mcan0", "mcan1", "flexcom0", ++ "flexcom1", "flexcom2", "flexcom3", ++ "timer1", "usb_refclk", ++}; ++ + struct lan966x_gck { + struct clk_hw hw; + void __iomem *reg; +@@ -61,6 +68,13 @@ static const struct clk_gate_soc_desc la + { } + }; + ++static const struct clk_gate_soc_desc lan969x_clk_gate_desc[] = { ++ { "usb_drd", 10 }, ++ { "mcramc", 9 }, ++ { "hmatrix", 8 }, ++ { } ++}; ++ + struct lan966x_match_data { + char *name; + const char * const *clk_name; +@@ -77,6 +91,14 @@ static struct lan966x_match_data lan966x + .num_generic_clks = 14, + }; + ++static struct lan966x_match_data lan969x_desc = { ++ .name = "lan969x", ++ .clk_name = lan969x_clk_names, ++ .clk_gate_desc = lan969x_clk_gate_desc, ++ .num_total_clks = 15, ++ .num_generic_clks = 12, ++}; ++ + static DEFINE_SPINLOCK(clk_gate_lock); + static void __iomem *base; + +@@ -281,6 +303,7 @@ static int lan966x_clk_probe(struct plat + + static const struct of_device_id lan966x_clk_dt_ids[] = { + { .compatible = "microchip,lan966x-gck", .data = &lan966x_desc }, ++ { .compatible = "microchip,lan9691-gck", .data = &lan969x_desc }, + { } + }; + MODULE_DEVICE_TABLE(of, lan966x_clk_dt_ids); diff --git a/target/linux/microchipsw/patches-6.12/0007-v6.13-phy-sparx5-serdes-add-support-for-private-match-data.patch b/target/linux/microchipsw/patches-6.12/0007-v6.13-phy-sparx5-serdes-add-support-for-private-match-data.patch new file mode 100644 index 0000000000..4e15737ef6 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0007-v6.13-phy-sparx5-serdes-add-support-for-private-match-data.patch @@ -0,0 +1,84 @@ +From 6c18e8aba5313a930a72c5b2143e73e2cc437a14 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 9 Sep 2024 17:14:41 +0200 +Subject: [PATCH 08/25] phy: sparx5-serdes: add support for private match data + +In order to reuse the existing Sparx5 SERDES driver for lan969x, we add +support for private match data, with initial fields for the iomap and +imap_size. + +Signed-off-by: Daniel Machon +Reviewed-by: Steen Hegelund +Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-1-d695bcb57b84@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/phy/microchip/sparx5_serdes.c | 16 +++++++++++++--- + drivers/phy/microchip/sparx5_serdes.h | 6 ++++++ + 2 files changed, 19 insertions(+), 3 deletions(-) + +--- a/drivers/phy/microchip/sparx5_serdes.c ++++ b/drivers/phy/microchip/sparx5_serdes.c +@@ -2507,6 +2507,11 @@ static struct sparx5_serdes_io_resource + { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */ + }; + ++static const struct sparx5_serdes_match_data sparx5_desc = { ++ .iomap = sparx5_serdes_iomap, ++ .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), ++}; ++ + /* Client lookup function, uses serdes index */ + static struct phy *sparx5_serdes_xlate(struct device *dev, + const struct of_phandle_args *args) +@@ -2555,6 +2560,10 @@ static int sparx5_serdes_probe(struct pl + platform_set_drvdata(pdev, priv); + priv->dev = &pdev->dev; + ++ priv->data = device_get_match_data(priv->dev); ++ if (!priv->data) ++ return -EINVAL; ++ + /* Get coreclock */ + clk = devm_clk_get(priv->dev, NULL); + if (IS_ERR(clk)) { +@@ -2579,8 +2588,9 @@ static int sparx5_serdes_probe(struct pl + iores->name); + return -ENOMEM; + } +- for (idx = 0; idx < ARRAY_SIZE(sparx5_serdes_iomap); idx++) { +- struct sparx5_serdes_io_resource *iomap = &sparx5_serdes_iomap[idx]; ++ for (idx = 0; idx < priv->data->iomap_size; idx++) { ++ const struct sparx5_serdes_io_resource *iomap = ++ &priv->data->iomap[idx]; + + priv->regs[iomap->id] = iomem + iomap->offset; + } +@@ -2599,7 +2609,7 @@ static int sparx5_serdes_probe(struct pl + } + + static const struct of_device_id sparx5_serdes_match[] = { +- { .compatible = "microchip,sparx5-serdes" }, ++ { .compatible = "microchip,sparx5-serdes", .data = &sparx5_desc }, + { } + }; + MODULE_DEVICE_TABLE(of, sparx5_serdes_match); +--- a/drivers/phy/microchip/sparx5_serdes.h ++++ b/drivers/phy/microchip/sparx5_serdes.h +@@ -26,11 +26,17 @@ enum sparx5_serdes_mode { + SPX5_SD_MODE_SFI, + }; + ++struct sparx5_serdes_match_data { ++ const struct sparx5_serdes_io_resource *iomap; ++ int iomap_size; ++}; ++ + struct sparx5_serdes_private { + struct device *dev; + void __iomem *regs[NUM_TARGETS]; + struct phy *phys[SPX5_SERDES_MAX]; + unsigned long coreclock; ++ const struct sparx5_serdes_match_data *data; + }; + + struct sparx5_serdes_macro { diff --git a/target/linux/microchipsw/patches-6.12/0008-v6.13-phy-sparx5-serdes-add-constants-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0008-v6.13-phy-sparx5-serdes-add-constants-to-match-data.patch new file mode 100644 index 0000000000..18f97bc4bd --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0008-v6.13-phy-sparx5-serdes-add-constants-to-match-data.patch @@ -0,0 +1,63 @@ +From 484f940614857bfb2766c6a0dadd6f77485ba992 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 9 Sep 2024 17:14:42 +0200 +Subject: [PATCH 09/25] phy: sparx5-serdes: add constants to match data + +We need to handle a few different constants that differ for Sparx5 and +lan969x. Add a new struct: sparx5_serdes_consts for this purpose. We +populate it with an initial field for the number of SERDES'es: sd_max. + +Signed-off-by: Daniel Machon +Reviewed-by: Steen Hegelund +Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-2-d695bcb57b84@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/phy/microchip/sparx5_serdes.c | 7 +++++-- + drivers/phy/microchip/sparx5_serdes.h | 5 +++++ + 2 files changed, 10 insertions(+), 2 deletions(-) + +--- a/drivers/phy/microchip/sparx5_serdes.c ++++ b/drivers/phy/microchip/sparx5_serdes.c +@@ -2510,6 +2510,9 @@ static struct sparx5_serdes_io_resource + static const struct sparx5_serdes_match_data sparx5_desc = { + .iomap = sparx5_serdes_iomap, + .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), ++ .consts = { ++ .sd_max = 33, ++ }, + }; + + /* Client lookup function, uses serdes index */ +@@ -2526,7 +2529,7 @@ static struct phy *sparx5_serdes_xlate(s + sidx = args->args[0]; + + /* Check validity: ERR_PTR(-ENODEV) if not valid */ +- for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { ++ for (idx = 0; idx < priv->data->consts.sd_max; idx++) { + struct sparx5_serdes_macro *macro = + phy_get_drvdata(priv->phys[idx]); + +@@ -2594,7 +2597,7 @@ static int sparx5_serdes_probe(struct pl + + priv->regs[iomap->id] = iomem + iomap->offset; + } +- for (idx = 0; idx < SPX5_SERDES_MAX; idx++) { ++ for (idx = 0; idx < priv->data->consts.sd_max; idx++) { + err = sparx5_phy_create(priv, idx, &priv->phys[idx]); + if (err) + return err; +--- a/drivers/phy/microchip/sparx5_serdes.h ++++ b/drivers/phy/microchip/sparx5_serdes.h +@@ -26,7 +26,12 @@ enum sparx5_serdes_mode { + SPX5_SD_MODE_SFI, + }; + ++struct sparx5_serdes_consts { ++ int sd_max; ++}; ++ + struct sparx5_serdes_match_data { ++ const struct sparx5_serdes_consts consts; + const struct sparx5_serdes_io_resource *iomap; + int iomap_size; + }; diff --git a/target/linux/microchipsw/patches-6.12/0009-v6.13-phy-sparx5-serdes-add-constant-for-the-number-of-CMU.patch b/target/linux/microchipsw/patches-6.12/0009-v6.13-phy-sparx5-serdes-add-constant-for-the-number-of-CMU.patch new file mode 100644 index 0000000000..ad4a3afc40 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0009-v6.13-phy-sparx5-serdes-add-constant-for-the-number-of-CMU.patch @@ -0,0 +1,56 @@ +From 25fec35ac0e5bf3f9da0920055c278bb170983d2 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 9 Sep 2024 17:14:43 +0200 +Subject: [PATCH 10/25] phy: sparx5-serdes: add constant for the number of + CMU's + +The number of CMU's differ for Sparx5 and lan969x, so add a new field: +cmu_max and use it throughout. + +Signed-off-by: Daniel Machon +Reviewed-by: Steen Hegelund +Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-3-d695bcb57b84@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/phy/microchip/sparx5_serdes.c | 5 ++--- + drivers/phy/microchip/sparx5_serdes.h | 1 + + 2 files changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/phy/microchip/sparx5_serdes.c ++++ b/drivers/phy/microchip/sparx5_serdes.c +@@ -21,8 +21,6 @@ + + #include "sparx5_serdes.h" + +-#define SPX5_CMU_MAX 14 +- + #define SPX5_SERDES_10G_START 13 + #define SPX5_SERDES_25G_START 25 + #define SPX5_SERDES_6G10G_CNT SPX5_SERDES_25G_START +@@ -1101,7 +1099,7 @@ static void sparx5_serdes_cmu_power_off( + int i; + + /* Power down each CMU */ +- for (i = 0; i < SPX5_CMU_MAX; i++) { ++ for (i = 0; i < priv->data->consts.cmu_max; i++) { + cmu_inst = sdx5_inst_get(priv, TARGET_SD_CMU, i); + cmu_cfg_inst = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, i); + +@@ -2512,6 +2510,7 @@ static const struct sparx5_serdes_match_ + .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), + .consts = { + .sd_max = 33, ++ .cmu_max = 14, + }, + }; + +--- a/drivers/phy/microchip/sparx5_serdes.h ++++ b/drivers/phy/microchip/sparx5_serdes.h +@@ -28,6 +28,7 @@ enum sparx5_serdes_mode { + + struct sparx5_serdes_consts { + int sd_max; ++ int cmu_max; + }; + + struct sparx5_serdes_match_data { diff --git a/target/linux/microchipsw/patches-6.12/0010-v6.13-phy-sparx5-serdes-add-ops-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0010-v6.13-phy-sparx5-serdes-add-ops-to-match-data.patch new file mode 100644 index 0000000000..151710ad27 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0010-v6.13-phy-sparx5-serdes-add-ops-to-match-data.patch @@ -0,0 +1,120 @@ +From 06d4a10a636ef4c97680007abb4625b9eebbf169 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 9 Sep 2024 17:14:44 +0200 +Subject: [PATCH 11/25] phy: sparx5-serdes: add ops to match data + +We need to handle code differently in a few places. Add a struct: +sparx5_serdes_ops for this purpose, and populate it a with function to +set the SERDES type. + +Signed-off-by: Daniel Machon +Reviewed-by: Steen Hegelund +Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-4-d695bcb57b84@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/phy/microchip/sparx5_serdes.c | 29 ++++++++++++++++++--------- + drivers/phy/microchip/sparx5_serdes.h | 27 +++++++++++++++---------- + 2 files changed, 35 insertions(+), 21 deletions(-) + +--- a/drivers/phy/microchip/sparx5_serdes.c ++++ b/drivers/phy/microchip/sparx5_serdes.c +@@ -2373,6 +2373,20 @@ static const struct phy_ops sparx5_serde + .owner = THIS_MODULE, + }; + ++static void sparx5_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx) ++{ ++ if (sidx < SPX5_SERDES_10G_START) { ++ macro->serdestype = SPX5_SDT_6G; ++ macro->stpidx = macro->sidx; ++ } else if (sidx < SPX5_SERDES_25G_START) { ++ macro->serdestype = SPX5_SDT_10G; ++ macro->stpidx = macro->sidx - SPX5_SERDES_10G_START; ++ } else { ++ macro->serdestype = SPX5_SDT_25G; ++ macro->stpidx = macro->sidx - SPX5_SERDES_25G_START; ++ } ++} ++ + static int sparx5_phy_create(struct sparx5_serdes_private *priv, + int idx, struct phy **phy) + { +@@ -2389,16 +2403,8 @@ static int sparx5_phy_create(struct spar + macro->sidx = idx; + macro->priv = priv; + macro->speed = SPEED_UNKNOWN; +- if (idx < SPX5_SERDES_10G_START) { +- macro->serdestype = SPX5_SDT_6G; +- macro->stpidx = macro->sidx; +- } else if (idx < SPX5_SERDES_25G_START) { +- macro->serdestype = SPX5_SDT_10G; +- macro->stpidx = macro->sidx - SPX5_SERDES_10G_START; +- } else { +- macro->serdestype = SPX5_SDT_25G; +- macro->stpidx = macro->sidx - SPX5_SERDES_25G_START; +- } ++ ++ priv->data->ops.serdes_type_set(macro, idx); + + phy_set_drvdata(*phy, macro); + +@@ -2512,6 +2518,9 @@ static const struct sparx5_serdes_match_ + .sd_max = 33, + .cmu_max = 14, + }, ++ .ops = { ++ .serdes_type_set = &sparx5_serdes_type_set, ++ }, + }; + + /* Client lookup function, uses serdes index */ +--- a/drivers/phy/microchip/sparx5_serdes.h ++++ b/drivers/phy/microchip/sparx5_serdes.h +@@ -26,13 +26,29 @@ enum sparx5_serdes_mode { + SPX5_SD_MODE_SFI, + }; + ++struct sparx5_serdes_macro { ++ struct sparx5_serdes_private *priv; ++ u32 sidx; ++ u32 stpidx; ++ enum sparx5_serdes_type serdestype; ++ enum sparx5_serdes_mode serdesmode; ++ phy_interface_t portmode; ++ int speed; ++ enum phy_media media; ++}; ++ + struct sparx5_serdes_consts { + int sd_max; + int cmu_max; + }; + ++struct sparx5_serdes_ops { ++ void (*serdes_type_set)(struct sparx5_serdes_macro *macro, int sidx); ++}; ++ + struct sparx5_serdes_match_data { + const struct sparx5_serdes_consts consts; ++ const struct sparx5_serdes_ops ops; + const struct sparx5_serdes_io_resource *iomap; + int iomap_size; + }; +@@ -45,17 +61,6 @@ struct sparx5_serdes_private { + const struct sparx5_serdes_match_data *data; + }; + +-struct sparx5_serdes_macro { +- struct sparx5_serdes_private *priv; +- u32 sidx; +- u32 stpidx; +- enum sparx5_serdes_type serdestype; +- enum sparx5_serdes_mode serdesmode; +- phy_interface_t portmode; +- int speed; +- enum phy_media media; +-}; +- + /* Read, Write and modify registers content. + * The register definition macros start at the id + */ diff --git a/target/linux/microchipsw/patches-6.12/0011-v6.13-phy-sparx5-serdes-add-function-for-getting-the-CMU-i.patch b/target/linux/microchipsw/patches-6.12/0011-v6.13-phy-sparx5-serdes-add-function-for-getting-the-CMU-i.patch new file mode 100644 index 0000000000..4807ba8b0b --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0011-v6.13-phy-sparx5-serdes-add-function-for-getting-the-CMU-i.patch @@ -0,0 +1,77 @@ +From e072ab8d032cd89a6c5333652c2ea909a8942b8a Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 9 Sep 2024 17:14:45 +0200 +Subject: [PATCH 12/25] phy: sparx5-serdes: add function for getting the CMU + index + +The SERDES to CMU mapping is different on Sparx5 and lan969x. Therefore +create a function for getting the CMU index on Sparx5. + +Signed-off-by: Daniel Machon +Reviewed-by: Steen Hegelund +Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-5-d695bcb57b84@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/phy/microchip/sparx5_serdes.c | 11 ++--------- + drivers/phy/microchip/sparx5_serdes.h | 9 +++++++++ + 2 files changed, 11 insertions(+), 9 deletions(-) + +--- a/drivers/phy/microchip/sparx5_serdes.c ++++ b/drivers/phy/microchip/sparx5_serdes.c +@@ -28,14 +28,6 @@ + /* Optimal power settings from GUC */ + #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c + +-enum sparx5_10g28cmu_mode { +- SPX5_SD10G28_CMU_MAIN = 0, +- SPX5_SD10G28_CMU_AUX1 = 1, +- SPX5_SD10G28_CMU_AUX2 = 3, +- SPX5_SD10G28_CMU_NONE = 4, +- SPX5_SD10G28_CMU_MAX, +-}; +- + enum sparx5_sd25g28_mode_preset_type { + SPX5_SD25G28_MODE_PRESET_25000, + SPX5_SD25G28_MODE_PRESET_10000, +@@ -1648,7 +1640,7 @@ static int sparx5_sd10g28_apply_params(s + if (params->skip_cmu_cfg) + return 0; + +- cmu_idx = sparx5_serdes_cmu_get(params->cmu_sel, lane_index); ++ cmu_idx = priv->data->ops.serdes_cmu_get(params->cmu_sel, macro->sidx); + err = sparx5_cmu_cfg(priv, cmu_idx); + if (err) + return err; +@@ -2520,6 +2512,7 @@ static const struct sparx5_serdes_match_ + }, + .ops = { + .serdes_type_set = &sparx5_serdes_type_set, ++ .serdes_cmu_get = &sparx5_serdes_cmu_get, + }, + }; + +--- a/drivers/phy/microchip/sparx5_serdes.h ++++ b/drivers/phy/microchip/sparx5_serdes.h +@@ -26,6 +26,14 @@ enum sparx5_serdes_mode { + SPX5_SD_MODE_SFI, + }; + ++enum sparx5_10g28cmu_mode { ++ SPX5_SD10G28_CMU_MAIN = 0, ++ SPX5_SD10G28_CMU_AUX1 = 1, ++ SPX5_SD10G28_CMU_AUX2 = 3, ++ SPX5_SD10G28_CMU_NONE = 4, ++ SPX5_SD10G28_CMU_MAX, ++}; ++ + struct sparx5_serdes_macro { + struct sparx5_serdes_private *priv; + u32 sidx; +@@ -44,6 +52,7 @@ struct sparx5_serdes_consts { + + struct sparx5_serdes_ops { + void (*serdes_type_set)(struct sparx5_serdes_macro *macro, int sidx); ++ int (*serdes_cmu_get)(enum sparx5_10g28cmu_mode mode, int sd_index); + }; + + struct sparx5_serdes_match_data { diff --git a/target/linux/microchipsw/patches-6.12/0012-v6.13-phy-sparx5-serdes-add-indirection-layer-to-register-.patch b/target/linux/microchipsw/patches-6.12/0012-v6.13-phy-sparx5-serdes-add-indirection-layer-to-register-.patch new file mode 100644 index 0000000000..d78fd26fac --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0012-v6.13-phy-sparx5-serdes-add-indirection-layer-to-register-.patch @@ -0,0 +1,1708 @@ +From e85358f6566d31441f580c33b6acde6a70589959 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 9 Sep 2024 17:14:46 +0200 +Subject: [PATCH 13/25] phy: sparx5-serdes: add indirection layer to register + macros + +The register macros are used to read and write to the SERDES registers. +The registers are largely the same on Sparx5 and lan969x, however some +register target sizes differ. Therefore we introduce a new indirection +to the register macros. The target sizes are looked up, using a mapping +table (sparx5_serdes_tsize) that maps the register target to the +register target size. + +With this addition, we can reuse all the existing macros for lan969x. + +Also the autogenerated macros are now formatted slightly different, to +adhere to a 80 character limit. + +Signed-off-by: Daniel Machon +Reviewed-by: Steen Hegelund +Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-6-d695bcb57b84@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/phy/microchip/sparx5_serdes.c | 14 + + drivers/phy/microchip/sparx5_serdes.h | 1 + + drivers/phy/microchip/sparx5_serdes_regs.h | 746 ++++++++++++++------- + 3 files changed, 507 insertions(+), 254 deletions(-) + +--- a/drivers/phy/microchip/sparx5_serdes.c ++++ b/drivers/phy/microchip/sparx5_serdes.c +@@ -28,6 +28,17 @@ + /* Optimal power settings from GUC */ + #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c + ++/* Register target sizes */ ++const unsigned int sparx5_serdes_tsize[TSIZE_LAST] = { ++ [TC_SD10G_LANE] = 12, ++ [TC_SD_CMU] = 14, ++ [TC_SD_CMU_CFG] = 14, ++ [TC_SD_LANE] = 25, ++}; ++ ++/* Pointer to the register target size table */ ++const unsigned int *tsize; ++ + enum sparx5_sd25g28_mode_preset_type { + SPX5_SD25G28_MODE_PRESET_25000, + SPX5_SD25G28_MODE_PRESET_10000, +@@ -2506,6 +2517,7 @@ static struct sparx5_serdes_io_resource + static const struct sparx5_serdes_match_data sparx5_desc = { + .iomap = sparx5_serdes_iomap, + .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), ++ .tsize = sparx5_serdes_tsize, + .consts = { + .sd_max = 33, + .cmu_max = 14, +@@ -2568,6 +2580,8 @@ static int sparx5_serdes_probe(struct pl + if (!priv->data) + return -EINVAL; + ++ tsize = priv->data->tsize; ++ + /* Get coreclock */ + clk = devm_clk_get(priv->dev, NULL); + if (IS_ERR(clk)) { +--- a/drivers/phy/microchip/sparx5_serdes.h ++++ b/drivers/phy/microchip/sparx5_serdes.h +@@ -60,6 +60,7 @@ struct sparx5_serdes_match_data { + const struct sparx5_serdes_ops ops; + const struct sparx5_serdes_io_resource *iomap; + int iomap_size; ++ const unsigned int *tsize; + }; + + struct sparx5_serdes_private { +--- a/drivers/phy/microchip/sparx5_serdes_regs.h ++++ b/drivers/phy/microchip/sparx5_serdes_regs.h +@@ -1,11 +1,11 @@ + /* SPDX-License-Identifier: GPL-2.0+ + * Microchip Sparx5 SerDes driver + * +- * Copyright (c) 2020 Microchip Technology Inc. ++ * Copyright (c) 2024 Microchip Technology Inc. + */ + +-/* This file is autogenerated by cml-utils 2020-11-16 13:11:27 +0100. +- * Commit ID: 13bdf073131d8bf40c54901df6988ae4e9c8f29f ++/* This file is autogenerated by cml-utils 2023-04-13 15:02:00 +0200. ++ * Commit ID: 5ac560288d46048f872ecdb8add53717f1efc0e1 + */ + + #ifndef _SPARX5_SERDES_REGS_H_ +@@ -26,10 +26,25 @@ enum sparx5_serdes_target { + NUM_TARGETS = 332 + }; + ++enum sparx5_serdes_tsize_enum { ++ TC_SD10G_LANE, ++ TC_SD_CMU, ++ TC_SD_CMU_CFG, ++ TC_SD_LANE, ++ TSIZE_LAST, ++}; ++ ++/* sparx5_serdes.c */ ++extern const unsigned int *tsize; ++ ++#define TSIZE(o) tsize[o] ++ + #define __REG(...) __VA_ARGS__ + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */ +-#define SD10G_LANE_LANE_01(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 4, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */ ++#define SD10G_LANE_LANE_01(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 4, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0) + #define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ +@@ -49,8 +64,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */ +-#define SD10G_LANE_LANE_02(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 8, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */ ++#define SD10G_LANE_LANE_02(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 8, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_02_CFG_EN_ADV BIT(0) + #define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\ +@@ -82,8 +99,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */ +-#define SD10G_LANE_LANE_03(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 12, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */ ++#define SD10G_LANE_LANE_03(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 12, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_03_CFG_TAP_MAIN BIT(0) + #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\ +@@ -91,8 +110,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */ +-#define SD10G_LANE_LANE_04(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 16, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */ ++#define SD10G_LANE_LANE_04(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 16, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0 GENMASK(4, 0) + #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\ +@@ -100,8 +121,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */ +-#define SD10G_LANE_LANE_06(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 24, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */ ++#define SD10G_LANE_LANE_06(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 24, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_06_CFG_PD_DRIVER BIT(0) + #define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\ +@@ -139,8 +162,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */ +-#define SD10G_LANE_LANE_0B(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 44, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */ ++#define SD10G_LANE_LANE_0B(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 44, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0 GENMASK(3, 0) + #define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\ +@@ -172,8 +197,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */ +-#define SD10G_LANE_LANE_0C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 48, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */ ++#define SD10G_LANE_LANE_0C(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 48, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE BIT(0) + #define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\ +@@ -223,8 +250,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */ +-#define SD10G_LANE_LANE_0D(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 52, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */ ++#define SD10G_LANE_LANE_0D(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 52, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0 GENMASK(1, 0) + #define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\ +@@ -238,8 +267,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */ +-#define SD10G_LANE_LANE_0E(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 56, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */ ++#define SD10G_LANE_LANE_0E(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 56, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 GENMASK(3, 0) + #define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\ +@@ -265,8 +296,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */ +-#define SD10G_LANE_LANE_0F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 60, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */ ++#define SD10G_LANE_LANE_0F(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 60, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0 GENMASK(7, 0) + #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\ +@@ -274,8 +307,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */ +-#define SD10G_LANE_LANE_13(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 76, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */ ++#define SD10G_LANE_LANE_13(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 76, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_13_CFG_DCDR_PD BIT(0) + #define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\ +@@ -295,8 +330,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */ +-#define SD10G_LANE_LANE_14(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 80, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */ ++#define SD10G_LANE_LANE_14(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 80, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0 GENMASK(7, 0) + #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\ +@@ -304,8 +341,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */ +-#define SD10G_LANE_LANE_15(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 84, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */ ++#define SD10G_LANE_LANE_15(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 84, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8 GENMASK(7, 0) + #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\ +@@ -313,8 +352,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */ +-#define SD10G_LANE_LANE_16(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 88, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */ ++#define SD10G_LANE_LANE_16(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 88, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16 GENMASK(7, 0) + #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\ +@@ -322,8 +363,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */ +-#define SD10G_LANE_LANE_1A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 104, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */ ++#define SD10G_LANE_LANE_1A(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 104, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN BIT(0) + #define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\ +@@ -355,8 +398,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */ +-#define SD10G_LANE_LANE_22(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 136, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */ ++#define SD10G_LANE_LANE_22(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 136, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1 GENMASK(4, 0) + #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\ +@@ -364,8 +409,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */ +-#define SD10G_LANE_LANE_23(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 140, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */ ++#define SD10G_LANE_LANE_23(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 140, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_23_CFG_DFE_PD BIT(0) + #define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\ +@@ -397,8 +444,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */ +-#define SD10G_LANE_LANE_24(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 144, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */ ++#define SD10G_LANE_LANE_24(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 144, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0 GENMASK(3, 0) + #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\ +@@ -412,8 +461,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */ +-#define SD10G_LANE_LANE_26(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 152, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */ ++#define SD10G_LANE_LANE_26(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 152, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0) + #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\ +@@ -421,8 +472,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */ +-#define SD10G_LANE_LANE_2F(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 188, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */ ++#define SD10G_LANE_LANE_2F(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 188, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0 GENMASK(2, 0) + #define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\ +@@ -436,8 +489,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */ +-#define SD10G_LANE_LANE_30(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 192, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */ ++#define SD10G_LANE_LANE_30(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 192, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_30_CFG_SUMMER_EN BIT(0) + #define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\ +@@ -451,8 +506,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */ +-#define SD10G_LANE_LANE_31(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 196, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */ ++#define SD10G_LANE_LANE_31(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 196, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_31_CFG_PI_RSTN BIT(0) + #define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\ +@@ -490,8 +547,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */ +-#define SD10G_LANE_LANE_32(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 200, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */ ++#define SD10G_LANE_LANE_32(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 200, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0) + #define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\ +@@ -505,8 +564,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */ +-#define SD10G_LANE_LANE_33(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 204, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */ ++#define SD10G_LANE_LANE_33(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 204, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0) + #define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ +@@ -520,8 +581,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */ +-#define SD10G_LANE_LANE_35(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 212, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */ ++#define SD10G_LANE_LANE_35(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 212, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0 GENMASK(1, 0) + #define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\ +@@ -535,8 +598,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */ +-#define SD10G_LANE_LANE_36(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 216, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */ ++#define SD10G_LANE_LANE_36(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 216, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0) + #define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\ +@@ -568,8 +633,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */ +-#define SD10G_LANE_LANE_37(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 220, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */ ++#define SD10G_LANE_LANE_37(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 220, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD BIT(0) + #define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\ +@@ -595,8 +662,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */ +-#define SD10G_LANE_LANE_39(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 228, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */ ++#define SD10G_LANE_LANE_39(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 228, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0 GENMASK(2, 0) + #define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\ +@@ -610,8 +679,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */ +-#define SD10G_LANE_LANE_3A(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 232, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */ ++#define SD10G_LANE_LANE_3A(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 232, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0 GENMASK(3, 0) + #define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\ +@@ -625,8 +696,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */ +-#define SD10G_LANE_LANE_3C(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 240, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */ ++#define SD10G_LANE_LANE_3C(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 240, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_3C_CFG_DIS_ACC BIT(0) + #define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\ +@@ -640,8 +713,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */ +-#define SD10G_LANE_LANE_40(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 256, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */ ++#define SD10G_LANE_LANE_40(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 256, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0 GENMASK(7, 0) + #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\ +@@ -649,8 +724,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */ +-#define SD10G_LANE_LANE_41(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 260, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */ ++#define SD10G_LANE_LANE_41(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 260, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0) + #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\ +@@ -658,8 +735,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */ +-#define SD10G_LANE_LANE_42(t) __REG(TARGET_SD10G_LANE, t, 12, 0, 0, 1, 288, 264, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */ ++#define SD10G_LANE_LANE_42(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 264, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0 GENMASK(2, 0) + #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\ +@@ -673,8 +752,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */ +-#define SD10G_LANE_LANE_48(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 0, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */ ++#define SD10G_LANE_LANE_48(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 0, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0 GENMASK(3, 0) + #define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\ +@@ -694,8 +775,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */ +-#define SD10G_LANE_LANE_50(t) __REG(TARGET_SD10G_LANE, t, 12, 288, 0, 1, 40, 32, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */ ++#define SD10G_LANE_LANE_50(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 32, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0 GENMASK(1, 0) + #define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\ +@@ -727,8 +810,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */ +-#define SD10G_LANE_LANE_52(t) __REG(TARGET_SD10G_LANE, t, 12, 328, 0, 1, 24, 0, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */ ++#define SD10G_LANE_LANE_52(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 328, 0, 1, 24, 0, 0, \ ++ 1, 4) + + #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0) + #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\ +@@ -736,8 +821,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */ +-#define SD10G_LANE_LANE_83(t) __REG(TARGET_SD10G_LANE, t, 12, 464, 0, 1, 112, 60, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */ ++#define SD10G_LANE_LANE_83(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 464, 0, 1, 112, 60, \ ++ 0, 1, 4) + + #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE BIT(0) + #define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\ +@@ -781,8 +868,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */ +-#define SD10G_LANE_LANE_93(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 12, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */ ++#define SD10G_LANE_LANE_93(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 12, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN BIT(0) + #define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\ +@@ -832,8 +921,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */ +-#define SD10G_LANE_LANE_94(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 16, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */ ++#define SD10G_LANE_LANE_94(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 16, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0 GENMASK(2, 0) + #define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\ +@@ -865,8 +956,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */ +-#define SD10G_LANE_LANE_9E(t) __REG(TARGET_SD10G_LANE, t, 12, 576, 0, 1, 64, 56, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */ ++#define SD10G_LANE_LANE_9E(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 56, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_9E_R_RXEQ_REG BIT(0) + #define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\ +@@ -886,8 +979,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */ +-#define SD10G_LANE_LANE_A1(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 4, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */ ++#define SD10G_LANE_LANE_A1(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 4, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0) + #define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\ +@@ -919,8 +1014,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */ +-#define SD10G_LANE_LANE_A2(t) __REG(TARGET_SD10G_LANE, t, 12, 640, 0, 1, 128, 8, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */ ++#define SD10G_LANE_LANE_A2(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 8, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0) + #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\ +@@ -928,8 +1025,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ +-#define SD10G_LANE_LANE_DF(t) __REG(TARGET_SD10G_LANE, t, 12, 832, 0, 1, 84, 60, 0, 1, 4) ++/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ ++#define SD10G_LANE_LANE_DF(t) \ ++ __REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 832, 0, 1, 84, 60, 0,\ ++ 1, 4) + + #define SD10G_LANE_LANE_DF_LOL_UDL BIT(0) + #define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\ +@@ -955,8 +1054,10 @@ enum sparx5_serdes_target { + #define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\ + FIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x) + +-/* SD25G_TARGET:CMU_GRP_0:CMU_09 */ +-#define SD25G_LANE_CMU_09(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_0:CMU_09 */ ++#define SD25G_LANE_CMU_09(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4) + + #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN BIT(0) + #define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\ +@@ -988,8 +1089,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x) + +-/* SD25G_TARGET:CMU_GRP_0:CMU_0B */ +-#define SD25G_LANE_CMU_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_0:CMU_0B */ ++#define SD25G_LANE_CMU_0B(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4) + + #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT BIT(0) + #define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\ +@@ -1039,8 +1142,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x) + +-/* SD25G_TARGET:CMU_GRP_0:CMU_0C */ +-#define SD25G_LANE_CMU_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_0:CMU_0C */ ++#define SD25G_LANE_CMU_0C(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4) + + #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET BIT(0) + #define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\ +@@ -1072,8 +1177,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x) + +-/* SD25G_TARGET:CMU_GRP_0:CMU_0D */ +-#define SD25G_LANE_CMU_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_0:CMU_0D */ ++#define SD25G_LANE_CMU_0D(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4) + + #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD BIT(0) + #define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\ +@@ -1105,8 +1212,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x) + +-/* SD25G_TARGET:CMU_GRP_0:CMU_0E */ +-#define SD25G_LANE_CMU_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_0:CMU_0E */ ++#define SD25G_LANE_CMU_0E(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4) + + #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0 GENMASK(3, 0) + #define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\ +@@ -1120,8 +1229,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x) + +-/* SD25G_TARGET:CMU_GRP_0:CMU_13 */ +-#define SD25G_LANE_CMU_13(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_0:CMU_13 */ ++#define SD25G_LANE_CMU_13(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4) + + #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0 GENMASK(3, 0) + #define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\ +@@ -1135,8 +1246,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x) + +-/* SD25G_TARGET:CMU_GRP_0:CMU_18 */ +-#define SD25G_LANE_CMU_18(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_0:CMU_18 */ ++#define SD25G_LANE_CMU_18(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4) + + #define SD25G_LANE_CMU_18_R_PLL_RSTN BIT(0) + #define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\ +@@ -1162,8 +1275,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x) + +-/* SD25G_TARGET:CMU_GRP_0:CMU_19 */ +-#define SD25G_LANE_CMU_19(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_0:CMU_19 */ ++#define SD25G_LANE_CMU_19(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4) + + #define SD25G_LANE_CMU_19_R_CK_RESETB BIT(0) + #define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\ +@@ -1177,8 +1292,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x) + +-/* SD25G_TARGET:CMU_GRP_0:CMU_1A */ +-#define SD25G_LANE_CMU_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_0:CMU_1A */ ++#define SD25G_LANE_CMU_1A(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4) + + #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0 GENMASK(2, 0) + #define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\ +@@ -1204,8 +1321,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x) + +-/* SD25G_TARGET:CMU_GRP_1:CMU_2A */ +-#define SD25G_LANE_CMU_2A(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_1:CMU_2A */ ++#define SD25G_LANE_CMU_2A(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4) + + #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0 GENMASK(1, 0) + #define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\ +@@ -1225,8 +1344,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x) + +-/* SD25G_TARGET:CMU_GRP_1:CMU_30 */ +-#define SD25G_LANE_CMU_30(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_1:CMU_30 */ ++#define SD25G_LANE_CMU_30(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4) + + #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0) + #define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\ +@@ -1240,8 +1361,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x) + +-/* SD25G_TARGET:CMU_GRP_1:CMU_31 */ +-#define SD25G_LANE_CMU_31(t) __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_1:CMU_31 */ ++#define SD25G_LANE_CMU_31(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4) + + #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0) + #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\ +@@ -1249,8 +1372,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x) + +-/* SD25G_TARGET:CMU_GRP_2:CMU_40 */ +-#define SD25G_LANE_CMU_40(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_2:CMU_40 */ ++#define SD25G_LANE_CMU_40(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4) + + #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL BIT(0) + #define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\ +@@ -1288,8 +1413,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x) + +-/* SD25G_TARGET:CMU_GRP_2:CMU_45 */ +-#define SD25G_LANE_CMU_45(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_2:CMU_45 */ ++#define SD25G_LANE_CMU_45(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4) + + #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0 GENMASK(7, 0) + #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\ +@@ -1297,8 +1424,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x) + +-/* SD25G_TARGET:CMU_GRP_2:CMU_46 */ +-#define SD25G_LANE_CMU_46(t) __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_2:CMU_46 */ ++#define SD25G_LANE_CMU_46(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4) + + #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0) + #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\ +@@ -1306,8 +1435,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x) + +-/* SD25G_TARGET:CMU_GRP_3:CMU_C0 */ +-#define SD25G_LANE_CMU_C0(t) __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_3:CMU_C0 */ ++#define SD25G_LANE_CMU_C0(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4) + + #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0 GENMASK(3, 0) + #define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\ +@@ -1321,8 +1452,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x) + +-/* SD25G_TARGET:CMU_GRP_4:CMU_FF */ +-#define SD25G_LANE_CMU_FF(t) __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:CMU_GRP_4:CMU_FF */ ++#define SD25G_LANE_CMU_FF(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4) + + #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX GENMASK(7, 0) + #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\ +@@ -1330,8 +1463,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\ + FIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_00 */ +-#define SD25G_LANE_LANE_00(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_00 */ ++#define SD25G_LANE_LANE_00(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4) + + #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0) + #define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\ +@@ -1345,8 +1480,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_01 */ +-#define SD25G_LANE_LANE_01(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_01 */ ++#define SD25G_LANE_LANE_01(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4) + + #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0) + #define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\ +@@ -1360,8 +1497,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_03 */ +-#define SD25G_LANE_LANE_03(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_03 */ ++#define SD25G_LANE_LANE_03(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4) + + #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0 GENMASK(4, 0) + #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\ +@@ -1369,8 +1508,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_04 */ +-#define SD25G_LANE_LANE_04(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_04 */ ++#define SD25G_LANE_LANE_04(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4) + + #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN BIT(0) + #define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\ +@@ -1408,8 +1549,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_05 */ +-#define SD25G_LANE_LANE_05(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_05 */ ++#define SD25G_LANE_LANE_05(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4) + + #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0 GENMASK(3, 0) + #define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\ +@@ -1423,8 +1566,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_06 */ +-#define SD25G_LANE_LANE_06(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_06 */ ++#define SD25G_LANE_LANE_06(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4) + + #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN BIT(0) + #define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\ +@@ -1438,8 +1583,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_07 */ +-#define SD25G_LANE_LANE_07(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_07 */ ++#define SD25G_LANE_LANE_07(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4) + + #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV BIT(0) + #define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\ +@@ -1459,8 +1606,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_09 */ +-#define SD25G_LANE_LANE_09(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_09 */ ++#define SD25G_LANE_LANE_09(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4) + + #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0) + #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\ +@@ -1468,8 +1617,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_0A */ +-#define SD25G_LANE_LANE_0A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_0A */ ++#define SD25G_LANE_LANE_0A(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4) + + #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0) + #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\ +@@ -1477,8 +1628,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_0B */ +-#define SD25G_LANE_LANE_0B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_0B */ ++#define SD25G_LANE_LANE_0B(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4) + + #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN BIT(0) + #define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\ +@@ -1498,8 +1651,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_0C */ +-#define SD25G_LANE_LANE_0C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_0C */ ++#define SD25G_LANE_LANE_0C(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4) + + #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0) + #define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\ +@@ -1519,8 +1674,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_0D */ +-#define SD25G_LANE_LANE_0D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_0D */ ++#define SD25G_LANE_LANE_0D(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4) + + #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0 GENMASK(2, 0) + #define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\ +@@ -1552,8 +1709,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_0E */ +-#define SD25G_LANE_LANE_0E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_0E */ ++#define SD25G_LANE_LANE_0E(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4) + + #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN BIT(0) + #define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\ +@@ -1579,8 +1738,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_0F */ +-#define SD25G_LANE_LANE_0F(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_0F */ ++#define SD25G_LANE_LANE_0F(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4) + + #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1 GENMASK(4, 0) + #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\ +@@ -1588,8 +1749,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_18 */ +-#define SD25G_LANE_LANE_18(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_18 */ ++#define SD25G_LANE_LANE_18(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4) + + #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN BIT(0) + #define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\ +@@ -1621,8 +1784,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_19 */ +-#define SD25G_LANE_LANE_19(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_19 */ ++#define SD25G_LANE_LANE_19(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4) + + #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD BIT(0) + #define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\ +@@ -1672,8 +1837,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_1A */ +-#define SD25G_LANE_LANE_1A(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_1A */ ++#define SD25G_LANE_LANE_1A(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4) + + #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN BIT(0) + #define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\ +@@ -1687,8 +1854,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_1B */ +-#define SD25G_LANE_LANE_1B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_1B */ ++#define SD25G_LANE_LANE_1B(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4) + + #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0 GENMASK(7, 0) + #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\ +@@ -1696,8 +1865,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_1C */ +-#define SD25G_LANE_LANE_1C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_1C */ ++#define SD25G_LANE_LANE_1C(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4) + + #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN BIT(0) + #define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\ +@@ -1723,8 +1894,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_1D */ +-#define SD25G_LANE_LANE_1D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_1D */ ++#define SD25G_LANE_LANE_1D(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4) + + #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR BIT(0) + #define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\ +@@ -1774,8 +1947,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_1E */ +-#define SD25G_LANE_LANE_1E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_1E */ ++#define SD25G_LANE_LANE_1E(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4) + + #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0 GENMASK(1, 0) + #define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\ +@@ -1807,8 +1982,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_21 */ +-#define SD25G_LANE_LANE_21(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_21 */ ++#define SD25G_LANE_LANE_21(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4) + + #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0) + #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\ +@@ -1816,8 +1993,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_22 */ +-#define SD25G_LANE_LANE_22(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_22 */ ++#define SD25G_LANE_LANE_22(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4) + + #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0 GENMASK(3, 0) + #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\ +@@ -1825,8 +2004,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_25 */ +-#define SD25G_LANE_LANE_25(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_25 */ ++#define SD25G_LANE_LANE_25(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4) + + #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0) + #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\ +@@ -1834,8 +2015,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_26 */ +-#define SD25G_LANE_LANE_26(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_26 */ ++#define SD25G_LANE_LANE_26(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4) + + #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0) + #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\ +@@ -1843,8 +2026,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_28 */ +-#define SD25G_LANE_LANE_28(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_28 */ ++#define SD25G_LANE_LANE_28(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4) + + #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN BIT(0) + #define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\ +@@ -1870,8 +2055,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_2B */ +-#define SD25G_LANE_LANE_2B(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_2B */ ++#define SD25G_LANE_LANE_2B(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4) + + #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0 GENMASK(3, 0) + #define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\ +@@ -1891,8 +2078,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_2C */ +-#define SD25G_LANE_LANE_2C(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_2C */ ++#define SD25G_LANE_LANE_2C(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4) + + #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0) + #define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\ +@@ -1906,8 +2095,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_2D */ +-#define SD25G_LANE_LANE_2D(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_2D */ ++#define SD25G_LANE_LANE_2D(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4) + + #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0 GENMASK(2, 0) + #define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\ +@@ -1921,8 +2112,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_2E */ +-#define SD25G_LANE_LANE_2E(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_2E */ ++#define SD25G_LANE_LANE_2E(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4) + + #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN BIT(0) + #define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\ +@@ -1972,8 +2165,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_40 */ +-#define SD25G_LANE_LANE_40(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_40 */ ++#define SD25G_LANE_LANE_40(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4) + + #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE BIT(0) + #define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\ +@@ -2017,8 +2212,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_42 */ +-#define SD25G_LANE_LANE_42(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_42 */ ++#define SD25G_LANE_LANE_42(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4) + + #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0) + #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\ +@@ -2026,8 +2223,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_43 */ +-#define SD25G_LANE_LANE_43(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_43 */ ++#define SD25G_LANE_LANE_43(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4) + + #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0) + #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\ +@@ -2035,8 +2234,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_44 */ +-#define SD25G_LANE_LANE_44(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_44 */ ++#define SD25G_LANE_LANE_44(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4) + + #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0) + #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\ +@@ -2044,8 +2245,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x) + +-/* SD25G_TARGET:LANE_GRP_0:LANE_45 */ +-#define SD25G_LANE_LANE_45(t) __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_0:LANE_45 */ ++#define SD25G_LANE_LANE_45(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4) + + #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0) + #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\ +@@ -2053,8 +2256,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x) + +-/* SD25G_TARGET:LANE_GRP_1:LANE_DE */ +-#define SD25G_LANE_LANE_DE(t) __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_TARGET:LANE_GRP_1:LANE_DE */ ++#define SD25G_LANE_LANE_DE(t) \ ++ __REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4) + + #define SD25G_LANE_LANE_DE_LN_LOL_UDL BIT(0) + #define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\ +@@ -2080,8 +2285,10 @@ enum sparx5_serdes_target { + #define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\ + FIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x) + +-/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ +-#define SD6G_LANE_LANE_DF(t) __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */ ++#define SD6G_LANE_LANE_DF(t) \ ++ __REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4) + + #define SD6G_LANE_LANE_DF_LOL_UDL BIT(0) + #define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\ +@@ -2107,8 +2314,9 @@ enum sparx5_serdes_target { + #define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\ + FIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */ +-#define SD_CMU_CMU_00(t) __REG(TARGET_SD_CMU, t, 14, 0, 0, 1, 20, 0, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */ ++#define SD_CMU_CMU_00(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 0, 0, 1, 20, 0, 0, 1, 4) + + #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE BIT(0) + #define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\ +@@ -2134,8 +2342,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\ + FIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */ +-#define SD_CMU_CMU_05(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 0, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */ ++#define SD_CMU_CMU_05(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 0, 0, 1, 4) + + #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN BIT(0) + #define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\ +@@ -2149,9 +2358,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\ + FIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */ +-#define SD_CMU_CMU_06(t) \ +- __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 4, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */ ++#define SD_CMU_CMU_06(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 4, 0, 1, 4) + + #define SD_CMU_CMU_06_CFG_DISLOS BIT(0) + #define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\ +@@ -2201,9 +2410,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\ + FIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */ +-#define SD_CMU_CMU_08(t) \ +- __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 12, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */ ++#define SD_CMU_CMU_08(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 12, 0, 1, 4) + + #define SD_CMU_CMU_08_CFG_VFILT2PAD BIT(0) + #define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\ +@@ -2235,8 +2444,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\ + FIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */ +-#define SD_CMU_CMU_09(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 16, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */ ++#define SD_CMU_CMU_09(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 16, 0, 1, 4) + + #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP BIT(0) + #define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\ +@@ -2262,8 +2472,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\ + FIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */ +-#define SD_CMU_CMU_0D(t) __REG(TARGET_SD_CMU, t, 14, 20, 0, 1, 72, 32, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */ ++#define SD_CMU_CMU_0D(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 32, 0, 1, 4) + + #define SD_CMU_CMU_0D_CFG_PD_DIV64 BIT(0) + #define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\ +@@ -2295,8 +2506,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\ + FIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */ +-#define SD_CMU_CMU_1B(t) __REG(TARGET_SD_CMU, t, 14, 104, 0, 1, 20, 4, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */ ++#define SD_CMU_CMU_1B(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 104, 0, 1, 20, 4, 0, 1, 4) + + #define SD_CMU_CMU_1B_CFG_RESERVE_7_0 GENMASK(7, 0) + #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\ +@@ -2304,8 +2516,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\ + FIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */ +-#define SD_CMU_CMU_1F(t) __REG(TARGET_SD_CMU, t, 14, 124, 0, 1, 68, 0, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */ ++#define SD_CMU_CMU_1F(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 124, 0, 1, 68, 0, 0, 1, 4) + + #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN BIT(0) + #define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\ +@@ -2331,8 +2544,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\ + FIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */ +-#define SD_CMU_CMU_30(t) __REG(TARGET_SD_CMU, t, 14, 192, 0, 1, 72, 0, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */ ++#define SD_CMU_CMU_30(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 192, 0, 1, 72, 0, 0, 1, 4) + + #define SD_CMU_CMU_30_R_PLL_DLOL_EN BIT(0) + #define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\ +@@ -2340,8 +2554,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\ + FIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */ +-#define SD_CMU_CMU_44(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 8, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */ ++#define SD_CMU_CMU_44(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 8, 0, 1, 4) + + #define SD_CMU_CMU_44_R_PLL_RSTN BIT(0) + #define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\ +@@ -2355,8 +2570,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\ + FIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */ +-#define SD_CMU_CMU_45(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 12, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */ ++#define SD_CMU_CMU_45(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 12, 0, 1, 4) + + #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL BIT(0) + #define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\ +@@ -2406,8 +2622,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\ + FIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */ +-#define SD_CMU_CMU_47(t) __REG(TARGET_SD_CMU, t, 14, 264, 0, 1, 632, 20, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */ ++#define SD_CMU_CMU_47(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 20, 0, 1, 4) + + #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0) + #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\ +@@ -2415,8 +2632,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\ + FIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x) + +-/* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */ +-#define SD_CMU_CMU_E0(t) __REG(TARGET_SD_CMU, t, 14, 896, 0, 1, 8, 0, 0, 1, 4) ++/* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */ ++#define SD_CMU_CMU_E0(t) \ ++ __REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 896, 0, 1, 8, 0, 0, 1, 4) + + #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0 GENMASK(3, 0) + #define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\ +@@ -2430,8 +2648,10 @@ enum sparx5_serdes_target { + #define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\ + FIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x) + +-/* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */ +-#define SD_CMU_CFG_SD_CMU_CFG(t) __REG(TARGET_SD_CMU_CFG, t, 14, 0, 0, 1, 8, 0, 0, 1, 4) ++/* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */ ++#define SD_CMU_CFG_SD_CMU_CFG(t) \ ++ __REG(TARGET_SD_CMU_CFG, t, TSIZE(TC_SD_CMU_CFG), 0, 0, 1, 8, 0, 0, 1, \ ++ 4) + + #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST BIT(0) + #define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\ +@@ -2445,8 +2665,9 @@ enum sparx5_serdes_target { + #define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\ + FIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x) + +-/* SD_LANE_TARGET:SD_RESET:SD_SER_RST */ +-#define SD_LANE_SD_SER_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 0, 0, 1, 4) ++/* SD_LANE_TARGET:SD_RESET:SD_SER_RST */ ++#define SD_LANE_SD_SER_RST(t) \ ++ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 0, 0, 1, 4) + + #define SD_LANE_SD_SER_RST_SER_RST BIT(0) + #define SD_LANE_SD_SER_RST_SER_RST_SET(x)\ +@@ -2454,8 +2675,9 @@ enum sparx5_serdes_target { + #define SD_LANE_SD_SER_RST_SER_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x) + +-/* SD_LANE_TARGET:SD_RESET:SD_DES_RST */ +-#define SD_LANE_SD_DES_RST(t) __REG(TARGET_SD_LANE, t, 25, 0, 0, 1, 8, 4, 0, 1, 4) ++/* SD_LANE_TARGET:SD_RESET:SD_DES_RST */ ++#define SD_LANE_SD_DES_RST(t) \ ++ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 4, 0, 1, 4) + + #define SD_LANE_SD_DES_RST_DES_RST BIT(0) + #define SD_LANE_SD_DES_RST_DES_RST_SET(x)\ +@@ -2463,8 +2685,9 @@ enum sparx5_serdes_target { + #define SD_LANE_SD_DES_RST_DES_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x) + +-/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ +-#define SD_LANE_SD_LANE_CFG(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 0, 0, 1, 4) ++/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ ++#define SD_LANE_SD_LANE_CFG(t) \ ++ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 0, 0, 1, 4) + + #define SD_LANE_SD_LANE_CFG_MACRO_RST BIT(0) + #define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\ +@@ -2508,8 +2731,9 @@ enum sparx5_serdes_target { + #define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x) + +-/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ +-#define SD_LANE_SD_LANE_STAT(t) __REG(TARGET_SD_LANE, t, 25, 8, 0, 1, 8, 4, 0, 1, 4) ++/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ ++#define SD_LANE_SD_LANE_STAT(t) \ ++ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 4, 0, 1, 4) + + #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE BIT(0) + #define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ +@@ -2529,9 +2753,9 @@ enum sparx5_serdes_target { + #define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\ + FIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x) + +-/* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ +-#define SD_LANE_QUIET_MODE_6G(t) \ +- __REG(TARGET_SD_LANE, t, 25, 24, 0, 1, 8, 4, 0, 1, 4) ++/* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ ++#define SD_LANE_QUIET_MODE_6G(t) \ ++ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 24, 0, 1, 8, 4, 0, 1, 4) + + #define SD_LANE_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0) + #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\ +@@ -2539,8 +2763,9 @@ enum sparx5_serdes_target { + #define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\ + FIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x) + +-/* SD_LANE_TARGET:CFG_STAT_FX100:MISC */ +-#define SD_LANE_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 0, 0, 1, 4) ++/* SD_LANE_TARGET:CFG_STAT_FX100:MISC */ ++#define SD_LANE_MISC(t) \ ++ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 0, 0, 1, 4) + + #define SD_LANE_MISC_SD_125_RST_DIS BIT(0) + #define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\ +@@ -2560,14 +2785,16 @@ enum sparx5_serdes_target { + #define SD_LANE_MISC_MUX_ENA_GET(x)\ + FIELD_GET(SD_LANE_MISC_MUX_ENA, x) + ++/* SPARX5 ONLY */ + #define SD_LANE_MISC_CORE_CLK_FREQ GENMASK(5, 4) + #define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\ + FIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x) + #define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\ + FIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x) + +-/* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */ +-#define SD_LANE_M_STAT_MISC(t) __REG(TARGET_SD_LANE, t, 25, 56, 0, 1, 56, 36, 0, 1, 4) ++/* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */ ++#define SD_LANE_M_STAT_MISC(t) \ ++ __REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 36, 0, 1, 4) + + #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0) + #define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\ +@@ -2581,8 +2808,10 @@ enum sparx5_serdes_target { + #define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\ + FIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x) + +-/* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */ +-#define SD_LANE_25G_SD_SER_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */ ++#define SD_LANE_25G_SD_SER_RST(t) \ ++ __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4) + + #define SD_LANE_25G_SD_SER_RST_SER_RST BIT(0) + #define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\ +@@ -2590,8 +2819,10 @@ enum sparx5_serdes_target { + #define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x) + +-/* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */ +-#define SD_LANE_25G_SD_DES_RST(t) __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */ ++#define SD_LANE_25G_SD_DES_RST(t) \ ++ __REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4) + + #define SD_LANE_25G_SD_DES_RST_DES_RST BIT(0) + #define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\ +@@ -2599,8 +2830,10 @@ enum sparx5_serdes_target { + #define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x) + +-/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ +-#define SD_LANE_25G_SD_LANE_CFG(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */ ++#define SD_LANE_25G_SD_LANE_CFG(t) \ ++ __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4) + + #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST BIT(0) + #define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\ +@@ -2698,8 +2931,10 @@ enum sparx5_serdes_target { + #define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x) + +-/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */ +-#define SD_LANE_25G_SD_LANE_CFG2(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */ ++#define SD_LANE_25G_SD_LANE_CFG2(t) \ ++ __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4) + + #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL GENMASK(2, 0) + #define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\ +@@ -2767,8 +3002,10 @@ enum sparx5_serdes_target { + #define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x) + +-/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ +-#define SD_LANE_25G_SD_LANE_STAT(t) __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */ ++#define SD_LANE_25G_SD_LANE_STAT(t) \ ++ __REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4) + + #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE BIT(0) + #define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\ +@@ -2788,8 +3025,9 @@ enum sparx5_serdes_target { + #define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\ + FIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x) + +-/* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ +-#define SD_LANE_25G_QUIET_MODE_6G(t) \ ++/* SPARX5 ONLY */ ++/* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */ ++#define SD_LANE_25G_QUIET_MODE_6G(t) \ + __REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4) + + #define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE GENMASK(24, 0) diff --git a/target/linux/microchipsw/patches-6.12/0013-v6.13-phy-sparx5-serdes-add-support-for-branching-on-chip-.patch b/target/linux/microchipsw/patches-6.12/0013-v6.13-phy-sparx5-serdes-add-support-for-branching-on-chip-.patch new file mode 100644 index 0000000000..daae2f40e1 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0013-v6.13-phy-sparx5-serdes-add-support-for-branching-on-chip-.patch @@ -0,0 +1,101 @@ +From db156d900072423be739b1aaaa68a712d3fcb8e4 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 9 Sep 2024 17:14:47 +0200 +Subject: [PATCH 14/25] phy: sparx5-serdes: add support for branching on chip + type + +In preparation for lan969x, add a way to branch out on code that is to +be executed on either Sparx5 or lan969x. Initially, this is required to +branch out when checking the SERDES types and SERDES speeds, since the +handling of these differ on the two platforms. This will also be used by +the lan969x driver introduced in a subsequent patch. + +Signed-off-by: Daniel Machon +Reviewed-by: Steen Hegelund +Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-7-d695bcb57b84@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/phy/microchip/sparx5_serdes.c | 29 +++++++++++++++++---------- + drivers/phy/microchip/sparx5_serdes.h | 5 +++++ + 2 files changed, 23 insertions(+), 11 deletions(-) + +--- a/drivers/phy/microchip/sparx5_serdes.c ++++ b/drivers/phy/microchip/sparx5_serdes.c +@@ -2298,10 +2298,12 @@ static int sparx5_serdes_set_speed(struc + { + struct sparx5_serdes_macro *macro = phy_get_drvdata(phy); + +- if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000) +- return -EINVAL; +- if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000) +- return -EINVAL; ++ if (macro->priv->data->type == SPX5_TARGET_SPARX5) { ++ if (macro->sidx < SPX5_SERDES_10G_START && speed > SPEED_5000) ++ return -EINVAL; ++ if (macro->sidx < SPX5_SERDES_25G_START && speed > SPEED_10000) ++ return -EINVAL; ++ } + if (speed != macro->speed) { + macro->speed = speed; + if (macro->serdesmode != SPX5_SD_MODE_NONE) +@@ -2338,11 +2340,14 @@ static int sparx5_serdes_validate(struct + if (macro->speed == 0) + return -EINVAL; + +- if (macro->sidx < SPX5_SERDES_10G_START && macro->speed > SPEED_5000) +- return -EINVAL; +- if (macro->sidx < SPX5_SERDES_25G_START && macro->speed > SPEED_10000) +- return -EINVAL; +- ++ if (macro->priv->data->type == SPX5_TARGET_SPARX5) { ++ if (macro->sidx < SPX5_SERDES_10G_START && ++ macro->speed > SPEED_5000) ++ return -EINVAL; ++ if (macro->sidx < SPX5_SERDES_25G_START && ++ macro->speed > SPEED_10000) ++ return -EINVAL; ++ } + switch (submode) { + case PHY_INTERFACE_MODE_1000BASEX: + if (macro->speed != SPEED_100 && /* This is for 100BASE-FX */ +@@ -2515,6 +2520,7 @@ static struct sparx5_serdes_io_resource + }; + + static const struct sparx5_serdes_match_data sparx5_desc = { ++ .type = SPX5_TARGET_SPARX5, + .iomap = sparx5_serdes_iomap, + .iomap_size = ARRAY_SIZE(sparx5_serdes_iomap), + .tsize = sparx5_serdes_tsize, +@@ -2618,8 +2624,9 @@ static int sparx5_serdes_probe(struct pl + return err; + } + +- /* Power down all CMUs by default */ +- sparx5_serdes_cmu_power_off(priv); ++ /* Power down all CMU's by default */ ++ if (priv->data->type == SPX5_TARGET_SPARX5) ++ sparx5_serdes_cmu_power_off(priv); + + provider = devm_of_phy_provider_register(priv->dev, sparx5_serdes_xlate); + +--- a/drivers/phy/microchip/sparx5_serdes.h ++++ b/drivers/phy/microchip/sparx5_serdes.h +@@ -34,6 +34,10 @@ enum sparx5_10g28cmu_mode { + SPX5_SD10G28_CMU_MAX, + }; + ++enum sparx5_target { ++ SPX5_TARGET_SPARX5, ++}; ++ + struct sparx5_serdes_macro { + struct sparx5_serdes_private *priv; + u32 sidx; +@@ -56,6 +60,7 @@ struct sparx5_serdes_ops { + }; + + struct sparx5_serdes_match_data { ++ enum sparx5_target type; + const struct sparx5_serdes_consts consts; + const struct sparx5_serdes_ops ops; + const struct sparx5_serdes_io_resource *iomap; diff --git a/target/linux/microchipsw/patches-6.12/0014-v6.13-phy-lan969x-serdes-add-support-for-lan969x-serdes-dr.patch b/target/linux/microchipsw/patches-6.12/0014-v6.13-phy-lan969x-serdes-add-support-for-lan969x-serdes-dr.patch new file mode 100644 index 0000000000..30b1375885 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0014-v6.13-phy-lan969x-serdes-add-support-for-lan969x-serdes-dr.patch @@ -0,0 +1,175 @@ +From ec933122868bb205d8cdecc2049c49f811d32397 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 9 Sep 2024 17:14:49 +0200 +Subject: [PATCH 15/25] phy: lan969x-serdes: add support for lan969x serdes + driver + +Add support for lan969x SERDES driver. Lan969x has ten 10G SERDES'es +which share the same features and data rates as the Sparx5 SERDES'es. + +Signed-off-by: Daniel Machon +Reviewed-by: Steen Hegelund +Link: https://lore.kernel.org/r/20240909-sparx5-lan969x-serdes-driver-v2-9-d695bcb57b84@microchip.com +Signed-off-by: Vinod Koul +--- + drivers/phy/microchip/sparx5_serdes.c | 88 +++++++++++++++++++++++++++ + drivers/phy/microchip/sparx5_serdes.h | 2 + + 2 files changed, 90 insertions(+) + +--- a/drivers/phy/microchip/sparx5_serdes.c ++++ b/drivers/phy/microchip/sparx5_serdes.c +@@ -25,6 +25,8 @@ + #define SPX5_SERDES_25G_START 25 + #define SPX5_SERDES_6G10G_CNT SPX5_SERDES_25G_START + ++#define LAN969X_SERDES_10G_CNT 10 ++ + /* Optimal power settings from GUC */ + #define SPX5_SERDES_QUIET_MODE_VAL 0x01ef4e0c + +@@ -36,6 +38,13 @@ const unsigned int sparx5_serdes_tsize[T + [TC_SD_LANE] = 25, + }; + ++const unsigned int lan969x_serdes_tsize[TSIZE_LAST] = { ++ [TC_SD10G_LANE] = 10, ++ [TC_SD_CMU] = 6, ++ [TC_SD_CMU_CFG] = 6, ++ [TC_SD_LANE] = 10, ++}; ++ + /* Pointer to the register target size table */ + const unsigned int *tsize; + +@@ -1096,6 +1105,24 @@ static int sparx5_serdes_cmu_get(enum sp + return sparx5_serdes_cmu_map[mode][sd_index]; + } + ++/* Map of 6G/10G serdes mode and index to CMU index. */ ++static const int ++lan969x_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][LAN969X_SERDES_10G_CNT] = { ++ [SPX5_SD10G28_CMU_MAIN] = { 2, 2, 2, 2, 2, ++ 2, 2, 2, 5, 5 }, ++ [SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3, ++ 3, 3, 3, 3, 3 }, ++ [SPX5_SD10G28_CMU_AUX2] = { 1, 1, 1, 1, 4, ++ 4, 4, 4, 4, 4 }, ++ [SPX5_SD10G28_CMU_NONE] = { 1, 1, 1, 1, 4, ++ 4, 4, 4, 4, 4 }, ++}; ++ ++static int lan969x_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index) ++{ ++ return lan969x_serdes_cmu_map[mode][sd_index]; ++} ++ + static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv) + { + void __iomem *cmu_inst, *cmu_cfg_inst; +@@ -2184,6 +2211,10 @@ static int sparx5_serdes_clock_config(st + { + struct sparx5_serdes_private *priv = macro->priv; + ++ /* Clock is auto-detected in 100Base-FX mode on lan969x */ ++ if (priv->data->type == SPX5_TARGET_LAN969X) ++ return 0; ++ + if (macro->serdesmode == SPX5_SD_MODE_100FX) { + u32 freq = priv->coreclock == 250000000 ? 2 : + priv->coreclock == 500000000 ? 1 : 0; +@@ -2395,6 +2426,12 @@ static void sparx5_serdes_type_set(struc + } + } + ++static void lan969x_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx) ++{ ++ macro->serdestype = SPX5_SDT_10G; ++ macro->stpidx = macro->sidx; ++} ++ + static int sparx5_phy_create(struct sparx5_serdes_private *priv, + int idx, struct phy **phy) + { +@@ -2519,6 +2556,41 @@ static struct sparx5_serdes_io_resource + { TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */ + }; + ++static const struct sparx5_serdes_io_resource lan969x_serdes_iomap[] = { ++ { TARGET_SD_CMU, 0x0 }, /* 0xe3410000 */ ++ { TARGET_SD_CMU + 1, 0x8000 }, /* 0xe3418000 */ ++ { TARGET_SD_CMU + 2, 0x10000 }, /* 0xe3420000 */ ++ { TARGET_SD_CMU + 3, 0x18000 }, /* 0xe3428000 */ ++ { TARGET_SD_CMU + 4, 0x20000 }, /* 0xe3430000 */ ++ { TARGET_SD_CMU + 5, 0x28000 }, /* 0xe3438000 */ ++ { TARGET_SD_CMU_CFG, 0x30000 }, /* 0xe3440000 */ ++ { TARGET_SD_CMU_CFG + 1, 0x38000 }, /* 0xe3448000 */ ++ { TARGET_SD_CMU_CFG + 2, 0x40000 }, /* 0xe3450000 */ ++ { TARGET_SD_CMU_CFG + 3, 0x48000 }, /* 0xe3458000 */ ++ { TARGET_SD_CMU_CFG + 4, 0x50000 }, /* 0xe3460000 */ ++ { TARGET_SD_CMU_CFG + 5, 0x58000 }, /* 0xe3468000 */ ++ { TARGET_SD10G_LANE, 0x60000 }, /* 0xe3470000 */ ++ { TARGET_SD10G_LANE + 1, 0x68000 }, /* 0xe3478000 */ ++ { TARGET_SD10G_LANE + 2, 0x70000 }, /* 0xe3480000 */ ++ { TARGET_SD10G_LANE + 3, 0x78000 }, /* 0xe3488000 */ ++ { TARGET_SD10G_LANE + 4, 0x80000 }, /* 0xe3490000 */ ++ { TARGET_SD10G_LANE + 5, 0x88000 }, /* 0xe3498000 */ ++ { TARGET_SD10G_LANE + 6, 0x90000 }, /* 0xe34a0000 */ ++ { TARGET_SD10G_LANE + 7, 0x98000 }, /* 0xe34a8000 */ ++ { TARGET_SD10G_LANE + 8, 0xa0000 }, /* 0xe34b0000 */ ++ { TARGET_SD10G_LANE + 9, 0xa8000 }, /* 0xe34b8000 */ ++ { TARGET_SD_LANE, 0x100000 }, /* 0xe3510000 */ ++ { TARGET_SD_LANE + 1, 0x108000 }, /* 0xe3518000 */ ++ { TARGET_SD_LANE + 2, 0x110000 }, /* 0xe3520000 */ ++ { TARGET_SD_LANE + 3, 0x118000 }, /* 0xe3528000 */ ++ { TARGET_SD_LANE + 4, 0x120000 }, /* 0xe3530000 */ ++ { TARGET_SD_LANE + 5, 0x128000 }, /* 0xe3538000 */ ++ { TARGET_SD_LANE + 6, 0x130000 }, /* 0xe3540000 */ ++ { TARGET_SD_LANE + 7, 0x138000 }, /* 0xe3548000 */ ++ { TARGET_SD_LANE + 8, 0x140000 }, /* 0xe3550000 */ ++ { TARGET_SD_LANE + 9, 0x148000 }, /* 0xe3558000 */ ++}; ++ + static const struct sparx5_serdes_match_data sparx5_desc = { + .type = SPX5_TARGET_SPARX5, + .iomap = sparx5_serdes_iomap, +@@ -2534,6 +2606,21 @@ static const struct sparx5_serdes_match_ + }, + }; + ++static const struct sparx5_serdes_match_data lan969x_desc = { ++ .type = SPX5_TARGET_LAN969X, ++ .iomap = lan969x_serdes_iomap, ++ .iomap_size = ARRAY_SIZE(lan969x_serdes_iomap), ++ .tsize = lan969x_serdes_tsize, ++ .consts = { ++ .sd_max = 10, ++ .cmu_max = 6, ++ }, ++ .ops = { ++ .serdes_type_set = &lan969x_serdes_type_set, ++ .serdes_cmu_get = &lan969x_serdes_cmu_get, ++ } ++}; ++ + /* Client lookup function, uses serdes index */ + static struct phy *sparx5_serdes_xlate(struct device *dev, + const struct of_phandle_args *args) +@@ -2635,6 +2722,7 @@ static int sparx5_serdes_probe(struct pl + + static const struct of_device_id sparx5_serdes_match[] = { + { .compatible = "microchip,sparx5-serdes", .data = &sparx5_desc }, ++ { .compatible = "microchip,lan9691-serdes", .data = &lan969x_desc }, + { } + }; + MODULE_DEVICE_TABLE(of, sparx5_serdes_match); +--- a/drivers/phy/microchip/sparx5_serdes.h ++++ b/drivers/phy/microchip/sparx5_serdes.h +@@ -36,6 +36,8 @@ enum sparx5_10g28cmu_mode { + + enum sparx5_target { + SPX5_TARGET_SPARX5, ++ SPX5_TARGET_LAN969X, ++ + }; + + struct sparx5_serdes_macro { diff --git a/target/linux/microchipsw/patches-6.12/0015-v6.14-tty-serial-atmel-make-it-selectable-for-ARCH_LAN969X.patch b/target/linux/microchipsw/patches-6.12/0015-v6.14-tty-serial-atmel-make-it-selectable-for-ARCH_LAN969X.patch new file mode 100644 index 0000000000..e9938a475f --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0015-v6.14-tty-serial-atmel-make-it-selectable-for-ARCH_LAN969X.patch @@ -0,0 +1,26 @@ +From 48a8c9defc691a038c1fa515b2b6c8edb6e55aa4 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 8 Jan 2025 14:09:28 +0100 +Subject: [PATCH 17/25] tty: serial: atmel: make it selectable for ARCH_LAN969X + +LAN969x uses the Atmel serial, so make it selectable for ARCH_LAN969X. + +Signed-off-by: Robert Marko +Acked-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20250108131045.40642-3-robert.marko@sartura.hr +Signed-off-by: Greg Kroah-Hartman +--- + drivers/tty/serial/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/tty/serial/Kconfig ++++ b/drivers/tty/serial/Kconfig +@@ -128,7 +128,7 @@ config SERIAL_SB1250_DUART_CONSOLE + config SERIAL_ATMEL + bool "AT91 on-chip serial port support" + depends on COMMON_CLK +- depends on ARCH_AT91 || COMPILE_TEST ++ depends on ARCH_AT91 || ARCH_LAN969X || COMPILE_TEST + select SERIAL_CORE + select SERIAL_MCTRL_GPIO if GPIOLIB + select MFD_AT91_USART diff --git a/target/linux/microchipsw/patches-6.12/0016-v6.15-mfd-at91-usart-Make-it-selectable-for-ARCH_LAN969X.patch b/target/linux/microchipsw/patches-6.12/0016-v6.15-mfd-at91-usart-Make-it-selectable-for-ARCH_LAN969X.patch new file mode 100644 index 0000000000..43bea8aca7 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0016-v6.15-mfd-at91-usart-Make-it-selectable-for-ARCH_LAN969X.patch @@ -0,0 +1,26 @@ +From 04d0fbaff226d574e698ba1f6220be173b3b554d Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 31 Jan 2025 18:14:10 +0100 +Subject: [PATCH 18/25] mfd: at91-usart: Make it selectable for ARCH_LAN969X + +LAN969x uses the AT91 USART IP so make it selectable for ARCH_LAN969X. + +Signed-off-by: Robert Marko +Acked-by: Nicolas Ferre +Link: https://lore.kernel.org/r/20250131171739.1044701-2-robert.marko@sartura.hr +Signed-off-by: Lee Jones +--- + drivers/mfd/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -138,7 +138,7 @@ config MFD_AAT2870_CORE + config MFD_AT91_USART + tristate "AT91 USART Driver" + select MFD_CORE +- depends on ARCH_AT91 || COMPILE_TEST ++ depends on ARCH_AT91 || ARCH_LAN969X || COMPILE_TEST + help + Select this to get support for AT91 USART IP. This is a wrapper + over at91-usart-serial driver and usart-spi-driver. Only one function diff --git a/target/linux/microchipsw/patches-6.12/0017-v6.17-dmaengine-xdmac-make-it-selectable-for-ARCH_MICROCHI.patch b/target/linux/microchipsw/patches-6.12/0017-v6.17-dmaengine-xdmac-make-it-selectable-for-ARCH_MICROCHI.patch new file mode 100644 index 0000000000..511283225f --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0017-v6.17-dmaengine-xdmac-make-it-selectable-for-ARCH_MICROCHI.patch @@ -0,0 +1,27 @@ +From 823122980e18bf20eac1689ebccad488e828b33b Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 2 Jul 2025 20:36:06 +0200 +Subject: [PATCH 19/25] dmaengine: xdmac: make it selectable for ARCH_MICROCHIP + +LAN969x uses the Atmel XDMAC, so make it selectable for ARCH_MICROCHIP to +avoid needing to update depends in future if other Microchip SoC-s use it +as well. + +Signed-off-by: Robert Marko +Link: https://lore.kernel.org/r/20250702183856.1727275-9-robert.marko@sartura.hr +Signed-off-by: Vinod Koul +--- + drivers/dma/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/dma/Kconfig ++++ b/drivers/dma/Kconfig +@@ -103,7 +103,7 @@ config AT_HDMAC + + config AT_XDMAC + tristate "Atmel XDMA support" +- depends on ARCH_AT91 ++ depends on ARCH_MICROCHIP + select DMA_ENGINE + help + Support the Atmel XDMA controller. diff --git a/target/linux/microchipsw/patches-6.12/0018-v6.18-mfd-at91-usart-Make-it-selectable-for-ARCH_MICROCHIP.patch b/target/linux/microchipsw/patches-6.12/0018-v6.18-mfd-at91-usart-Make-it-selectable-for-ARCH_MICROCHIP.patch new file mode 100644 index 0000000000..4631eebf8c --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0018-v6.18-mfd-at91-usart-Make-it-selectable-for-ARCH_MICROCHIP.patch @@ -0,0 +1,28 @@ +From a1166284ce7eecc7ff3b0611ba58cbbee2e3953a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 13 Aug 2025 19:44:40 +0200 +Subject: [PATCH 20/25] mfd: at91-usart: Make it selectable for ARCH_MICROCHIP + +LAN969x uses the Atmel USART, so make it selectable for ARCH_MICROCHIP to +avoid needing to update depends in future if other Microchip SoC-s use it +as well. + +Signed-off-by: Robert Marko +Acked-by: Daniel Machon +Acked-by: Lee Jones +Signed-off-by: Nicolas Ferre +--- + drivers/mfd/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -138,7 +138,7 @@ config MFD_AAT2870_CORE + config MFD_AT91_USART + tristate "AT91 USART Driver" + select MFD_CORE +- depends on ARCH_AT91 || ARCH_LAN969X || COMPILE_TEST ++ depends on ARCH_MICROCHIP || COMPILE_TEST + help + Select this to get support for AT91 USART IP. This is a wrapper + over at91-usart-serial driver and usart-spi-driver. Only one function diff --git a/target/linux/microchipsw/patches-6.12/0019-v6.18-tty-serial-atmel-make-it-selectable-for-ARCH_MICROCH.patch b/target/linux/microchipsw/patches-6.12/0019-v6.18-tty-serial-atmel-make-it-selectable-for-ARCH_MICROCH.patch new file mode 100644 index 0000000000..aaa59ecdc7 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0019-v6.18-tty-serial-atmel-make-it-selectable-for-ARCH_MICROCH.patch @@ -0,0 +1,29 @@ +From 67a4c049056d6de07460d576e785c2fdbf64bc7c Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 13 Aug 2025 19:44:41 +0200 +Subject: [PATCH 21/25] tty: serial: atmel: make it selectable for + ARCH_MICROCHIP + +LAN969x uses the Atmel USART serial, so make it selectable for +ARCH_MICROCHIP to avoid needing to update depends in future if other +Microchip SoC-s use it as well. + +Signed-off-by: Robert Marko +Acked-by: Greg Kroah-Hartman +Acked-by: Daniel Machon +Signed-off-by: Nicolas Ferre +--- + drivers/tty/serial/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/tty/serial/Kconfig ++++ b/drivers/tty/serial/Kconfig +@@ -128,7 +128,7 @@ config SERIAL_SB1250_DUART_CONSOLE + config SERIAL_ATMEL + bool "AT91 on-chip serial port support" + depends on COMMON_CLK +- depends on ARCH_AT91 || ARCH_LAN969X || COMPILE_TEST ++ depends on ARCH_MICROCHIP || COMPILE_TEST + select SERIAL_CORE + select SERIAL_MCTRL_GPIO if GPIOLIB + select MFD_AT91_USART diff --git a/target/linux/microchipsw/patches-6.12/0020-v6.18-spi-atmel-make-it-selectable-for-ARCH_MICROCHIP.patch b/target/linux/microchipsw/patches-6.12/0020-v6.18-spi-atmel-make-it-selectable-for-ARCH_MICROCHIP.patch new file mode 100644 index 0000000000..2049712ce4 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0020-v6.18-spi-atmel-make-it-selectable-for-ARCH_MICROCHIP.patch @@ -0,0 +1,28 @@ +From e761a7b6753f3d4db9fde26dacab5ecff3b5d0e8 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 13 Aug 2025 19:44:42 +0200 +Subject: [PATCH 22/25] spi: atmel: make it selectable for ARCH_MICROCHIP + +LAN969x uses the Atmel SPI, so make it selectable for ARCH_MICROCHIP to +avoid needing to update depends in future if other Microchip SoC-s use it +as well. + +Signed-off-by: Robert Marko +Acked-by: Mark Brown +Acked-by: Daniel Machon +Signed-off-by: Nicolas Ferre +--- + drivers/spi/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -131,7 +131,7 @@ config SPI_ASPEED_SMC + + config SPI_ATMEL + tristate "Atmel SPI Controller" +- depends on ARCH_AT91 || COMPILE_TEST ++ depends on ARCH_MICROCHIP || COMPILE_TEST + depends on OF + help + This selects a driver for the Atmel SPI Controller, present on diff --git a/target/linux/microchipsw/patches-6.12/0021-v6.18-i2c-at91-make-it-selectable-for-ARCH_MICROCHIP.patch b/target/linux/microchipsw/patches-6.12/0021-v6.18-i2c-at91-make-it-selectable-for-ARCH_MICROCHIP.patch new file mode 100644 index 0000000000..c29745b9f6 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0021-v6.18-i2c-at91-make-it-selectable-for-ARCH_MICROCHIP.patch @@ -0,0 +1,28 @@ +From 0ee61e26871b1c039b905569cf74382c800c1e8b Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 13 Aug 2025 19:44:43 +0200 +Subject: [PATCH 23/25] i2c: at91: make it selectable for ARCH_MICROCHIP + +LAN969x uses the Atmel TWI I2C, so make it selectable for ARCH_MICROCHIP to +avoid needing to update depends in future if other Microchip SoC-s use it +as well. + +Signed-off-by: Robert Marko +Acked-by: Wolfram Sang +Acked-by: Daniel Machon +Signed-off-by: Nicolas Ferre +--- + drivers/i2c/busses/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -423,7 +423,7 @@ config I2C_ASPEED + + config I2C_AT91 + tristate "Atmel AT91 I2C Two-Wire interface (TWI)" +- depends on ARCH_AT91 || COMPILE_TEST ++ depends on ARCH_MICROCHIP || COMPILE_TEST + help + This supports the use of the I2C interface on Atmel AT91 + processors. diff --git a/target/linux/microchipsw/patches-6.12/0022-v6.18-char-hw_random-atmel-make-it-selectable-for-ARCH_MIC.patch b/target/linux/microchipsw/patches-6.12/0022-v6.18-char-hw_random-atmel-make-it-selectable-for-ARCH_MIC.patch new file mode 100644 index 0000000000..717572e31e --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0022-v6.18-char-hw_random-atmel-make-it-selectable-for-ARCH_MIC.patch @@ -0,0 +1,28 @@ +From 25e23abbc37484862c411b7317878d448b47fad5 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 13 Aug 2025 19:44:44 +0200 +Subject: [PATCH 24/25] char: hw_random: atmel: make it selectable for + ARCH_MICROCHIP + +LAN969x uses the Atmel HWRNG, so make it selectable for ARCH_MICROCHIP to +avoid needing to update depends in future if other Microchip SoC-s use it +as well. + +Signed-off-by: Robert Marko +Acked-by: Daniel Machon +Signed-off-by: Nicolas Ferre +--- + drivers/char/hw_random/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/char/hw_random/Kconfig ++++ b/drivers/char/hw_random/Kconfig +@@ -64,7 +64,7 @@ config HW_RANDOM_AMD + + config HW_RANDOM_ATMEL + tristate "Atmel Random Number Generator support" +- depends on (ARCH_AT91 || COMPILE_TEST) ++ depends on (ARCH_MICROCHIP || COMPILE_TEST) + default HW_RANDOM + help + This driver provides kernel-side support for the Random Number diff --git a/target/linux/microchipsw/patches-6.12/0023-v6.18-crypto-atmel-aes-make-it-selectable-for-ARCH_MICROCH.patch b/target/linux/microchipsw/patches-6.12/0023-v6.18-crypto-atmel-aes-make-it-selectable-for-ARCH_MICROCH.patch new file mode 100644 index 0000000000..a4db1d2eba --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0023-v6.18-crypto-atmel-aes-make-it-selectable-for-ARCH_MICROCH.patch @@ -0,0 +1,29 @@ +From 405fad723d71997ca9ad894ba7ac755a75fa5443 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 13 Aug 2025 19:44:45 +0200 +Subject: [PATCH 25/25] crypto: atmel-aes: make it selectable for + ARCH_MICROCHIP + +LAN969x uses the Atmel crypto, so make it selectable for ARCH_MICROCHIP to +avoid needing to update depends in future if other Microchip SoC-s use it +as well. + +Signed-off-by: Robert Marko +Acked-by: Herbert Xu +Acked-by: Daniel Machon +Signed-off-by: Nicolas Ferre +--- + drivers/crypto/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/crypto/Kconfig ++++ b/drivers/crypto/Kconfig +@@ -421,7 +421,7 @@ config CRYPTO_DEV_ATMEL_AUTHENC + + config CRYPTO_DEV_ATMEL_AES + tristate "Support for Atmel AES hw accelerator" +- depends on ARCH_AT91 || COMPILE_TEST ++ depends on ARCH_MICROCHIP || COMPILE_TEST + select CRYPTO_AES + select CRYPTO_AEAD + select CRYPTO_SKCIPHER diff --git a/target/linux/microchipsw/patches-6.12/0024-v6.13-net-sparx5-add-support-for-private-match-data.patch b/target/linux/microchipsw/patches-6.12/0024-v6.13-net-sparx5-add-support-for-private-match-data.patch new file mode 100644 index 0000000000..ad21cb6240 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0024-v6.13-net-sparx5-add-support-for-private-match-data.patch @@ -0,0 +1,135 @@ +From 7b27e8e600e75b493c97a3fd5b764064fa61dd91 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:27 +0200 +Subject: [PATCH 29/82] net: sparx5: add support for private match data + +In preparation for lan969x, add support for private match data. This +will be needed for abstracting away differences between the Sparx5 and +lan969x platforms. We initially add values for: iomap, iomap size and +ioranges. Update the use of these throughout. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../ethernet/microchip/sparx5/sparx5_main.c | 36 +++++++++++-------- + .../ethernet/microchip/sparx5/sparx5_main.h | 13 +++++++ + 2 files changed, 34 insertions(+), 15 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -45,12 +45,6 @@ struct sparx5_ram_config { + u32 init_val; + }; + +-struct sparx5_main_io_resource { +- enum sparx5_target id; +- phys_addr_t offset; +- int range; +-}; +- + static const struct sparx5_main_io_resource sparx5_main_iomap[] = { + { TARGET_CPU, 0, 0 }, /* 0x600000000 */ + { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */ +@@ -216,21 +210,24 @@ static const struct sparx5_main_io_resou + + static int sparx5_create_targets(struct sparx5 *sparx5) + { ++ const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; ++ int iomap_size = sparx5->data->iomap_size; ++ int ioranges = sparx5->data->ioranges; + struct resource *iores[IO_RANGES]; + void __iomem *iomem[IO_RANGES]; + void __iomem *begin[IO_RANGES]; + int range_id[IO_RANGES]; + int idx, jdx; + +- for (idx = 0, jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { +- const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; ++ for (idx = 0, jdx = 0; jdx < iomap_size; jdx++) { ++ const struct sparx5_main_io_resource *io = &iomap[jdx]; + +- if (idx == iomap->range) { ++ if (idx == io->range) { + range_id[idx] = jdx; + idx++; + } + } +- for (idx = 0; idx < IO_RANGES; idx++) { ++ for (idx = 0; idx < ioranges; idx++) { + iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, + idx); + if (!iores[idx]) { +@@ -245,12 +242,12 @@ static int sparx5_create_targets(struct + iores[idx]->name); + return -ENOMEM; + } +- begin[idx] = iomem[idx] - sparx5_main_iomap[range_id[idx]].offset; ++ begin[idx] = iomem[idx] - iomap[range_id[idx]].offset; + } +- for (jdx = 0; jdx < ARRAY_SIZE(sparx5_main_iomap); jdx++) { +- const struct sparx5_main_io_resource *iomap = &sparx5_main_iomap[jdx]; ++ for (jdx = 0; jdx < iomap_size; jdx++) { ++ const struct sparx5_main_io_resource *io = &iomap[jdx]; + +- sparx5->regs[iomap->id] = begin[iomap->range] + iomap->offset; ++ sparx5->regs[io->id] = begin[io->range] + io->offset; + } + return 0; + } +@@ -758,6 +755,9 @@ static int mchp_sparx5_probe(struct plat + sparx5->dev = &pdev->dev; + spin_lock_init(&sparx5->tx_lock); + ++ sparx5->data = device_get_match_data(sparx5->dev); ++ if (!sparx5->data) ++ return -EINVAL; + /* Do switch core reset if available */ + reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); + if (IS_ERR(reset)) +@@ -936,8 +936,14 @@ static void mchp_sparx5_remove(struct pl + destroy_workqueue(sparx5->mact_queue); + } + ++static const struct sparx5_match_data sparx5_desc = { ++ .iomap = sparx5_main_iomap, ++ .iomap_size = ARRAY_SIZE(sparx5_main_iomap), ++ .ioranges = 3, ++}; ++ + static const struct of_device_id mchp_sparx5_match[] = { +- { .compatible = "microchip,sparx5-switch" }, ++ { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, + { } + }; + MODULE_DEVICE_TABLE(of, mchp_sparx5_match); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -226,6 +226,18 @@ struct sparx5_mall_entry { + #define SPARX5_SKB_CB(skb) \ + ((struct sparx5_skb_cb *)((skb)->cb)) + ++struct sparx5_main_io_resource { ++ enum sparx5_target id; ++ phys_addr_t offset; ++ int range; ++}; ++ ++struct sparx5_match_data { ++ const struct sparx5_main_io_resource *iomap; ++ int ioranges; ++ int iomap_size; ++}; ++ + struct sparx5 { + struct platform_device *pdev; + struct device *dev; +@@ -293,6 +305,7 @@ struct sparx5 { + struct list_head mall_entries; + /* Common root for debugfs */ + struct dentry *debugfs_root; ++ const struct sparx5_match_data *data; + }; + + /* sparx5_switchdev.c */ diff --git a/target/linux/microchipsw/patches-6.12/0025-v6.13-net-sparx5-add-indirection-layer-to-register-macros.patch b/target/linux/microchipsw/patches-6.12/0025-v6.13-net-sparx5-add-indirection-layer-to-register-macros.patch new file mode 100644 index 0000000000..00fd6fb95f --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0025-v6.13-net-sparx5-add-indirection-layer-to-register-macros.patch @@ -0,0 +1,7398 @@ +From 161b518a0b6af89f7fc883c78503cb9472ae8791 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:28 +0200 +Subject: [PATCH 30/82] net: sparx5: add indirection layer to register macros + +The register macros are used to read and write to the switch registers. +The registers are largely the same on Sparx5 and lan969x, however in some +cases they differ. The differences can be one or more of the following: +target size, register address, register count, group address, group +count, group size, field position, field size. + +In order to handle these differences, we introduce a new indirection +layer, that defines and maps them to corresponding values, based on the +platform. As the register macro arguments can now be non-constants, we +also add non-constant variants of FIELD_GET and FIELD_PREP. + +Since the indirection layer contributes to longer macros, we have +changed the formatting of them slightly, to adhere to a 80 character +limit, and added a comment if a macro is platform-specific. + +With these additions, we can reuse all the existing macros for +lan969x. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/microchip/sparx5/Makefile | 2 +- + .../ethernet/microchip/sparx5/sparx5_main.c | 17 + + .../ethernet/microchip/sparx5/sparx5_main.h | 12 + + .../microchip/sparx5/sparx5_main_regs.h | 4469 ++++++++++------- + .../ethernet/microchip/sparx5/sparx5_regs.c | 219 + + .../ethernet/microchip/sparx5/sparx5_regs.h | 244 + + 6 files changed, 3009 insertions(+), 1954 deletions(-) + create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_regs.c + create mode 100644 drivers/net/ethernet/microchip/sparx5/sparx5_regs.h + +--- a/drivers/net/ethernet/microchip/sparx5/Makefile ++++ b/drivers/net/ethernet/microchip/sparx5/Makefile +@@ -11,7 +11,7 @@ sparx5-switch-y := sparx5_main.o sparx5 + sparx5_ptp.o sparx5_pgid.o sparx5_tc.o sparx5_qos.o \ + sparx5_vcap_impl.o sparx5_vcap_ag_api.o sparx5_tc_flower.o \ + sparx5_tc_matchall.o sparx5_pool.o sparx5_sdlb.o sparx5_police.o \ +- sparx5_psfp.o sparx5_mirror.o ++ sparx5_psfp.o sparx5_mirror.o sparx5_regs.o + + sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o + sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -29,6 +29,8 @@ + #include "sparx5_port.h" + #include "sparx5_qos.h" + ++const struct sparx5_regs *regs; ++ + #define QLIM_WM(fraction) \ + ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100) + #define IO_RANGES 3 +@@ -758,6 +760,9 @@ static int mchp_sparx5_probe(struct plat + sparx5->data = device_get_match_data(sparx5->dev); + if (!sparx5->data) + return -EINVAL; ++ ++ regs = sparx5->data->regs; ++ + /* Do switch core reset if available */ + reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); + if (IS_ERR(reset)) +@@ -936,10 +941,22 @@ static void mchp_sparx5_remove(struct pl + destroy_workqueue(sparx5->mact_queue); + } + ++static const struct sparx5_regs sparx5_regs = { ++ .tsize = sparx5_tsize, ++ .gaddr = sparx5_gaddr, ++ .gcnt = sparx5_gcnt, ++ .gsize = sparx5_gsize, ++ .raddr = sparx5_raddr, ++ .rcnt = sparx5_rcnt, ++ .fpos = sparx5_fpos, ++ .fsize = sparx5_fsize, ++}; ++ + static const struct sparx5_match_data sparx5_desc = { + .iomap = sparx5_main_iomap, + .iomap_size = ARRAY_SIZE(sparx5_main_iomap), + .ioranges = 3, ++ .regs = &sparx5_regs, + }; + + static const struct of_device_id mchp_sparx5_match[] = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -226,6 +226,17 @@ struct sparx5_mall_entry { + #define SPARX5_SKB_CB(skb) \ + ((struct sparx5_skb_cb *)((skb)->cb)) + ++struct sparx5_regs { ++ const unsigned int *tsize; ++ const unsigned int *gaddr; ++ const unsigned int *gcnt; ++ const unsigned int *gsize; ++ const unsigned int *raddr; ++ const unsigned int *rcnt; ++ const unsigned int *fpos; ++ const unsigned int *fsize; ++}; ++ + struct sparx5_main_io_resource { + enum sparx5_target id; + phys_addr_t offset; +@@ -233,6 +244,7 @@ struct sparx5_main_io_resource { + }; + + struct sparx5_match_data { ++ const struct sparx5_regs *regs; + const struct sparx5_main_io_resource *iomap; + int ioranges; + int iomap_size; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h +@@ -1,11 +1,11 @@ + /* SPDX-License-Identifier: GPL-2.0+ + * Microchip Sparx5 Switch driver + * +- * Copyright (c) 2021 Microchip Technology Inc. ++ * Copyright (c) 2024 Microchip Technology Inc. + */ + +-/* This file is autogenerated by cml-utils 2023-02-10 11:18:53 +0100. +- * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada ++/* This file is autogenerated by cml-utils 2024-10-04 10:40:40 +0200. ++ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b + */ + + #ifndef _SPARX5_MAIN_REGS_H_ +@@ -15,6 +15,8 @@ + #include + #include + ++#include "sparx5_regs.h" ++ + enum sparx5_target { + TARGET_ANA_AC = 1, + TARGET_ANA_ACL = 2, +@@ -52,14 +54,27 @@ enum sparx5_target { + TARGET_VCAP_SUPER = 326, + TARGET_VOP = 327, + TARGET_XQS = 331, +- NUM_TARGETS = 332 ++ NUM_TARGETS = 517 + }; + ++/* sparx5_main.c ++ * ++ * This is used by the register macros to access chip differences (if any) in: ++ * target size, register address, register count, group address, group count, ++ * group size, field position and field size. ++ */ ++extern const struct sparx5_regs *regs; ++ ++/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */ ++#define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) ++#define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) ++ + #define __REG(...) __VA_ARGS__ + +-/* ANA_AC:RAM_CTRL:RAM_INIT */ +-#define ANA_AC_RAM_INIT __REG(TARGET_ANA_AC,\ +- 0, 1, 839108, 0, 1, 4, 0, 0, 1, 4) ++/* ANA_AC:RAM_CTRL:RAM_INIT */ ++#define ANA_AC_RAM_INIT \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_RAM_CTRL], 0, 1, 4, 0,\ ++ 0, 1, 4) + + #define ANA_AC_RAM_INIT_RAM_INIT BIT(1) + #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\ +@@ -73,9 +88,10 @@ enum sparx5_target { + #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\ + FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) + +-/* ANA_AC:PS_COMMON:OWN_UPSID */ +-#define ANA_AC_OWN_UPSID(r) __REG(TARGET_ANA_AC,\ +- 0, 1, 894472, 0, 1, 352, 52, r, 3, 4) ++/* ANA_AC:PS_COMMON:OWN_UPSID */ ++#define ANA_AC_OWN_UPSID(r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PS_COMMON], 0, 1, 352,\ ++ 52, r, regs->rcnt[RC_ANA_AC_OWN_UPSID], 4) + + #define ANA_AC_OWN_UPSID_OWN_UPSID GENMASK(4, 0) + #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\ +@@ -83,75 +99,86 @@ enum sparx5_target { + #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\ + FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x) + +-/* ANA_AC:MIRROR_PROBE:PROBE_CFG */ +-#define ANA_AC_PROBE_CFG(g) \ +- __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 0, 0, 1, 4) ++/* ANA_AC:MIRROR_PROBE:PROBE_CFG */ ++#define ANA_AC_PROBE_CFG(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ ++ 32, 0, 0, 1, 4) + +-#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27) ++#define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD GENMASK(31, 27) + #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\ + FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) + #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\ + FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x) + +-#define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19) ++#define ANA_AC_PROBE_CFG_PROBE_CPU_SET GENMASK(26, 19) + #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\ + FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) + #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\ + FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x) + +-#define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6) ++#define ANA_AC_PROBE_CFG_PROBE_VID GENMASK(18, 6) + #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\ + FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x) + #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\ + FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x) + +-#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4) ++#define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE GENMASK(5, 4) + #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\ + FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) + #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\ + FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x) + +-#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2) ++#define ANA_AC_PROBE_CFG_PROBE_MAC_MODE GENMASK(3, 2) + #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\ + FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) + #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\ + FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x) + +-#define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0) ++#define ANA_AC_PROBE_CFG_PROBE_DIRECTION GENMASK(1, 0) + #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\ + FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) + #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\ + FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x) + +-/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ +-#define ANA_AC_PROBE_PORT_CFG(g) \ +- __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 8, 0, 1, 4) +- +-/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ +-#define ANA_AC_PROBE_PORT_CFG1(g) \ +- __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 12, 0, 1, 4) +- +-/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ +-#define ANA_AC_PROBE_PORT_CFG2(g) \ +- __REG(TARGET_ANA_AC, 0, 1, 893696, g, 3, 32, 16, 0, 1, 4) ++/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */ ++#define ANA_AC_PROBE_PORT_CFG(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ ++ 32, 8, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */ ++#define ANA_AC_PROBE_PORT_CFG1(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ ++ 32, 12, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */ ++#define ANA_AC_PROBE_PORT_CFG2(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3, \ ++ 32, 16, 0, 1, 4) + +-#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0) ++#define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2 BIT(0) + #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\ + FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) + #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\ + FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x) + +-/* ANA_AC:SRC:SRC_CFG */ +-#define ANA_AC_SRC_CFG(g) __REG(TARGET_ANA_AC,\ +- 0, 1, 849920, g, 102, 16, 0, 0, 1, 4) +- +-/* ANA_AC:SRC:SRC_CFG1 */ +-#define ANA_AC_SRC_CFG1(g) __REG(TARGET_ANA_AC,\ +- 0, 1, 849920, g, 102, 16, 4, 0, 1, 4) +- +-/* ANA_AC:SRC:SRC_CFG2 */ +-#define ANA_AC_SRC_CFG2(g) __REG(TARGET_ANA_AC,\ +- 0, 1, 849920, g, 102, 16, 8, 0, 1, 4) ++/* ANA_AC:SRC:SRC_CFG */ ++#define ANA_AC_SRC_CFG(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ ++ regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 0, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_AC:SRC:SRC_CFG1 */ ++#define ANA_AC_SRC_CFG1(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ ++ regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 4, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_AC:SRC:SRC_CFG2 */ ++#define ANA_AC_SRC_CFG2(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g, \ ++ regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 8, 0, 1, 4) + + #define ANA_AC_SRC_CFG2_PORT_MASK2 BIT(0) + #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\ +@@ -159,17 +186,22 @@ enum sparx5_target { + #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\ + FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x) + +-/* ANA_AC:PGID:PGID_CFG */ +-#define ANA_AC_PGID_CFG(g) __REG(TARGET_ANA_AC,\ +- 0, 1, 786432, g, 3290, 16, 0, 0, 1, 4) +- +-/* ANA_AC:PGID:PGID_CFG1 */ +-#define ANA_AC_PGID_CFG1(g) __REG(TARGET_ANA_AC,\ +- 0, 1, 786432, g, 3290, 16, 4, 0, 1, 4) +- +-/* ANA_AC:PGID:PGID_CFG2 */ +-#define ANA_AC_PGID_CFG2(g) __REG(TARGET_ANA_AC,\ +- 0, 1, 786432, g, 3290, 16, 8, 0, 1, 4) ++/* ANA_AC:PGID:PGID_CFG */ ++#define ANA_AC_PGID_CFG(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ ++ regs->gcnt[GC_ANA_AC_PGID], 16, 0, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_AC:PGID:PGID_CFG1 */ ++#define ANA_AC_PGID_CFG1(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ ++ regs->gcnt[GC_ANA_AC_PGID], 16, 4, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_AC:PGID:PGID_CFG2 */ ++#define ANA_AC_PGID_CFG2(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ ++ regs->gcnt[GC_ANA_AC_PGID], 16, 8, 0, 1, 4) + + #define ANA_AC_PGID_CFG2_PORT_MASK2 BIT(0) + #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\ +@@ -177,9 +209,10 @@ enum sparx5_target { + #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\ + FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x) + +-/* ANA_AC:PGID:PGID_MISC_CFG */ +-#define ANA_AC_PGID_MISC_CFG(g) __REG(TARGET_ANA_AC,\ +- 0, 1, 786432, g, 3290, 16, 12, 0, 1, 4) ++/* ANA_AC:PGID:PGID_MISC_CFG */ ++#define ANA_AC_PGID_MISC_CFG(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g, \ ++ regs->gcnt[GC_ANA_AC_PGID], 16, 12, 0, 1, 4) + + #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU GENMASK(6, 4) + #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\ +@@ -199,9 +232,10 @@ enum sparx5_target { + #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\ + FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) + +-/* ANA_AC:TSN_SF:TSN_SF */ +-#define ANA_AC_TSN_SF __REG(TARGET_ANA_AC,\ +- 0, 1, 839136, 0, 1, 4, 0, 0, 1, 4) ++/* ANA_AC:TSN_SF:TSN_SF */ ++#define ANA_AC_TSN_SF \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF], 0, 1, 4, 0, \ ++ 0, 1, 4) + + #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9) + #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\ +@@ -209,21 +243,24 @@ enum sparx5_target { + #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\ + FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) + +-#define ANA_AC_TSN_SF_PORT_NUM GENMASK(8, 0) ++#define ANA_AC_TSN_SF_PORT_NUM\ ++ GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_PORT_NUM] + 0 - 1, 0) + #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\ +- FIELD_PREP(ANA_AC_TSN_SF_PORT_NUM, x) ++ spx5_field_prep(ANA_AC_TSN_SF_PORT_NUM, x) + #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\ +- FIELD_GET(ANA_AC_TSN_SF_PORT_NUM, x) ++ spx5_field_get(ANA_AC_TSN_SF_PORT_NUM, x) + +-/* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ +-#define ANA_AC_TSN_SF_CFG(g) __REG(TARGET_ANA_AC,\ +- 0, 1, 839680, g, 1024, 4, 0, 0, 1, 4) ++/* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */ ++#define ANA_AC_TSN_SF_CFG(g) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_CFG], g, \ ++ regs->gcnt[GC_ANA_AC_TSN_SF_CFG], 4, 0, 0, 1, 4) + +-#define ANA_AC_TSN_SF_CFG_TSN_SGID GENMASK(25, 16) ++#define ANA_AC_TSN_SF_CFG_TSN_SGID\ ++ GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] + 16 - 1, 16) + #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\ +- FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_SGID, x) ++ spx5_field_prep(ANA_AC_TSN_SF_CFG_TSN_SGID, x) + #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\ +- FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_SGID, x) ++ spx5_field_get(ANA_AC_TSN_SF_CFG_TSN_SGID, x) + + #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU GENMASK(15, 2) + #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\ +@@ -243,9 +280,10 @@ enum sparx5_target { + #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\ + FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x) + +-/* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ +-#define ANA_AC_TSN_SF_STATUS __REG(TARGET_ANA_AC,\ +- 0, 1, 839072, 0, 1, 16, 0, 0, 1, 4) ++/* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */ ++#define ANA_AC_TSN_SF_STATUS \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_STATUS], 0, 1, \ ++ 16, 0, 0, 1, 4) + + #define ANA_AC_TSN_SF_STATUS_FRM_LEN GENMASK(25, 12) + #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\ +@@ -259,11 +297,12 @@ enum sparx5_target { + #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\ + FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x) + +-#define ANA_AC_TSN_SF_STATUS_TSN_SFID GENMASK(10, 1) ++#define ANA_AC_TSN_SF_STATUS_TSN_SFID\ ++ GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] + 1 - 1, 1) + #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\ +- FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) ++ spx5_field_prep(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) + #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\ +- FIELD_GET(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) ++ spx5_field_get(ANA_AC_TSN_SF_STATUS_TSN_SFID, x) + + #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD BIT(0) + #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\ +@@ -271,15 +310,17 @@ enum sparx5_target { + #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\ + FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x) + +-/* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ +-#define ANA_AC_SG_ACCESS_CTRL __REG(TARGET_ANA_AC,\ +- 0, 1, 839140, 0, 1, 12, 0, 0, 1, 4) ++/* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */ ++#define ANA_AC_SG_ACCESS_CTRL \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ ++ 0, 0, 1, 4) + +-#define ANA_AC_SG_ACCESS_CTRL_SGID GENMASK(9, 0) ++#define ANA_AC_SG_ACCESS_CTRL_SGID\ ++ GENMASK(regs->fsize[FW_ANA_AC_SG_ACCESS_CTRL_SGID] + 0 - 1, 0) + #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\ +- FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_SGID, x) ++ spx5_field_prep(ANA_AC_SG_ACCESS_CTRL_SGID, x) + #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\ +- FIELD_GET(ANA_AC_SG_ACCESS_CTRL_SGID, x) ++ spx5_field_get(ANA_AC_SG_ACCESS_CTRL_SGID, x) + + #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE BIT(28) + #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\ +@@ -287,9 +328,10 @@ enum sparx5_target { + #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\ + FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x) + +-/* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ +-#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD __REG(TARGET_ANA_AC,\ +- 0, 1, 839140, 0, 1, 12, 8, 0, 1, 4) ++/* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */ ++#define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \ ++ 8, 0, 1, 4) + + #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0) + #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\ +@@ -303,17 +345,20 @@ enum sparx5_target { + #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\ + FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x) + +-/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ +-#define ANA_AC_SG_CONFIG_REG_1 __REG(TARGET_ANA_AC,\ +- 0, 1, 851584, 0, 1, 128, 48, 0, 1, 4) +- +-/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ +-#define ANA_AC_SG_CONFIG_REG_2 __REG(TARGET_ANA_AC,\ +- 0, 1, 851584, 0, 1, 128, 52, 0, 1, 4) +- +-/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ +-#define ANA_AC_SG_CONFIG_REG_3 __REG(TARGET_ANA_AC,\ +- 0, 1, 851584, 0, 1, 128, 56, 0, 1, 4) ++/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */ ++#define ANA_AC_SG_CONFIG_REG_1 \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ ++ 48, 0, 1, 4) ++ ++/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */ ++#define ANA_AC_SG_CONFIG_REG_2 \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ ++ 52, 0, 1, 4) ++ ++/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */ ++#define ANA_AC_SG_CONFIG_REG_3 \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ ++ 56, 0, 1, 4) + + #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0) + #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\ +@@ -369,17 +414,20 @@ enum sparx5_target { + #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\ + FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x) + +-/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ +-#define ANA_AC_SG_CONFIG_REG_4 __REG(TARGET_ANA_AC,\ +- 0, 1, 851584, 0, 1, 128, 60, 0, 1, 4) +- +-/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ +-#define ANA_AC_SG_CONFIG_REG_5 __REG(TARGET_ANA_AC,\ +- 0, 1, 851584, 0, 1, 128, 64, 0, 1, 4) +- +-/* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ +-#define ANA_AC_SG_GCL_GS_CONFIG(r) __REG(TARGET_ANA_AC,\ +- 0, 1, 851584, 0, 1, 128, 0, r, 4, 4) ++/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */ ++#define ANA_AC_SG_CONFIG_REG_4 \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ ++ 60, 0, 1, 4) ++ ++/* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */ ++#define ANA_AC_SG_CONFIG_REG_5 \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ ++ 64, 0, 1, 4) ++ ++/* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */ ++#define ANA_AC_SG_GCL_GS_CONFIG(r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ ++ 0, r, 4, 4) + + #define ANA_AC_SG_GCL_GS_CONFIG_IPS GENMASK(3, 0) + #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\ +@@ -393,25 +441,30 @@ enum sparx5_target { + #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\ + FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x) + +-/* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ +-#define ANA_AC_SG_GCL_TI_CONFIG(r) __REG(TARGET_ANA_AC,\ +- 0, 1, 851584, 0, 1, 128, 16, r, 4, 4) +- +-/* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ +-#define ANA_AC_SG_GCL_OCT_CONFIG(r) __REG(TARGET_ANA_AC,\ +- 0, 1, 851584, 0, 1, 128, 32, r, 4, 4) +- +-/* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ +-#define ANA_AC_SG_STATUS_REG_1 __REG(TARGET_ANA_AC,\ +- 0, 1, 839088, 0, 1, 16, 0, 0, 1, 4) +- +-/* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ +-#define ANA_AC_SG_STATUS_REG_2 __REG(TARGET_ANA_AC,\ +- 0, 1, 839088, 0, 1, 16, 4, 0, 1, 4) +- +-/* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ +-#define ANA_AC_SG_STATUS_REG_3 __REG(TARGET_ANA_AC,\ +- 0, 1, 839088, 0, 1, 16, 8, 0, 1, 4) ++/* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */ ++#define ANA_AC_SG_GCL_TI_CONFIG(r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ ++ 16, r, 4, 4) ++ ++/* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */ ++#define ANA_AC_SG_GCL_OCT_CONFIG(r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\ ++ 32, r, 4, 4) ++ ++/* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */ ++#define ANA_AC_SG_STATUS_REG_1 \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ ++ 0, 0, 1, 4) ++ ++/* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */ ++#define ANA_AC_SG_STATUS_REG_2 \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ ++ 4, 0, 1, 4) ++ ++/* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */ ++#define ANA_AC_SG_STATUS_REG_3 \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ ++ 8, 0, 1, 4) + + #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0) + #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\ +@@ -443,23 +496,27 @@ enum sparx5_target { + #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\ + FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x) + +-/* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ +-#define ANA_AC_SG_STATUS_REG_4 __REG(TARGET_ANA_AC,\ +- 0, 1, 839088, 0, 1, 16, 12, 0, 1, 4) +- +-/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ +-#define ANA_AC_PORT_SGE_CFG(r) __REG(TARGET_ANA_AC,\ +- 0, 1, 851552, 0, 1, 20, 0, r, 4, 4) ++/* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */ ++#define ANA_AC_SG_STATUS_REG_4 \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \ ++ 12, 0, 1, 4) ++ ++/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */ ++#define ANA_AC_PORT_SGE_CFG(r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ ++ 0, 1, 20, 0, r, 4, 4) + +-#define ANA_AC_PORT_SGE_CFG_MASK GENMASK(15, 0) ++#define ANA_AC_PORT_SGE_CFG_MASK\ ++ GENMASK(regs->fsize[FW_ANA_AC_PORT_SGE_CFG_MASK] + 0 - 1, 0) + #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\ +- FIELD_PREP(ANA_AC_PORT_SGE_CFG_MASK, x) ++ spx5_field_prep(ANA_AC_PORT_SGE_CFG_MASK, x) + #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\ +- FIELD_GET(ANA_AC_PORT_SGE_CFG_MASK, x) ++ spx5_field_get(ANA_AC_PORT_SGE_CFG_MASK, x) + +-/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ +-#define ANA_AC_STAT_RESET __REG(TARGET_ANA_AC,\ +- 0, 1, 851552, 0, 1, 20, 16, 0, 1, 4) ++/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */ ++#define ANA_AC_STAT_RESET \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\ ++ 0, 1, 20, 16, 0, 1, 4) + + #define ANA_AC_STAT_RESET_RESET BIT(0) + #define ANA_AC_STAT_RESET_RESET_SET(x)\ +@@ -467,9 +524,10 @@ enum sparx5_target { + #define ANA_AC_STAT_RESET_RESET_GET(x)\ + FIELD_GET(ANA_AC_STAT_RESET_RESET, x) + +-/* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ +-#define ANA_AC_PORT_STAT_CFG(g, r) __REG(TARGET_ANA_AC,\ +- 0, 1, 843776, g, 70, 64, 4, r, 4, 4) ++/* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */ ++#define ANA_AC_PORT_STAT_CFG(g, r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ ++ regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 4, r, 4, 4) + + #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK GENMASK(11, 4) + #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\ +@@ -489,13 +547,15 @@ enum sparx5_target { + #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\ + FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x) + +-/* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ +-#define ANA_AC_PORT_STAT_LSB_CNT(g, r) __REG(TARGET_ANA_AC,\ +- 0, 1, 843776, g, 70, 64, 20, r, 4, 4) +- +-/* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ +-#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) __REG(TARGET_ANA_AC,\ +- 0, 1, 893792, 0, 1, 24, 0, r, 2, 4) ++/* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */ ++#define ANA_AC_PORT_STAT_LSB_CNT(g, r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\ ++ regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 20, r, 4, 4) ++ ++/* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */ ++#define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ ++ 0, 1, 24, 0, r, 2, 4) + + #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0) + #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\ +@@ -503,9 +563,10 @@ enum sparx5_target { + #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\ + FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x) + +-/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ +-#define ANA_AC_ACL_STAT_GLOBAL_CFG(r) __REG(TARGET_ANA_AC,\ +- 0, 1, 893792, 0, 1, 24, 8, r, 2, 4) ++/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */ ++#define ANA_AC_ACL_STAT_GLOBAL_CFG(r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ ++ 0, 1, 24, 8, r, 2, 4) + + #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE BIT(0) + #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\ +@@ -513,9 +574,10 @@ enum sparx5_target { + #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\ + FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x) + +-/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ +-#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) __REG(TARGET_ANA_AC,\ +- 0, 1, 893792, 0, 1, 24, 16, r, 2, 4) ++/* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */ ++#define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r) \ ++ __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \ ++ 0, 1, 24, 16, r, 2, 4) + + #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0) + #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\ +@@ -523,9 +585,10 @@ enum sparx5_target { + #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\ + FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x) + +-/* ANA_ACL:COMMON:VCAP_S2_CFG */ +-#define ANA_ACL_VCAP_S2_CFG(r) __REG(TARGET_ANA_ACL,\ +- 0, 1, 32768, 0, 1, 592, 0, r, 70, 4) ++/* ANA_ACL:COMMON:VCAP_S2_CFG */ ++#define ANA_ACL_VCAP_S2_CFG(r) \ ++ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ ++ 0, r, regs->rcnt[RC_ANA_ACL_VCAP_S2_CFG], 4) + + #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28) + #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\ +@@ -611,9 +674,10 @@ enum sparx5_target { + #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\ + FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x) + +-/* ANA_ACL:COMMON:SWAP_IP_CTRL */ +-#define ANA_ACL_SWAP_IP_CTRL __REG(TARGET_ANA_ACL,\ +- 0, 1, 32768, 0, 1, 592, 412, 0, 1, 4) ++/* ANA_ACL:COMMON:SWAP_IP_CTRL */ ++#define ANA_ACL_SWAP_IP_CTRL \ ++ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ ++ 412, 0, 1, 4) + + #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18) + #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\ +@@ -645,9 +709,10 @@ enum sparx5_target { + #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\ + FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x) + +-/* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ +-#define ANA_ACL_VCAP_S2_RLEG_STAT(r) __REG(TARGET_ANA_ACL,\ +- 0, 1, 32768, 0, 1, 592, 424, r, 4, 4) ++/* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */ ++#define ANA_ACL_VCAP_S2_RLEG_STAT(r) \ ++ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ ++ 424, r, 4, 4) + + #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6) + #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\ +@@ -661,9 +726,10 @@ enum sparx5_target { + #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\ + FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x) + +-/* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ +-#define ANA_ACL_VCAP_S2_FRAGMENT_CFG __REG(TARGET_ANA_ACL,\ +- 0, 1, 32768, 0, 1, 592, 440, 0, 1, 4) ++/* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */ ++#define ANA_ACL_VCAP_S2_FRAGMENT_CFG \ ++ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ ++ 440, 0, 1, 4) + + #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN GENMASK(9, 5) + #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\ +@@ -683,9 +749,10 @@ enum sparx5_target { + #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\ + FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x) + +-/* ANA_ACL:COMMON:OWN_UPSID */ +-#define ANA_ACL_OWN_UPSID(r) __REG(TARGET_ANA_ACL,\ +- 0, 1, 32768, 0, 1, 592, 580, r, 3, 4) ++/* ANA_ACL:COMMON:OWN_UPSID */ ++#define ANA_ACL_OWN_UPSID(r) \ ++ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \ ++ 580, r, regs->rcnt[RC_ANA_ACL_OWN_UPSID], 4) + + #define ANA_ACL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) + #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\ +@@ -693,9 +760,10 @@ enum sparx5_target { + #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\ + FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x) + +-/* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ +-#define ANA_ACL_VCAP_S2_KEY_SEL(g, r) __REG(TARGET_ANA_ACL,\ +- 0, 1, 34200, g, 134, 16, 0, r, 4, 4) ++/* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */ ++#define ANA_ACL_VCAP_S2_KEY_SEL(g, r) \ ++ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_KEY_SEL], g, \ ++ regs->gcnt[GC_ANA_ACL_KEY_SEL], 16, 0, r, 4, 4) + + #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA BIT(13) + #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\ +@@ -745,17 +813,20 @@ enum sparx5_target { + #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\ + FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x) + +-/* ANA_ACL:CNT_A:CNT_A */ +-#define ANA_ACL_CNT_A(g) __REG(TARGET_ANA_ACL,\ +- 0, 1, 0, g, 4096, 4, 0, 0, 1, 4) +- +-/* ANA_ACL:CNT_B:CNT_B */ +-#define ANA_ACL_CNT_B(g) __REG(TARGET_ANA_ACL,\ +- 0, 1, 16384, g, 4096, 4, 0, 0, 1, 4) +- +-/* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ +-#define ANA_ACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_ANA_ACL,\ +- 0, 1, 36408, 0, 1, 16, 0, r, 4, 4) ++/* ANA_ACL:CNT_A:CNT_A */ ++#define ANA_ACL_CNT_A(g) \ ++ __REG(TARGET_ANA_ACL, 0, 1, 0, g, regs->gcnt[GC_ANA_ACL_CNT_A], 4, 0, \ ++ 0, 1, 4) ++ ++/* ANA_ACL:CNT_B:CNT_B */ ++#define ANA_ACL_CNT_B(g) \ ++ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_CNT_B], g, \ ++ regs->gcnt[GC_ANA_ACL_CNT_B], 4, 0, 0, 1, 4) ++ ++/* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */ ++#define ANA_ACL_SEC_LOOKUP_STICKY(r) \ ++ __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_STICKY], 0, 1, 16, \ ++ 0, r, 4, 4) + + #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17) + #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\ +@@ -865,9 +936,10 @@ enum sparx5_target { + #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ + FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) + +-/* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ +-#define ANA_AC_POL_POL_UPD_INT_CFG __REG(TARGET_ANA_AC_POL,\ +- 0, 1, 75968, 0, 1, 1160, 1148, 0, 1, 4) ++/* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */ ++#define ANA_AC_POL_POL_UPD_INT_CFG \ ++ __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_POL_ALL_CFG], \ ++ 0, 1, 1160, 1148, 0, 1, 4) + + #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT GENMASK(9, 0) + #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\ +@@ -875,9 +947,10 @@ enum sparx5_target { + #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\ + FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x) + +-/* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ +-#define ANA_AC_POL_BDLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\ +- 0, 1, 79048, 0, 1, 8, 0, 0, 1, 4) ++/* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */ ++#define ANA_AC_POL_BDLB_DLB_CTRL \ ++ __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_COMMON_BDLB], \ ++ 0, 1, 8, 0, 0, 1, 4) + + #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) + #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ +@@ -903,9 +976,10 @@ enum sparx5_target { + #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ + FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x) + +-/* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ +-#define ANA_AC_POL_SLB_DLB_CTRL __REG(TARGET_ANA_AC_POL,\ +- 0, 1, 79056, 0, 1, 20, 0, 0, 1, 4) ++/* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */ ++#define ANA_AC_POL_SLB_DLB_CTRL \ ++ __REG(TARGET_ANA_AC_POL, 0, 1, \ ++ regs->gaddr[GA_ANA_AC_POL_COMMON_BUM_SLB], 0, 1, 20, 0, 0, 1, 4) + + #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19) + #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\ +@@ -931,19 +1005,22 @@ enum sparx5_target { + #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\ + FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x) + +-/* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ +-#define ANA_AC_SDLB_XLB_START(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 295468, g, 10, 24, 0, 0, 1, 4) ++/* ANA_AC_SDLB:LBGRP_TBL:XLB_START */ ++#define ANA_AC_SDLB_XLB_START(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ ++ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 0, 0, 1, 4) + +-#define ANA_AC_SDLB_XLB_START_LBSET_START GENMASK(12, 0) ++#define ANA_AC_SDLB_XLB_START_LBSET_START\ ++ GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_START_LBSET_START] + 0 - 1, 0) + #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\ +- FIELD_PREP(ANA_AC_SDLB_XLB_START_LBSET_START, x) ++ spx5_field_prep(ANA_AC_SDLB_XLB_START_LBSET_START, x) + #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\ +- FIELD_GET(ANA_AC_SDLB_XLB_START_LBSET_START, x) ++ spx5_field_get(ANA_AC_SDLB_XLB_START_LBSET_START, x) + +-/* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ +-#define ANA_AC_SDLB_PUP_INTERVAL(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 295468, g, 10, 24, 4, 0, 1, 4) ++/* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */ ++#define ANA_AC_SDLB_PUP_INTERVAL(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ ++ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 4, 0, 1, 4) + + #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL GENMASK(19, 0) + #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\ +@@ -951,9 +1028,10 @@ enum sparx5_target { + #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\ + FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x) + +-/* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ +-#define ANA_AC_SDLB_PUP_CTRL(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 295468, g, 10, 24, 8, 0, 1, 4) ++/* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */ ++#define ANA_AC_SDLB_PUP_CTRL(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ ++ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 8, 0, 1, 4) + + #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT GENMASK(18, 0) + #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\ +@@ -967,19 +1045,22 @@ enum sparx5_target { + #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\ + FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x) + +-/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ +-#define ANA_AC_SDLB_LBGRP_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 295468, g, 10, 24, 12, 0, 1, 4) ++/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */ ++#define ANA_AC_SDLB_LBGRP_MISC(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ ++ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 12, 0, 1, 4) + +-#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT GENMASK(12, 8) ++#define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT\ ++ GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] + 8 - 1, 8) + #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\ +- FIELD_PREP(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) ++ spx5_field_prep(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) + #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\ +- FIELD_GET(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) ++ spx5_field_get(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x) + +-/* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ +-#define ANA_AC_SDLB_FRM_RATE_TOKENS(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 295468, g, 10, 24, 16, 0, 1, 4) ++/* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */ ++#define ANA_AC_SDLB_FRM_RATE_TOKENS(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ ++ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 16, 0, 1, 4) + + #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0) + #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\ +@@ -987,9 +1068,10 @@ enum sparx5_target { + #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\ + FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x) + +-/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ +-#define ANA_AC_SDLB_LBGRP_STATE_TBL(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 295468, g, 10, 24, 20, 0, 1, 4) ++/* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */ ++#define ANA_AC_SDLB_LBGRP_STATE_TBL(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \ ++ g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 20, 0, 1, 4) + + #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING BIT(0) + #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\ +@@ -1003,15 +1085,17 @@ enum sparx5_target { + #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\ + FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x) + +-#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT GENMASK(28, 16) ++#define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT\ ++ GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] + 16 - 1, 16) + #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\ +- FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) ++ spx5_field_prep(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) + #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\ +- FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) ++ spx5_field_get(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x) + +-/* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ +-#define ANA_AC_SDLB_PUP_TOKENS(g, r) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 0, g, 4616, 64, 0, r, 2, 4) ++/* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */ ++#define ANA_AC_SDLB_PUP_TOKENS(g, r) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ ++ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 0, r, 2, 4) + + #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS GENMASK(12, 0) + #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\ +@@ -1019,9 +1103,10 @@ enum sparx5_target { + #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\ + FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x) + +-/* ANA_AC_SDLB:LBSET_TBL:THRES */ +-#define ANA_AC_SDLB_THRES(g, r) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 0, g, 4616, 64, 8, r, 2, 4) ++/* ANA_AC_SDLB:LBSET_TBL:THRES */ ++#define ANA_AC_SDLB_THRES(g, r) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ ++ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 8, r, 2, 4) + + #define ANA_AC_SDLB_THRES_THRES GENMASK(9, 0) + #define ANA_AC_SDLB_THRES_THRES_SET(x)\ +@@ -1035,25 +1120,29 @@ enum sparx5_target { + #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\ + FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x) + +-/* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ +-#define ANA_AC_SDLB_XLB_NEXT(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 0, g, 4616, 64, 16, 0, 1, 4) ++/* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */ ++#define ANA_AC_SDLB_XLB_NEXT(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ ++ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 16, 0, 1, 4) + +-#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT GENMASK(12, 0) ++#define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT\ ++ GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] + 0 - 1, 0) + #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\ +- FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) ++ spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) + #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\ +- FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) ++ spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x) + +-#define ANA_AC_SDLB_XLB_NEXT_LBGRP GENMASK(27, 24) ++#define ANA_AC_SDLB_XLB_NEXT_LBGRP\ ++ GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] + 24 - 1, 24) + #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\ +- FIELD_PREP(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) ++ spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) + #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\ +- FIELD_GET(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) ++ spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBGRP, x) + +-/* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ +-#define ANA_AC_SDLB_INH_CTRL(g, r) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 0, g, 4616, 64, 20, r, 2, 4) ++/* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */ ++#define ANA_AC_SDLB_INH_CTRL(g, r) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ ++ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 20, r, 2, 4) + + #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX GENMASK(12, 0) + #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\ +@@ -1073,19 +1162,22 @@ enum sparx5_target { + #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\ + FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x) + +-/* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ +-#define ANA_AC_SDLB_INH_LBSET_ADDR(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 0, g, 4616, 64, 28, 0, 1, 4) ++/* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */ ++#define ANA_AC_SDLB_INH_LBSET_ADDR(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ ++ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 28, 0, 1, 4) + +-#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR GENMASK(12, 0) ++#define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR\ ++ GENMASK(regs->fsize[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] + 0 - 1, 0) + #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\ +- FIELD_PREP(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) ++ spx5_field_prep(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) + #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\ +- FIELD_GET(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) ++ spx5_field_get(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x) + +-/* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ +-#define ANA_AC_SDLB_DLB_MISC(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 0, g, 4616, 64, 32, 0, 1, 4) ++/* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */ ++#define ANA_AC_SDLB_DLB_MISC(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ ++ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 32, 0, 1, 4) + + #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA BIT(0) + #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\ +@@ -1105,9 +1197,10 @@ enum sparx5_target { + #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\ + FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x) + +-/* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ +-#define ANA_AC_SDLB_DLB_CFG(g) __REG(TARGET_ANA_AC_SDLB,\ +- 0, 1, 0, g, 4616, 64, 36, 0, 1, 4) ++/* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */ ++#define ANA_AC_SDLB_DLB_CFG(g) \ ++ __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g, \ ++ regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 36, 0, 1, 4) + + #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA BIT(11) + #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\ +@@ -1157,9 +1250,10 @@ enum sparx5_target { + #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\ + FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x) + +-/* ANA_CL:PORT:FILTER_CTRL */ +-#define ANA_CL_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 4, 0, 1, 4) ++/* ANA_CL:PORT:FILTER_CTRL */ ++#define ANA_CL_FILTER_CTRL(g) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 4, 0, 1, 4) + + #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS BIT(2) + #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\ +@@ -1179,9 +1273,10 @@ enum sparx5_target { + #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\ + FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x) + +-/* ANA_CL:PORT:VLAN_FILTER_CTRL */ +-#define ANA_CL_VLAN_FILTER_CTRL(g, r) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 8, r, 3, 4) ++/* ANA_CL:PORT:VLAN_FILTER_CTRL */ ++#define ANA_CL_VLAN_FILTER_CTRL(g, r) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 8, r, 3, 4) + + #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10) + #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\ +@@ -1249,9 +1344,10 @@ enum sparx5_target { + #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\ + FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x) + +-/* ANA_CL:PORT:ETAG_FILTER_CTRL */ +-#define ANA_CL_ETAG_FILTER_CTRL(g) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 20, 0, 1, 4) ++/* ANA_CL:PORT:ETAG_FILTER_CTRL */ ++#define ANA_CL_ETAG_FILTER_CTRL(g) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 20, 0, 1, 4) + + #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1) + #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\ +@@ -1265,9 +1361,10 @@ enum sparx5_target { + #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\ + FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x) + +-/* ANA_CL:PORT:VLAN_CTRL */ +-#define ANA_CL_VLAN_CTRL(g) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 32, 0, 1, 4) ++/* ANA_CL:PORT:VLAN_CTRL */ ++#define ANA_CL_VLAN_CTRL(g) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 32, 0, 1, 4) + + #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26) + #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\ +@@ -1335,9 +1432,10 @@ enum sparx5_target { + #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\ + FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x) + +-/* ANA_CL:PORT:VLAN_CTRL_2 */ +-#define ANA_CL_VLAN_CTRL_2(g) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 36, 0, 1, 4) ++/* ANA_CL:PORT:VLAN_CTRL_2 */ ++#define ANA_CL_VLAN_CTRL_2(g) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 36, 0, 1, 4) + + #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT GENMASK(1, 0) + #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\ +@@ -1345,9 +1443,10 @@ enum sparx5_target { + #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\ + FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x) + +-/* ANA_CL:PORT:PCP_DEI_MAP_CFG */ +-#define ANA_CL_PCP_DEI_MAP_CFG(g, r) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 108, r, 16, 4) ++/* ANA_CL:PORT:PCP_DEI_MAP_CFG */ ++#define ANA_CL_PCP_DEI_MAP_CFG(g, r) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 108, r, 16, 4) + + #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL GENMASK(4, 3) + #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\ +@@ -1361,9 +1460,10 @@ enum sparx5_target { + #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\ + FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x) + +-/* ANA_CL:PORT:QOS_CFG */ +-#define ANA_CL_QOS_CFG(g) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 172, 0, 1, 4) ++/* ANA_CL:PORT:QOS_CFG */ ++#define ANA_CL_QOS_CFG(g) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 172, 0, 1, 4) + + #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA BIT(17) + #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\ +@@ -1437,13 +1537,15 @@ enum sparx5_target { + #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\ + FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x) + +-/* ANA_CL:PORT:CAPTURE_BPDU_CFG */ +-#define ANA_CL_CAPTURE_BPDU_CFG(g) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 196, 0, 1, 4) +- +-/* ANA_CL:PORT:ADV_CL_CFG_2 */ +-#define ANA_CL_ADV_CL_CFG_2(g, r) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 200, r, 6, 4) ++/* ANA_CL:PORT:CAPTURE_BPDU_CFG */ ++#define ANA_CL_CAPTURE_BPDU_CFG(g) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 196, 0, 1, 4) ++ ++/* ANA_CL:PORT:ADV_CL_CFG_2 */ ++#define ANA_CL_ADV_CL_CFG_2(g, r) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 200, r, 6, 4) + + #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA BIT(1) + #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\ +@@ -1457,9 +1559,10 @@ enum sparx5_target { + #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\ + FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x) + +-/* ANA_CL:PORT:ADV_CL_CFG */ +-#define ANA_CL_ADV_CL_CFG(g, r) __REG(TARGET_ANA_CL,\ +- 0, 1, 131072, g, 70, 512, 224, r, 6, 4) ++/* ANA_CL:PORT:ADV_CL_CFG */ ++#define ANA_CL_ADV_CL_CFG(g, r) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g, \ ++ regs->gcnt[GC_ANA_CL_PORT], 512, 224, r, 6, 4) + + #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL GENMASK(30, 26) + #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\ +@@ -1503,9 +1606,10 @@ enum sparx5_target { + #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\ + FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x) + +-/* ANA_CL:COMMON:OWN_UPSID */ +-#define ANA_CL_OWN_UPSID(r) __REG(TARGET_ANA_CL,\ +- 0, 1, 166912, 0, 1, 756, 0, r, 3, 4) ++/* ANA_CL:COMMON:OWN_UPSID */ ++#define ANA_CL_OWN_UPSID(r) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, 0,\ ++ r, regs->rcnt[RC_ANA_CL_OWN_UPSID], 4) + + #define ANA_CL_OWN_UPSID_OWN_UPSID GENMASK(4, 0) + #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\ +@@ -1513,9 +1617,10 @@ enum sparx5_target { + #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\ + FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x) + +-/* ANA_CL:COMMON:DSCP_CFG */ +-#define ANA_CL_DSCP_CFG(r) __REG(TARGET_ANA_CL,\ +- 0, 1, 166912, 0, 1, 756, 256, r, 64, 4) ++/* ANA_CL:COMMON:DSCP_CFG */ ++#define ANA_CL_DSCP_CFG(r) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ ++ 256, r, 64, 4) + + #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL GENMASK(12, 7) + #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\ +@@ -1547,9 +1652,10 @@ enum sparx5_target { + #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\ + FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x) + +-/* ANA_CL:COMMON:QOS_MAP_CFG */ +-#define ANA_CL_QOS_MAP_CFG(r) __REG(TARGET_ANA_CL,\ +- 0, 1, 166912, 0, 1, 756, 512, r, 32, 4) ++/* ANA_CL:COMMON:QOS_MAP_CFG */ ++#define ANA_CL_QOS_MAP_CFG(r) \ ++ __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, \ ++ 512, r, 32, 4) + + #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL GENMASK(9, 4) + #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\ +@@ -1557,9 +1663,10 @@ enum sparx5_target { + #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\ + FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x) + +-/* ANA_L2:COMMON:FWD_CFG */ +-#define ANA_L2_FWD_CFG __REG(TARGET_ANA_L2,\ +- 0, 1, 566024, 0, 1, 700, 0, 0, 1, 4) ++/* ANA_L2:COMMON:FWD_CFG */ ++#define ANA_L2_FWD_CFG \ ++ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ ++ regs->gsize[GW_ANA_L2_COMMON], 0, 0, 1, 4) + + #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL GENMASK(21, 20) + #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\ +@@ -1633,17 +1740,22 @@ enum sparx5_target { + #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\ + FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x) + +-/* ANA_L2:COMMON:AUTO_LRN_CFG */ +-#define ANA_L2_AUTO_LRN_CFG __REG(TARGET_ANA_L2,\ +- 0, 1, 566024, 0, 1, 700, 24, 0, 1, 4) +- +-/* ANA_L2:COMMON:AUTO_LRN_CFG1 */ +-#define ANA_L2_AUTO_LRN_CFG1 __REG(TARGET_ANA_L2,\ +- 0, 1, 566024, 0, 1, 700, 28, 0, 1, 4) +- +-/* ANA_L2:COMMON:AUTO_LRN_CFG2 */ +-#define ANA_L2_AUTO_LRN_CFG2 __REG(TARGET_ANA_L2,\ +- 0, 1, 566024, 0, 1, 700, 32, 0, 1, 4) ++/* ANA_L2:COMMON:AUTO_LRN_CFG */ ++#define ANA_L2_AUTO_LRN_CFG \ ++ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ ++ regs->gsize[GW_ANA_L2_COMMON], 24, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_L2:COMMON:AUTO_LRN_CFG1 */ ++#define ANA_L2_AUTO_LRN_CFG1 \ ++ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ ++ regs->gsize[GW_ANA_L2_COMMON], 28, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_L2:COMMON:AUTO_LRN_CFG2 */ ++#define ANA_L2_AUTO_LRN_CFG2 \ ++ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ ++ regs->gsize[GW_ANA_L2_COMMON], 32, 0, 1, 4) + + #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2 BIT(0) + #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\ +@@ -1651,9 +1763,11 @@ enum sparx5_target { + #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\ + FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x) + +-/* ANA_L2:COMMON:OWN_UPSID */ +-#define ANA_L2_OWN_UPSID(r) __REG(TARGET_ANA_L2,\ +- 0, 1, 566024, 0, 1, 700, 672, r, 3, 4) ++/* ANA_L2:COMMON:OWN_UPSID */ ++#define ANA_L2_OWN_UPSID(r) \ ++ __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1, \ ++ regs->gsize[GW_ANA_L2_COMMON], 672, r, \ ++ regs->rcnt[RC_ANA_L2_OWN_UPSID], 4) + + #define ANA_L2_OWN_UPSID_OWN_UPSID GENMASK(4, 0) + #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\ +@@ -1661,29 +1775,34 @@ enum sparx5_target { + #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\ + FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x) + +-/* ANA_L2:ISDX:DLB_CFG */ +-#define ANA_L2_DLB_CFG(g) __REG(TARGET_ANA_L2,\ +- 0, 1, 0, g, 4096, 128, 56, 0, 1, 4) ++/* ANA_L2:ISDX:DLB_CFG */ ++#define ANA_L2_DLB_CFG(g) \ ++ __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 56, \ ++ 0, 1, 4) + +-#define ANA_L2_DLB_CFG_DLB_IDX GENMASK(12, 0) ++#define ANA_L2_DLB_CFG_DLB_IDX\ ++ GENMASK(regs->fsize[FW_ANA_L2_DLB_CFG_DLB_IDX] + 0 - 1, 0) + #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\ +- FIELD_PREP(ANA_L2_DLB_CFG_DLB_IDX, x) ++ spx5_field_prep(ANA_L2_DLB_CFG_DLB_IDX, x) + #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\ +- FIELD_GET(ANA_L2_DLB_CFG_DLB_IDX, x) ++ spx5_field_get(ANA_L2_DLB_CFG_DLB_IDX, x) + +-/* ANA_L2:ISDX:TSN_CFG */ +-#define ANA_L2_TSN_CFG(g) __REG(TARGET_ANA_L2,\ +- 0, 1, 0, g, 4096, 128, 100, 0, 1, 4) ++/* ANA_L2:ISDX:TSN_CFG */ ++#define ANA_L2_TSN_CFG(g) \ ++ __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 100, \ ++ 0, 1, 4) + +-#define ANA_L2_TSN_CFG_TSN_SFID GENMASK(9, 0) ++#define ANA_L2_TSN_CFG_TSN_SFID\ ++ GENMASK(regs->fsize[FW_ANA_L2_TSN_CFG_TSN_SFID] + 0 - 1, 0) + #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\ +- FIELD_PREP(ANA_L2_TSN_CFG_TSN_SFID, x) ++ spx5_field_prep(ANA_L2_TSN_CFG_TSN_SFID, x) + #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\ +- FIELD_GET(ANA_L2_TSN_CFG_TSN_SFID, x) ++ spx5_field_get(ANA_L2_TSN_CFG_TSN_SFID, x) + +-/* ANA_L3:COMMON:VLAN_CTRL */ +-#define ANA_L3_VLAN_CTRL __REG(TARGET_ANA_L3,\ +- 0, 1, 493632, 0, 1, 184, 4, 0, 1, 4) ++/* ANA_L3:COMMON:VLAN_CTRL */ ++#define ANA_L3_VLAN_CTRL \ ++ __REG(TARGET_ANA_L3, 0, 1, regs->gaddr[GA_ANA_L3_COMMON], 0, 1, 184, 4,\ ++ 0, 1, 4) + + #define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0) + #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\ +@@ -1691,9 +1810,10 @@ enum sparx5_target { + #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\ + FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x) + +-/* ANA_L3:VLAN:VLAN_CFG */ +-#define ANA_L3_VLAN_CFG(g) __REG(TARGET_ANA_L3,\ +- 0, 1, 0, g, 5120, 64, 8, 0, 1, 4) ++/* ANA_L3:VLAN:VLAN_CFG */ ++#define ANA_L3_VLAN_CFG(g) \ ++ __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 8, 0, \ ++ 1, 4) + + #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR GENMASK(30, 24) + #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\ +@@ -1749,17 +1869,22 @@ enum sparx5_target { + #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\ + FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x) + +-/* ANA_L3:VLAN:VLAN_MASK_CFG */ +-#define ANA_L3_VLAN_MASK_CFG(g) __REG(TARGET_ANA_L3,\ +- 0, 1, 0, g, 5120, 64, 16, 0, 1, 4) +- +-/* ANA_L3:VLAN:VLAN_MASK_CFG1 */ +-#define ANA_L3_VLAN_MASK_CFG1(g) __REG(TARGET_ANA_L3,\ +- 0, 1, 0, g, 5120, 64, 20, 0, 1, 4) +- +-/* ANA_L3:VLAN:VLAN_MASK_CFG2 */ +-#define ANA_L3_VLAN_MASK_CFG2(g) __REG(TARGET_ANA_L3,\ +- 0, 1, 0, g, 5120, 64, 24, 0, 1, 4) ++/* ANA_L3:VLAN:VLAN_MASK_CFG */ ++#define ANA_L3_VLAN_MASK_CFG(g) \ ++ __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 16, 0,\ ++ 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_L3:VLAN:VLAN_MASK_CFG1 */ ++#define ANA_L3_VLAN_MASK_CFG1(g) \ ++ __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 20, 0,\ ++ 1, 4) ++ ++/* SPARX5 ONLY */ ++/* ANA_L3:VLAN:VLAN_MASK_CFG2 */ ++#define ANA_L3_VLAN_MASK_CFG2(g) \ ++ __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 24, 0,\ ++ 1, 4) + + #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2 BIT(0) + #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\ +@@ -1767,365 +1892,455 @@ enum sparx5_target { + #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\ + FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x) + +-/* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ +-#define ASM_RX_IN_BYTES_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 0, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ +-#define ASM_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 4, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ +-#define ASM_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 8, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ +-#define ASM_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 12, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ +-#define ASM_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 16, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ +-#define ASM_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 20, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_UC_CNT */ +-#define ASM_RX_UC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 24, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_MC_CNT */ +-#define ASM_RX_MC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 28, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_BC_CNT */ +-#define ASM_RX_BC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 32, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ +-#define ASM_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 36, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ +-#define ASM_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 40, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ +-#define ASM_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 44, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ +-#define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 48, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ +-#define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 52, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ +-#define ASM_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 56, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ +-#define ASM_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 60, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ +-#define ASM_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 64, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ +-#define ASM_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 68, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ +-#define ASM_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 72, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ +-#define ASM_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 76, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ +-#define ASM_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 80, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ +-#define ASM_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 84, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ +-#define ASM_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 88, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ +-#define ASM_RX_IPG_SHRINK_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 92, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ +-#define ASM_TX_OUT_BYTES_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 96, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ +-#define ASM_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 100, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ +-#define ASM_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 104, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_UC_CNT */ +-#define ASM_TX_UC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 108, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_MC_CNT */ +-#define ASM_TX_MC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 112, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_BC_CNT */ +-#define ASM_TX_BC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 116, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ +-#define ASM_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 120, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ +-#define ASM_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 124, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ +-#define ASM_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 128, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ +-#define ASM_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 132, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ +-#define ASM_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 136, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ +-#define ASM_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 140, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ +-#define ASM_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 144, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ +-#define ASM_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 148, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ +-#define ASM_RX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 152, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ +-#define ASM_RX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 156, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ +-#define ASM_TX_TAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 160, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ +-#define ASM_TX_UNTAGGED_FRMS_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 164, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ +-#define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 168, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ +-#define ASM_PMAC_RX_PAUSE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 172, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ +-#define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 176, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ +-#define ASM_PMAC_RX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 180, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ +-#define ASM_PMAC_RX_BAD_BYTES_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 184, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ +-#define ASM_PMAC_RX_UC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 188, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ +-#define ASM_PMAC_RX_MC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 192, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ +-#define ASM_PMAC_RX_BC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 196, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ +-#define ASM_PMAC_RX_CRC_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 200, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ +-#define ASM_PMAC_RX_UNDERSIZE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 204, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ +-#define ASM_PMAC_RX_FRAGMENTS_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 208, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ +-#define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 212, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ +-#define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 216, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ +-#define ASM_PMAC_RX_OVERSIZE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 220, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ +-#define ASM_PMAC_RX_JABBERS_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 224, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ +-#define ASM_PMAC_RX_SIZE64_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 228, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ +-#define ASM_PMAC_RX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 232, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ +-#define ASM_PMAC_RX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 236, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ +-#define ASM_PMAC_RX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 240, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ +-#define ASM_PMAC_RX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 244, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ +-#define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 248, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ +-#define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 252, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ +-#define ASM_PMAC_TX_PAUSE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 256, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ +-#define ASM_PMAC_TX_OK_BYTES_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 260, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ +-#define ASM_PMAC_TX_UC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 264, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ +-#define ASM_PMAC_TX_MC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 268, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ +-#define ASM_PMAC_TX_BC_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 272, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ +-#define ASM_PMAC_TX_SIZE64_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 276, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ +-#define ASM_PMAC_TX_SIZE65TO127_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 280, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ +-#define ASM_PMAC_TX_SIZE128TO255_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 284, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ +-#define ASM_PMAC_TX_SIZE256TO511_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 288, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ +-#define ASM_PMAC_TX_SIZE512TO1023_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 292, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ +-#define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 296, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ +-#define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 300, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ +-#define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 304, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ +-#define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 308, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ +-#define ASM_MM_RX_SMD_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 312, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ +-#define ASM_MM_RX_ASSEMBLY_OK_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 316, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ +-#define ASM_MM_RX_MERGE_FRAG_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 320, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ +-#define ASM_MM_TX_PFRAGMENT_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 324, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ +-#define ASM_TX_MULTI_COLL_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 328, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ +-#define ASM_TX_LATE_COLL_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 332, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ +-#define ASM_TX_XCOLL_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 336, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_DEFER_CNT */ +-#define ASM_TX_DEFER_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 340, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ +-#define ASM_TX_XDEFER_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 344, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ +-#define ASM_TX_BACKOFF1_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 348, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ +-#define ASM_TX_CSENSE_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 352, 0, 1, 4) +- +-/* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ +-#define ASM_RX_IN_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 356, 0, 1, 4) ++/* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */ ++#define ASM_RX_IN_BYTES_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 0, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */ ++#define ASM_RX_SYMBOL_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 4, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_PAUSE_CNT */ ++#define ASM_RX_PAUSE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 8, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */ ++#define ASM_RX_UNSUP_OPCODE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 12, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */ ++#define ASM_RX_OK_BYTES_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 16, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */ ++#define ASM_RX_BAD_BYTES_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 20, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_UC_CNT */ ++#define ASM_RX_UC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 24, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_MC_CNT */ ++#define ASM_RX_MC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 28, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_BC_CNT */ ++#define ASM_RX_BC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 32, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */ ++#define ASM_RX_CRC_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 36, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */ ++#define ASM_RX_UNDERSIZE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 40, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */ ++#define ASM_RX_FRAGMENTS_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 44, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */ ++#define ASM_RX_IN_RANGE_LEN_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 48, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */ ++#define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 52, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */ ++#define ASM_RX_OVERSIZE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 56, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_JABBERS_CNT */ ++#define ASM_RX_JABBERS_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 60, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_SIZE64_CNT */ ++#define ASM_RX_SIZE64_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 64, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */ ++#define ASM_RX_SIZE65TO127_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 68, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */ ++#define ASM_RX_SIZE128TO255_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 72, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */ ++#define ASM_RX_SIZE256TO511_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 76, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */ ++#define ASM_RX_SIZE512TO1023_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 80, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */ ++#define ASM_RX_SIZE1024TO1518_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 84, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */ ++#define ASM_RX_SIZE1519TOMAX_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 88, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */ ++#define ASM_RX_IPG_SHRINK_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 92, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */ ++#define ASM_TX_OUT_BYTES_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 96, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_PAUSE_CNT */ ++#define ASM_TX_PAUSE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 100, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */ ++#define ASM_TX_OK_BYTES_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 104, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_UC_CNT */ ++#define ASM_TX_UC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 108, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_MC_CNT */ ++#define ASM_TX_MC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 112, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_BC_CNT */ ++#define ASM_TX_BC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 116, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_SIZE64_CNT */ ++#define ASM_TX_SIZE64_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 120, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */ ++#define ASM_TX_SIZE65TO127_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 124, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */ ++#define ASM_TX_SIZE128TO255_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 128, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */ ++#define ASM_TX_SIZE256TO511_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 132, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */ ++#define ASM_TX_SIZE512TO1023_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 136, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */ ++#define ASM_TX_SIZE1024TO1518_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 140, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */ ++#define ASM_TX_SIZE1519TOMAX_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 144, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */ ++#define ASM_RX_ALIGNMENT_LOST_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 148, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */ ++#define ASM_RX_TAGGED_FRMS_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 152, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */ ++#define ASM_RX_UNTAGGED_FRMS_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 156, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */ ++#define ASM_TX_TAGGED_FRMS_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 160, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */ ++#define ASM_TX_UNTAGGED_FRMS_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 164, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */ ++#define ASM_PMAC_RX_SYMBOL_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 168, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */ ++#define ASM_PMAC_RX_PAUSE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 172, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */ ++#define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 176, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */ ++#define ASM_PMAC_RX_OK_BYTES_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 180, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */ ++#define ASM_PMAC_RX_BAD_BYTES_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 184, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */ ++#define ASM_PMAC_RX_UC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 188, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */ ++#define ASM_PMAC_RX_MC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 192, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */ ++#define ASM_PMAC_RX_BC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 196, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */ ++#define ASM_PMAC_RX_CRC_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 200, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */ ++#define ASM_PMAC_RX_UNDERSIZE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 204, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */ ++#define ASM_PMAC_RX_FRAGMENTS_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 208, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ ++#define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 212, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ ++#define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 216, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */ ++#define ASM_PMAC_RX_OVERSIZE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 220, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */ ++#define ASM_PMAC_RX_JABBERS_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 224, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */ ++#define ASM_PMAC_RX_SIZE64_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 228, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */ ++#define ASM_PMAC_RX_SIZE65TO127_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 232, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */ ++#define ASM_PMAC_RX_SIZE128TO255_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 236, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */ ++#define ASM_PMAC_RX_SIZE256TO511_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 240, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */ ++#define ASM_PMAC_RX_SIZE512TO1023_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 244, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */ ++#define ASM_PMAC_RX_SIZE1024TO1518_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 248, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */ ++#define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 252, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */ ++#define ASM_PMAC_TX_PAUSE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 256, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */ ++#define ASM_PMAC_TX_OK_BYTES_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 260, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */ ++#define ASM_PMAC_TX_UC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 264, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */ ++#define ASM_PMAC_TX_MC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 268, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */ ++#define ASM_PMAC_TX_BC_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 272, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */ ++#define ASM_PMAC_TX_SIZE64_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 276, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */ ++#define ASM_PMAC_TX_SIZE65TO127_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 280, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */ ++#define ASM_PMAC_TX_SIZE128TO255_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 284, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */ ++#define ASM_PMAC_TX_SIZE256TO511_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 288, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */ ++#define ASM_PMAC_TX_SIZE512TO1023_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 292, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */ ++#define ASM_PMAC_TX_SIZE1024TO1518_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 296, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */ ++#define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 300, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */ ++#define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 304, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */ ++#define ASM_MM_RX_ASSEMBLY_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 308, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */ ++#define ASM_MM_RX_SMD_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 312, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */ ++#define ASM_MM_RX_ASSEMBLY_OK_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 316, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */ ++#define ASM_MM_RX_MERGE_FRAG_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 320, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */ ++#define ASM_MM_TX_PFRAGMENT_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 324, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */ ++#define ASM_TX_MULTI_COLL_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 328, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */ ++#define ASM_TX_LATE_COLL_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 332, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_XCOLL_CNT */ ++#define ASM_TX_XCOLL_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 336, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_DEFER_CNT */ ++#define ASM_TX_DEFER_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 340, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_XDEFER_CNT */ ++#define ASM_TX_XDEFER_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 344, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */ ++#define ASM_TX_BACKOFF1_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 348, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:TX_CSENSE_CNT */ ++#define ASM_TX_CSENSE_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 352, 0, 1, 4) ++ ++/* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */ ++#define ASM_RX_IN_BYTES_MSB_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 356, 0, 1, 4) + + #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0) + #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ +@@ -2133,9 +2348,10 @@ enum sparx5_target { + #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) + +-/* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ +-#define ASM_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 360, 0, 1, 4) ++/* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */ ++#define ASM_RX_OK_BYTES_MSB_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 360, 0, 1, 4) + + #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) + #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ +@@ -2143,9 +2359,10 @@ enum sparx5_target { + #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) + +-/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ +-#define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 364, 0, 1, 4) ++/* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */ ++#define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 364, 0, 1, 4) + + #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0) + #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ +@@ -2153,9 +2370,10 @@ enum sparx5_target { + #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) + +-/* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ +-#define ASM_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 368, 0, 1, 4) ++/* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */ ++#define ASM_RX_BAD_BYTES_MSB_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 368, 0, 1, 4) + + #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) + #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ +@@ -2163,9 +2381,10 @@ enum sparx5_target { + #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) + +-/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ +-#define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 372, 0, 1, 4) ++/* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */ ++#define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 372, 0, 1, 4) + + #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0) + #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ +@@ -2173,9 +2392,10 @@ enum sparx5_target { + #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) + +-/* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ +-#define ASM_TX_OUT_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 376, 0, 1, 4) ++/* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */ ++#define ASM_TX_OUT_BYTES_MSB_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 376, 0, 1, 4) + + #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0) + #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ +@@ -2183,9 +2403,10 @@ enum sparx5_target { + #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) + +-/* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ +-#define ASM_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 380, 0, 1, 4) ++/* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */ ++#define ASM_TX_OK_BYTES_MSB_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 380, 0, 1, 4) + + #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) + #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ +@@ -2193,9 +2414,10 @@ enum sparx5_target { + #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) + +-/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ +-#define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 384, 0, 1, 4) ++/* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */ ++#define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 384, 0, 1, 4) + + #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0) + #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ +@@ -2203,13 +2425,15 @@ enum sparx5_target { + #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) + +-/* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ +-#define ASM_RX_SYNC_LOST_ERR_CNT(g) __REG(TARGET_ASM,\ +- 0, 1, 0, g, 65, 512, 388, 0, 1, 4) +- +-/* ASM:CFG:STAT_CFG */ +-#define ASM_STAT_CFG __REG(TARGET_ASM,\ +- 0, 1, 33280, 0, 1, 1088, 0, 0, 1, 4) ++/* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */ ++#define ASM_RX_SYNC_LOST_ERR_CNT(g) \ ++ __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512, \ ++ 388, 0, 1, 4) ++ ++/* ASM:CFG:STAT_CFG */ ++#define ASM_STAT_CFG \ ++ __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ ++ regs->gsize[GW_ASM_CFG], 0, 0, 1, 4) + + #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT BIT(0) + #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\ +@@ -2217,9 +2441,10 @@ enum sparx5_target { + #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\ + FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x) + +-/* ASM:CFG:PORT_CFG */ +-#define ASM_PORT_CFG(r) __REG(TARGET_ASM,\ +- 0, 1, 33280, 0, 1, 1088, 540, r, 67, 4) ++/* ASM:CFG:PORT_CFG */ ++#define ASM_PORT_CFG(r) \ ++ __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1, \ ++ regs->gsize[GW_ASM_CFG], 540, r, regs->rcnt[RC_ASM_PORT_CFG], 4) + + #define ASM_PORT_CFG_CSC_STAT_DIS BIT(12) + #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\ +@@ -2287,9 +2512,10 @@ enum sparx5_target { + #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\ + FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x) + +-/* ASM:RAM_CTRL:RAM_INIT */ +-#define ASM_RAM_INIT __REG(TARGET_ASM,\ +- 0, 1, 34832, 0, 1, 4, 0, 0, 1, 4) ++/* ASM:RAM_CTRL:RAM_INIT */ ++#define ASM_RAM_INIT \ ++ __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ ++ 4) + + #define ASM_RAM_INIT_RAM_INIT BIT(1) + #define ASM_RAM_INIT_RAM_INIT_SET(x)\ +@@ -2303,9 +2529,10 @@ enum sparx5_target { + #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ + FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x) + +-/* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ +-#define CLKGEN_LCPLL1_CORE_CLK_CFG __REG(TARGET_CLKGEN,\ +- 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */ ++#define CLKGEN_LCPLL1_CORE_CLK_CFG \ ++ __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4) + + #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV GENMASK(7, 0) + #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\ +@@ -2343,91 +2570,106 @@ enum sparx5_target { + #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\ + FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x) + +-/* CPU:CPU_REGS:PROC_CTRL */ +-#define CPU_PROC_CTRL __REG(TARGET_CPU,\ +- 0, 1, 0, 0, 1, 204, 176, 0, 1, 4) ++/* CPU:CPU_REGS:PROC_CTRL */ ++#define CPU_PROC_CTRL \ ++ __REG(TARGET_CPU, 0, 1, 0, 0, 1, regs->gsize[GW_CPU_CPU_REGS], \ ++ regs->raddr[RA_CPU_PROC_CTRL], 0, 1, 4) + +-#define CPU_PROC_CTRL_AARCH64_MODE_ENA BIT(12) ++#define CPU_PROC_CTRL_AARCH64_MODE_ENA\ ++ BIT(regs->fpos[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA]) + #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\ +- FIELD_PREP(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) ++ spx5_field_prep(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) + #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\ +- FIELD_GET(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) ++ spx5_field_get(CPU_PROC_CTRL_AARCH64_MODE_ENA, x) + +-#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS BIT(11) ++#define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS\ ++ BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS]) + #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\ +- FIELD_PREP(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) ++ spx5_field_prep(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) + #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\ +- FIELD_GET(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) ++ spx5_field_get(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x) + +-#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS BIT(10) ++#define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS\ ++ BIT(regs->fpos[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS]) + #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\ +- FIELD_PREP(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) ++ spx5_field_prep(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) + #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\ +- FIELD_GET(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) ++ spx5_field_get(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x) + +-#define CPU_PROC_CTRL_BE_EXCEP_MODE BIT(9) ++#define CPU_PROC_CTRL_BE_EXCEP_MODE\ ++ BIT(regs->fpos[FP_CPU_PROC_CTRL_BE_EXCEP_MODE]) + #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\ +- FIELD_PREP(CPU_PROC_CTRL_BE_EXCEP_MODE, x) ++ spx5_field_prep(CPU_PROC_CTRL_BE_EXCEP_MODE, x) + #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\ +- FIELD_GET(CPU_PROC_CTRL_BE_EXCEP_MODE, x) ++ spx5_field_get(CPU_PROC_CTRL_BE_EXCEP_MODE, x) + +-#define CPU_PROC_CTRL_VINITHI BIT(8) ++#define CPU_PROC_CTRL_VINITHI\ ++ BIT(regs->fpos[FP_CPU_PROC_CTRL_VINITHI]) + #define CPU_PROC_CTRL_VINITHI_SET(x)\ +- FIELD_PREP(CPU_PROC_CTRL_VINITHI, x) ++ spx5_field_prep(CPU_PROC_CTRL_VINITHI, x) + #define CPU_PROC_CTRL_VINITHI_GET(x)\ +- FIELD_GET(CPU_PROC_CTRL_VINITHI, x) ++ spx5_field_get(CPU_PROC_CTRL_VINITHI, x) + +-#define CPU_PROC_CTRL_CFGTE BIT(7) ++#define CPU_PROC_CTRL_CFGTE\ ++ BIT(regs->fpos[FP_CPU_PROC_CTRL_CFGTE]) + #define CPU_PROC_CTRL_CFGTE_SET(x)\ +- FIELD_PREP(CPU_PROC_CTRL_CFGTE, x) ++ spx5_field_prep(CPU_PROC_CTRL_CFGTE, x) + #define CPU_PROC_CTRL_CFGTE_GET(x)\ +- FIELD_GET(CPU_PROC_CTRL_CFGTE, x) ++ spx5_field_get(CPU_PROC_CTRL_CFGTE, x) + +-#define CPU_PROC_CTRL_CP15S_DISABLE BIT(6) ++#define CPU_PROC_CTRL_CP15S_DISABLE\ ++ BIT(regs->fpos[FP_CPU_PROC_CTRL_CP15S_DISABLE]) + #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\ +- FIELD_PREP(CPU_PROC_CTRL_CP15S_DISABLE, x) ++ spx5_field_prep(CPU_PROC_CTRL_CP15S_DISABLE, x) + #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\ +- FIELD_GET(CPU_PROC_CTRL_CP15S_DISABLE, x) ++ spx5_field_get(CPU_PROC_CTRL_CP15S_DISABLE, x) + +-#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE BIT(5) ++#define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE\ ++ BIT(regs->fpos[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE]) + #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\ +- FIELD_PREP(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) ++ spx5_field_prep(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) + #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\ +- FIELD_GET(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) ++ spx5_field_get(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x) + ++/* SPARX5 ONLY */ + #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA BIT(4) + #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\ + FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) + #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\ + FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x) + ++/* SPARX5 ONLY */ + #define CPU_PROC_CTRL_ACP_AWCACHE BIT(3) + #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\ + FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x) + #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\ + FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x) + ++/* SPARX5 ONLY */ + #define CPU_PROC_CTRL_ACP_ARCACHE BIT(2) + #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\ + FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x) + #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\ + FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x) + +-#define CPU_PROC_CTRL_L2_FLUSH_REQ BIT(1) ++#define CPU_PROC_CTRL_L2_FLUSH_REQ\ ++ BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_FLUSH_REQ]) + #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\ +- FIELD_PREP(CPU_PROC_CTRL_L2_FLUSH_REQ, x) ++ spx5_field_prep(CPU_PROC_CTRL_L2_FLUSH_REQ, x) + #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\ +- FIELD_GET(CPU_PROC_CTRL_L2_FLUSH_REQ, x) ++ spx5_field_get(CPU_PROC_CTRL_L2_FLUSH_REQ, x) + ++/* SPARX5 ONLY */ + #define CPU_PROC_CTRL_ACP_DISABLE BIT(0) + #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\ + FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x) + #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ + FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ +-#define DEV10G_MAC_ENA_CFG(t) __REG(TARGET_DEV10G,\ +- t, 12, 0, 0, 1, 60, 0, 0, 1, 4) ++/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ ++#define DEV10G_MAC_ENA_CFG(t) \ ++ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \ ++ 4) + + #define DEV10G_MAC_ENA_CFG_RX_ENA BIT(4) + #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\ +@@ -2441,9 +2683,10 @@ enum sparx5_target { + #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\ + FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ +-#define DEV10G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV10G,\ +- t, 12, 0, 0, 1, 60, 8, 0, 1, 4) ++/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ ++#define DEV10G_MAC_MAXLEN_CFG(t) \ ++ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 8, 0, 1, \ ++ 4) + + #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) + #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ +@@ -2457,9 +2700,10 @@ enum sparx5_target { + #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ + FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ +-#define DEV10G_MAC_NUM_TAGS_CFG(t) __REG(TARGET_DEV10G,\ +- t, 12, 0, 0, 1, 60, 12, 0, 1, 4) ++/* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */ ++#define DEV10G_MAC_NUM_TAGS_CFG(t) \ ++ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 12, 0, 1, \ ++ 4) + + #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS GENMASK(1, 0) + #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\ +@@ -2467,9 +2711,10 @@ enum sparx5_target { + #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\ + FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ +-#define DEV10G_MAC_TAGS_CFG(t, r) __REG(TARGET_DEV10G,\ +- t, 12, 0, 0, 1, 60, 16, r, 3, 4) ++/* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */ ++#define DEV10G_MAC_TAGS_CFG(t, r) \ ++ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 16, r, 3, \ ++ 4) + + #define DEV10G_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) + #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\ +@@ -2483,9 +2728,10 @@ enum sparx5_target { + #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\ + FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ +-#define DEV10G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV10G,\ +- t, 12, 0, 0, 1, 60, 28, 0, 1, 4) ++/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ ++#define DEV10G_MAC_ADV_CHK_CFG(t) \ ++ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 28, 0, 1, \ ++ 4) + + #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) + #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ +@@ -2529,9 +2775,10 @@ enum sparx5_target { + #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ + FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ +-#define DEV10G_MAC_TX_MONITOR_STICKY(t) __REG(TARGET_DEV10G,\ +- t, 12, 0, 0, 1, 60, 48, 0, 1, 4) ++/* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */ ++#define DEV10G_MAC_TX_MONITOR_STICKY(t) \ ++ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 48, 0, 1, \ ++ 4) + + #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4) + #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\ +@@ -2563,9 +2810,10 @@ enum sparx5_target { + #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\ + FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x) + +-/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ +-#define DEV10G_DEV_RST_CTRL(t) __REG(TARGET_DEV10G,\ +- t, 12, 436, 0, 1, 52, 0, 0, 1, 4) ++/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ ++#define DEV10G_DEV_RST_CTRL(t) \ ++ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 0, 0, 1,\ ++ 4) + + #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) + #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ +@@ -2621,9 +2869,10 @@ enum sparx5_target { + #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ + FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) + +-/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ +-#define DEV10G_PCS25G_CFG(t) __REG(TARGET_DEV10G,\ +- t, 12, 488, 0, 1, 32, 0, 0, 1, 4) ++/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ ++#define DEV10G_PCS25G_CFG(t) \ ++ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\ ++ 4) + + #define DEV10G_PCS25G_CFG_PCS25G_ENA BIT(0) + #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\ +@@ -2631,9 +2880,10 @@ enum sparx5_target { + #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\ + FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ +-#define DEV25G_MAC_ENA_CFG(t) __REG(TARGET_DEV25G,\ +- t, 8, 0, 0, 1, 60, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ ++#define DEV25G_MAC_ENA_CFG(t) \ ++ __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4) + + #define DEV25G_MAC_ENA_CFG_RX_ENA BIT(4) + #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\ +@@ -2647,9 +2897,10 @@ enum sparx5_target { + #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\ + FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ +-#define DEV25G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV25G,\ +- t, 8, 0, 0, 1, 60, 8, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ ++#define DEV25G_MAC_MAXLEN_CFG(t) \ ++ __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4) + + #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) + #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ +@@ -2663,9 +2914,10 @@ enum sparx5_target { + #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ + FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ +-#define DEV25G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV25G,\ +- t, 8, 0, 0, 1, 60, 28, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ ++#define DEV25G_MAC_ADV_CHK_CFG(t) \ ++ __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4) + + #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) + #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ +@@ -2709,9 +2961,10 @@ enum sparx5_target { + #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ + FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) + +-/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ +-#define DEV25G_DEV_RST_CTRL(t) __REG(TARGET_DEV25G,\ +- t, 8, 436, 0, 1, 52, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ ++#define DEV25G_DEV_RST_CTRL(t) \ ++ __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4) + + #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) + #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ +@@ -2767,9 +3020,10 @@ enum sparx5_target { + #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ + FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x) + +-/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ +-#define DEV25G_PCS25G_CFG(t) __REG(TARGET_DEV25G,\ +- t, 8, 488, 0, 1, 32, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ ++#define DEV25G_PCS25G_CFG(t) \ ++ __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4) + + #define DEV25G_PCS25G_CFG_PCS25G_ENA BIT(0) + #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\ +@@ -2777,9 +3031,10 @@ enum sparx5_target { + #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\ + FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x) + +-/* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ +-#define DEV25G_PCS25G_SD_CFG(t) __REG(TARGET_DEV25G,\ +- t, 8, 488, 0, 1, 32, 4, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */ ++#define DEV25G_PCS25G_SD_CFG(t) \ ++ __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4) + + #define DEV25G_PCS25G_SD_CFG_SD_SEL BIT(8) + #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\ +@@ -2799,9 +3054,10 @@ enum sparx5_target { + #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\ + FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x) + +-/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ +-#define DEV2G5_DEV_RST_CTRL(t) __REG(TARGET_DEV2G5,\ +- t, 65, 0, 0, 1, 36, 0, 0, 1, 4) ++/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ ++#define DEV2G5_DEV_RST_CTRL(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 0, 0, 1, 36, 0, 0, 1, \ ++ 4) + + #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23) + #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\ +@@ -2851,9 +3107,10 @@ enum sparx5_target { + #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ + FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x) + +-/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ +-#define DEV2G5_MAC_ENA_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 52, 0, 1, 36, 0, 0, 1, 4) ++/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ ++#define DEV2G5_MAC_ENA_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 0, 0, 1, \ ++ 4) + + #define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4) + #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\ +@@ -2867,9 +3124,10 @@ enum sparx5_target { + #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\ + FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x) + +-/* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ +-#define DEV2G5_MAC_MODE_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 52, 0, 1, 36, 4, 0, 1, 4) ++/* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */ ++#define DEV2G5_MAC_MODE_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 4, 0, 1, \ ++ 4) + + #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA BIT(8) + #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\ +@@ -2889,9 +3147,10 @@ enum sparx5_target { + #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\ + FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x) + +-/* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ +-#define DEV2G5_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 52, 0, 1, 36, 8, 0, 1, 4) ++/* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ ++#define DEV2G5_MAC_MAXLEN_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 8, 0, 1, \ ++ 4) + + #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN GENMASK(15, 0) + #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\ +@@ -2899,9 +3158,10 @@ enum sparx5_target { + #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ + FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x) + +-/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ +-#define DEV2G5_MAC_TAGS_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 52, 0, 1, 36, 12, 0, 1, 4) ++/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ ++#define DEV2G5_MAC_TAGS_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 12, 0, 1,\ ++ 4) + + #define DEV2G5_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) + #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\ +@@ -2927,9 +3187,10 @@ enum sparx5_target { + #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ + FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x) + +-/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ +-#define DEV2G5_MAC_TAGS_CFG2(t) __REG(TARGET_DEV2G5,\ +- t, 65, 52, 0, 1, 36, 16, 0, 1, 4) ++/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */ ++#define DEV2G5_MAC_TAGS_CFG2(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 16, 0, 1,\ ++ 4) + + #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3 GENMASK(31, 16) + #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\ +@@ -2943,9 +3204,10 @@ enum sparx5_target { + #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\ + FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x) + +-/* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ +-#define DEV2G5_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 52, 0, 1, 36, 20, 0, 1, 4) ++/* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ ++#define DEV2G5_MAC_ADV_CHK_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 20, 0, 1,\ ++ 4) + + #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA BIT(0) + #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\ +@@ -2953,9 +3215,10 @@ enum sparx5_target { + #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\ + FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x) + +-/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ +-#define DEV2G5_MAC_IFG_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 52, 0, 1, 36, 24, 0, 1, 4) ++/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ ++#define DEV2G5_MAC_IFG_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 24, 0, 1,\ ++ 4) + + #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17) + #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\ +@@ -2981,9 +3244,10 @@ enum sparx5_target { + #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\ + FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x) + +-/* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ +-#define DEV2G5_MAC_HDX_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 52, 0, 1, 36, 28, 0, 1, 4) ++/* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */ ++#define DEV2G5_MAC_HDX_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 28, 0, 1,\ ++ 4) + + #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC BIT(26) + #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\ +@@ -3015,9 +3279,10 @@ enum sparx5_target { + #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\ + FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x) + +-/* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ +-#define DEV2G5_PCS1G_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 88, 0, 1, 68, 0, 0, 1, 4) ++/* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */ ++#define DEV2G5_PCS1G_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 0, 0, 1, \ ++ 4) + + #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE BIT(4) + #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\ +@@ -3037,9 +3302,10 @@ enum sparx5_target { + #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\ + FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x) + +-/* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ +-#define DEV2G5_PCS1G_MODE_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 88, 0, 1, 68, 4, 0, 1, 4) ++/* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */ ++#define DEV2G5_PCS1G_MODE_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 4, 0, 1, \ ++ 4) + + #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA BIT(4) + #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\ +@@ -3059,9 +3325,10 @@ enum sparx5_target { + #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\ + FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x) + +-/* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ +-#define DEV2G5_PCS1G_SD_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 88, 0, 1, 68, 8, 0, 1, 4) ++/* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */ ++#define DEV2G5_PCS1G_SD_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 8, 0, 1, \ ++ 4) + + #define DEV2G5_PCS1G_SD_CFG_SD_SEL BIT(8) + #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\ +@@ -3081,9 +3348,10 @@ enum sparx5_target { + #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\ + FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x) + +-/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ +-#define DEV2G5_PCS1G_ANEG_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 88, 0, 1, 68, 12, 0, 1, 4) ++/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */ ++#define DEV2G5_PCS1G_ANEG_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 12, 0, 1,\ ++ 4) + + #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16) + #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\ +@@ -3109,9 +3377,10 @@ enum sparx5_target { + #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\ + FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x) + +-/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ +-#define DEV2G5_PCS1G_LB_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 88, 0, 1, 68, 20, 0, 1, 4) ++/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */ ++#define DEV2G5_PCS1G_LB_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 20, 0, 1,\ ++ 4) + + #define DEV2G5_PCS1G_LB_CFG_RA_ENA BIT(4) + #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\ +@@ -3131,9 +3400,10 @@ enum sparx5_target { + #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\ + FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x) + +-/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ +-#define DEV2G5_PCS1G_ANEG_STATUS(t) __REG(TARGET_DEV2G5,\ +- t, 65, 88, 0, 1, 68, 32, 0, 1, 4) ++/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */ ++#define DEV2G5_PCS1G_ANEG_STATUS(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 32, 0, 1,\ ++ 4) + + #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY GENMASK(31, 16) + #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\ +@@ -3159,9 +3429,10 @@ enum sparx5_target { + #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\ + FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x) + +-/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ +-#define DEV2G5_PCS1G_LINK_STATUS(t) __REG(TARGET_DEV2G5,\ +- t, 65, 88, 0, 1, 68, 40, 0, 1, 4) ++/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */ ++#define DEV2G5_PCS1G_LINK_STATUS(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 40, 0, 1,\ ++ 4) + + #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR GENMASK(15, 12) + #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\ +@@ -3187,9 +3458,10 @@ enum sparx5_target { + #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\ + FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x) + +-/* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ +-#define DEV2G5_PCS1G_STICKY(t) __REG(TARGET_DEV2G5,\ +- t, 65, 88, 0, 1, 68, 48, 0, 1, 4) ++/* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */ ++#define DEV2G5_PCS1G_STICKY(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 48, 0, 1,\ ++ 4) + + #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY BIT(4) + #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\ +@@ -3203,9 +3475,10 @@ enum sparx5_target { + #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\ + FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x) + +-/* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ +-#define DEV2G5_PCS_FX100_CFG(t) __REG(TARGET_DEV2G5,\ +- t, 65, 164, 0, 1, 4, 0, 0, 1, 4) ++/* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */ ++#define DEV2G5_PCS_FX100_CFG(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 164, 0, 1, 4, 0, 0, 1, \ ++ 4) + + #define DEV2G5_PCS_FX100_CFG_SD_SEL BIT(26) + #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\ +@@ -3285,9 +3558,10 @@ enum sparx5_target { + #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\ + FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x) + +-/* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ +-#define DEV2G5_PCS_FX100_STATUS(t) __REG(TARGET_DEV2G5,\ +- t, 65, 168, 0, 1, 4, 0, 0, 1, 4) ++/* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */ ++#define DEV2G5_PCS_FX100_STATUS(t) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 168, 0, 1, 4, 0, 0, 1, \ ++ 4) + + #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP GENMASK(11, 8) + #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\ +@@ -3337,9 +3611,9 @@ enum sparx5_target { + #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\ + FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ +-#define DEV5G_MAC_ENA_CFG(t) __REG(TARGET_DEV5G,\ +- t, 13, 0, 0, 1, 60, 0, 0, 1, 4) ++/* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ ++#define DEV5G_MAC_ENA_CFG(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 0, 0, 1, 4) + + #define DEV5G_MAC_ENA_CFG_RX_ENA BIT(4) + #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\ +@@ -3353,9 +3627,9 @@ enum sparx5_target { + #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\ + FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ +-#define DEV5G_MAC_MAXLEN_CFG(t) __REG(TARGET_DEV5G,\ +- t, 13, 0, 0, 1, 60, 8, 0, 1, 4) ++/* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */ ++#define DEV5G_MAC_MAXLEN_CFG(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 8, 0, 1, 4) + + #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK BIT(16) + #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\ +@@ -3369,9 +3643,10 @@ enum sparx5_target { + #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\ + FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x) + +-/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ +-#define DEV5G_MAC_ADV_CHK_CFG(t) __REG(TARGET_DEV5G,\ +- t, 13, 0, 0, 1, 60, 28, 0, 1, 4) ++/* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */ ++#define DEV5G_MAC_ADV_CHK_CFG(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 28, 0, 1, \ ++ 4) + + #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA BIT(24) + #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\ +@@ -3415,325 +3690,405 @@ enum sparx5_target { + #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\ + FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x) + +-/* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ +-#define DEV5G_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 0, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ +-#define DEV5G_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 4, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ +-#define DEV5G_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 8, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ +-#define DEV5G_RX_UC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 12, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ +-#define DEV5G_RX_MC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 16, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ +-#define DEV5G_RX_BC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 20, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ +-#define DEV5G_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 24, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ +-#define DEV5G_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 28, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ +-#define DEV5G_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 32, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ +-#define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 36, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ +-#define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 40, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ +-#define DEV5G_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 44, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ +-#define DEV5G_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 48, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ +-#define DEV5G_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 52, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ +-#define DEV5G_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 56, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ +-#define DEV5G_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 60, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ +-#define DEV5G_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 64, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ +-#define DEV5G_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 68, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ +-#define DEV5G_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 72, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ +-#define DEV5G_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 76, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ +-#define DEV5G_RX_IPG_SHRINK_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 80, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ +-#define DEV5G_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 84, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ +-#define DEV5G_TX_UC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 88, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ +-#define DEV5G_TX_MC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 92, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ +-#define DEV5G_TX_BC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 96, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ +-#define DEV5G_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 100, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ +-#define DEV5G_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 104, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ +-#define DEV5G_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 108, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ +-#define DEV5G_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 112, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ +-#define DEV5G_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 116, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ +-#define DEV5G_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 120, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ +-#define DEV5G_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 124, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ +-#define DEV5G_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 128, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ +-#define DEV5G_RX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 132, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ +-#define DEV5G_RX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 136, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ +-#define DEV5G_TX_TAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 140, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ +-#define DEV5G_TX_UNTAGGED_FRMS_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 144, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ +-#define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 148, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ +-#define DEV5G_PMAC_RX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 152, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ +-#define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 156, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ +-#define DEV5G_PMAC_RX_UC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 160, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ +-#define DEV5G_PMAC_RX_MC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 164, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ +-#define DEV5G_PMAC_RX_BC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 168, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ +-#define DEV5G_PMAC_RX_CRC_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 172, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ +-#define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 176, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ +-#define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 180, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ +-#define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 184, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ +-#define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 188, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ +-#define DEV5G_PMAC_RX_OVERSIZE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 192, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ +-#define DEV5G_PMAC_RX_JABBERS_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 196, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ +-#define DEV5G_PMAC_RX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 200, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ +-#define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 204, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ +-#define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 208, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ +-#define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 212, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ +-#define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 216, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ +-#define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 220, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ +-#define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 224, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ +-#define DEV5G_PMAC_TX_PAUSE_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 228, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ +-#define DEV5G_PMAC_TX_UC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 232, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ +-#define DEV5G_PMAC_TX_MC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 236, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ +-#define DEV5G_PMAC_TX_BC_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 240, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ +-#define DEV5G_PMAC_TX_SIZE64_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 244, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ +-#define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 248, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ +-#define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 252, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ +-#define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 256, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ +-#define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 260, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ +-#define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 264, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ +-#define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 268, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ +-#define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 272, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ +-#define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 276, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ +-#define DEV5G_MM_RX_SMD_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 280, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ +-#define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 284, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ +-#define DEV5G_MM_RX_MERGE_FRAG_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 288, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ +-#define DEV5G_MM_TX_PFRAGMENT_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 292, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ +-#define DEV5G_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 296, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ +-#define DEV5G_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 300, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ +-#define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 304, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ +-#define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 60, 0, 1, 312, 308, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ +-#define DEV5G_RX_IN_BYTES_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 0, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ +-#define DEV5G_RX_IN_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 4, 0, 1, 4) ++/* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */ ++#define DEV5G_RX_SYMBOL_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 0, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */ ++#define DEV5G_RX_PAUSE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 4, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */ ++#define DEV5G_RX_UNSUP_OPCODE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 8, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */ ++#define DEV5G_RX_UC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 12, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */ ++#define DEV5G_RX_MC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 16, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */ ++#define DEV5G_RX_BC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 20, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */ ++#define DEV5G_RX_CRC_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 24, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */ ++#define DEV5G_RX_UNDERSIZE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 28, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */ ++#define DEV5G_RX_FRAGMENTS_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 32, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */ ++#define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 36, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */ ++#define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 40, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */ ++#define DEV5G_RX_OVERSIZE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 44, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */ ++#define DEV5G_RX_JABBERS_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 48, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */ ++#define DEV5G_RX_SIZE64_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 52, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */ ++#define DEV5G_RX_SIZE65TO127_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 56, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */ ++#define DEV5G_RX_SIZE128TO255_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 60, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */ ++#define DEV5G_RX_SIZE256TO511_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 64, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */ ++#define DEV5G_RX_SIZE512TO1023_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 68, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */ ++#define DEV5G_RX_SIZE1024TO1518_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 72, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */ ++#define DEV5G_RX_SIZE1519TOMAX_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 76, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */ ++#define DEV5G_RX_IPG_SHRINK_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 80, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */ ++#define DEV5G_TX_PAUSE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 84, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */ ++#define DEV5G_TX_UC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 88, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */ ++#define DEV5G_TX_MC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 92, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */ ++#define DEV5G_TX_BC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 96, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */ ++#define DEV5G_TX_SIZE64_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 100, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */ ++#define DEV5G_TX_SIZE65TO127_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 104, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */ ++#define DEV5G_TX_SIZE128TO255_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 108, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */ ++#define DEV5G_TX_SIZE256TO511_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 112, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */ ++#define DEV5G_TX_SIZE512TO1023_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 116, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */ ++#define DEV5G_TX_SIZE1024TO1518_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 120, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */ ++#define DEV5G_TX_SIZE1519TOMAX_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 124, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */ ++#define DEV5G_RX_ALIGNMENT_LOST_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 128, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */ ++#define DEV5G_RX_TAGGED_FRMS_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 132, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */ ++#define DEV5G_RX_UNTAGGED_FRMS_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 136, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */ ++#define DEV5G_TX_TAGGED_FRMS_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 140, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */ ++#define DEV5G_TX_UNTAGGED_FRMS_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 144, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */ ++#define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 148, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */ ++#define DEV5G_PMAC_RX_PAUSE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 152, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */ ++#define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 156, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */ ++#define DEV5G_PMAC_RX_UC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 160, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */ ++#define DEV5G_PMAC_RX_MC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 164, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */ ++#define DEV5G_PMAC_RX_BC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 168, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */ ++#define DEV5G_PMAC_RX_CRC_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 172, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */ ++#define DEV5G_PMAC_RX_UNDERSIZE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 176, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */ ++#define DEV5G_PMAC_RX_FRAGMENTS_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 180, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */ ++#define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 184, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */ ++#define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 188, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */ ++#define DEV5G_PMAC_RX_OVERSIZE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 192, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */ ++#define DEV5G_PMAC_RX_JABBERS_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 196, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */ ++#define DEV5G_PMAC_RX_SIZE64_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 200, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */ ++#define DEV5G_PMAC_RX_SIZE65TO127_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 204, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */ ++#define DEV5G_PMAC_RX_SIZE128TO255_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 208, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */ ++#define DEV5G_PMAC_RX_SIZE256TO511_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 212, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */ ++#define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 216, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */ ++#define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 220, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */ ++#define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 224, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */ ++#define DEV5G_PMAC_TX_PAUSE_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 228, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */ ++#define DEV5G_PMAC_TX_UC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 232, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */ ++#define DEV5G_PMAC_TX_MC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 236, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */ ++#define DEV5G_PMAC_TX_BC_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 240, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */ ++#define DEV5G_PMAC_TX_SIZE64_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 244, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */ ++#define DEV5G_PMAC_TX_SIZE65TO127_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 248, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */ ++#define DEV5G_PMAC_TX_SIZE128TO255_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 252, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */ ++#define DEV5G_PMAC_TX_SIZE256TO511_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 256, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */ ++#define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 260, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */ ++#define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 264, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */ ++#define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 268, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */ ++#define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 272, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */ ++#define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 276, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */ ++#define DEV5G_MM_RX_SMD_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 280, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */ ++#define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 284, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */ ++#define DEV5G_MM_RX_MERGE_FRAG_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 288, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */ ++#define DEV5G_MM_TX_PFRAGMENT_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 292, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */ ++#define DEV5G_RX_HIH_CKSM_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 296, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */ ++#define DEV5G_RX_XGMII_PROT_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 300, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */ ++#define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 304, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */ ++#define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 308, 0, 1,\ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */ ++#define DEV5G_RX_IN_BYTES_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 0, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */ ++#define DEV5G_RX_IN_BYTES_MSB_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 4, 0, 1, \ ++ 4) + + #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0) + #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\ +@@ -3741,13 +4096,15 @@ enum sparx5_target { + #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x) + +-/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ +-#define DEV5G_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 8, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ +-#define DEV5G_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 12, 0, 1, 4) ++/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */ ++#define DEV5G_RX_OK_BYTES_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 8, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */ ++#define DEV5G_RX_OK_BYTES_MSB_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 12, 0, 1, \ ++ 4) + + #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) + #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\ +@@ -3755,13 +4112,15 @@ enum sparx5_target { + #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x) + +-/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ +-#define DEV5G_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 16, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ +-#define DEV5G_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 20, 0, 1, 4) ++/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */ ++#define DEV5G_RX_BAD_BYTES_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 16, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */ ++#define DEV5G_RX_BAD_BYTES_MSB_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 20, 0, 1, \ ++ 4) + + #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) + #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\ +@@ -3769,13 +4128,15 @@ enum sparx5_target { + #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x) + +-/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ +-#define DEV5G_TX_OUT_BYTES_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 24, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ +-#define DEV5G_TX_OUT_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 28, 0, 1, 4) ++/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */ ++#define DEV5G_TX_OUT_BYTES_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 24, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */ ++#define DEV5G_TX_OUT_BYTES_MSB_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 28, 0, 1, \ ++ 4) + + #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0) + #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\ +@@ -3783,13 +4144,15 @@ enum sparx5_target { + #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x) + +-/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ +-#define DEV5G_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 32, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ +-#define DEV5G_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 36, 0, 1, 4) ++/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */ ++#define DEV5G_TX_OK_BYTES_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 32, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */ ++#define DEV5G_TX_OK_BYTES_MSB_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 36, 0, 1, \ ++ 4) + + #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) + #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\ +@@ -3797,13 +4160,15 @@ enum sparx5_target { + #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x) + +-/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ +-#define DEV5G_PMAC_RX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 40, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ +-#define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 44, 0, 1, 4) ++/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */ ++#define DEV5G_PMAC_RX_OK_BYTES_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 40, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */ ++#define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 44, 0, 1, \ ++ 4) + + #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0) + #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\ +@@ -3811,13 +4176,15 @@ enum sparx5_target { + #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x) + +-/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ +-#define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 48, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ +-#define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 52, 0, 1, 4) ++/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */ ++#define DEV5G_PMAC_RX_BAD_BYTES_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 48, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */ ++#define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 52, 0, 1, \ ++ 4) + + #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0) + #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\ +@@ -3825,13 +4192,15 @@ enum sparx5_target { + #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x) + +-/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ +-#define DEV5G_PMAC_TX_OK_BYTES_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 56, 0, 1, 4) +- +-/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ +-#define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) __REG(TARGET_DEV5G,\ +- t, 13, 372, 0, 1, 64, 60, 0, 1, 4) ++/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */ ++#define DEV5G_PMAC_TX_OK_BYTES_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 56, 0, 1, \ ++ 4) ++ ++/* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */ ++#define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 60, 0, 1, \ ++ 4) + + #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0) + #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\ +@@ -3839,9 +4208,10 @@ enum sparx5_target { + #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\ + FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x) + +-/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ +-#define DEV5G_DEV_RST_CTRL(t) __REG(TARGET_DEV5G,\ +- t, 13, 436, 0, 1, 52, 0, 0, 1, 4) ++/* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */ ++#define DEV5G_DEV_RST_CTRL(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 0, 0, 1, \ ++ 4) + + #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA BIT(28) + #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\ +@@ -3897,9 +4267,9 @@ enum sparx5_target { + #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ + FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) + +-/* DSM:RAM_CTRL:RAM_INIT */ +-#define DSM_RAM_INIT __REG(TARGET_DSM,\ +- 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) ++/* DSM:RAM_CTRL:RAM_INIT */ ++#define DSM_RAM_INIT \ ++ __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) + + #define DSM_RAM_INIT_RAM_INIT BIT(1) + #define DSM_RAM_INIT_RAM_INIT_SET(x)\ +@@ -3913,9 +4283,10 @@ enum sparx5_target { + #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\ + FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x) + +-/* DSM:CFG:BUF_CFG */ +-#define DSM_BUF_CFG(r) __REG(TARGET_DSM,\ +- 0, 1, 20, 0, 1, 3528, 0, r, 67, 4) ++/* DSM:CFG:BUF_CFG */ ++#define DSM_BUF_CFG(r) \ ++ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r, \ ++ regs->rcnt[RC_DSM_BUF_CFG], 4) + + #define DSM_BUF_CFG_CSC_STAT_DIS BIT(13) + #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\ +@@ -3941,9 +4312,10 @@ enum sparx5_target { + #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\ + FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x) + +-/* DSM:CFG:DEV_TX_STOP_WM_CFG */ +-#define DSM_DEV_TX_STOP_WM_CFG(r) __REG(TARGET_DSM,\ +- 0, 1, 20, 0, 1, 3528, 1360, r, 67, 4) ++/* DSM:CFG:DEV_TX_STOP_WM_CFG */ ++#define DSM_DEV_TX_STOP_WM_CFG(r) \ ++ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, \ ++ regs->rcnt[RC_DSM_DEV_TX_STOP_WM_CFG], 4) + + #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA BIT(9) + #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\ +@@ -3969,9 +4341,10 @@ enum sparx5_target { + #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\ + FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x) + +-/* DSM:CFG:RX_PAUSE_CFG */ +-#define DSM_RX_PAUSE_CFG(r) __REG(TARGET_DSM,\ +- 0, 1, 20, 0, 1, 3528, 1628, r, 67, 4) ++/* DSM:CFG:RX_PAUSE_CFG */ ++#define DSM_RX_PAUSE_CFG(r) \ ++ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r, \ ++ regs->rcnt[RC_DSM_RX_PAUSE_CFG], 4) + + #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN BIT(1) + #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\ +@@ -3985,9 +4358,10 @@ enum sparx5_target { + #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\ + FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x) + +-/* DSM:CFG:MAC_CFG */ +-#define DSM_MAC_CFG(r) __REG(TARGET_DSM,\ +- 0, 1, 20, 0, 1, 3528, 2432, r, 67, 4) ++/* DSM:CFG:MAC_CFG */ ++#define DSM_MAC_CFG(r) \ ++ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r, \ ++ regs->rcnt[RC_DSM_MAC_CFG], 4) + + #define DSM_MAC_CFG_TX_PAUSE_VAL GENMASK(31, 16) + #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\ +@@ -4013,9 +4387,10 @@ enum sparx5_target { + #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\ + FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x) + +-/* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ +-#define DSM_MAC_ADDR_BASE_HIGH_CFG(r) __REG(TARGET_DSM,\ +- 0, 1, 20, 0, 1, 3528, 2700, r, 65, 4) ++/* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */ ++#define DSM_MAC_ADDR_BASE_HIGH_CFG(r) \ ++ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r, \ ++ regs->rcnt[RC_DSM_MAC_ADDR_BASE_HIGH_CFG], 4) + + #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0) + #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\ +@@ -4023,9 +4398,10 @@ enum sparx5_target { + #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\ + FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x) + +-/* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ +-#define DSM_MAC_ADDR_BASE_LOW_CFG(r) __REG(TARGET_DSM,\ +- 0, 1, 20, 0, 1, 3528, 2960, r, 65, 4) ++/* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */ ++#define DSM_MAC_ADDR_BASE_LOW_CFG(r) \ ++ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r, \ ++ regs->rcnt[RC_DSM_MAC_ADDR_BASE_LOW_CFG], 4) + + #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW GENMASK(23, 0) + #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\ +@@ -4033,9 +4409,10 @@ enum sparx5_target { + #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\ + FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x) + +-/* DSM:CFG:TAXI_CAL_CFG */ +-#define DSM_TAXI_CAL_CFG(r) __REG(TARGET_DSM,\ +- 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4) ++/* DSM:CFG:TAXI_CAL_CFG */ ++#define DSM_TAXI_CAL_CFG(r) \ ++ __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, \ ++ regs->rcnt[RC_DSM_TAXI_CAL_CFG], 4) + + #define DSM_TAXI_CAL_CFG_CAL_IDX GENMASK(20, 15) + #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\ +@@ -4067,9 +4444,10 @@ enum sparx5_target { + #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ + FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) + +-/* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ +-#define EACL_VCAP_ES2_KEY_SEL(g, r) __REG(TARGET_EACL,\ +- 0, 1, 149504, g, 138, 8, 0, r, 2, 4) ++/* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ ++#define EACL_VCAP_ES2_KEY_SEL(g, r) \ ++ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \ ++ g, regs->gcnt[GC_EACL_ES2_KEY_SELECT_PROFILE], 8, 0, r, 2, 4) + + #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL GENMASK(7, 5) + #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\ +@@ -4095,13 +4473,15 @@ enum sparx5_target { + #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\ + FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x) + +-/* EACL:CNT_TBL:ES2_CNT */ +-#define EACL_ES2_CNT(g) __REG(TARGET_EACL,\ +- 0, 1, 122880, g, 2048, 4, 0, 0, 1, 4) +- +-/* EACL:POL_CFG:POL_EACL_CFG */ +-#define EACL_POL_EACL_CFG __REG(TARGET_EACL,\ +- 0, 1, 150608, 0, 1, 780, 768, 0, 1, 4) ++/* EACL:CNT_TBL:ES2_CNT */ ++#define EACL_ES2_CNT(g) \ ++ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_CNT_TBL], g, \ ++ regs->gcnt[GC_EACL_CNT_TBL], 4, 0, 0, 1, 4) ++ ++/* EACL:POL_CFG:POL_EACL_CFG */ ++#define EACL_POL_EACL_CFG \ ++ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_POL_CFG], 0, 1, 780, 768, \ ++ 0, 1, 4) + + #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5) + #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\ +@@ -4139,9 +4519,10 @@ enum sparx5_target { + #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\ + FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x) + +-/* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ +-#define EACL_SEC_LOOKUP_STICKY(r) __REG(TARGET_EACL,\ +- 0, 1, 118696, 0, 1, 8, 0, r, 2, 4) ++/* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */ ++#define EACL_SEC_LOOKUP_STICKY(r) \ ++ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_STICKY], 0, 1, 8, 0, \ ++ r, 2, 4) + + #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7) + #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\ +@@ -4191,9 +4572,10 @@ enum sparx5_target { + #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\ + FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x) + +-/* EACL:RAM_CTRL:RAM_INIT */ +-#define EACL_RAM_INIT __REG(TARGET_EACL,\ +- 0, 1, 118736, 0, 1, 4, 0, 0, 1, 4) ++/* EACL:RAM_CTRL:RAM_INIT */ ++#define EACL_RAM_INIT \ ++ __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_RAM_CTRL], 0, 1, 4, 0, 0, \ ++ 1, 4) + + #define EACL_RAM_INIT_RAM_INIT BIT(1) + #define EACL_RAM_INIT_RAM_INIT_SET(x)\ +@@ -4207,9 +4589,10 @@ enum sparx5_target { + #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\ + FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x) + +-/* FDMA:FDMA:FDMA_CH_ACTIVATE */ +-#define FDMA_CH_ACTIVATE __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 0, 0, 1, 4) ++/* FDMA:FDMA:FDMA_CH_ACTIVATE */ ++#define FDMA_CH_ACTIVATE \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 0, 0, 1, \ ++ 4) + + #define FDMA_CH_ACTIVATE_CH_ACTIVATE GENMASK(7, 0) + #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\ +@@ -4217,9 +4600,10 @@ enum sparx5_target { + #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\ + FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x) + +-/* FDMA:FDMA:FDMA_CH_RELOAD */ +-#define FDMA_CH_RELOAD __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 4, 0, 1, 4) ++/* FDMA:FDMA:FDMA_CH_RELOAD */ ++#define FDMA_CH_RELOAD \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 4, 0, 1, \ ++ 4) + + #define FDMA_CH_RELOAD_CH_RELOAD GENMASK(7, 0) + #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\ +@@ -4227,9 +4611,10 @@ enum sparx5_target { + #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\ + FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x) + +-/* FDMA:FDMA:FDMA_CH_DISABLE */ +-#define FDMA_CH_DISABLE __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 8, 0, 1, 4) ++/* FDMA:FDMA:FDMA_CH_DISABLE */ ++#define FDMA_CH_DISABLE \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 8, 0, 1, \ ++ 4) + + #define FDMA_CH_DISABLE_CH_DISABLE GENMASK(7, 0) + #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\ +@@ -4237,49 +4622,58 @@ enum sparx5_target { + #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\ + FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x) + +-/* FDMA:FDMA:FDMA_DCB_LLP */ +-#define FDMA_DCB_LLP(r) __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 52, r, 8, 4) +- +-/* FDMA:FDMA:FDMA_DCB_LLP1 */ +-#define FDMA_DCB_LLP1(r) __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 84, r, 8, 4) +- +-/* FDMA:FDMA:FDMA_DCB_LLP_PREV */ +-#define FDMA_DCB_LLP_PREV(r) __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 116, r, 8, 4) +- +-/* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ +-#define FDMA_DCB_LLP_PREV1(r) __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 148, r, 8, 4) +- +-/* FDMA:FDMA:FDMA_CH_CFG */ +-#define FDMA_CH_CFG(r) __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 224, r, 8, 4) ++/* FDMA:FDMA:FDMA_DCB_LLP */ ++#define FDMA_DCB_LLP(r) \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 52, r, 8, \ ++ 4) ++ ++/* FDMA:FDMA:FDMA_DCB_LLP1 */ ++#define FDMA_DCB_LLP1(r) \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 84, r, 8, \ ++ 4) ++ ++/* FDMA:FDMA:FDMA_DCB_LLP_PREV */ ++#define FDMA_DCB_LLP_PREV(r) \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 116, r, 8,\ ++ 4) ++ ++/* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */ ++#define FDMA_DCB_LLP_PREV1(r) \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 148, r, 8,\ ++ 4) ++ ++/* FDMA:FDMA:FDMA_CH_CFG */ ++#define FDMA_CH_CFG(r) \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 224, r, 8,\ ++ 4) + +-#define FDMA_CH_CFG_CH_XTR_STATUS_MODE BIT(7) ++#define FDMA_CH_CFG_CH_XTR_STATUS_MODE\ ++ BIT(regs->fpos[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE]) + #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\ +- FIELD_PREP(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) ++ spx5_field_prep(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) + #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\ +- FIELD_GET(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) ++ spx5_field_get(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x) + +-#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY BIT(6) ++#define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY\ ++ BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY]) + #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\ +- FIELD_PREP(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) ++ spx5_field_prep(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) + #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\ +- FIELD_GET(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) ++ spx5_field_get(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x) + +-#define FDMA_CH_CFG_CH_INJ_PORT BIT(5) ++#define FDMA_CH_CFG_CH_INJ_PORT\ ++ BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INJ_PORT]) + #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\ +- FIELD_PREP(FDMA_CH_CFG_CH_INJ_PORT, x) ++ spx5_field_prep(FDMA_CH_CFG_CH_INJ_PORT, x) + #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\ +- FIELD_GET(FDMA_CH_CFG_CH_INJ_PORT, x) ++ spx5_field_get(FDMA_CH_CFG_CH_INJ_PORT, x) + +-#define FDMA_CH_CFG_CH_DCB_DB_CNT GENMASK(4, 1) ++#define FDMA_CH_CFG_CH_DCB_DB_CNT\ ++ GENMASK(regs->fsize[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] + 1 - 1, 1) + #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\ +- FIELD_PREP(FDMA_CH_CFG_CH_DCB_DB_CNT, x) ++ spx5_field_prep(FDMA_CH_CFG_CH_DCB_DB_CNT, x) + #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\ +- FIELD_GET(FDMA_CH_CFG_CH_DCB_DB_CNT, x) ++ spx5_field_get(FDMA_CH_CFG_CH_DCB_DB_CNT, x) + + #define FDMA_CH_CFG_CH_MEM BIT(0) + #define FDMA_CH_CFG_CH_MEM_SET(x)\ +@@ -4287,9 +4681,10 @@ enum sparx5_target { + #define FDMA_CH_CFG_CH_MEM_GET(x)\ + FIELD_GET(FDMA_CH_CFG_CH_MEM, x) + +-/* FDMA:FDMA:FDMA_CH_TRANSLATE */ +-#define FDMA_CH_TRANSLATE(r) __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 256, r, 8, 4) ++/* FDMA:FDMA:FDMA_CH_TRANSLATE */ ++#define FDMA_CH_TRANSLATE(r) \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 256, r, 8,\ ++ 4) + + #define FDMA_CH_TRANSLATE_OFFSET GENMASK(15, 0) + #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\ +@@ -4297,9 +4692,10 @@ enum sparx5_target { + #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\ + FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x) + +-/* FDMA:FDMA:FDMA_XTR_CFG */ +-#define FDMA_XTR_CFG __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 364, 0, 1, 4) ++/* FDMA:FDMA:FDMA_XTR_CFG */ ++#define FDMA_XTR_CFG \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 364, 0, 1,\ ++ 4) + + #define FDMA_XTR_CFG_XTR_FIFO_WM GENMASK(15, 11) + #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\ +@@ -4313,9 +4709,10 @@ enum sparx5_target { + #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\ + FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x) + +-/* FDMA:FDMA:FDMA_PORT_CTRL */ +-#define FDMA_PORT_CTRL(r) __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 376, r, 2, 4) ++/* FDMA:FDMA:FDMA_PORT_CTRL */ ++#define FDMA_PORT_CTRL(r) \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 376, r, 2,\ ++ 4) + + #define FDMA_PORT_CTRL_INJ_STOP BIT(4) + #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\ +@@ -4347,9 +4744,10 @@ enum sparx5_target { + #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\ + FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x) + +-/* FDMA:FDMA:FDMA_INTR_DCB */ +-#define FDMA_INTR_DCB __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 384, 0, 1, 4) ++/* FDMA:FDMA:FDMA_INTR_DCB */ ++#define FDMA_INTR_DCB \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 384, 0, 1,\ ++ 4) + + #define FDMA_INTR_DCB_INTR_DCB GENMASK(7, 0) + #define FDMA_INTR_DCB_INTR_DCB_SET(x)\ +@@ -4357,9 +4755,10 @@ enum sparx5_target { + #define FDMA_INTR_DCB_INTR_DCB_GET(x)\ + FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x) + +-/* FDMA:FDMA:FDMA_INTR_DCB_ENA */ +-#define FDMA_INTR_DCB_ENA __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 388, 0, 1, 4) ++/* FDMA:FDMA:FDMA_INTR_DCB_ENA */ ++#define FDMA_INTR_DCB_ENA \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 388, 0, 1,\ ++ 4) + + #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA GENMASK(7, 0) + #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\ +@@ -4367,9 +4766,10 @@ enum sparx5_target { + #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\ + FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x) + +-/* FDMA:FDMA:FDMA_INTR_DB */ +-#define FDMA_INTR_DB __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 392, 0, 1, 4) ++/* FDMA:FDMA:FDMA_INTR_DB */ ++#define FDMA_INTR_DB \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 392, 0, 1,\ ++ 4) + + #define FDMA_INTR_DB_INTR_DB GENMASK(7, 0) + #define FDMA_INTR_DB_INTR_DB_SET(x)\ +@@ -4377,9 +4777,10 @@ enum sparx5_target { + #define FDMA_INTR_DB_INTR_DB_GET(x)\ + FIELD_GET(FDMA_INTR_DB_INTR_DB, x) + +-/* FDMA:FDMA:FDMA_INTR_DB_ENA */ +-#define FDMA_INTR_DB_ENA __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 396, 0, 1, 4) ++/* FDMA:FDMA:FDMA_INTR_DB_ENA */ ++#define FDMA_INTR_DB_ENA \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 396, 0, 1,\ ++ 4) + + #define FDMA_INTR_DB_ENA_INTR_DB_ENA GENMASK(7, 0) + #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\ +@@ -4387,9 +4788,10 @@ enum sparx5_target { + #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\ + FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x) + +-/* FDMA:FDMA:FDMA_INTR_ERR */ +-#define FDMA_INTR_ERR __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 400, 0, 1, 4) ++/* FDMA:FDMA:FDMA_INTR_ERR */ ++#define FDMA_INTR_ERR \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 400, 0, 1,\ ++ 4) + + #define FDMA_INTR_ERR_INTR_PORT_ERR GENMASK(9, 8) + #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\ +@@ -4403,9 +4805,10 @@ enum sparx5_target { + #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\ + FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x) + +-/* FDMA:FDMA:FDMA_ERRORS */ +-#define FDMA_ERRORS __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 412, 0, 1, 4) ++/* FDMA:FDMA:FDMA_ERRORS */ ++#define FDMA_ERRORS \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 412, 0, 1,\ ++ 4) + + #define FDMA_ERRORS_ERR_XTR_WR GENMASK(31, 30) + #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\ +@@ -4455,9 +4858,10 @@ enum sparx5_target { + #define FDMA_ERRORS_ERR_CH_WR_GET(x)\ + FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x) + +-/* FDMA:FDMA:FDMA_ERRORS_2 */ +-#define FDMA_ERRORS_2 __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 416, 0, 1, 4) ++/* FDMA:FDMA:FDMA_ERRORS_2 */ ++#define FDMA_ERRORS_2 \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 416, 0, 1,\ ++ 4) + + #define FDMA_ERRORS_2_ERR_XTR_FRAG GENMASK(1, 0) + #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\ +@@ -4465,9 +4869,10 @@ enum sparx5_target { + #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\ + FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x) + +-/* FDMA:FDMA:FDMA_CTRL */ +-#define FDMA_CTRL __REG(TARGET_FDMA,\ +- 0, 1, 8, 0, 1, 428, 424, 0, 1, 4) ++/* FDMA:FDMA:FDMA_CTRL */ ++#define FDMA_CTRL \ ++ __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 424, 0, 1,\ ++ 4) + + #define FDMA_CTRL_NRESET BIT(0) + #define FDMA_CTRL_NRESET_SET(x)\ +@@ -4475,9 +4880,10 @@ enum sparx5_target { + #define FDMA_CTRL_NRESET_GET(x)\ + FIELD_GET(FDMA_CTRL_NRESET, x) + +-/* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ +-#define GCB_CHIP_ID __REG(TARGET_GCB,\ +- 0, 1, 0, 0, 1, 424, 0, 0, 1, 4) ++/* DEVCPU_GCB:CHIP_REGS:CHIP_ID */ ++#define GCB_CHIP_ID \ ++ __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 0, 0, \ ++ 1, 4) + + #define GCB_CHIP_ID_REV_ID GENMASK(31, 28) + #define GCB_CHIP_ID_REV_ID_SET(x)\ +@@ -4503,10 +4909,12 @@ enum sparx5_target { + #define GCB_CHIP_ID_ONE_GET(x)\ + FIELD_GET(GCB_CHIP_ID_ONE, x) + +-/* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ +-#define GCB_SOFT_RST __REG(TARGET_GCB,\ +- 0, 1, 0, 0, 1, 424, 8, 0, 1, 4) ++/* DEVCPU_GCB:CHIP_REGS:SOFT_RST */ ++#define GCB_SOFT_RST \ ++ __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ ++ regs->raddr[RA_GCB_SOFT_RST], 0, 1, 4) + ++/* SPARX5 ONLY */ + #define GCB_SOFT_RST_SOFT_NON_CFG_RST BIT(2) + #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\ + FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x) +@@ -4525,9 +4933,11 @@ enum sparx5_target { + #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\ + FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x) + +-/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ +-#define GCB_HW_SGPIO_SD_CFG __REG(TARGET_GCB,\ +- 0, 1, 0, 0, 1, 424, 20, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */ ++#define GCB_HW_SGPIO_SD_CFG \ ++ __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 20, 0, \ ++ 1, 4) + + #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA BIT(1) + #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\ +@@ -4541,19 +4951,23 @@ enum sparx5_target { + #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\ + FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x) + +-/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ +-#define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) __REG(TARGET_GCB,\ +- 0, 1, 0, 0, 1, 424, 24, r, 65, 4) ++/* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */ ++#define GCB_HW_SGPIO_TO_SD_MAP_CFG(r) \ ++ __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], \ ++ regs->raddr[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG], r, \ ++ regs->rcnt[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG], 4) + +-#define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL GENMASK(8, 0) ++#define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL\ ++ GENMASK(regs->fsize[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] + 0 - 1, 0) + #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\ +- FIELD_PREP(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) ++ spx5_field_prep(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) + #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\ +- FIELD_GET(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) ++ spx5_field_get(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x) + +-/* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ +-#define GCB_SIO_CLOCK(g) __REG(TARGET_GCB,\ +- 0, 1, 876, g, 3, 280, 20, 0, 1, 4) ++/* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */ ++#define GCB_SIO_CLOCK(g) \ ++ __REG(TARGET_GCB, 0, 1, regs->gaddr[GA_GCB_SIO_CTRL], g, \ ++ regs->gcnt[GC_GCB_SIO_CTRL], 280, 20, 0, 1, 4) + + #define GCB_SIO_CLOCK_SIO_CLK_FREQ GENMASK(19, 8) + #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\ +@@ -4567,9 +4981,10 @@ enum sparx5_target { + #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\ + FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x) + +-/* HSCH:HSCH_CFG:CIR_CFG */ +-#define HSCH_CIR_CFG(g) __REG(TARGET_HSCH,\ +- 0, 1, 0, g, 5040, 32, 0, 0, 1, 4) ++/* HSCH:HSCH_CFG:CIR_CFG */ ++#define HSCH_CIR_CFG(g) \ ++ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 0, 0, \ ++ 1, 4) + + #define HSCH_CIR_CFG_CIR_RATE GENMASK(22, 6) + #define HSCH_CIR_CFG_CIR_RATE_SET(x)\ +@@ -4583,9 +4998,10 @@ enum sparx5_target { + #define HSCH_CIR_CFG_CIR_BURST_GET(x)\ + FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x) + +-/* HSCH:HSCH_CFG:EIR_CFG */ +-#define HSCH_EIR_CFG(g) __REG(TARGET_HSCH,\ +- 0, 1, 0, g, 5040, 32, 4, 0, 1, 4) ++/* HSCH:HSCH_CFG:EIR_CFG */ ++#define HSCH_EIR_CFG(g) \ ++ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 4, 0, \ ++ 1, 4) + + #define HSCH_EIR_CFG_EIR_RATE GENMASK(22, 6) + #define HSCH_EIR_CFG_EIR_RATE_SET(x)\ +@@ -4599,15 +5015,17 @@ enum sparx5_target { + #define HSCH_EIR_CFG_EIR_BURST_GET(x)\ + FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x) + +-/* HSCH:HSCH_CFG:SE_CFG */ +-#define HSCH_SE_CFG(g) __REG(TARGET_HSCH,\ +- 0, 1, 0, g, 5040, 32, 8, 0, 1, 4) ++/* HSCH:HSCH_CFG:SE_CFG */ ++#define HSCH_SE_CFG(g) \ ++ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 8, 0, \ ++ 1, 4) + +-#define HSCH_SE_CFG_SE_DWRR_CNT GENMASK(12, 6) ++#define HSCH_SE_CFG_SE_DWRR_CNT\ ++ GENMASK(regs->fsize[FW_HSCH_SE_CFG_SE_DWRR_CNT] + 6 - 1, 6) + #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\ +- FIELD_PREP(HSCH_SE_CFG_SE_DWRR_CNT, x) ++ spx5_field_prep(HSCH_SE_CFG_SE_DWRR_CNT, x) + #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\ +- FIELD_GET(HSCH_SE_CFG_SE_DWRR_CNT, x) ++ spx5_field_get(HSCH_SE_CFG_SE_DWRR_CNT, x) + + #define HSCH_SE_CFG_SE_AVB_ENA BIT(5) + #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\ +@@ -4633,19 +5051,22 @@ enum sparx5_target { + #define HSCH_SE_CFG_SE_STOP_GET(x)\ + FIELD_GET(HSCH_SE_CFG_SE_STOP, x) + +-/* HSCH:HSCH_CFG:SE_CONNECT */ +-#define HSCH_SE_CONNECT(g) __REG(TARGET_HSCH,\ +- 0, 1, 0, g, 5040, 32, 12, 0, 1, 4) ++/* HSCH:HSCH_CFG:SE_CONNECT */ ++#define HSCH_SE_CONNECT(g) \ ++ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 12, 0,\ ++ 1, 4) + +-#define HSCH_SE_CONNECT_SE_LEAK_LINK GENMASK(15, 0) ++#define HSCH_SE_CONNECT_SE_LEAK_LINK\ ++ GENMASK(regs->fsize[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] + 0 - 1, 0) + #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\ +- FIELD_PREP(HSCH_SE_CONNECT_SE_LEAK_LINK, x) ++ spx5_field_prep(HSCH_SE_CONNECT_SE_LEAK_LINK, x) + #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\ +- FIELD_GET(HSCH_SE_CONNECT_SE_LEAK_LINK, x) ++ spx5_field_get(HSCH_SE_CONNECT_SE_LEAK_LINK, x) + +-/* HSCH:HSCH_CFG:SE_DLB_SENSE */ +-#define HSCH_SE_DLB_SENSE(g) __REG(TARGET_HSCH,\ +- 0, 1, 0, g, 5040, 32, 16, 0, 1, 4) ++/* HSCH:HSCH_CFG:SE_DLB_SENSE */ ++#define HSCH_SE_DLB_SENSE(g) \ ++ __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 16, 0,\ ++ 1, 4) + + #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO GENMASK(12, 10) + #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\ +@@ -4653,11 +5074,12 @@ enum sparx5_target { + #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\ + FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x) + +-#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT GENMASK(9, 3) ++#define HSCH_SE_DLB_SENSE_SE_DLB_DPORT\ ++ GENMASK(regs->fsize[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] + 3 - 1, 3) + #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\ +- FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) ++ spx5_field_prep(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) + #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\ +- FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) ++ spx5_field_get(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x) + + #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA BIT(2) + #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\ +@@ -4677,9 +5099,10 @@ enum sparx5_target { + #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\ + FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x) + +-/* HSCH:HSCH_DWRR:DWRR_ENTRY */ +-#define HSCH_DWRR_ENTRY(g) __REG(TARGET_HSCH,\ +- 0, 1, 162816, g, 72, 4, 0, 0, 1, 4) ++/* HSCH:HSCH_DWRR:DWRR_ENTRY */ ++#define HSCH_DWRR_ENTRY(g) \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_DWRR], g, \ ++ regs->gcnt[GC_HSCH_HSCH_DWRR], 4, 0, 0, 1, 4) + + #define HSCH_DWRR_ENTRY_DWRR_COST GENMASK(24, 20) + #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\ +@@ -4693,15 +5116,17 @@ enum sparx5_target { + #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\ + FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x) + +-/* HSCH:HSCH_MISC:HSCH_CFG_CFG */ +-#define HSCH_HSCH_CFG_CFG __REG(TARGET_HSCH,\ +- 0, 1, 163104, 0, 1, 648, 284, 0, 1, 4) ++/* HSCH:HSCH_MISC:HSCH_CFG_CFG */ ++#define HSCH_HSCH_CFG_CFG \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ ++ 284, 0, 1, 4) + +-#define HSCH_HSCH_CFG_CFG_CFG_SE_IDX GENMASK(26, 14) ++#define HSCH_HSCH_CFG_CFG_CFG_SE_IDX\ ++ GENMASK(regs->fsize[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] + 14 - 1, 14) + #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\ +- FIELD_PREP(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) ++ spx5_field_prep(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) + #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\ +- FIELD_GET(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) ++ spx5_field_get(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x) + + #define HSCH_HSCH_CFG_CFG_HSCH_LAYER GENMASK(13, 12) + #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\ +@@ -4715,9 +5140,11 @@ enum sparx5_target { + #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\ + FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x) + +-/* HSCH:HSCH_MISC:SYS_CLK_PER */ +-#define HSCH_SYS_CLK_PER __REG(TARGET_HSCH,\ +- 0, 1, 163104, 0, 1, 648, 640, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* HSCH:HSCH_MISC:SYS_CLK_PER */ ++#define HSCH_SYS_CLK_PER \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648, \ ++ 640, 0, 1, 4) + + #define HSCH_SYS_CLK_PER_100PS GENMASK(7, 0) + #define HSCH_SYS_CLK_PER_100PS_SET(x)\ +@@ -4725,9 +5152,10 @@ enum sparx5_target { + #define HSCH_SYS_CLK_PER_100PS_GET(x)\ + FIELD_GET(HSCH_SYS_CLK_PER_100PS, x) + +-/* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ +-#define HSCH_HSCH_TIMER_CFG(g, r) __REG(TARGET_HSCH,\ +- 0, 1, 161664, g, 4, 32, 0, r, 4, 4) ++/* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */ ++#define HSCH_HSCH_TIMER_CFG(g, r) \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ ++ 32, 0, r, 4, 4) + + #define HSCH_HSCH_TIMER_CFG_LEAK_TIME GENMASK(17, 0) + #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\ +@@ -4735,15 +5163,17 @@ enum sparx5_target { + #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\ + FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x) + +-/* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ +-#define HSCH_HSCH_LEAK_CFG(g, r) __REG(TARGET_HSCH,\ +- 0, 1, 161664, g, 4, 32, 16, r, 4, 4) ++/* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */ ++#define HSCH_HSCH_LEAK_CFG(g, r) \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4, \ ++ 32, 16, r, 4, 4) + +-#define HSCH_HSCH_LEAK_CFG_LEAK_FIRST GENMASK(16, 1) ++#define HSCH_HSCH_LEAK_CFG_LEAK_FIRST\ ++ GENMASK(regs->fsize[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] + 1 - 1, 1) + #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\ +- FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) ++ spx5_field_prep(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) + #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\ +- FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) ++ spx5_field_get(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x) + + #define HSCH_HSCH_LEAK_CFG_LEAK_ERR BIT(0) + #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\ +@@ -4751,9 +5181,10 @@ enum sparx5_target { + #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\ + FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x) + +-/* HSCH:SYSTEM:FLUSH_CTRL */ +-#define HSCH_FLUSH_CTRL __REG(TARGET_HSCH,\ +- 0, 1, 184000, 0, 1, 312, 4, 0, 1, 4) ++/* HSCH:SYSTEM:FLUSH_CTRL */ ++#define HSCH_FLUSH_CTRL \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 4, 0, \ ++ 1, 4) + + #define HSCH_FLUSH_CTRL_FLUSH_ENA BIT(27) + #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\ +@@ -4773,11 +5204,12 @@ enum sparx5_target { + #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\ + FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x) + +-#define HSCH_FLUSH_CTRL_FLUSH_PORT GENMASK(24, 18) ++#define HSCH_FLUSH_CTRL_FLUSH_PORT\ ++ GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] + 18 - 1, 18) + #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\ +- FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_PORT, x) ++ spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_PORT, x) + #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\ +- FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_PORT, x) ++ spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_PORT, x) + + #define HSCH_FLUSH_CTRL_FLUSH_QUEUE BIT(17) + #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\ +@@ -4791,15 +5223,17 @@ enum sparx5_target { + #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\ + FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x) + +-#define HSCH_FLUSH_CTRL_FLUSH_HIER GENMASK(15, 0) ++#define HSCH_FLUSH_CTRL_FLUSH_HIER\ ++ GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] + 0 - 1, 0) + #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\ +- FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_HIER, x) ++ spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_HIER, x) + #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\ +- FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_HIER, x) ++ spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_HIER, x) + +-/* HSCH:SYSTEM:PORT_MODE */ +-#define HSCH_PORT_MODE(r) __REG(TARGET_HSCH,\ +- 0, 1, 184000, 0, 1, 312, 8, r, 70, 4) ++/* HSCH:SYSTEM:PORT_MODE */ ++#define HSCH_PORT_MODE(r) \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 8, r, \ ++ regs->rcnt[RC_HSCH_PORT_MODE], 4) + + #define HSCH_PORT_MODE_DEQUEUE_DIS BIT(4) + #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\ +@@ -4831,9 +5265,10 @@ enum sparx5_target { + #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\ + FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x) + +-/* HSCH:SYSTEM:OUTB_SHARE_ENA */ +-#define HSCH_OUTB_SHARE_ENA(r) __REG(TARGET_HSCH,\ +- 0, 1, 184000, 0, 1, 312, 288, r, 5, 4) ++/* HSCH:SYSTEM:OUTB_SHARE_ENA */ ++#define HSCH_OUTB_SHARE_ENA(r) \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 288, \ ++ r, 5, 4) + + #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA GENMASK(7, 0) + #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\ +@@ -4841,9 +5276,10 @@ enum sparx5_target { + #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\ + FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x) + +-/* HSCH:MMGT:RESET_CFG */ +-#define HSCH_RESET_CFG __REG(TARGET_HSCH,\ +- 0, 1, 162368, 0, 1, 16, 8, 0, 1, 4) ++/* HSCH:MMGT:RESET_CFG */ ++#define HSCH_RESET_CFG \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_MMGT], 0, 1, 16, 8, 0, 1, \ ++ 4) + + #define HSCH_RESET_CFG_CORE_ENA BIT(0) + #define HSCH_RESET_CFG_CORE_ENA_SET(x)\ +@@ -4851,9 +5287,10 @@ enum sparx5_target { + #define HSCH_RESET_CFG_CORE_ENA_GET(x)\ + FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x) + +-/* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ +-#define HSCH_TAS_STATEMACHINE_CFG __REG(TARGET_HSCH,\ +- 0, 1, 162384, 0, 1, 12, 8, 0, 1, 4) ++/* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */ ++#define HSCH_TAS_STATEMACHINE_CFG \ ++ __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_TAS_CONFIG], 0, 1, \ ++ regs->gsize[GW_HSCH_TAS_CONFIG], 8, 0, 1, 4) + + #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY GENMASK(7, 0) + #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\ +@@ -4861,9 +5298,9 @@ enum sparx5_target { + #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ + FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) + +-/* LRN:COMMON:COMMON_ACCESS_CTRL */ +-#define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) ++/* LRN:COMMON:COMMON_ACCESS_CTRL */ ++#define LRN_COMMON_ACCESS_CTRL \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) + + #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20) + #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\ +@@ -4877,11 +5314,12 @@ enum sparx5_target { + #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\ + FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x) + +-#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW GENMASK(18, 5) ++#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW\ ++ GENMASK(regs->fsize[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] + 5 - 1, 5) + #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\ +- FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) ++ spx5_field_prep(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) + #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\ +- FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) ++ spx5_field_get(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x) + + #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1) + #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\ +@@ -4895,9 +5333,9 @@ enum sparx5_target { + #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\ + FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x) + +-/* LRN:COMMON:MAC_ACCESS_CFG_0 */ +-#define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) ++/* LRN:COMMON:MAC_ACCESS_CFG_0 */ ++#define LRN_MAC_ACCESS_CFG_0 \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4) + + #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID GENMASK(28, 16) + #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\ +@@ -4911,13 +5349,13 @@ enum sparx5_target { + #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\ + FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x) + +-/* LRN:COMMON:MAC_ACCESS_CFG_1 */ +-#define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) +- +-/* LRN:COMMON:MAC_ACCESS_CFG_2 */ +-#define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) ++/* LRN:COMMON:MAC_ACCESS_CFG_1 */ ++#define LRN_MAC_ACCESS_CFG_1 \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4) ++ ++/* LRN:COMMON:MAC_ACCESS_CFG_2 */ ++#define LRN_MAC_ACCESS_CFG_2 \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4) + + #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28) + #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\ +@@ -4991,19 +5429,20 @@ enum sparx5_target { + #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\ + FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x) + +-/* LRN:COMMON:MAC_ACCESS_CFG_3 */ +-#define LRN_MAC_ACCESS_CFG_3 __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) ++/* LRN:COMMON:MAC_ACCESS_CFG_3 */ ++#define LRN_MAC_ACCESS_CFG_3 \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4) + +-#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0) ++#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX\ ++ GENMASK(regs->fsize[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] + 0 - 1, 0) + #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\ +- FIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) ++ spx5_field_prep(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) + #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\ +- FIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) ++ spx5_field_get(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x) + +-/* LRN:COMMON:SCAN_NEXT_CFG */ +-#define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) ++/* LRN:COMMON:SCAN_NEXT_CFG */ ++#define LRN_SCAN_NEXT_CFG \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4) + + #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19) + #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\ +@@ -5095,9 +5534,9 @@ enum sparx5_target { + #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\ + FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x) + +-/* LRN:COMMON:SCAN_NEXT_CFG_1 */ +-#define LRN_SCAN_NEXT_CFG_1 __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) ++/* LRN:COMMON:SCAN_NEXT_CFG_1 */ ++#define LRN_SCAN_NEXT_CFG_1 \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4) + + #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR GENMASK(30, 16) + #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\ +@@ -5111,9 +5550,9 @@ enum sparx5_target { + #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\ + FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x) + +-/* LRN:COMMON:AUTOAGE_CFG */ +-#define LRN_AUTOAGE_CFG(r) __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 36, r, 4, 4) ++/* LRN:COMMON:AUTOAGE_CFG */ ++#define LRN_AUTOAGE_CFG(r) \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4) + + #define LRN_AUTOAGE_CFG_UNIT_SIZE GENMASK(29, 28) + #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\ +@@ -5127,9 +5566,9 @@ enum sparx5_target { + #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\ + FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x) + +-/* LRN:COMMON:AUTOAGE_CFG_1 */ +-#define LRN_AUTOAGE_CFG_1 __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) ++/* LRN:COMMON:AUTOAGE_CFG_1 */ ++#define LRN_AUTOAGE_CFG_1 \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4) + + #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA BIT(25) + #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\ +@@ -5173,15 +5612,16 @@ enum sparx5_target { + #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\ + FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x) + +-/* LRN:COMMON:AUTOAGE_CFG_2 */ +-#define LRN_AUTOAGE_CFG_2 __REG(TARGET_LRN,\ +- 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) ++/* LRN:COMMON:AUTOAGE_CFG_2 */ ++#define LRN_AUTOAGE_CFG_2 \ ++ __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4) + +-#define LRN_AUTOAGE_CFG_2_NEXT_ROW GENMASK(17, 4) ++#define LRN_AUTOAGE_CFG_2_NEXT_ROW\ ++ GENMASK(regs->fsize[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] + 4 - 1, 4) + #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\ +- FIELD_PREP(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) ++ spx5_field_prep(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) + #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\ +- FIELD_GET(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) ++ spx5_field_get(LRN_AUTOAGE_CFG_2_NEXT_ROW, x) + + #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS GENMASK(3, 0) + #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\ +@@ -5189,9 +5629,10 @@ enum sparx5_target { + #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\ + FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x) + +-/* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ +-#define PCEP_RCTRL_2_OUT_0 __REG(TARGET_PCEP,\ +- 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */ ++#define PCEP_RCTRL_2_OUT_0 \ ++ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4) + + #define PCEP_RCTRL_2_OUT_0_MSG_CODE GENMASK(7, 0) + #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\ +@@ -5253,9 +5694,10 @@ enum sparx5_target { + #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\ + FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x) + +-/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ +-#define PCEP_ADDR_LWR_OUT_0 __REG(TARGET_PCEP,\ +- 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */ ++#define PCEP_ADDR_LWR_OUT_0 \ ++ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4) + + #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW GENMASK(15, 0) + #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\ +@@ -5269,13 +5711,15 @@ enum sparx5_target { + #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\ + FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x) + +-/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ +-#define PCEP_ADDR_UPR_OUT_0 __REG(TARGET_PCEP,\ +- 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) +- +-/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ +-#define PCEP_ADDR_LIM_OUT_0 __REG(TARGET_PCEP,\ +- 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */ ++#define PCEP_ADDR_UPR_OUT_0 \ ++ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */ ++#define PCEP_ADDR_LIM_OUT_0 \ ++ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4) + + #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW GENMASK(15, 0) + #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\ +@@ -5289,17 +5733,20 @@ enum sparx5_target { + #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\ + FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x) + +-/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ +-#define PCEP_ADDR_LWR_TGT_OUT_0 __REG(TARGET_PCEP,\ +- 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) +- +-/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ +-#define PCEP_ADDR_UPR_TGT_OUT_0 __REG(TARGET_PCEP,\ +- 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) +- +-/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ +-#define PCEP_ADDR_UPR_LIM_OUT_0 __REG(TARGET_PCEP,\ +- 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */ ++#define PCEP_ADDR_LWR_TGT_OUT_0 \ ++ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */ ++#define PCEP_ADDR_UPR_TGT_OUT_0 \ ++ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */ ++#define PCEP_ADDR_UPR_LIM_OUT_0 \ ++ __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4) + + #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0) + #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\ +@@ -5313,9 +5760,10 @@ enum sparx5_target { + #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\ + FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x) + +-/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ +-#define PCS10G_BR_PCS_CFG(t) __REG(TARGET_PCS10G_BR,\ +- t, 12, 0, 0, 1, 56, 0, 0, 1, 4) ++/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ ++#define PCS10G_BR_PCS_CFG(t) \ ++ __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 0, \ ++ 0, 1, 4) + + #define PCS10G_BR_PCS_CFG_PCS_ENA BIT(31) + #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\ +@@ -5389,9 +5837,10 @@ enum sparx5_target { + #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ + FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x) + +-/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ +-#define PCS10G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS10G_BR,\ +- t, 12, 0, 0, 1, 56, 4, 0, 1, 4) ++/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ ++#define PCS10G_BR_PCS_SD_CFG(t) \ ++ __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 4, \ ++ 0, 1, 4) + + #define PCS10G_BR_PCS_SD_CFG_SD_SEL BIT(8) + #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ +@@ -5411,9 +5860,10 @@ enum sparx5_target { + #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ + FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x) + +-/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ +-#define PCS25G_BR_PCS_CFG(t) __REG(TARGET_PCS25G_BR,\ +- t, 8, 0, 0, 1, 56, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ ++#define PCS25G_BR_PCS_CFG(t) \ ++ __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4) + + #define PCS25G_BR_PCS_CFG_PCS_ENA BIT(31) + #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\ +@@ -5487,9 +5937,10 @@ enum sparx5_target { + #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ + FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x) + +-/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ +-#define PCS25G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS25G_BR,\ +- t, 8, 0, 0, 1, 56, 4, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ ++#define PCS25G_BR_PCS_SD_CFG(t) \ ++ __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4) + + #define PCS25G_BR_PCS_SD_CFG_SD_SEL BIT(8) + #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ +@@ -5509,9 +5960,10 @@ enum sparx5_target { + #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ + FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x) + +-/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ +-#define PCS5G_BR_PCS_CFG(t) __REG(TARGET_PCS5G_BR,\ +- t, 13, 0, 0, 1, 56, 0, 0, 1, 4) ++/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */ ++#define PCS5G_BR_PCS_CFG(t) \ ++ __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 0, 0, \ ++ 1, 4) + + #define PCS5G_BR_PCS_CFG_PCS_ENA BIT(31) + #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\ +@@ -5585,9 +6037,10 @@ enum sparx5_target { + #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\ + FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x) + +-/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ +-#define PCS5G_BR_PCS_SD_CFG(t) __REG(TARGET_PCS5G_BR,\ +- t, 13, 0, 0, 1, 56, 4, 0, 1, 4) ++/* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */ ++#define PCS5G_BR_PCS_SD_CFG(t) \ ++ __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 4, 0, \ ++ 1, 4) + + #define PCS5G_BR_PCS_SD_CFG_SD_SEL BIT(8) + #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\ +@@ -5607,58 +6060,67 @@ enum sparx5_target { + #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\ + FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x) + +-/* PORT_CONF:HW_CFG:DEV5G_MODES */ +-#define PORT_CONF_DEV5G_MODES __REG(TARGET_PORT_CONF,\ +- 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) ++/* PORT_CONF:HW_CFG:DEV5G_MODES */ ++#define PORT_CONF_DEV5G_MODES \ ++ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE BIT(0) + #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE BIT(1) + #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE BIT(2) + #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE BIT(3) + #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE BIT(4) + #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE BIT(5) + #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE BIT(6) + #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE BIT(7) + #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE BIT(8) + #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x) +@@ -5671,27 +6133,30 @@ enum sparx5_target { + #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE BIT(10) + #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE BIT(11) + #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12) + #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) + #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x) + +-/* PORT_CONF:HW_CFG:DEV10G_MODES */ +-#define PORT_CONF_DEV10G_MODES __REG(TARGET_PORT_CONF,\ +- 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) ++/* PORT_CONF:HW_CFG:DEV10G_MODES */ ++#define PORT_CONF_DEV10G_MODES \ ++ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4) + + #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE BIT(0) + #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\ +@@ -5699,75 +6164,87 @@ enum sparx5_target { + #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE BIT(1) + #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE BIT(2) + #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE BIT(3) + #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE BIT(4) + #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE BIT(5) + #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE BIT(6) + #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE BIT(7) + #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE BIT(8) + #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE BIT(9) + #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE BIT(10) + #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE BIT(11) + #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\ + FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) + #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x) + +-/* PORT_CONF:HW_CFG:DEV25G_MODES */ +-#define PORT_CONF_DEV25G_MODES __REG(TARGET_PORT_CONF,\ +- 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* PORT_CONF:HW_CFG:DEV25G_MODES */ ++#define PORT_CONF_DEV25G_MODES \ ++ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4) + + #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE BIT(0) + #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\ +@@ -5817,9 +6294,9 @@ enum sparx5_target { + #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\ + FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x) + +-/* PORT_CONF:HW_CFG:QSGMII_ENA */ +-#define PORT_CONF_QSGMII_ENA __REG(TARGET_PORT_CONF,\ +- 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) ++/* PORT_CONF:HW_CFG:QSGMII_ENA */ ++#define PORT_CONF_QSGMII_ENA \ ++ __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4) + + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0 BIT(0) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\ +@@ -5857,45 +6334,52 @@ enum sparx5_target { + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\ + FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6 BIT(6) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\ + FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\ + FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7 BIT(7) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\ + FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\ + FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8 BIT(8) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\ + FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\ + FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9 BIT(9) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\ + FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\ + FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10 BIT(10) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\ + FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\ + FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x) + ++/* SPARX5 ONLY */ + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11 BIT(11) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\ + FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) + #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\ + FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x) + +-/* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ +-#define PORT_CONF_USGMII_CFG(g) __REG(TARGET_PORT_CONF,\ +- 0, 1, 72, g, 6, 8, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */ ++#define PORT_CONF_USGMII_CFG(g) \ ++ __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4) + + #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM BIT(9) + #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\ +@@ -5939,39 +6423,46 @@ enum sparx5_target { + #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\ + FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x) + +-/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ +-#define PTP_PTP_PIN_INTR __REG(TARGET_PTP,\ +- 0, 1, 320, 0, 1, 16, 0, 0, 1, 4) ++/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */ ++#define PTP_PTP_PIN_INTR \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 0, 0, 1,\ ++ 4) + +-#define PTP_PTP_PIN_INTR_INTR_PTP GENMASK(4, 0) ++#define PTP_PTP_PIN_INTR_INTR_PTP\ ++ GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_INTR_PTP] + 0 - 1, 0) + #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\ +- FIELD_PREP(PTP_PTP_PIN_INTR_INTR_PTP, x) ++ spx5_field_prep(PTP_PTP_PIN_INTR_INTR_PTP, x) + #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\ +- FIELD_GET(PTP_PTP_PIN_INTR_INTR_PTP, x) ++ spx5_field_get(PTP_PTP_PIN_INTR_INTR_PTP, x) + +-/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ +-#define PTP_PTP_PIN_INTR_ENA __REG(TARGET_PTP,\ +- 0, 1, 320, 0, 1, 16, 4, 0, 1, 4) ++/* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */ ++#define PTP_PTP_PIN_INTR_ENA \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 4, 0, 1,\ ++ 4) + +-#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA GENMASK(4, 0) ++#define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA\ ++ GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] + 0 - 1, 0) + #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\ +- FIELD_PREP(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) ++ spx5_field_prep(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) + #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\ +- FIELD_GET(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) ++ spx5_field_get(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x) + +-/* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ +-#define PTP_PTP_INTR_IDENT __REG(TARGET_PTP,\ +- 0, 1, 320, 0, 1, 16, 8, 0, 1, 4) ++/* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */ ++#define PTP_PTP_INTR_IDENT \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 8, 0, 1,\ ++ 4) + +-#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT GENMASK(4, 0) ++#define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT\ ++ GENMASK(regs->fsize[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] + 0 - 1, 0) + #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\ +- FIELD_PREP(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) ++ spx5_field_prep(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) + #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\ +- FIELD_GET(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) ++ spx5_field_get(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x) + +-/* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ +-#define PTP_PTP_DOM_CFG __REG(TARGET_PTP,\ +- 0, 1, 320, 0, 1, 16, 12, 0, 1, 4) ++/* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */ ++#define PTP_PTP_DOM_CFG \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 12, 0, \ ++ 1, 4) + + #define PTP_PTP_DOM_CFG_PTP_ENA GENMASK(11, 9) + #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\ +@@ -5997,13 +6488,15 @@ enum sparx5_target { + #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\ + FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x) + +-/* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ +-#define PTP_CLK_PER_CFG(g, r) __REG(TARGET_PTP,\ +- 0, 1, 336, g, 3, 28, 0, r, 2, 4) +- +-/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ +-#define PTP_PTP_CUR_NSEC(g) __REG(TARGET_PTP,\ +- 0, 1, 336, g, 3, 28, 8, 0, 1, 4) ++/* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */ ++#define PTP_CLK_PER_CFG(g, r) \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ ++ 0, r, 2, 4) ++ ++/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */ ++#define PTP_PTP_CUR_NSEC(g) \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ ++ 8, 0, 1, 4) + + #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC GENMASK(29, 0) + #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\ +@@ -6011,9 +6504,10 @@ enum sparx5_target { + #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\ + FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x) + +-/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ +-#define PTP_PTP_CUR_NSEC_FRAC(g) __REG(TARGET_PTP,\ +- 0, 1, 336, g, 3, 28, 12, 0, 1, 4) ++/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */ ++#define PTP_PTP_CUR_NSEC_FRAC(g) \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ ++ 12, 0, 1, 4) + + #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC GENMASK(7, 0) + #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\ +@@ -6021,13 +6515,15 @@ enum sparx5_target { + #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\ + FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x) + +-/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ +-#define PTP_PTP_CUR_SEC_LSB(g) __REG(TARGET_PTP,\ +- 0, 1, 336, g, 3, 28, 16, 0, 1, 4) +- +-/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ +-#define PTP_PTP_CUR_SEC_MSB(g) __REG(TARGET_PTP,\ +- 0, 1, 336, g, 3, 28, 20, 0, 1, 4) ++/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */ ++#define PTP_PTP_CUR_SEC_LSB(g) \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ ++ 16, 0, 1, 4) ++ ++/* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */ ++#define PTP_PTP_CUR_SEC_MSB(g) \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ ++ 20, 0, 1, 4) + + #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB GENMASK(15, 0) + #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\ +@@ -6035,37 +6531,43 @@ enum sparx5_target { + #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\ + FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x) + +-/* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ +-#define PTP_NTP_CUR_NSEC(g) __REG(TARGET_PTP,\ +- 0, 1, 336, g, 3, 28, 24, 0, 1, 4) +- +-/* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ +-#define PTP_PTP_PIN_CFG(g) __REG(TARGET_PTP,\ +- 0, 1, 0, g, 5, 64, 0, 0, 1, 4) ++/* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */ ++#define PTP_NTP_CUR_NSEC(g) \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \ ++ 24, 0, 1, 4) ++ ++/* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */ ++#define PTP_PTP_PIN_CFG(g) \ ++ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 0, 0, 1,\ ++ 4) + +-#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION GENMASK(28, 26) ++#define PTP_PTP_PIN_CFG_PTP_PIN_ACTION\ ++ GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] + 2, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION]) + #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\ +- FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) ++ spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) + #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\ +- FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) ++ spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x) + +-#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC GENMASK(25, 24) ++#define PTP_PTP_PIN_CFG_PTP_PIN_SYNC\ ++ GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] + 1, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC]) + #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\ +- FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) ++ spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) + #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\ +- FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) ++ spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x) + +-#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL BIT(23) ++#define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL\ ++ BIT(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL]) + #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\ +- FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) ++ spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) + #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\ +- FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) ++ spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x) + +-#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT GENMASK(22, 21) ++#define PTP_PTP_PIN_CFG_PTP_PIN_SELECT\ ++ GENMASK(regs->fsize[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] + 21 - 1, 21) + #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\ +- FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) ++ spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) + #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\ +- FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) ++ spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x) + + #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT GENMASK(20, 18) + #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\ +@@ -6097,9 +6599,10 @@ enum sparx5_target { + #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\ + FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x) + +-/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ +-#define PTP_PTP_TOD_SEC_MSB(g) __REG(TARGET_PTP,\ +- 0, 1, 0, g, 5, 64, 4, 0, 1, 4) ++/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */ ++#define PTP_PTP_TOD_SEC_MSB(g) \ ++ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 4, 0, 1,\ ++ 4) + + #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB GENMASK(15, 0) + #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\ +@@ -6107,13 +6610,15 @@ enum sparx5_target { + #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\ + FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x) + +-/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ +-#define PTP_PTP_TOD_SEC_LSB(g) __REG(TARGET_PTP,\ +- 0, 1, 0, g, 5, 64, 8, 0, 1, 4) +- +-/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ +-#define PTP_PTP_TOD_NSEC(g) __REG(TARGET_PTP,\ +- 0, 1, 0, g, 5, 64, 12, 0, 1, 4) ++/* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */ ++#define PTP_PTP_TOD_SEC_LSB(g) \ ++ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 8, 0, 1,\ ++ 4) ++ ++/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */ ++#define PTP_PTP_TOD_NSEC(g) \ ++ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 12, 0, \ ++ 1, 4) + + #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC GENMASK(29, 0) + #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\ +@@ -6121,9 +6626,10 @@ enum sparx5_target { + #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\ + FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x) + +-/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ +-#define PTP_PTP_TOD_NSEC_FRAC(g) __REG(TARGET_PTP,\ +- 0, 1, 0, g, 5, 64, 16, 0, 1, 4) ++/* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */ ++#define PTP_PTP_TOD_NSEC_FRAC(g) \ ++ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 16, 0, \ ++ 1, 4) + + #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC GENMASK(7, 0) + #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\ +@@ -6131,13 +6637,15 @@ enum sparx5_target { + #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\ + FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x) + +-/* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ +-#define PTP_NTP_NSEC(g) __REG(TARGET_PTP,\ +- 0, 1, 0, g, 5, 64, 20, 0, 1, 4) +- +-/* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ +-#define PTP_PIN_WF_HIGH_PERIOD(g) __REG(TARGET_PTP,\ +- 0, 1, 0, g, 5, 64, 24, 0, 1, 4) ++/* DEVCPU_PTP:PTP_PINS:NTP_NSEC */ ++#define PTP_NTP_NSEC(g) \ ++ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 20, 0, \ ++ 1, 4) ++ ++/* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */ ++#define PTP_PIN_WF_HIGH_PERIOD(g) \ ++ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 24, 0, \ ++ 1, 4) + + #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH GENMASK(29, 0) + #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\ +@@ -6145,9 +6653,10 @@ enum sparx5_target { + #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\ + FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x) + +-/* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ +-#define PTP_PIN_WF_LOW_PERIOD(g) __REG(TARGET_PTP,\ +- 0, 1, 0, g, 5, 64, 28, 0, 1, 4) ++/* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */ ++#define PTP_PIN_WF_LOW_PERIOD(g) \ ++ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 28, 0, \ ++ 1, 4) + + #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL GENMASK(29, 0) + #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\ +@@ -6155,9 +6664,10 @@ enum sparx5_target { + #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\ + FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x) + +-/* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ +-#define PTP_PIN_IOBOUNCH_DELAY(g) __REG(TARGET_PTP,\ +- 0, 1, 0, g, 5, 64, 32, 0, 1, 4) ++/* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */ ++#define PTP_PIN_IOBOUNCH_DELAY(g) \ ++ __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 32, 0, \ ++ 1, 4) + + #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL GENMASK(18, 3) + #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\ +@@ -6171,22 +6681,27 @@ enum sparx5_target { + #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\ + FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x) + +-/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ +-#define PTP_PHAD_CTRL(g) __REG(TARGET_PTP,\ +- 0, 1, 420, g, 5, 8, 0, 0, 1, 4) ++/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */ ++#define PTP_PHAD_CTRL(g) \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ ++ regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ ++ regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) + +-#define PTP_PHAD_CTRL_PHAD_ENA BIT(7) ++#define PTP_PHAD_CTRL_PHAD_ENA\ ++ BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_ENA]) + #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\ +- FIELD_PREP(PTP_PHAD_CTRL_PHAD_ENA, x) ++ spx5_field_prep(PTP_PHAD_CTRL_PHAD_ENA, x) + #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\ +- FIELD_GET(PTP_PHAD_CTRL_PHAD_ENA, x) ++ spx5_field_get(PTP_PHAD_CTRL_PHAD_ENA, x) + +-#define PTP_PHAD_CTRL_PHAD_FAILED BIT(6) ++#define PTP_PHAD_CTRL_PHAD_FAILED\ ++ BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_FAILED]) + #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\ +- FIELD_PREP(PTP_PHAD_CTRL_PHAD_FAILED, x) ++ spx5_field_prep(PTP_PHAD_CTRL_PHAD_FAILED, x) + #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\ +- FIELD_GET(PTP_PHAD_CTRL_PHAD_FAILED, x) ++ spx5_field_get(PTP_PHAD_CTRL_PHAD_FAILED, x) + ++/* SPARX5 ONLY */ + #define PTP_PHAD_CTRL_REDUCED_RES GENMASK(5, 3) + #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\ + FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x) +@@ -6199,13 +6714,16 @@ enum sparx5_target { + #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\ + FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x) + +-/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ +-#define PTP_PHAD_CYC_STAT(g) __REG(TARGET_PTP,\ +- 0, 1, 420, g, 5, 8, 4, 0, 1, 4) +- +-/* QFWD:SYSTEM:SWITCH_PORT_MODE */ +-#define QFWD_SWITCH_PORT_MODE(r) __REG(TARGET_QFWD,\ +- 0, 1, 0, 0, 1, 340, 0, r, 70, 4) ++/* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */ ++#define PTP_PHAD_CYC_STAT(g) \ ++ __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g, \ ++ regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ ++ regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4) ++ ++/* QFWD:SYSTEM:SWITCH_PORT_MODE */ ++#define QFWD_SWITCH_PORT_MODE(r) \ ++ __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \ ++ regs->rcnt[RC_QFWD_SWITCH_PORT_MODE], 4) + + #define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19) + #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\ +@@ -6261,49 +6779,53 @@ enum sparx5_target { + #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\ + FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x) + +-/* QFWD:SYSTEM:FRAME_COPY_CFG */ +-#define QFWD_FRAME_COPY_CFG(r)\ ++/* QFWD:SYSTEM:FRAME_COPY_CFG */ ++#define QFWD_FRAME_COPY_CFG(r) \ + __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4) + +-#define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL GENMASK(12, 6) ++#define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL\ ++ GENMASK(regs->fsize[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] + 6 - 1, 6) + #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\ +- FIELD_PREP(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) ++ spx5_field_prep(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) + #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\ +- FIELD_GET(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) ++ spx5_field_get(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x) + +-/* QRES:RES_CTRL:RES_CFG */ +-#define QRES_RES_CFG(g) __REG(TARGET_QRES,\ +- 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) ++/* QRES:RES_CTRL:RES_CFG */ ++#define QRES_RES_CFG(g) \ ++ __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4) + +-#define QRES_RES_CFG_WM_HIGH GENMASK(11, 0) ++#define QRES_RES_CFG_WM_HIGH\ ++ GENMASK(regs->fsize[FW_QRES_RES_CFG_WM_HIGH] + 0 - 1, 0) + #define QRES_RES_CFG_WM_HIGH_SET(x)\ +- FIELD_PREP(QRES_RES_CFG_WM_HIGH, x) ++ spx5_field_prep(QRES_RES_CFG_WM_HIGH, x) + #define QRES_RES_CFG_WM_HIGH_GET(x)\ +- FIELD_GET(QRES_RES_CFG_WM_HIGH, x) ++ spx5_field_get(QRES_RES_CFG_WM_HIGH, x) + +-/* QRES:RES_CTRL:RES_STAT */ +-#define QRES_RES_STAT(g) __REG(TARGET_QRES,\ +- 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) ++/* QRES:RES_CTRL:RES_STAT */ ++#define QRES_RES_STAT(g) \ ++ __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4) + +-#define QRES_RES_STAT_MAXUSE GENMASK(20, 0) ++#define QRES_RES_STAT_MAXUSE\ ++ GENMASK(regs->fsize[FW_QRES_RES_STAT_MAXUSE] + 0 - 1, 0) + #define QRES_RES_STAT_MAXUSE_SET(x)\ +- FIELD_PREP(QRES_RES_STAT_MAXUSE, x) ++ spx5_field_prep(QRES_RES_STAT_MAXUSE, x) + #define QRES_RES_STAT_MAXUSE_GET(x)\ +- FIELD_GET(QRES_RES_STAT_MAXUSE, x) ++ spx5_field_get(QRES_RES_STAT_MAXUSE, x) + +-/* QRES:RES_CTRL:RES_STAT_CUR */ +-#define QRES_RES_STAT_CUR(g) __REG(TARGET_QRES,\ +- 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) ++/* QRES:RES_CTRL:RES_STAT_CUR */ ++#define QRES_RES_STAT_CUR(g) \ ++ __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4) + +-#define QRES_RES_STAT_CUR_INUSE GENMASK(20, 0) ++#define QRES_RES_STAT_CUR_INUSE\ ++ GENMASK(regs->fsize[FW_QRES_RES_STAT_CUR_INUSE] + 0 - 1, 0) + #define QRES_RES_STAT_CUR_INUSE_SET(x)\ +- FIELD_PREP(QRES_RES_STAT_CUR_INUSE, x) ++ spx5_field_prep(QRES_RES_STAT_CUR_INUSE, x) + #define QRES_RES_STAT_CUR_INUSE_GET(x)\ +- FIELD_GET(QRES_RES_STAT_CUR_INUSE, x) ++ spx5_field_get(QRES_RES_STAT_CUR_INUSE, x) + +-/* DEVCPU_QS:XTR:XTR_GRP_CFG */ +-#define QS_XTR_GRP_CFG(r) __REG(TARGET_QS,\ +- 0, 1, 0, 0, 1, 36, 0, r, 2, 4) ++/* DEVCPU_QS:XTR:XTR_GRP_CFG */ ++#define QS_XTR_GRP_CFG(r) \ ++ __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4) + + #define QS_XTR_GRP_CFG_MODE GENMASK(3, 2) + #define QS_XTR_GRP_CFG_MODE_SET(x)\ +@@ -6323,13 +6845,13 @@ enum sparx5_target { + #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\ + FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x) + +-/* DEVCPU_QS:XTR:XTR_RD */ +-#define QS_XTR_RD(r) __REG(TARGET_QS,\ +- 0, 1, 0, 0, 1, 36, 8, r, 2, 4) +- +-/* DEVCPU_QS:XTR:XTR_FLUSH */ +-#define QS_XTR_FLUSH __REG(TARGET_QS,\ +- 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) ++/* DEVCPU_QS:XTR:XTR_RD */ ++#define QS_XTR_RD(r) \ ++ __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4) ++ ++/* DEVCPU_QS:XTR:XTR_FLUSH */ ++#define QS_XTR_FLUSH \ ++ __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4) + + #define QS_XTR_FLUSH_FLUSH GENMASK(1, 0) + #define QS_XTR_FLUSH_FLUSH_SET(x)\ +@@ -6337,9 +6859,9 @@ enum sparx5_target { + #define QS_XTR_FLUSH_FLUSH_GET(x)\ + FIELD_GET(QS_XTR_FLUSH_FLUSH, x) + +-/* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ +-#define QS_XTR_DATA_PRESENT __REG(TARGET_QS,\ +- 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) ++/* DEVCPU_QS:XTR:XTR_DATA_PRESENT */ ++#define QS_XTR_DATA_PRESENT \ ++ __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4) + + #define QS_XTR_DATA_PRESENT_DATA_PRESENT GENMASK(1, 0) + #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\ +@@ -6347,9 +6869,9 @@ enum sparx5_target { + #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\ + FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x) + +-/* DEVCPU_QS:INJ:INJ_GRP_CFG */ +-#define QS_INJ_GRP_CFG(r) __REG(TARGET_QS,\ +- 0, 1, 36, 0, 1, 40, 0, r, 2, 4) ++/* DEVCPU_QS:INJ:INJ_GRP_CFG */ ++#define QS_INJ_GRP_CFG(r) \ ++ __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4) + + #define QS_INJ_GRP_CFG_MODE GENMASK(3, 2) + #define QS_INJ_GRP_CFG_MODE_SET(x)\ +@@ -6363,13 +6885,13 @@ enum sparx5_target { + #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\ + FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x) + +-/* DEVCPU_QS:INJ:INJ_WR */ +-#define QS_INJ_WR(r) __REG(TARGET_QS,\ +- 0, 1, 36, 0, 1, 40, 8, r, 2, 4) +- +-/* DEVCPU_QS:INJ:INJ_CTRL */ +-#define QS_INJ_CTRL(r) __REG(TARGET_QS,\ +- 0, 1, 36, 0, 1, 40, 16, r, 2, 4) ++/* DEVCPU_QS:INJ:INJ_WR */ ++#define QS_INJ_WR(r) \ ++ __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4) ++ ++/* DEVCPU_QS:INJ:INJ_CTRL */ ++#define QS_INJ_CTRL(r) \ ++ __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4) + + #define QS_INJ_CTRL_GAP_SIZE GENMASK(24, 21) + #define QS_INJ_CTRL_GAP_SIZE_SET(x)\ +@@ -6401,9 +6923,9 @@ enum sparx5_target { + #define QS_INJ_CTRL_VLD_BYTES_GET(x)\ + FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x) + +-/* DEVCPU_QS:INJ:INJ_STATUS */ +-#define QS_INJ_STATUS __REG(TARGET_QS,\ +- 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) ++/* DEVCPU_QS:INJ:INJ_STATUS */ ++#define QS_INJ_STATUS \ ++ __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4) + + #define QS_INJ_STATUS_WMARK_REACHED GENMASK(5, 4) + #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\ +@@ -6423,21 +6945,24 @@ enum sparx5_target { + #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\ + FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x) + +-/* QSYS:PAUSE_CFG:PAUSE_CFG */ +-#define QSYS_PAUSE_CFG(r) __REG(TARGET_QSYS,\ +- 0, 1, 544, 0, 1, 1128, 0, r, 70, 4) ++/* QSYS:PAUSE_CFG:PAUSE_CFG */ ++#define QSYS_PAUSE_CFG(r) \ ++ __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], 0, \ ++ r, regs->rcnt[RC_QSYS_PAUSE_CFG], 4) + +-#define QSYS_PAUSE_CFG_PAUSE_START GENMASK(25, 14) ++#define QSYS_PAUSE_CFG_PAUSE_START\ ++ GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_START] + 14 - 1, 14) + #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\ +- FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_START, x) ++ spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_START, x) + #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\ +- FIELD_GET(QSYS_PAUSE_CFG_PAUSE_START, x) ++ spx5_field_get(QSYS_PAUSE_CFG_PAUSE_START, x) + +-#define QSYS_PAUSE_CFG_PAUSE_STOP GENMASK(13, 2) ++#define QSYS_PAUSE_CFG_PAUSE_STOP\ ++ GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_STOP] + 2 - 1, 2) + #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\ +- FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_STOP, x) ++ spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_STOP, x) + #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\ +- FIELD_GET(QSYS_PAUSE_CFG_PAUSE_STOP, x) ++ spx5_field_get(QSYS_PAUSE_CFG_PAUSE_STOP, x) + + #define QSYS_PAUSE_CFG_PAUSE_ENA BIT(1) + #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\ +@@ -6451,19 +6976,22 @@ enum sparx5_target { + #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\ + FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x) + +-/* QSYS:PAUSE_CFG:ATOP */ +-#define QSYS_ATOP(r) __REG(TARGET_QSYS,\ +- 0, 1, 544, 0, 1, 1128, 284, r, 70, 4) ++/* QSYS:PAUSE_CFG:ATOP */ ++#define QSYS_ATOP(r) \ ++ __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ ++ 284, r, regs->rcnt[RC_QSYS_ATOP], 4) + +-#define QSYS_ATOP_ATOP GENMASK(11, 0) ++#define QSYS_ATOP_ATOP\ ++ GENMASK(regs->fsize[FW_QSYS_ATOP_ATOP] + 0 - 1, 0) + #define QSYS_ATOP_ATOP_SET(x)\ +- FIELD_PREP(QSYS_ATOP_ATOP, x) ++ spx5_field_prep(QSYS_ATOP_ATOP, x) + #define QSYS_ATOP_ATOP_GET(x)\ +- FIELD_GET(QSYS_ATOP_ATOP, x) ++ spx5_field_get(QSYS_ATOP_ATOP, x) + +-/* QSYS:PAUSE_CFG:FWD_PRESSURE */ +-#define QSYS_FWD_PRESSURE(r) __REG(TARGET_QSYS,\ +- 0, 1, 544, 0, 1, 1128, 564, r, 70, 4) ++/* QSYS:PAUSE_CFG:FWD_PRESSURE */ ++#define QSYS_FWD_PRESSURE(r) \ ++ __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ ++ 564, r, regs->rcnt[RC_QSYS_FWD_PRESSURE], 4) + + #define QSYS_FWD_PRESSURE_FWD_PRESSURE GENMASK(11, 1) + #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\ +@@ -6477,19 +7005,22 @@ enum sparx5_target { + #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\ + FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x) + +-/* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ +-#define QSYS_ATOP_TOT_CFG __REG(TARGET_QSYS,\ +- 0, 1, 544, 0, 1, 1128, 844, 0, 1, 4) ++/* QSYS:PAUSE_CFG:ATOP_TOT_CFG */ ++#define QSYS_ATOP_TOT_CFG \ ++ __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], \ ++ 844, 0, 1, 4) + +-#define QSYS_ATOP_TOT_CFG_ATOP_TOT GENMASK(11, 0) ++#define QSYS_ATOP_TOT_CFG_ATOP_TOT\ ++ GENMASK(regs->fsize[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] + 0 - 1, 0) + #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\ +- FIELD_PREP(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) ++ spx5_field_prep(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) + #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\ +- FIELD_GET(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) ++ spx5_field_get(QSYS_ATOP_TOT_CFG_ATOP_TOT, x) + +-/* QSYS:CALCFG:CAL_AUTO */ +-#define QSYS_CAL_AUTO(r) __REG(TARGET_QSYS,\ +- 0, 1, 2304, 0, 1, 40, 0, r, 7, 4) ++/* QSYS:CALCFG:CAL_AUTO */ ++#define QSYS_CAL_AUTO(r) \ ++ __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 0, r, \ ++ regs->rcnt[RC_QSYS_CAL_AUTO], 4) + + #define QSYS_CAL_AUTO_CAL_AUTO GENMASK(29, 0) + #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\ +@@ -6497,9 +7028,10 @@ enum sparx5_target { + #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\ + FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x) + +-/* QSYS:CALCFG:CAL_CTRL */ +-#define QSYS_CAL_CTRL __REG(TARGET_QSYS,\ +- 0, 1, 2304, 0, 1, 40, 36, 0, 1, 4) ++/* QSYS:CALCFG:CAL_CTRL */ ++#define QSYS_CAL_CTRL \ ++ __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 36, 0, \ ++ 1, 4) + + #define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11) + #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\ +@@ -6519,9 +7051,10 @@ enum sparx5_target { + #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\ + FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x) + +-/* QSYS:RAM_CTRL:RAM_INIT */ +-#define QSYS_RAM_INIT __REG(TARGET_QSYS,\ +- 0, 1, 2344, 0, 1, 4, 0, 0, 1, 4) ++/* QSYS:RAM_CTRL:RAM_INIT */ ++#define QSYS_RAM_INIT \ ++ __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_RAM_CTRL], 0, 1, 4, 0, 0, \ ++ 1, 4) + + #define QSYS_RAM_INIT_RAM_INIT BIT(1) + #define QSYS_RAM_INIT_RAM_INIT_SET(x)\ +@@ -6535,9 +7068,10 @@ enum sparx5_target { + #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\ + FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x) + +-/* REW:COMMON:OWN_UPSID */ +-#define REW_OWN_UPSID(r) __REG(TARGET_REW,\ +- 0, 1, 387264, 0, 1, 1232, 0, r, 3, 4) ++/* REW:COMMON:OWN_UPSID */ ++#define REW_OWN_UPSID(r) \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 0, r, \ ++ regs->rcnt[RC_REW_OWN_UPSID], 4) + + #define REW_OWN_UPSID_OWN_UPSID GENMASK(4, 0) + #define REW_OWN_UPSID_OWN_UPSID_SET(x)\ +@@ -6545,15 +7079,17 @@ enum sparx5_target { + #define REW_OWN_UPSID_OWN_UPSID_GET(x)\ + FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x) + +-/* REW:COMMON:RTAG_ETAG_CTRL */ +-#define REW_RTAG_ETAG_CTRL(r) __REG(TARGET_REW,\ +- 0, 1, 387264, 0, 1, 1232, 560, r, 70, 4) ++/* REW:COMMON:RTAG_ETAG_CTRL */ ++#define REW_RTAG_ETAG_CTRL(r) \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 560, r,\ ++ regs->rcnt[RC_REW_RTAG_ETAG_CTRL], 4) + +-#define REW_RTAG_ETAG_CTRL_IPE_TBL GENMASK(9, 3) ++#define REW_RTAG_ETAG_CTRL_IPE_TBL\ ++ GENMASK(regs->fsize[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] + 3 - 1, 3) + #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\ +- FIELD_PREP(REW_RTAG_ETAG_CTRL_IPE_TBL, x) ++ spx5_field_prep(REW_RTAG_ETAG_CTRL_IPE_TBL, x) + #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\ +- FIELD_GET(REW_RTAG_ETAG_CTRL_IPE_TBL, x) ++ spx5_field_get(REW_RTAG_ETAG_CTRL_IPE_TBL, x) + + #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA GENMASK(2, 1) + #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\ +@@ -6567,9 +7103,10 @@ enum sparx5_target { + #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\ + FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x) + +-/* REW:COMMON:ES0_CTRL */ +-#define REW_ES0_CTRL __REG(TARGET_REW,\ +- 0, 1, 387264, 0, 1, 1232, 852, 0, 1, 4) ++/* REW:COMMON:ES0_CTRL */ ++#define REW_ES0_CTRL \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 852, 0,\ ++ 1, 4) + + #define REW_ES0_CTRL_ES0_BY_RT_FWD BIT(5) + #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\ +@@ -6607,9 +7144,10 @@ enum sparx5_target { + #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\ + FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x) + +-/* REW:PORT:PORT_VLAN_CFG */ +-#define REW_PORT_VLAN_CFG(g) __REG(TARGET_REW,\ +- 0, 1, 360448, g, 70, 256, 0, 0, 1, 4) ++/* REW:PORT:PORT_VLAN_CFG */ ++#define REW_PORT_VLAN_CFG(g) \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ ++ regs->gcnt[GC_REW_PORT], 256, 0, 0, 1, 4) + + #define REW_PORT_VLAN_CFG_PORT_PCP GENMASK(15, 13) + #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\ +@@ -6629,9 +7167,10 @@ enum sparx5_target { + #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\ + FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x) + +-/* REW:PORT:PCP_MAP_DE0 */ +-#define REW_PCP_MAP_DE0(g, r) __REG(TARGET_REW,\ +- 0, 1, 360448, g, 70, 256, 4, r, 8, 4) ++/* REW:PORT:PCP_MAP_DE0 */ ++#define REW_PCP_MAP_DE0(g, r) \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ ++ regs->gcnt[GC_REW_PORT], 256, 4, r, 8, 4) + + #define REW_PCP_MAP_DE0_PCP_DE0 GENMASK(2, 0) + #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\ +@@ -6639,9 +7178,10 @@ enum sparx5_target { + #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\ + FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x) + +-/* REW:PORT:PCP_MAP_DE1 */ +-#define REW_PCP_MAP_DE1(g, r) __REG(TARGET_REW,\ +- 0, 1, 360448, g, 70, 256, 36, r, 8, 4) ++/* REW:PORT:PCP_MAP_DE1 */ ++#define REW_PCP_MAP_DE1(g, r) \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ ++ regs->gcnt[GC_REW_PORT], 256, 36, r, 8, 4) + + #define REW_PCP_MAP_DE1_PCP_DE1 GENMASK(2, 0) + #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\ +@@ -6649,9 +7189,10 @@ enum sparx5_target { + #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\ + FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x) + +-/* REW:PORT:DEI_MAP_DE0 */ +-#define REW_DEI_MAP_DE0(g, r) __REG(TARGET_REW,\ +- 0, 1, 360448, g, 70, 256, 68, r, 8, 4) ++/* REW:PORT:DEI_MAP_DE0 */ ++#define REW_DEI_MAP_DE0(g, r) \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ ++ regs->gcnt[GC_REW_PORT], 256, 68, r, 8, 4) + + #define REW_DEI_MAP_DE0_DEI_DE0 BIT(0) + #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\ +@@ -6659,9 +7200,10 @@ enum sparx5_target { + #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\ + FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x) + +-/* REW:PORT:DEI_MAP_DE1 */ +-#define REW_DEI_MAP_DE1(g, r) __REG(TARGET_REW,\ +- 0, 1, 360448, g, 70, 256, 100, r, 8, 4) ++/* REW:PORT:DEI_MAP_DE1 */ ++#define REW_DEI_MAP_DE1(g, r) \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ ++ regs->gcnt[GC_REW_PORT], 256, 100, r, 8, 4) + + #define REW_DEI_MAP_DE1_DEI_DE1 BIT(0) + #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\ +@@ -6669,9 +7211,10 @@ enum sparx5_target { + #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\ + FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x) + +-/* REW:PORT:TAG_CTRL */ +-#define REW_TAG_CTRL(g) __REG(TARGET_REW,\ +- 0, 1, 360448, g, 70, 256, 132, 0, 1, 4) ++/* REW:PORT:TAG_CTRL */ ++#define REW_TAG_CTRL(g) \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ ++ regs->gcnt[GC_REW_PORT], 256, 132, 0, 1, 4) + + #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED BIT(13) + #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\ +@@ -6709,9 +7252,10 @@ enum sparx5_target { + #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\ + FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x) + +-/* REW:PORT:DSCP_MAP */ +-#define REW_DSCP_MAP(g) __REG(TARGET_REW,\ +- 0, 1, 360448, g, 70, 256, 136, 0, 1, 4) ++/* REW:PORT:DSCP_MAP */ ++#define REW_DSCP_MAP(g) \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g, \ ++ regs->gcnt[GC_REW_PORT], 256, 136, 0, 1, 4) + + #define REW_DSCP_MAP_DSCP_UPDATE_ENA BIT(1) + #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\ +@@ -6725,9 +7269,10 @@ enum sparx5_target { + #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\ + FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x) + +-/* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ +-#define REW_PTP_TWOSTEP_CTRL __REG(TARGET_REW,\ +- 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */ ++#define REW_PTP_TWOSTEP_CTRL \ ++ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4) + + #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) + #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ +@@ -6765,9 +7310,10 @@ enum sparx5_target { + #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ + FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x) + +-/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ +-#define REW_PTP_TWOSTEP_STAMP __REG(TARGET_REW,\ +- 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */ ++#define REW_PTP_TWOSTEP_STAMP \ ++ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4) + + #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC GENMASK(29, 0) + #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\ +@@ -6775,9 +7321,10 @@ enum sparx5_target { + #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\ + FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x) + +-/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ +-#define REW_PTP_TWOSTEP_STAMP_SUBNS __REG(TARGET_REW,\ +- 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */ ++#define REW_PTP_TWOSTEP_STAMP_SUBNS \ ++ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4) + + #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0) + #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\ +@@ -6785,17 +7332,20 @@ enum sparx5_target { + #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\ + FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x) + +-/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ +-#define REW_PTP_RSRV_NOT_ZERO __REG(TARGET_REW,\ +- 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) +- +-/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ +-#define REW_PTP_RSRV_NOT_ZERO1 __REG(TARGET_REW,\ +- 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) +- +-/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ +-#define REW_PTP_RSRV_NOT_ZERO2 __REG(TARGET_REW,\ +- 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) ++/* SPARX5 ONLY */ ++/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */ ++#define REW_PTP_RSRV_NOT_ZERO \ ++ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */ ++#define REW_PTP_RSRV_NOT_ZERO1 \ ++ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4) ++ ++/* SPARX5 ONLY */ ++/* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */ ++#define REW_PTP_RSRV_NOT_ZERO2 \ ++ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4) + + #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0) + #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\ +@@ -6803,9 +7353,10 @@ enum sparx5_target { + #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\ + FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x) + +-/* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ +-#define REW_PTP_GEN_STAMP_FMT(r) __REG(TARGET_REW,\ +- 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) ++/* SPARX5 ONLY */ ++/* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */ ++#define REW_PTP_GEN_STAMP_FMT(r) \ ++ __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4) + + #define REW_PTP_GEN_STAMP_FMT_RT_OFS GENMASK(6, 2) + #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\ +@@ -6819,9 +7370,10 @@ enum sparx5_target { + #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\ + FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x) + +-/* REW:RAM_CTRL:RAM_INIT */ +-#define REW_RAM_INIT __REG(TARGET_REW,\ +- 0, 1, 378696, 0, 1, 4, 0, 0, 1, 4) ++/* REW:RAM_CTRL:RAM_INIT */ ++#define REW_RAM_INIT \ ++ __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ ++ 4) + + #define REW_RAM_INIT_RAM_INIT BIT(1) + #define REW_RAM_INIT_RAM_INIT_SET(x)\ +@@ -6835,9 +7387,9 @@ enum sparx5_target { + #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\ + FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x) + +-/* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ +-#define VCAP_ES0_CTRL __REG(TARGET_VCAP_ES0,\ +- 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) ++/* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ ++#define VCAP_ES0_CTRL \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) + + #define VCAP_ES0_CTRL_UPDATE_CMD GENMASK(24, 22) + #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\ +@@ -6887,9 +7439,9 @@ enum sparx5_target { + #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\ + FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x) + +-/* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ +-#define VCAP_ES0_CFG __REG(TARGET_VCAP_ES0,\ +- 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) ++/* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */ ++#define VCAP_ES0_CFG \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) + + #define VCAP_ES0_CFG_MV_NUM_POS GENMASK(31, 16) + #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\ +@@ -6903,33 +7455,33 @@ enum sparx5_target { + #define VCAP_ES0_CFG_MV_SIZE_GET(x)\ + FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x) + +-/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ +-#define VCAP_ES0_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES0,\ +- 0, 1, 8, 0, 1, 904, 0, r, 64, 4) +- +-/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ +-#define VCAP_ES0_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES0,\ +- 0, 1, 8, 0, 1, 904, 256, r, 64, 4) +- +-/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ +-#define VCAP_ES0_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES0,\ +- 0, 1, 8, 0, 1, 904, 512, r, 64, 4) +- +-/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ +-#define VCAP_ES0_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES0,\ +- 0, 1, 8, 0, 1, 904, 768, r, 32, 4) +- +-/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ +-#define VCAP_ES0_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES0,\ +- 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ +-#define VCAP_ES0_VCAP_TG_DAT __REG(TARGET_VCAP_ES0,\ +- 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ +-#define VCAP_ES0_IDX __REG(TARGET_VCAP_ES0,\ +- 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) ++/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ ++#define VCAP_ES0_VCAP_ENTRY_DAT(r) \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) ++ ++/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */ ++#define VCAP_ES0_VCAP_MASK_DAT(r) \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) ++ ++/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ ++#define VCAP_ES0_VCAP_ACTION_DAT(r) \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) ++ ++/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */ ++#define VCAP_ES0_VCAP_CNT_DAT(r) \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) ++ ++/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ ++#define VCAP_ES0_VCAP_CNT_FW_DAT \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */ ++#define VCAP_ES0_VCAP_TG_DAT \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */ ++#define VCAP_ES0_IDX \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) + + #define VCAP_ES0_IDX_CORE_IDX GENMASK(3, 0) + #define VCAP_ES0_IDX_CORE_IDX_SET(x)\ +@@ -6937,9 +7489,9 @@ enum sparx5_target { + #define VCAP_ES0_IDX_CORE_IDX_GET(x)\ + FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x) + +-/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ +-#define VCAP_ES0_MAP __REG(TARGET_VCAP_ES0,\ +- 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) ++/* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */ ++#define VCAP_ES0_MAP \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) + + #define VCAP_ES0_MAP_CORE_MAP GENMASK(2, 0) + #define VCAP_ES0_MAP_CORE_MAP_SET(x)\ +@@ -6947,9 +7499,9 @@ enum sparx5_target { + #define VCAP_ES0_MAP_CORE_MAP_GET(x)\ + FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x) + +-/* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ +-#define VCAP_ES0_VCAP_STICKY __REG(TARGET_VCAP_ES0,\ +- 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) ++/* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */ ++#define VCAP_ES0_VCAP_STICKY \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) + + #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) + #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ +@@ -6957,49 +7509,49 @@ enum sparx5_target { + #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ + FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) + +-/* VCAP_ES0:VCAP_CONST:VCAP_VER */ +-#define VCAP_ES0_VCAP_VER __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ +-#define VCAP_ES0_ENTRY_WIDTH __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ +-#define VCAP_ES0_ENTRY_CNT __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ +-#define VCAP_ES0_ENTRY_SWCNT __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ +-#define VCAP_ES0_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ +-#define VCAP_ES0_ACTION_DEF_CNT __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ +-#define VCAP_ES0_ACTION_WIDTH __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ +-#define VCAP_ES0_CNT_WIDTH __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CONST:CORE_CNT */ +-#define VCAP_ES0_CORE_CNT __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) +- +-/* VCAP_ES0:VCAP_CONST:IF_CNT */ +-#define VCAP_ES0_IF_CNT __REG(TARGET_VCAP_ES0,\ +- 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ +-#define VCAP_ES2_CTRL __REG(TARGET_VCAP_ES2,\ +- 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) ++/* VCAP_ES0:VCAP_CONST:VCAP_VER */ ++#define VCAP_ES0_VCAP_VER \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */ ++#define VCAP_ES0_ENTRY_WIDTH \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CONST:ENTRY_CNT */ ++#define VCAP_ES0_ENTRY_CNT \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */ ++#define VCAP_ES0_ENTRY_SWCNT \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */ ++#define VCAP_ES0_ENTRY_TG_WIDTH \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */ ++#define VCAP_ES0_ACTION_DEF_CNT \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */ ++#define VCAP_ES0_ACTION_WIDTH \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CONST:CNT_WIDTH */ ++#define VCAP_ES0_CNT_WIDTH \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CONST:CORE_CNT */ ++#define VCAP_ES0_CORE_CNT \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) ++ ++/* VCAP_ES0:VCAP_CONST:IF_CNT */ ++#define VCAP_ES0_IF_CNT \ ++ __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ ++#define VCAP_ES2_CTRL \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) + + #define VCAP_ES2_CTRL_UPDATE_CMD GENMASK(24, 22) + #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\ +@@ -7049,9 +7601,9 @@ enum sparx5_target { + #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\ + FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x) + +-/* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ +-#define VCAP_ES2_CFG __REG(TARGET_VCAP_ES2,\ +- 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) ++/* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */ ++#define VCAP_ES2_CFG \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) + + #define VCAP_ES2_CFG_MV_NUM_POS GENMASK(31, 16) + #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\ +@@ -7065,33 +7617,33 @@ enum sparx5_target { + #define VCAP_ES2_CFG_MV_SIZE_GET(x)\ + FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x) + +-/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ +-#define VCAP_ES2_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_ES2,\ +- 0, 1, 8, 0, 1, 904, 0, r, 64, 4) +- +-/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ +-#define VCAP_ES2_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_ES2,\ +- 0, 1, 8, 0, 1, 904, 256, r, 64, 4) +- +-/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ +-#define VCAP_ES2_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_ES2,\ +- 0, 1, 8, 0, 1, 904, 512, r, 64, 4) +- +-/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ +-#define VCAP_ES2_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_ES2,\ +- 0, 1, 8, 0, 1, 904, 768, r, 32, 4) +- +-/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ +-#define VCAP_ES2_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_ES2,\ +- 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ +-#define VCAP_ES2_VCAP_TG_DAT __REG(TARGET_VCAP_ES2,\ +- 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ +-#define VCAP_ES2_IDX __REG(TARGET_VCAP_ES2,\ +- 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) ++/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ ++#define VCAP_ES2_VCAP_ENTRY_DAT(r) \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) ++ ++/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */ ++#define VCAP_ES2_VCAP_MASK_DAT(r) \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) ++ ++/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ ++#define VCAP_ES2_VCAP_ACTION_DAT(r) \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) ++ ++/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */ ++#define VCAP_ES2_VCAP_CNT_DAT(r) \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) ++ ++/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ ++#define VCAP_ES2_VCAP_CNT_FW_DAT \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */ ++#define VCAP_ES2_VCAP_TG_DAT \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */ ++#define VCAP_ES2_IDX \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) + + #define VCAP_ES2_IDX_CORE_IDX GENMASK(3, 0) + #define VCAP_ES2_IDX_CORE_IDX_SET(x)\ +@@ -7099,9 +7651,9 @@ enum sparx5_target { + #define VCAP_ES2_IDX_CORE_IDX_GET(x)\ + FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x) + +-/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ +-#define VCAP_ES2_MAP __REG(TARGET_VCAP_ES2,\ +- 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) ++/* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */ ++#define VCAP_ES2_MAP \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) + + #define VCAP_ES2_MAP_CORE_MAP GENMASK(2, 0) + #define VCAP_ES2_MAP_CORE_MAP_SET(x)\ +@@ -7109,9 +7661,9 @@ enum sparx5_target { + #define VCAP_ES2_MAP_CORE_MAP_GET(x)\ + FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x) + +-/* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ +-#define VCAP_ES2_VCAP_STICKY __REG(TARGET_VCAP_ES2,\ +- 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) ++/* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */ ++#define VCAP_ES2_VCAP_STICKY \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4) + + #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0) + #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\ +@@ -7119,49 +7671,49 @@ enum sparx5_target { + #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\ + FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x) + +-/* VCAP_ES2:VCAP_CONST:VCAP_VER */ +-#define VCAP_ES2_VCAP_VER __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ +-#define VCAP_ES2_ENTRY_WIDTH __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ +-#define VCAP_ES2_ENTRY_CNT __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ +-#define VCAP_ES2_ENTRY_SWCNT __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ +-#define VCAP_ES2_ENTRY_TG_WIDTH __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ +-#define VCAP_ES2_ACTION_DEF_CNT __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ +-#define VCAP_ES2_ACTION_WIDTH __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ +-#define VCAP_ES2_CNT_WIDTH __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CONST:CORE_CNT */ +-#define VCAP_ES2_CORE_CNT __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) +- +-/* VCAP_ES2:VCAP_CONST:IF_CNT */ +-#define VCAP_ES2_IF_CNT __REG(TARGET_VCAP_ES2,\ +- 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ +-#define VCAP_SUPER_CTRL __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) ++/* VCAP_ES2:VCAP_CONST:VCAP_VER */ ++#define VCAP_ES2_VCAP_VER \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */ ++#define VCAP_ES2_ENTRY_WIDTH \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CONST:ENTRY_CNT */ ++#define VCAP_ES2_ENTRY_CNT \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */ ++#define VCAP_ES2_ENTRY_SWCNT \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */ ++#define VCAP_ES2_ENTRY_TG_WIDTH \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */ ++#define VCAP_ES2_ACTION_DEF_CNT \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */ ++#define VCAP_ES2_ACTION_WIDTH \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CONST:CNT_WIDTH */ ++#define VCAP_ES2_CNT_WIDTH \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CONST:CORE_CNT */ ++#define VCAP_ES2_CORE_CNT \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) ++ ++/* VCAP_ES2:VCAP_CONST:IF_CNT */ ++#define VCAP_ES2_IF_CNT \ ++ __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */ ++#define VCAP_SUPER_CTRL \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4) + + #define VCAP_SUPER_CTRL_UPDATE_CMD GENMASK(24, 22) + #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\ +@@ -7211,9 +7763,9 @@ enum sparx5_target { + #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\ + FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x) + +-/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ +-#define VCAP_SUPER_CFG __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) ++/* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */ ++#define VCAP_SUPER_CFG \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4) + + #define VCAP_SUPER_CFG_MV_NUM_POS GENMASK(31, 16) + #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\ +@@ -7227,33 +7779,33 @@ enum sparx5_target { + #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\ + FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x) + +-/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ +-#define VCAP_SUPER_VCAP_ENTRY_DAT(r) __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 8, 0, 1, 904, 0, r, 64, 4) +- +-/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ +-#define VCAP_SUPER_VCAP_MASK_DAT(r) __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 8, 0, 1, 904, 256, r, 64, 4) +- +-/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ +-#define VCAP_SUPER_VCAP_ACTION_DAT(r) __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 8, 0, 1, 904, 512, r, 64, 4) +- +-/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ +-#define VCAP_SUPER_VCAP_CNT_DAT(r) __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 8, 0, 1, 904, 768, r, 32, 4) +- +-/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ +-#define VCAP_SUPER_VCAP_CNT_FW_DAT __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ +-#define VCAP_SUPER_VCAP_TG_DAT __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ +-#define VCAP_SUPER_IDX __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) ++/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */ ++#define VCAP_SUPER_VCAP_ENTRY_DAT(r) \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 0, r, 64, 4) ++ ++/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */ ++#define VCAP_SUPER_VCAP_MASK_DAT(r) \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 256, r, 64, 4) ++ ++/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */ ++#define VCAP_SUPER_VCAP_ACTION_DAT(r) \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 512, r, 64, 4) ++ ++/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */ ++#define VCAP_SUPER_VCAP_CNT_DAT(r) \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 768, r, 32, 4) ++ ++/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */ ++#define VCAP_SUPER_VCAP_CNT_FW_DAT \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */ ++#define VCAP_SUPER_VCAP_TG_DAT \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */ ++#define VCAP_SUPER_IDX \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4) + + #define VCAP_SUPER_IDX_CORE_IDX GENMASK(3, 0) + #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\ +@@ -7261,9 +7813,9 @@ enum sparx5_target { + #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\ + FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x) + +-/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ +-#define VCAP_SUPER_MAP __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) ++/* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */ ++#define VCAP_SUPER_MAP \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4) + + #define VCAP_SUPER_MAP_CORE_MAP GENMASK(2, 0) + #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\ +@@ -7271,49 +7823,49 @@ enum sparx5_target { + #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\ + FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x) + +-/* VCAP_SUPER:VCAP_CONST:VCAP_VER */ +-#define VCAP_SUPER_VCAP_VER __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ +-#define VCAP_SUPER_ENTRY_WIDTH __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ +-#define VCAP_SUPER_ENTRY_CNT __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ +-#define VCAP_SUPER_ENTRY_SWCNT __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ +-#define VCAP_SUPER_ENTRY_TG_WIDTH __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ +-#define VCAP_SUPER_ACTION_DEF_CNT __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ +-#define VCAP_SUPER_ACTION_WIDTH __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ +-#define VCAP_SUPER_CNT_WIDTH __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CONST:CORE_CNT */ +-#define VCAP_SUPER_CORE_CNT __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) +- +-/* VCAP_SUPER:VCAP_CONST:IF_CNT */ +-#define VCAP_SUPER_IF_CNT __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) +- +-/* VCAP_SUPER:RAM_CTRL:RAM_INIT */ +-#define VCAP_SUPER_RAM_INIT __REG(TARGET_VCAP_SUPER,\ +- 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) ++/* VCAP_SUPER:VCAP_CONST:VCAP_VER */ ++#define VCAP_SUPER_VCAP_VER \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */ ++#define VCAP_SUPER_ENTRY_WIDTH \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */ ++#define VCAP_SUPER_ENTRY_CNT \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */ ++#define VCAP_SUPER_ENTRY_SWCNT \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */ ++#define VCAP_SUPER_ENTRY_TG_WIDTH \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */ ++#define VCAP_SUPER_ACTION_DEF_CNT \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */ ++#define VCAP_SUPER_ACTION_WIDTH \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */ ++#define VCAP_SUPER_CNT_WIDTH \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CONST:CORE_CNT */ ++#define VCAP_SUPER_CORE_CNT \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4) ++ ++/* VCAP_SUPER:VCAP_CONST:IF_CNT */ ++#define VCAP_SUPER_IF_CNT \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4) ++ ++/* VCAP_SUPER:RAM_CTRL:RAM_INIT */ ++#define VCAP_SUPER_RAM_INIT \ ++ __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4) + + #define VCAP_SUPER_RAM_INIT_RAM_INIT BIT(1) + #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\ +@@ -7327,9 +7879,10 @@ enum sparx5_target { + #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\ + FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x) + +-/* VOP:RAM_CTRL:RAM_INIT */ +-#define VOP_RAM_INIT __REG(TARGET_VOP,\ +- 0, 1, 279176, 0, 1, 4, 0, 0, 1, 4) ++/* VOP:RAM_CTRL:RAM_INIT */ ++#define VOP_RAM_INIT \ ++ __REG(TARGET_VOP, 0, 1, regs->gaddr[GA_VOP_RAM_CTRL], 0, 1, 4, 0, 0, 1,\ ++ 4) + + #define VOP_RAM_INIT_RAM_INIT BIT(1) + #define VOP_RAM_INIT_RAM_INIT_SET(x)\ +@@ -7343,9 +7896,10 @@ enum sparx5_target { + #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\ + FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x) + +-/* XQS:SYSTEM:STAT_CFG */ +-#define XQS_STAT_CFG __REG(TARGET_XQS,\ +- 0, 1, 6768, 0, 1, 872, 860, 0, 1, 4) ++/* XQS:SYSTEM:STAT_CFG */ ++#define XQS_STAT_CFG \ ++ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_SYSTEM], 0, 1, 872, 860, 0, \ ++ 1, 4) + + #define XQS_STAT_CFG_STAT_CLEAR_SHOT GENMASK(21, 18) + #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\ +@@ -7353,11 +7907,12 @@ enum sparx5_target { + #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\ + FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x) + +-#define XQS_STAT_CFG_STAT_VIEW GENMASK(17, 5) ++#define XQS_STAT_CFG_STAT_VIEW\ ++ GENMASK(regs->fsize[FW_XQS_STAT_CFG_STAT_VIEW] + 5 - 1, 5) + #define XQS_STAT_CFG_STAT_VIEW_SET(x)\ +- FIELD_PREP(XQS_STAT_CFG_STAT_VIEW, x) ++ spx5_field_prep(XQS_STAT_CFG_STAT_VIEW, x) + #define XQS_STAT_CFG_STAT_VIEW_GET(x)\ +- FIELD_GET(XQS_STAT_CFG_STAT_VIEW, x) ++ spx5_field_get(XQS_STAT_CFG_STAT_VIEW, x) + + #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY BIT(4) + #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\ +@@ -7371,48 +7926,56 @@ enum sparx5_target { + #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\ + FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x) + +-/* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ +-#define XQS_QLIMIT_SHR_TOP_CFG(g) __REG(TARGET_XQS,\ +- 0, 1, 7936, g, 4, 48, 0, 0, 1, 4) ++/* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */ ++#define XQS_QLIMIT_SHR_TOP_CFG(g) \ ++ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 0, 0,\ ++ 1, 4) + +-#define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP GENMASK(14, 0) ++#define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP\ ++ GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] + 0 - 1, 0) + #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\ +- FIELD_PREP(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) ++ spx5_field_prep(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) + #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\ +- FIELD_GET(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) ++ spx5_field_get(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x) + +-/* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ +-#define XQS_QLIMIT_SHR_ATOP_CFG(g) __REG(TARGET_XQS,\ +- 0, 1, 7936, g, 4, 48, 4, 0, 1, 4) ++/* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */ ++#define XQS_QLIMIT_SHR_ATOP_CFG(g) \ ++ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 4, 0,\ ++ 1, 4) + +-#define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP GENMASK(14, 0) ++#define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP\ ++ GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] + 0 - 1, 0) + #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\ +- FIELD_PREP(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) ++ spx5_field_prep(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) + #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\ +- FIELD_GET(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) ++ spx5_field_get(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x) + +-/* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ +-#define XQS_QLIMIT_SHR_CTOP_CFG(g) __REG(TARGET_XQS,\ +- 0, 1, 7936, g, 4, 48, 8, 0, 1, 4) ++/* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */ ++#define XQS_QLIMIT_SHR_CTOP_CFG(g) \ ++ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 8, 0,\ ++ 1, 4) + +-#define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP GENMASK(14, 0) ++#define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP\ ++ GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] + 0 - 1, 0) + #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\ +- FIELD_PREP(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) ++ spx5_field_prep(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) + #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\ +- FIELD_GET(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) ++ spx5_field_get(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x) + +-/* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ +-#define XQS_QLIMIT_SHR_QLIM_CFG(g) __REG(TARGET_XQS,\ +- 0, 1, 7936, g, 4, 48, 12, 0, 1, 4) ++/* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */ ++#define XQS_QLIMIT_SHR_QLIM_CFG(g) \ ++ __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 12, \ ++ 0, 1, 4) + +-#define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM GENMASK(14, 0) ++#define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM\ ++ GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] + 0 - 1, 0) + #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\ +- FIELD_PREP(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) ++ spx5_field_prep(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) + #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\ +- FIELD_GET(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) ++ spx5_field_get(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x) + +-/* XQS:STAT:CNT */ +-#define XQS_CNT(g) __REG(TARGET_XQS,\ +- 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) ++/* XQS:STAT:CNT */ ++#define XQS_CNT(g) \ ++ __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) + + #endif /* _SPARX5_MAIN_REGS_H_ */ +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c +@@ -0,0 +1,219 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* Microchip Sparx5 Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. ++ */ ++ ++/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. ++ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b ++ */ ++ ++#include "sparx5_regs.h" ++ ++const unsigned int sparx5_tsize[TSIZE_LAST] = { ++ [TC_DEV10G] = 12, ++ [TC_DEV2G5] = 65, ++ [TC_DEV5G] = 13, ++ [TC_PCS10G_BR] = 12, ++ [TC_PCS5G_BR] = 13, ++}; ++ ++const unsigned int sparx5_raddr[RADDR_LAST] = { ++ [RA_CPU_PROC_CTRL] = 176, ++ [RA_GCB_SOFT_RST] = 8, ++ [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 24, ++}; ++ ++const unsigned int sparx5_rcnt[RCNT_LAST] = { ++ [RC_ANA_AC_OWN_UPSID] = 3, ++ [RC_ANA_ACL_VCAP_S2_CFG] = 70, ++ [RC_ANA_ACL_OWN_UPSID] = 3, ++ [RC_ANA_CL_OWN_UPSID] = 3, ++ [RC_ANA_L2_OWN_UPSID] = 3, ++ [RC_ASM_PORT_CFG] = 67, ++ [RC_DSM_BUF_CFG] = 67, ++ [RC_DSM_DEV_TX_STOP_WM_CFG] = 67, ++ [RC_DSM_RX_PAUSE_CFG] = 67, ++ [RC_DSM_MAC_CFG] = 67, ++ [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 65, ++ [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 65, ++ [RC_DSM_TAXI_CAL_CFG] = 9, ++ [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 65, ++ [RC_HSCH_PORT_MODE] = 70, ++ [RC_QFWD_SWITCH_PORT_MODE] = 70, ++ [RC_QSYS_PAUSE_CFG] = 70, ++ [RC_QSYS_ATOP] = 70, ++ [RC_QSYS_FWD_PRESSURE] = 70, ++ [RC_QSYS_CAL_AUTO] = 7, ++ [RC_REW_OWN_UPSID] = 3, ++ [RC_REW_RTAG_ETAG_CTRL] = 70, ++}; ++ ++const unsigned int sparx5_gaddr[GADDR_LAST] = { ++ [GA_ANA_AC_RAM_CTRL] = 839108, ++ [GA_ANA_AC_PS_COMMON] = 894472, ++ [GA_ANA_AC_MIRROR_PROBE] = 893696, ++ [GA_ANA_AC_SRC] = 849920, ++ [GA_ANA_AC_PGID] = 786432, ++ [GA_ANA_AC_TSN_SF] = 839136, ++ [GA_ANA_AC_TSN_SF_CFG] = 839680, ++ [GA_ANA_AC_TSN_SF_STATUS] = 839072, ++ [GA_ANA_AC_SG_ACCESS] = 839140, ++ [GA_ANA_AC_SG_CONFIG] = 851584, ++ [GA_ANA_AC_SG_STATUS] = 839088, ++ [GA_ANA_AC_SG_STATUS_STICKY] = 839152, ++ [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 851552, ++ [GA_ANA_AC_STAT_CNT_CFG_PORT] = 843776, ++ [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 893792, ++ [GA_ANA_ACL_COMMON] = 32768, ++ [GA_ANA_ACL_KEY_SEL] = 34200, ++ [GA_ANA_ACL_CNT_B] = 16384, ++ [GA_ANA_ACL_STICKY] = 36408, ++ [GA_ANA_AC_POL_POL_ALL_CFG] = 75968, ++ [GA_ANA_AC_POL_COMMON_BDLB] = 79048, ++ [GA_ANA_AC_POL_COMMON_BUM_SLB] = 79056, ++ [GA_ANA_AC_SDLB_LBGRP_TBL] = 295468, ++ [GA_ANA_CL_PORT] = 131072, ++ [GA_ANA_CL_COMMON] = 166912, ++ [GA_ANA_L2_COMMON] = 566024, ++ [GA_ANA_L3_COMMON] = 493632, ++ [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 491460, ++ [GA_ASM_CFG] = 33280, ++ [GA_ASM_PFC_TIMER_CFG] = 34716, ++ [GA_ASM_LBK_WM_CFG] = 34744, ++ [GA_ASM_LBK_MISC_CFG] = 34756, ++ [GA_ASM_RAM_CTRL] = 34832, ++ [GA_EACL_ES2_KEY_SELECT_PROFILE] = 149504, ++ [GA_EACL_CNT_TBL] = 122880, ++ [GA_EACL_POL_CFG] = 150608, ++ [GA_EACL_ES2_STICKY] = 118696, ++ [GA_EACL_RAM_CTRL] = 118736, ++ [GA_GCB_SIO_CTRL] = 876, ++ [GA_HSCH_HSCH_DWRR] = 162816, ++ [GA_HSCH_HSCH_MISC] = 163104, ++ [GA_HSCH_HSCH_LEAK_LISTS] = 161664, ++ [GA_HSCH_SYSTEM] = 184000, ++ [GA_HSCH_MMGT] = 162368, ++ [GA_HSCH_TAS_CONFIG] = 162384, ++ [GA_PTP_PTP_CFG] = 320, ++ [GA_PTP_PTP_TOD_DOMAINS] = 336, ++ [GA_PTP_PHASE_DETECTOR_CTRL] = 420, ++ [GA_QSYS_CALCFG] = 2304, ++ [GA_QSYS_RAM_CTRL] = 2344, ++ [GA_REW_COMMON] = 387264, ++ [GA_REW_PORT] = 360448, ++ [GA_REW_VOE_PORT_LM_CNT] = 393216, ++ [GA_REW_RAM_CTRL] = 378696, ++ [GA_VOP_RAM_CTRL] = 279176, ++ [GA_XQS_SYSTEM] = 6768, ++ [GA_XQS_QLIMIT_SHR] = 7936, ++}; ++ ++const unsigned int sparx5_gcnt[GCNT_LAST] = { ++ [GC_ANA_AC_SRC] = 102, ++ [GC_ANA_AC_PGID] = 3290, ++ [GC_ANA_AC_TSN_SF_CFG] = 1024, ++ [GC_ANA_AC_STAT_CNT_CFG_PORT] = 70, ++ [GC_ANA_ACL_KEY_SEL] = 134, ++ [GC_ANA_ACL_CNT_A] = 4096, ++ [GC_ANA_ACL_CNT_B] = 4096, ++ [GC_ANA_AC_SDLB_LBGRP_TBL] = 10, ++ [GC_ANA_AC_SDLB_LBSET_TBL] = 4616, ++ [GC_ANA_CL_PORT] = 70, ++ [GC_ANA_L2_ISDX_LIMIT] = 1536, ++ [GC_ANA_L2_ISDX] = 4096, ++ [GC_ANA_L3_VLAN] = 5120, ++ [GC_ASM_DEV_STATISTICS] = 65, ++ [GC_EACL_ES2_KEY_SELECT_PROFILE] = 138, ++ [GC_EACL_CNT_TBL] = 2048, ++ [GC_GCB_SIO_CTRL] = 3, ++ [GC_HSCH_HSCH_CFG] = 5040, ++ [GC_HSCH_HSCH_DWRR] = 72, ++ [GC_PTP_PTP_PINS] = 5, ++ [GC_PTP_PHASE_DETECTOR_CTRL] = 5, ++ [GC_REW_PORT] = 70, ++ [GC_REW_VOE_PORT_LM_CNT] = 520, ++}; ++ ++const unsigned int sparx5_gsize[GSIZE_LAST] = { ++ [GW_ANA_AC_SRC] = 16, ++ [GW_ANA_L2_COMMON] = 700, ++ [GW_ASM_CFG] = 1088, ++ [GW_CPU_CPU_REGS] = 204, ++ [GW_FDMA_FDMA] = 428, ++ [GW_GCB_CHIP_REGS] = 424, ++ [GW_HSCH_TAS_CONFIG] = 12, ++ [GW_PTP_PHASE_DETECTOR_CTRL] = 8, ++ [GW_QSYS_PAUSE_CFG] = 1128, ++}; ++ ++const unsigned int sparx5_fpos[FPOS_LAST] = { ++ [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 12, ++ [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 11, ++ [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 10, ++ [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 9, ++ [FP_CPU_PROC_CTRL_VINITHI] = 8, ++ [FP_CPU_PROC_CTRL_CFGTE] = 7, ++ [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 6, ++ [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 5, ++ [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 1, ++ [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 7, ++ [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 6, ++ [FP_FDMA_CH_CFG_CH_INJ_PORT] = 5, ++ [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 26, ++ [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 24, ++ [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 23, ++ [FP_PTP_PHAD_CTRL_PHAD_ENA] = 7, ++ [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 6, ++}; ++ ++const unsigned int sparx5_fsize[FSIZE_LAST] = { ++ [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 32, ++ [FW_ANA_AC_SRC_CFG_PORT_MASK] = 32, ++ [FW_ANA_AC_PGID_CFG_PORT_MASK] = 32, ++ [FW_ANA_AC_TSN_SF_PORT_NUM] = 9, ++ [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 10, ++ [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 10, ++ [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 10, ++ [FW_ANA_AC_PORT_SGE_CFG_MASK] = 16, ++ [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 13, ++ [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 5, ++ [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 13, ++ [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 13, ++ [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 4, ++ [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 13, ++ [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 32, ++ [FW_ANA_L2_DLB_CFG_DLB_IDX] = 13, ++ [FW_ANA_L2_TSN_CFG_TSN_SFID] = 10, ++ [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 32, ++ [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 4, ++ [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 9, ++ [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 7, ++ [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 16, ++ [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 7, ++ [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 13, ++ [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 16, ++ [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 7, ++ [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 16, ++ [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 14, ++ [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 11, ++ [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 14, ++ [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 5, ++ [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 5, ++ [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 5, ++ [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 2, ++ [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 7, ++ [FW_QRES_RES_CFG_WM_HIGH] = 12, ++ [FW_QRES_RES_STAT_MAXUSE] = 21, ++ [FW_QRES_RES_STAT_CUR_INUSE] = 21, ++ [FW_QSYS_PAUSE_CFG_PAUSE_START] = 12, ++ [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 12, ++ [FW_QSYS_ATOP_ATOP] = 12, ++ [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 12, ++ [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 7, ++ [FW_XQS_STAT_CFG_STAT_VIEW] = 13, ++ [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 15, ++ [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 15, ++ [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 15, ++ [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 15, ++}; +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h +@@ -0,0 +1,244 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* Microchip Sparx5 Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. ++ */ ++ ++/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. ++ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b ++ */ ++ ++#ifndef _SPARX5_REGS_H_ ++#define _SPARX5_REGS_H_ ++ ++/* These enumerated values are used to index the platform specific structs ++ * containing the addresses, counts, size and positions, of register groups, ++ * registers and fields. ++ */ ++ ++enum sparx5_tsize_enum { ++ TC_DEV10G, ++ TC_DEV2G5, ++ TC_DEV5G, ++ TC_PCS10G_BR, ++ TC_PCS5G_BR, ++ TSIZE_LAST, ++}; ++ ++enum sparx5_raddr_enum { ++ RA_CPU_PROC_CTRL, ++ RA_GCB_SOFT_RST, ++ RA_GCB_HW_SGPIO_TO_SD_MAP_CFG, ++ RADDR_LAST, ++}; ++ ++enum sparx5_rcnt_enum { ++ RC_ANA_AC_OWN_UPSID, ++ RC_ANA_ACL_VCAP_S2_CFG, ++ RC_ANA_ACL_OWN_UPSID, ++ RC_ANA_CL_OWN_UPSID, ++ RC_ANA_L2_OWN_UPSID, ++ RC_ASM_PORT_CFG, ++ RC_DSM_BUF_CFG, ++ RC_DSM_DEV_TX_STOP_WM_CFG, ++ RC_DSM_RX_PAUSE_CFG, ++ RC_DSM_MAC_CFG, ++ RC_DSM_MAC_ADDR_BASE_HIGH_CFG, ++ RC_DSM_MAC_ADDR_BASE_LOW_CFG, ++ RC_DSM_TAXI_CAL_CFG, ++ RC_GCB_HW_SGPIO_TO_SD_MAP_CFG, ++ RC_HSCH_PORT_MODE, ++ RC_QFWD_SWITCH_PORT_MODE, ++ RC_QSYS_PAUSE_CFG, ++ RC_QSYS_ATOP, ++ RC_QSYS_FWD_PRESSURE, ++ RC_QSYS_CAL_AUTO, ++ RC_REW_OWN_UPSID, ++ RC_REW_RTAG_ETAG_CTRL, ++ RCNT_LAST, ++}; ++ ++enum sparx5_gaddr_enum { ++ GA_ANA_AC_RAM_CTRL, ++ GA_ANA_AC_PS_COMMON, ++ GA_ANA_AC_MIRROR_PROBE, ++ GA_ANA_AC_SRC, ++ GA_ANA_AC_PGID, ++ GA_ANA_AC_TSN_SF, ++ GA_ANA_AC_TSN_SF_CFG, ++ GA_ANA_AC_TSN_SF_STATUS, ++ GA_ANA_AC_SG_ACCESS, ++ GA_ANA_AC_SG_CONFIG, ++ GA_ANA_AC_SG_STATUS, ++ GA_ANA_AC_SG_STATUS_STICKY, ++ GA_ANA_AC_STAT_GLOBAL_CFG_PORT, ++ GA_ANA_AC_STAT_CNT_CFG_PORT, ++ GA_ANA_AC_STAT_GLOBAL_CFG_ACL, ++ GA_ANA_ACL_COMMON, ++ GA_ANA_ACL_KEY_SEL, ++ GA_ANA_ACL_CNT_B, ++ GA_ANA_ACL_STICKY, ++ GA_ANA_AC_POL_POL_ALL_CFG, ++ GA_ANA_AC_POL_COMMON_BDLB, ++ GA_ANA_AC_POL_COMMON_BUM_SLB, ++ GA_ANA_AC_SDLB_LBGRP_TBL, ++ GA_ANA_CL_PORT, ++ GA_ANA_CL_COMMON, ++ GA_ANA_L2_COMMON, ++ GA_ANA_L3_COMMON, ++ GA_ANA_L3_VLAN_ARP_L3MC_STICKY, ++ GA_ASM_CFG, ++ GA_ASM_PFC_TIMER_CFG, ++ GA_ASM_LBK_WM_CFG, ++ GA_ASM_LBK_MISC_CFG, ++ GA_ASM_RAM_CTRL, ++ GA_EACL_ES2_KEY_SELECT_PROFILE, ++ GA_EACL_CNT_TBL, ++ GA_EACL_POL_CFG, ++ GA_EACL_ES2_STICKY, ++ GA_EACL_RAM_CTRL, ++ GA_GCB_SIO_CTRL, ++ GA_HSCH_HSCH_DWRR, ++ GA_HSCH_HSCH_MISC, ++ GA_HSCH_HSCH_LEAK_LISTS, ++ GA_HSCH_SYSTEM, ++ GA_HSCH_MMGT, ++ GA_HSCH_TAS_CONFIG, ++ GA_PTP_PTP_CFG, ++ GA_PTP_PTP_TOD_DOMAINS, ++ GA_PTP_PHASE_DETECTOR_CTRL, ++ GA_QSYS_CALCFG, ++ GA_QSYS_RAM_CTRL, ++ GA_REW_COMMON, ++ GA_REW_PORT, ++ GA_REW_VOE_PORT_LM_CNT, ++ GA_REW_RAM_CTRL, ++ GA_VOP_RAM_CTRL, ++ GA_XQS_SYSTEM, ++ GA_XQS_QLIMIT_SHR, ++ GADDR_LAST, ++}; ++ ++enum sparx5_gcnt_enum { ++ GC_ANA_AC_SRC, ++ GC_ANA_AC_PGID, ++ GC_ANA_AC_TSN_SF_CFG, ++ GC_ANA_AC_STAT_CNT_CFG_PORT, ++ GC_ANA_ACL_KEY_SEL, ++ GC_ANA_ACL_CNT_A, ++ GC_ANA_ACL_CNT_B, ++ GC_ANA_AC_SDLB_LBGRP_TBL, ++ GC_ANA_AC_SDLB_LBSET_TBL, ++ GC_ANA_CL_PORT, ++ GC_ANA_L2_ISDX_LIMIT, ++ GC_ANA_L2_ISDX, ++ GC_ANA_L3_VLAN, ++ GC_ASM_DEV_STATISTICS, ++ GC_EACL_ES2_KEY_SELECT_PROFILE, ++ GC_EACL_CNT_TBL, ++ GC_GCB_SIO_CTRL, ++ GC_HSCH_HSCH_CFG, ++ GC_HSCH_HSCH_DWRR, ++ GC_PTP_PTP_PINS, ++ GC_PTP_PHASE_DETECTOR_CTRL, ++ GC_REW_PORT, ++ GC_REW_VOE_PORT_LM_CNT, ++ GCNT_LAST, ++}; ++ ++enum sparx5_gsize_enum { ++ GW_ANA_AC_SRC, ++ GW_ANA_L2_COMMON, ++ GW_ASM_CFG, ++ GW_CPU_CPU_REGS, ++ GW_FDMA_FDMA, ++ GW_GCB_CHIP_REGS, ++ GW_HSCH_TAS_CONFIG, ++ GW_PTP_PHASE_DETECTOR_CTRL, ++ GW_QSYS_PAUSE_CFG, ++ GSIZE_LAST, ++}; ++ ++enum sparx5_fpos_enum { ++ FP_CPU_PROC_CTRL_AARCH64_MODE_ENA, ++ FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, ++ FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, ++ FP_CPU_PROC_CTRL_BE_EXCEP_MODE, ++ FP_CPU_PROC_CTRL_VINITHI, ++ FP_CPU_PROC_CTRL_CFGTE, ++ FP_CPU_PROC_CTRL_CP15S_DISABLE, ++ FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, ++ FP_CPU_PROC_CTRL_L2_FLUSH_REQ, ++ FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE, ++ FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, ++ FP_FDMA_CH_CFG_CH_INJ_PORT, ++ FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION, ++ FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC, ++ FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, ++ FP_PTP_PHAD_CTRL_PHAD_ENA, ++ FP_PTP_PHAD_CTRL_PHAD_FAILED, ++ FPOS_LAST, ++}; ++ ++enum sparx5_fsize_enum { ++ FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK, ++ FW_ANA_AC_SRC_CFG_PORT_MASK, ++ FW_ANA_AC_PGID_CFG_PORT_MASK, ++ FW_ANA_AC_TSN_SF_PORT_NUM, ++ FW_ANA_AC_TSN_SF_CFG_TSN_SGID, ++ FW_ANA_AC_TSN_SF_STATUS_TSN_SFID, ++ FW_ANA_AC_SG_ACCESS_CTRL_SGID, ++ FW_ANA_AC_PORT_SGE_CFG_MASK, ++ FW_ANA_AC_SDLB_XLB_START_LBSET_START, ++ FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, ++ FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, ++ FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, ++ FW_ANA_AC_SDLB_XLB_NEXT_LBGRP, ++ FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, ++ FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA, ++ FW_ANA_L2_DLB_CFG_DLB_IDX, ++ FW_ANA_L2_TSN_CFG_TSN_SFID, ++ FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK, ++ FW_FDMA_CH_CFG_CH_DCB_DB_CNT, ++ FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, ++ FW_HSCH_SE_CFG_SE_DWRR_CNT, ++ FW_HSCH_SE_CONNECT_SE_LEAK_LINK, ++ FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT, ++ FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX, ++ FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST, ++ FW_HSCH_FLUSH_CTRL_FLUSH_PORT, ++ FW_HSCH_FLUSH_CTRL_FLUSH_HIER, ++ FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, ++ FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, ++ FW_LRN_AUTOAGE_CFG_2_NEXT_ROW, ++ FW_PTP_PTP_PIN_INTR_INTR_PTP, ++ FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, ++ FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, ++ FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT, ++ FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, ++ FW_QRES_RES_CFG_WM_HIGH, ++ FW_QRES_RES_STAT_MAXUSE, ++ FW_QRES_RES_STAT_CUR_INUSE, ++ FW_QSYS_PAUSE_CFG_PAUSE_START, ++ FW_QSYS_PAUSE_CFG_PAUSE_STOP, ++ FW_QSYS_ATOP_ATOP, ++ FW_QSYS_ATOP_TOT_CFG_ATOP_TOT, ++ FW_REW_RTAG_ETAG_CTRL_IPE_TBL, ++ FW_XQS_STAT_CFG_STAT_VIEW, ++ FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, ++ FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, ++ FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, ++ FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, ++ FSIZE_LAST, ++}; ++ ++extern const unsigned int sparx5_tsize[TSIZE_LAST]; ++extern const unsigned int sparx5_raddr[RADDR_LAST]; ++extern const unsigned int sparx5_rcnt[RCNT_LAST]; ++extern const unsigned int sparx5_gaddr[GADDR_LAST]; ++extern const unsigned int sparx5_gcnt[GCNT_LAST]; ++extern const unsigned int sparx5_gsize[GSIZE_LAST]; ++extern const unsigned int sparx5_fpos[FPOS_LAST]; ++extern const unsigned int sparx5_fsize[FSIZE_LAST]; ++ ++#endif /* _SPARX5_REGS_H_ */ diff --git a/target/linux/microchipsw/patches-6.12/0026-v6.13-net-sparx5-modify-SPX5_PORTS_ALL-macro.patch b/target/linux/microchipsw/patches-6.12/0026-v6.13-net-sparx5-modify-SPX5_PORTS_ALL-macro.patch new file mode 100644 index 0000000000..226e52435a --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0026-v6.13-net-sparx5-modify-SPX5_PORTS_ALL-macro.patch @@ -0,0 +1,36 @@ +From 9f4b9996e892cd721bf1f6664c3ba95a7592924c Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:29 +0200 +Subject: [PATCH 31/82] net: sparx5: modify SPX5_PORTS_ALL macro + +In preparation for lan969x, we need to define the SPX5_PORTS_ALL macro +as 70 (65 front ports + 5 internal ports). This is required as the +SPX5_PORT_CPU will be redefined as an offset to the number of front +ports, in a subsequent patch. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -52,13 +52,14 @@ enum sparx5_vlan_port_type { + }; + + #define SPX5_PORTS 65 ++#define SPX5_PORTS_ALL 70 /* Total number of ports */ ++ + #define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ + #define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ + #define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ + #define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ + #define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ + #define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ +-#define SPX5_PORTS_ALL (SPX5_PORT_CPU + 5) /* Total number of ports */ + + #define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ + #define PGID_UC_FLOOD (PGID_BASE + 0) diff --git a/target/linux/microchipsw/patches-6.12/0027-v6.13-net-sparx5-add-sparx5-argument-to-a-few-functions.patch b/target/linux/microchipsw/patches-6.12/0027-v6.13-net-sparx5-add-sparx5-argument-to-a-few-functions.patch new file mode 100644 index 0000000000..556c0c8945 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0027-v6.13-net-sparx5-add-sparx5-argument-to-a-few-functions.patch @@ -0,0 +1,355 @@ +From fc875dc858249c8c2c2eac758c3f89b3a7719f74 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:30 +0200 +Subject: [PATCH 32/82] net: sparx5: add *sparx5 argument to a few functions + +The *sparx5 context pointer is required in functions that need to access +platform constants (which will be added in a subsequent patch). Prepare +for this by updating the prototype and use of such functions. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../microchip/sparx5/sparx5_ethtool.c | 24 ++++++++-------- + .../ethernet/microchip/sparx5/sparx5_main.h | 2 +- + .../ethernet/microchip/sparx5/sparx5_netdev.c | 2 +- + .../ethernet/microchip/sparx5/sparx5_packet.c | 2 +- + .../ethernet/microchip/sparx5/sparx5_port.c | 28 +++++++++---------- + .../ethernet/microchip/sparx5/sparx5_port.h | 6 ++-- + .../ethernet/microchip/sparx5/sparx5_psfp.c | 24 ++++++++-------- + .../net/ethernet/microchip/sparx5/sparx5_tc.c | 8 +++--- + 8 files changed, 48 insertions(+), 48 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c +@@ -505,8 +505,8 @@ static void sparx5_get_dev_misc_stats(u6 + static void sparx5_get_device_stats(struct sparx5 *sparx5, int portno) + { + u64 *portstats = &sparx5->stats[portno * sparx5->num_stats]; +- u32 tinst = sparx5_port_dev_index(portno); +- u32 dev = sparx5_to_high_dev(portno); ++ u32 tinst = sparx5_port_dev_index(sparx5, portno); ++ u32 dev = sparx5_to_high_dev(sparx5, portno); + void __iomem *inst; + + inst = spx5_inst_get(sparx5, dev, tinst); +@@ -819,8 +819,8 @@ static void sparx5_get_eth_phy_stats(str + + portstats = &sparx5->stats[portno * sparx5->num_stats]; + if (sparx5_is_baser(port->conf.portmode)) { +- u32 tinst = sparx5_port_dev_index(portno); +- u32 dev = sparx5_to_high_dev(portno); ++ u32 tinst = sparx5_port_dev_index(sparx5, portno); ++ u32 dev = sparx5_to_high_dev(sparx5, portno); + + inst = spx5_inst_get(sparx5, dev, tinst); + sparx5_get_dev_phy_stats(portstats, inst, tinst); +@@ -844,8 +844,8 @@ static void sparx5_get_eth_mac_stats(str + + portstats = &sparx5->stats[portno * sparx5->num_stats]; + if (sparx5_is_baser(port->conf.portmode)) { +- u32 tinst = sparx5_port_dev_index(portno); +- u32 dev = sparx5_to_high_dev(portno); ++ u32 tinst = sparx5_port_dev_index(sparx5, portno); ++ u32 dev = sparx5_to_high_dev(sparx5, portno); + + inst = spx5_inst_get(sparx5, dev, tinst); + sparx5_get_dev_mac_stats(portstats, inst, tinst); +@@ -912,8 +912,8 @@ static void sparx5_get_eth_mac_ctrl_stat + + portstats = &sparx5->stats[portno * sparx5->num_stats]; + if (sparx5_is_baser(port->conf.portmode)) { +- u32 tinst = sparx5_port_dev_index(portno); +- u32 dev = sparx5_to_high_dev(portno); ++ u32 tinst = sparx5_port_dev_index(sparx5, portno); ++ u32 dev = sparx5_to_high_dev(sparx5, portno); + + inst = spx5_inst_get(sparx5, dev, tinst); + sparx5_get_dev_mac_ctrl_stats(portstats, inst, tinst); +@@ -944,8 +944,8 @@ static void sparx5_get_eth_rmon_stats(st + + portstats = &sparx5->stats[portno * sparx5->num_stats]; + if (sparx5_is_baser(port->conf.portmode)) { +- u32 tinst = sparx5_port_dev_index(portno); +- u32 dev = sparx5_to_high_dev(portno); ++ u32 tinst = sparx5_port_dev_index(sparx5, portno); ++ u32 dev = sparx5_to_high_dev(sparx5, portno); + + inst = spx5_inst_get(sparx5, dev, tinst); + sparx5_get_dev_rmon_stats(portstats, inst, tinst); +@@ -1027,8 +1027,8 @@ static void sparx5_get_sset_data(struct + + portstats = &sparx5->stats[portno * sparx5->num_stats]; + if (sparx5_is_baser(port->conf.portmode)) { +- u32 tinst = sparx5_port_dev_index(portno); +- u32 dev = sparx5_to_high_dev(portno); ++ u32 tinst = sparx5_port_dev_index(sparx5, portno); ++ u32 dev = sparx5_to_high_dev(sparx5, portno); + + inst = spx5_inst_get(sparx5, dev, tinst); + sparx5_get_dev_misc_stats(portstats, inst, tinst); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -401,7 +401,7 @@ void sparx5_set_port_ifh_timestamp(void + void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); + void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); + void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); +-void sparx5_set_port_ifh(void *ifh_hdr, u16 portno); ++void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno); + bool sparx5_netdevice_check(const struct net_device *dev); + struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); + int sparx5_register_netdevs(struct sparx5 *sparx5); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c +@@ -55,7 +55,7 @@ static void __ifh_encode_bitfield(void * + ifh_hdr[byte - 5] |= (u8)((encode & 0xFF0000000000) >> 40); + } + +-void sparx5_set_port_ifh(void *ifh_hdr, u16 portno) ++void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno) + { + /* VSTAX.RSV = 1. MSBit must be 1 */ + ifh_encode_bitfield(ifh_hdr, 1, VSTAX + 79, 1); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +@@ -235,7 +235,7 @@ netdev_tx_t sparx5_port_xmit_impl(struct + netdev_tx_t ret; + + memset(ifh, 0, IFH_LEN * 4); +- sparx5_set_port_ifh(ifh, port->portno); ++ sparx5_set_port_ifh(sparx5, ifh, port->portno); + + if (sparx5->ptp && skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) { + if (sparx5_ptp_txtstamp_request(port, skb) < 0) +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -132,8 +132,8 @@ static int sparx5_get_sfi_status(struct + return -EINVAL; + } + +- dev = sparx5_to_high_dev(portno); +- tinst = sparx5_port_dev_index(portno); ++ dev = sparx5_to_high_dev(sparx5, portno); ++ tinst = sparx5_port_dev_index(sparx5, portno); + inst = spx5_inst_get(sparx5, dev, tinst); + + value = spx5_inst_rd(inst, DEV10G_MAC_TX_MONITOR_STICKY(0)); +@@ -316,9 +316,9 @@ static int sparx5_port_flush_poll(struct + static int sparx5_port_disable(struct sparx5 *sparx5, struct sparx5_port *port, bool high_spd_dev) + { + u32 tinst = high_spd_dev ? +- sparx5_port_dev_index(port->portno) : port->portno; ++ sparx5_port_dev_index(sparx5, port->portno) : port->portno; + u32 dev = high_spd_dev ? +- sparx5_to_high_dev(port->portno) : TARGET_DEV2G5; ++ sparx5_to_high_dev(sparx5, port->portno) : TARGET_DEV2G5; + void __iomem *devinst = spx5_inst_get(sparx5, dev, tinst); + u32 spd = port->conf.speed; + u32 spd_prm; +@@ -427,7 +427,7 @@ static int sparx5_port_disable(struct sp + HSCH_FLUSH_CTRL); + + if (high_spd_dev) { +- u32 pcs = sparx5_to_pcs_dev(port->portno); ++ u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); + void __iomem *pcsinst = spx5_inst_get(sparx5, pcs, tinst); + + /* 12: Disable 5G/10G/25 BaseR PCS */ +@@ -558,8 +558,8 @@ static int sparx5_port_max_tags_set(stru + bool dtag = max_tags == SPX5_PORT_MAX_TAGS_TWO; + enum sparx5_vlan_port_type vlan_type = port->vlan_type; + bool dotag = max_tags != SPX5_PORT_MAX_TAGS_NONE; +- u32 dev = sparx5_to_high_dev(port->portno); +- u32 tinst = sparx5_port_dev_index(port->portno); ++ u32 dev = sparx5_to_high_dev(sparx5, port->portno); ++ u32 tinst = sparx5_port_dev_index(sparx5, port->portno); + void __iomem *inst = spx5_inst_get(sparx5, dev, tinst); + u32 etype; + +@@ -789,9 +789,9 @@ static int sparx5_port_pcs_high_set(stru + struct sparx5_port_config *conf) + { + u32 clk_spd = conf->portmode == PHY_INTERFACE_MODE_5GBASER ? 1 : 0; +- u32 pix = sparx5_port_dev_index(port->portno); +- u32 dev = sparx5_to_high_dev(port->portno); +- u32 pcs = sparx5_to_pcs_dev(port->portno); ++ u32 pix = sparx5_port_dev_index(sparx5, port->portno); ++ u32 dev = sparx5_to_high_dev(sparx5, port->portno); ++ u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); + void __iomem *devinst; + void __iomem *pcsinst; + int err; +@@ -843,7 +843,7 @@ static int sparx5_port_pcs_high_set(stru + /* Switch between 1G/2500 and 5G/10G/25G devices */ + static void sparx5_dev_switch(struct sparx5 *sparx5, int port, bool hsd) + { +- int bt_indx = BIT(sparx5_port_dev_index(port)); ++ int bt_indx = BIT(sparx5_port_dev_index(sparx5, port)); + + if (sparx5_port_is_5g(port)) { + spx5_rmw(hsd ? 0 : bt_indx, +@@ -1016,9 +1016,9 @@ int sparx5_port_init(struct sparx5 *spar + { + u32 pause_start = sparx5_wm_enc(6 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); + u32 atop = sparx5_wm_enc(20 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); +- u32 devhigh = sparx5_to_high_dev(port->portno); +- u32 pix = sparx5_port_dev_index(port->portno); +- u32 pcs = sparx5_to_pcs_dev(port->portno); ++ u32 devhigh = sparx5_to_high_dev(sparx5, port->portno); ++ u32 pix = sparx5_port_dev_index(sparx5, port->portno); ++ u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); + bool sd_pol = port->signd_active_high; + bool sd_sel = !port->signd_internal; + bool sd_ena = port->signd_enable; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h +@@ -40,7 +40,7 @@ static inline bool sparx5_port_is_25g(in + return portno >= 56 && portno <= 63; + } + +-static inline u32 sparx5_to_high_dev(int port) ++static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) + { + if (sparx5_port_is_5g(port)) + return TARGET_DEV5G; +@@ -49,7 +49,7 @@ static inline u32 sparx5_to_high_dev(int + return TARGET_DEV25G; + } + +-static inline u32 sparx5_to_pcs_dev(int port) ++static inline u32 sparx5_to_pcs_dev(struct sparx5 *sparx5, int port) + { + if (sparx5_port_is_5g(port)) + return TARGET_PCS5G_BR; +@@ -58,7 +58,7 @@ static inline u32 sparx5_to_pcs_dev(int + return TARGET_PCS25G_BR; + } + +-static inline int sparx5_port_dev_index(int port) ++static inline int sparx5_port_dev_index(struct sparx5 *sparx5, int port) + { + if (sparx5_port_is_2g5(port)) + return port; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c +@@ -20,34 +20,34 @@ static struct sparx5_pool_entry sparx5_p + /* Pool of available stream filters */ + static struct sparx5_pool_entry sparx5_psfp_sf_pool[SPX5_PSFP_SF_CNT]; + +-static int sparx5_psfp_sf_get(u32 *id) ++static int sparx5_psfp_sf_get(struct sparx5 *sparx5, u32 *id) + { + return sparx5_pool_get(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); + } + +-static int sparx5_psfp_sf_put(u32 id) ++static int sparx5_psfp_sf_put(struct sparx5 *sparx5, u32 id) + { + return sparx5_pool_put(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); + } + +-static int sparx5_psfp_sg_get(u32 idx, u32 *id) ++static int sparx5_psfp_sg_get(struct sparx5 *sparx5, u32 idx, u32 *id) + { + return sparx5_pool_get_with_idx(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, + idx, id); + } + +-static int sparx5_psfp_sg_put(u32 id) ++static int sparx5_psfp_sg_put(struct sparx5 *sparx5, u32 id) + { + return sparx5_pool_put(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, id); + } + +-static int sparx5_psfp_fm_get(u32 idx, u32 *id) ++static int sparx5_psfp_fm_get(struct sparx5 *sparx5, u32 idx, u32 *id) + { + return sparx5_pool_get_with_idx(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, idx, + id); + } + +-static int sparx5_psfp_fm_put(u32 id) ++static int sparx5_psfp_fm_put(struct sparx5 *sparx5, u32 id) + { + return sparx5_pool_put(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, id); + } +@@ -205,7 +205,7 @@ int sparx5_psfp_sf_add(struct sparx5 *sp + { + int ret; + +- ret = sparx5_psfp_sf_get(id); ++ ret = sparx5_psfp_sf_get(sparx5, id); + if (ret < 0) + return ret; + +@@ -220,7 +220,7 @@ int sparx5_psfp_sf_del(struct sparx5 *sp + + sparx5_psfp_sf_set(sparx5, id, &sf); + +- return sparx5_psfp_sf_put(id); ++ return sparx5_psfp_sf_put(sparx5, id); + } + + int sparx5_psfp_sg_add(struct sparx5 *sparx5, u32 uidx, +@@ -229,7 +229,7 @@ int sparx5_psfp_sg_add(struct sparx5 *sp + ktime_t basetime; + int ret; + +- ret = sparx5_psfp_sg_get(uidx, id); ++ ret = sparx5_psfp_sg_get(sparx5, uidx, id); + if (ret < 0) + return ret; + /* Was already in use, no need to reconfigure */ +@@ -253,7 +253,7 @@ int sparx5_psfp_sg_del(struct sparx5 *sp + const struct sparx5_psfp_sg sg = { 0 }; + int ret; + +- ret = sparx5_psfp_sg_put(id); ++ ret = sparx5_psfp_sg_put(sparx5, id); + if (ret < 0) + return ret; + /* Stream gate still in use ? */ +@@ -270,7 +270,7 @@ int sparx5_psfp_fm_add(struct sparx5 *sp + int ret; + + /* Get flow meter */ +- ret = sparx5_psfp_fm_get(uidx, &fm->pol.idx); ++ ret = sparx5_psfp_fm_get(sparx5, uidx, &fm->pol.idx); + if (ret < 0) + return ret; + /* Was already in use, no need to reconfigure */ +@@ -303,7 +303,7 @@ int sparx5_psfp_fm_del(struct sparx5 *sp + if (ret < 0) + return ret; + +- ret = sparx5_psfp_fm_put(id); ++ ret = sparx5_psfp_fm_put(sparx5, id); + if (ret < 0) + return ret; + /* Do not reset flow-meter if still in use. */ +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_tc.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_tc.c +@@ -60,8 +60,8 @@ static int sparx5_tc_setup_block(struct + cb, ndev, ndev, false); + } + +-static void sparx5_tc_get_layer_and_idx(u32 parent, u32 portno, u32 *layer, +- u32 *idx) ++static void sparx5_tc_get_layer_and_idx(struct sparx5 *sparx5, u32 parent, ++ u32 portno, u32 *layer, u32 *idx) + { + if (parent == TC_H_ROOT) { + *layer = 2; +@@ -90,8 +90,8 @@ static int sparx5_tc_setup_qdisc_tbf(str + struct sparx5_port *port = netdev_priv(ndev); + u32 layer, se_idx; + +- sparx5_tc_get_layer_and_idx(qopt->parent, port->portno, &layer, +- &se_idx); ++ sparx5_tc_get_layer_and_idx(port->sparx5, qopt->parent, port->portno, ++ &layer, &se_idx); + + switch (qopt->command) { + case TC_TBF_REPLACE: diff --git a/target/linux/microchipsw/patches-6.12/0028-v6.13-net-sparx5-add-constants-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0028-v6.13-net-sparx5-add-constants-to-match-data.patch new file mode 100644 index 0000000000..219d1e8d34 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0028-v6.13-net-sparx5-add-constants-to-match-data.patch @@ -0,0 +1,88 @@ +From e263a2c741eef417e769075e11d32318b8b2b8ab Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:31 +0200 +Subject: [PATCH 33/82] net: sparx5: add constants to match data + +Add new struct sparx5_consts, containing all the chip constants that are +known to be different for Sparx5 and lan969x. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../ethernet/microchip/sparx5/sparx5_main.c | 21 +++++++++++++++++++ + .../ethernet/microchip/sparx5/sparx5_main.h | 21 +++++++++++++++++++ + 2 files changed, 42 insertions(+) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -952,11 +952,32 @@ static const struct sparx5_regs sparx5_r + .fsize = sparx5_fsize, + }; + ++static const struct sparx5_consts sparx5_consts = { ++ .n_ports = 65, ++ .n_ports_all = 70, ++ .n_hsch_l1_elems = 64, ++ .n_hsch_queues = 8, ++ .n_lb_groups = 10, ++ .n_pgids = 2113, /* (2048 + n_ports) */ ++ .n_sio_clks = 3, ++ .n_own_upsids = 3, ++ .n_auto_cals = 7, ++ .n_filters = 1024, ++ .n_gates = 1024, ++ .n_sdlbs = 4096, ++ .n_dsm_cal_taxis = 8, ++ .buf_size = 4194280, ++ .qres_max_prio_idx = 630, ++ .qres_max_colour_idx = 638, ++ .tod_pin = 4, ++}; ++ + static const struct sparx5_match_data sparx5_desc = { + .iomap = sparx5_main_iomap, + .iomap_size = ARRAY_SIZE(sparx5_main_iomap), + .ioranges = 3, + .regs = &sparx5_regs, ++ .consts = &sparx5_consts, + }; + + static const struct of_device_id mchp_sparx5_match[] = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -238,6 +238,26 @@ struct sparx5_regs { + const unsigned int *fsize; + }; + ++struct sparx5_consts { ++ u32 n_ports; /* Number of front ports */ ++ u32 n_ports_all; /* Number of front ports + internal ports */ ++ u32 n_hsch_l1_elems; /* Number of HSCH layer 1 elements */ ++ u32 n_hsch_queues; /* Number of HSCH queues */ ++ u32 n_lb_groups; /* Number of leacky bucket groupd */ ++ u32 n_pgids; /* Number of PGID's */ ++ u32 n_sio_clks; /* Number of serial IO clocks */ ++ u32 n_own_upsids; /* Number of own UPSID's */ ++ u32 n_auto_cals; /* Number of auto calendars */ ++ u32 n_filters; /* Number of PSFP filters */ ++ u32 n_gates; /* Number of PSFP gates */ ++ u32 n_sdlbs; /* Number of service dual leaky buckets */ ++ u32 n_dsm_cal_taxis; /* Number of DSM calendar taxis */ ++ u32 buf_size; /* Amount of QLIM watermark memory */ ++ u32 qres_max_prio_idx; /* Maximum QRES prio index */ ++ u32 qres_max_colour_idx; /* Maximum QRES colour index */ ++ u32 tod_pin; /* PTP TOD pin */ ++}; ++ + struct sparx5_main_io_resource { + enum sparx5_target id; + phys_addr_t offset; +@@ -246,6 +266,7 @@ struct sparx5_main_io_resource { + + struct sparx5_match_data { + const struct sparx5_regs *regs; ++ const struct sparx5_consts *consts; + const struct sparx5_main_io_resource *iomap; + int ioranges; + int iomap_size; diff --git a/target/linux/microchipsw/patches-6.12/0029-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-alread.patch b/target/linux/microchipsw/patches-6.12/0029-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-alread.patch new file mode 100644 index 0000000000..a0832128b8 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0029-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-alread.patch @@ -0,0 +1,600 @@ +From 27584455298c4d27246bfcb7ac6c570128648847 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:32 +0200 +Subject: [PATCH 34/82] net: sparx5: use SPX5_CONST for constants which already + have a symbol + +Now that we have indentified all the chip constants, update the use of +them where a symbol is already defined for the constant. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../microchip/sparx5/sparx5_calendar.c | 13 +++--- + .../ethernet/microchip/sparx5/sparx5_dcb.c | 5 ++- + .../microchip/sparx5/sparx5_ethtool.c | 8 ++-- + .../ethernet/microchip/sparx5/sparx5_fdma.c | 6 ++- + .../microchip/sparx5/sparx5_mactable.c | 7 +-- + .../ethernet/microchip/sparx5/sparx5_main.c | 21 +++++---- + .../ethernet/microchip/sparx5/sparx5_netdev.c | 7 ++- + .../ethernet/microchip/sparx5/sparx5_packet.c | 2 +- + .../ethernet/microchip/sparx5/sparx5_pgid.c | 6 +-- + .../ethernet/microchip/sparx5/sparx5_psfp.c | 22 ++++++---- + .../ethernet/microchip/sparx5/sparx5_ptp.c | 44 ++++++++++++------- + .../ethernet/microchip/sparx5/sparx5_sdlb.c | 4 +- + .../microchip/sparx5/sparx5_switchdev.c | 2 +- + .../microchip/sparx5/sparx5_tc_flower.c | 4 +- + .../ethernet/microchip/sparx5/sparx5_vlan.c | 2 +- + 15 files changed, 90 insertions(+), 63 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +@@ -131,7 +131,7 @@ static enum sparx5_cal_bw sparx5_get_por + { + struct sparx5_port *port; + +- if (portno >= SPX5_PORTS) { ++ if (portno >= sparx5->data->consts->n_ports) { + /* Internal ports */ + if (portno == SPX5_PORT_CPU_0 || portno == SPX5_PORT_CPU_1) { + /* Equals 1.25G */ +@@ -159,6 +159,7 @@ static enum sparx5_cal_bw sparx5_get_por + /* Auto configure the QSYS calendar based on port configuration */ + int sparx5_config_auto_calendar(struct sparx5 *sparx5) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + u32 cal[7], value, idx, portno; + u32 max_core_bw; + u32 total_bw = 0, used_port_bw = 0; +@@ -174,7 +175,7 @@ int sparx5_config_auto_calendar(struct s + } + + /* Setup the calendar with the bandwidth to each port */ +- for (portno = 0; portno < SPX5_PORTS_ALL; portno++) { ++ for (portno = 0; portno < consts->n_ports_all; portno++) { + u64 reg, offset, this_bw; + + spd = sparx5_get_port_cal_speed(sparx5, portno); +@@ -182,7 +183,7 @@ int sparx5_config_auto_calendar(struct s + continue; + + this_bw = sparx5_cal_speed_to_value(spd); +- if (portno < SPX5_PORTS) ++ if (portno < consts->n_ports) + used_port_bw += this_bw; + else + /* Internal ports are granted half the value */ +@@ -213,7 +214,7 @@ int sparx5_config_auto_calendar(struct s + sparx5, QSYS_CAL_CTRL); + + /* Assign port bandwidth to auto calendar */ +- for (idx = 0; idx < ARRAY_SIZE(cal); idx++) ++ for (idx = 0; idx < consts->n_auto_cals; idx++) + spx5_wr(cal[idx], sparx5, QSYS_CAL_AUTO(idx)); + + /* Increase grant rate of all ports to account for +@@ -304,7 +305,7 @@ static int sparx5_dsm_calendar_calc(stru + for (idx = 0; idx < SPX5_DSM_CAL_MAX_DEVS_PER_TAXI; idx++) { + u32 portno = data->taxi_ports[idx]; + +- if (portno < SPX5_TAXI_PORT_MAX) { ++ if (portno < sparx5->data->consts->n_ports_all) { + data->taxi_speeds[idx] = sparx5_cal_speed_to_value + (sparx5_get_port_cal_speed(sparx5, portno)); + } else { +@@ -573,7 +574,7 @@ int sparx5_config_dsm_calendar(struct sp + if (!data) + return -ENOMEM; + +- for (taxi = 0; taxi < SPX5_DSM_CAL_TAXIS; ++taxi) { ++ for (taxi = 0; taxi < sparx5->data->consts->n_dsm_cal_taxis; ++taxi) { + err = sparx5_dsm_calendar_calc(sparx5, taxi, data); + if (err) { + dev_err(sparx5->dev, "DSM calendar calculation failed\n"); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_dcb.c +@@ -234,10 +234,11 @@ static int sparx5_dcb_ieee_dscp_setdel(s + struct dcb_app *)) + { + struct sparx5_port *port = netdev_priv(dev); ++ struct sparx5 *sparx5 = port->sparx5; + struct sparx5_port *port_itr; + int err, i; + +- for (i = 0; i < SPX5_PORTS; i++) { ++ for (i = 0; i < sparx5->data->consts->n_ports; i++) { + port_itr = port->sparx5->ports[i]; + if (!port_itr) + continue; +@@ -386,7 +387,7 @@ int sparx5_dcb_init(struct sparx5 *sparx + struct sparx5_port *port; + int i; + +- for (i = 0; i < SPX5_PORTS; i++) { ++ for (i = 0; i < sparx5->data->consts->n_ports; i++) { + port = sparx5->ports[i]; + if (!port) + continue; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c +@@ -1122,7 +1122,7 @@ static void sparx5_update_stats(struct s + { + int idx; + +- for (idx = 0; idx < SPX5_PORTS; idx++) ++ for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) + if (sparx5->ports[idx]) + sparx5_update_port_stats(sparx5, idx); + } +@@ -1228,6 +1228,7 @@ const struct ethtool_ops sparx5_ethtool_ + + int sparx_stats_init(struct sparx5 *sparx5) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + char queue_name[32]; + int portno; + +@@ -1235,14 +1236,15 @@ int sparx_stats_init(struct sparx5 *spar + sparx5->num_stats = spx5_stats_count; + sparx5->num_ethtool_stats = ARRAY_SIZE(sparx5_stats_layout); + sparx5->stats = devm_kcalloc(sparx5->dev, +- SPX5_PORTS_ALL * sparx5->num_stats, ++ consts->n_ports_all * ++ sparx5->num_stats, + sizeof(u64), GFP_KERNEL); + if (!sparx5->stats) + return -ENOMEM; + + mutex_init(&sparx5->queue_stats_lock); + sparx5_config_stats(sparx5); +- for (portno = 0; portno < SPX5_PORTS; portno++) ++ for (portno = 0; portno < consts->n_ports; portno++) + if (sparx5->ports[portno]) + sparx5_config_port_stats(sparx5, portno); + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c +@@ -156,7 +156,9 @@ static bool sparx5_fdma_rx_get_frame(str + /* Now do the normal processing of the skb */ + sparx5_ifh_parse((u32 *)skb->data, &fi); + /* Map to port netdev */ +- port = fi.src_port < SPX5_PORTS ? sparx5->ports[fi.src_port] : NULL; ++ port = fi.src_port < sparx5->data->consts->n_ports ? ++ sparx5->ports[fi.src_port] : ++ NULL; + if (!port || !port->ndev) { + dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); + sparx5_xtr_flush(sparx5, XTR_QUEUE); +@@ -296,7 +298,7 @@ static void sparx5_fdma_rx_init(struct s + fdma->ops.dataptr_cb = &sparx5_fdma_rx_dataptr_cb; + fdma->ops.nextptr_cb = &fdma_nextptr_cb; + /* Fetch a netdev for SKB and NAPI use, any will do */ +- for (idx = 0; idx < SPX5_PORTS; ++idx) { ++ for (idx = 0; idx < sparx5->data->consts->n_ports; ++idx) { + struct sparx5_port *port = sparx5->ports[idx]; + + if (port && port->ndev) { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c +@@ -80,15 +80,16 @@ static void sparx5_mact_select(struct sp + int sparx5_mact_learn(struct sparx5 *sparx5, int pgid, + const unsigned char mac[ETH_ALEN], u16 vid) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + int addr, type, ret; + +- if (pgid < SPX5_PORTS) { ++ if (pgid < consts->n_ports) { + type = MAC_ENTRY_ADDR_TYPE_UPSID_PN; + addr = pgid % 32; + addr += (pgid / 32) << 5; /* Add upsid */ + } else { + type = MAC_ENTRY_ADDR_TYPE_MC_IDX; +- addr = pgid - SPX5_PORTS; ++ addr = pgid - consts->n_ports; + } + + mutex_lock(&sparx5->lock); +@@ -371,7 +372,7 @@ static void sparx5_mact_handle_entry(str + return; + + port = LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(cfg2); +- if (port >= SPX5_PORTS) ++ if (port >= sparx5->data->consts->n_ports) + return; + + if (!test_bit(port, sparx5->bridge_mask)) +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -31,8 +31,6 @@ + + const struct sparx5_regs *regs; + +-#define QLIM_WM(fraction) \ +- ((SPX5_BUFFER_MEMORY / SPX5_BUFFER_CELL_SZ - 100) * (fraction) / 100) + #define IO_RANGES 3 + + struct initial_port_config { +@@ -544,6 +542,12 @@ static int sparx5_init_coreclock(struct + return 0; + } + ++static u32 qlim_wm(struct sparx5 *sparx5, int fraction) ++{ ++ return (sparx5->data->consts->buf_size / SPX5_BUFFER_CELL_SZ - 100) * ++ fraction / 100; ++} ++ + static int sparx5_qlim_set(struct sparx5 *sparx5) + { + u32 res, dp, prio; +@@ -559,10 +563,10 @@ static int sparx5_qlim_set(struct sparx5 + } + + /* Set 80,90,95,100% of memory size for top watermarks */ +- spx5_wr(QLIM_WM(80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); +- spx5_wr(QLIM_WM(90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); +- spx5_wr(QLIM_WM(95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); +- spx5_wr(QLIM_WM(100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); ++ spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); ++ spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); ++ spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); ++ spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); + + return 0; + } +@@ -584,7 +588,7 @@ static void sparx5_board_init(struct spa + GCB_HW_SGPIO_SD_CFG); + + /* Refer to LOS SGPIO */ +- for (idx = 0; idx < SPX5_PORTS; idx++) ++ for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) + if (sparx5->ports[idx]) + if (sparx5->ports[idx]->conf.sd_sgpio != ~0) + spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, +@@ -595,6 +599,7 @@ static void sparx5_board_init(struct spa + static int sparx5_start(struct sparx5 *sparx5) + { + u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; ++ const struct sparx5_consts *consts = sparx5->data->consts; + char queue_name[32]; + u32 idx; + int err; +@@ -608,7 +613,7 @@ static int sparx5_start(struct sparx5 *s + } + + /* Enable CPU ports */ +- for (idx = SPX5_PORTS; idx < SPX5_PORTS_ALL; idx++) ++ for (idx = consts->n_ports; idx < consts->n_ports_all; idx++) + spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1), + QFWD_SWITCH_PORT_MODE_PORT_ENA, + sparx5, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c +@@ -290,7 +290,7 @@ int sparx5_register_netdevs(struct sparx + int portno; + int err; + +- for (portno = 0; portno < SPX5_PORTS; portno++) ++ for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) + if (sparx5->ports[portno]) { + err = register_netdev(sparx5->ports[portno]->ndev); + if (err) { +@@ -309,7 +309,7 @@ void sparx5_destroy_netdevs(struct sparx + struct sparx5_port *port; + int portno; + +- for (portno = 0; portno < SPX5_PORTS; portno++) { ++ for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) { + port = sparx5->ports[portno]; + if (port && port->phylink) { + /* Disconnect the phy */ +@@ -327,8 +327,7 @@ void sparx5_unregister_netdevs(struct sp + { + int portno; + +- for (portno = 0; portno < SPX5_PORTS; portno++) ++ for (portno = 0; portno < sparx5->data->consts->n_ports; portno++) + if (sparx5->ports[portno]) + unregister_netdev(sparx5->ports[portno]->ndev); + } +- +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +@@ -75,7 +75,7 @@ static void sparx5_xtr_grp(struct sparx5 + sparx5_ifh_parse(ifh, &fi); + + /* Map to port netdev */ +- port = fi.src_port < SPX5_PORTS ? ++ port = fi.src_port < sparx5->data->consts->n_ports ? + sparx5->ports[fi.src_port] : NULL; + if (!port || !port->ndev) { + dev_err(sparx5->dev, "Data on inactive port %d\n", fi.src_port); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_pgid.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_pgid.c +@@ -5,7 +5,7 @@ void sparx5_pgid_init(struct sparx5 *spx + { + int i; + +- for (i = 0; i < PGID_TABLE_SIZE; i++) ++ for (i = 0; i < spx5->data->consts->n_pgids; i++) + spx5->pgid_map[i] = SPX5_PGID_FREE; + + /* Reserved for unicast, flood control, broadcast, and CPU. +@@ -22,7 +22,7 @@ int sparx5_pgid_alloc_mcast(struct sparx + /* The multicast area starts at index 65, but the first 7 + * are reserved for flood masks and CPU. Start alloc after that. + */ +- for (i = PGID_MCAST_START; i < PGID_TABLE_SIZE; i++) { ++ for (i = PGID_MCAST_START; i < spx5->data->consts->n_pgids; i++) { + if (spx5->pgid_map[i] == SPX5_PGID_FREE) { + spx5->pgid_map[i] = SPX5_PGID_MULTICAST; + *idx = i; +@@ -35,7 +35,7 @@ int sparx5_pgid_alloc_mcast(struct sparx + + int sparx5_pgid_free(struct sparx5 *spx5, u16 idx) + { +- if (idx <= PGID_CPU || idx >= PGID_TABLE_SIZE) ++ if (idx <= PGID_CPU || idx >= spx5->data->consts->n_pgids) + return -EINVAL; + + if (spx5->pgid_map[idx] == SPX5_PGID_FREE) +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c +@@ -22,34 +22,38 @@ static struct sparx5_pool_entry sparx5_p + + static int sparx5_psfp_sf_get(struct sparx5 *sparx5, u32 *id) + { +- return sparx5_pool_get(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); ++ return sparx5_pool_get(sparx5_psfp_sf_pool, ++ sparx5->data->consts->n_filters, id); + } + + static int sparx5_psfp_sf_put(struct sparx5 *sparx5, u32 id) + { +- return sparx5_pool_put(sparx5_psfp_sf_pool, SPX5_PSFP_SF_CNT, id); ++ return sparx5_pool_put(sparx5_psfp_sf_pool, ++ sparx5->data->consts->n_filters, id); + } + + static int sparx5_psfp_sg_get(struct sparx5 *sparx5, u32 idx, u32 *id) + { +- return sparx5_pool_get_with_idx(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, +- idx, id); ++ return sparx5_pool_get_with_idx(sparx5_psfp_sg_pool, ++ sparx5->data->consts->n_gates, idx, id); + } + + static int sparx5_psfp_sg_put(struct sparx5 *sparx5, u32 id) + { +- return sparx5_pool_put(sparx5_psfp_sg_pool, SPX5_PSFP_SG_CNT, id); ++ return sparx5_pool_put(sparx5_psfp_sg_pool, ++ sparx5->data->consts->n_gates, id); + } + + static int sparx5_psfp_fm_get(struct sparx5 *sparx5, u32 idx, u32 *id) + { +- return sparx5_pool_get_with_idx(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, idx, +- id); ++ return sparx5_pool_get_with_idx(sparx5_psfp_fm_pool, ++ sparx5->data->consts->n_sdlbs, idx, id); + } + + static int sparx5_psfp_fm_put(struct sparx5 *sparx5, u32 id) + { +- return sparx5_pool_put(sparx5_psfp_fm_pool, SPX5_SDLB_CNT, id); ++ return sparx5_pool_put(sparx5_psfp_fm_pool, ++ sparx5->data->consts->n_sdlbs, id); + } + + u32 sparx5_psfp_isdx_get_sf(struct sparx5 *sparx5, u32 isdx) +@@ -318,7 +322,7 @@ void sparx5_psfp_init(struct sparx5 *spa + const struct sparx5_sdlb_group *group; + int i; + +- for (i = 0; i < SPX5_SDLB_GROUP_CNT; i++) { ++ for (i = 0; i < sparx5->data->consts->n_lb_groups; i++) { + group = &sdlb_groups[i]; + sparx5_sdlb_group_init(sparx5, group->max_rate, + group->min_burst, group->frame_size, i); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c +@@ -274,6 +274,7 @@ static void sparx5_get_hwtimestamp(struc + u32 nsec) + { + /* Read current PTP time to get seconds */ ++ const struct sparx5_consts *consts = sparx5->data->consts; + unsigned long flags; + u32 curr_nsec; + +@@ -285,10 +286,10 @@ static void sparx5_get_hwtimestamp(struc + PTP_PTP_PIN_CFG_PTP_PIN_ACTION | + PTP_PTP_PIN_CFG_PTP_PIN_DOM | + PTP_PTP_PIN_CFG_PTP_PIN_SYNC, +- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); ++ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); + +- ts->tv_sec = spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); +- curr_nsec = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); ++ ts->tv_sec = spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(consts->tod_pin)); ++ curr_nsec = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); + + ts->tv_nsec = nsec; + +@@ -440,8 +441,11 @@ static int sparx5_ptp_settime64(struct p + { + struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info); + struct sparx5 *sparx5 = phc->sparx5; ++ const struct sparx5_consts *consts; + unsigned long flags; + ++ consts = sparx5->data->consts; ++ + spin_lock_irqsave(&sparx5->ptp_clock_lock, flags); + + /* Must be in IDLE mode before the time can be loaded */ +@@ -451,14 +455,14 @@ static int sparx5_ptp_settime64(struct p + PTP_PTP_PIN_CFG_PTP_PIN_ACTION | + PTP_PTP_PIN_CFG_PTP_PIN_DOM | + PTP_PTP_PIN_CFG_PTP_PIN_SYNC, +- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); ++ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); + + /* Set new value */ + spx5_wr(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(upper_32_bits(ts->tv_sec)), +- sparx5, PTP_PTP_TOD_SEC_MSB(TOD_ACC_PIN)); ++ sparx5, PTP_PTP_TOD_SEC_MSB(consts->tod_pin)); + spx5_wr(lower_32_bits(ts->tv_sec), +- sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); +- spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); ++ sparx5, PTP_PTP_TOD_SEC_LSB(consts->tod_pin)); ++ spx5_wr(ts->tv_nsec, sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); + + /* Apply new values */ + spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_LOAD) | +@@ -467,7 +471,7 @@ static int sparx5_ptp_settime64(struct p + PTP_PTP_PIN_CFG_PTP_PIN_ACTION | + PTP_PTP_PIN_CFG_PTP_PIN_DOM | + PTP_PTP_PIN_CFG_PTP_PIN_SYNC, +- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); ++ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); + + spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); + +@@ -478,10 +482,13 @@ int sparx5_ptp_gettime64(struct ptp_cloc + { + struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info); + struct sparx5 *sparx5 = phc->sparx5; ++ const struct sparx5_consts *consts; + unsigned long flags; + time64_t s; + s64 ns; + ++ consts = sparx5->data->consts; ++ + spin_lock_irqsave(&sparx5->ptp_clock_lock, flags); + + spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_SAVE) | +@@ -490,12 +497,12 @@ int sparx5_ptp_gettime64(struct ptp_cloc + PTP_PTP_PIN_CFG_PTP_PIN_ACTION | + PTP_PTP_PIN_CFG_PTP_PIN_DOM | + PTP_PTP_PIN_CFG_PTP_PIN_SYNC, +- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); ++ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); + +- s = spx5_rd(sparx5, PTP_PTP_TOD_SEC_MSB(TOD_ACC_PIN)); ++ s = spx5_rd(sparx5, PTP_PTP_TOD_SEC_MSB(consts->tod_pin)); + s <<= 32; +- s |= spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(TOD_ACC_PIN)); +- ns = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); ++ s |= spx5_rd(sparx5, PTP_PTP_TOD_SEC_LSB(consts->tod_pin)); ++ ns = spx5_rd(sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); + ns &= PTP_PTP_TOD_NSEC_PTP_TOD_NSEC; + + spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); +@@ -515,6 +522,9 @@ static int sparx5_ptp_adjtime(struct ptp + { + struct sparx5_phc *phc = container_of(ptp, struct sparx5_phc, info); + struct sparx5 *sparx5 = phc->sparx5; ++ const struct sparx5_consts *consts; ++ ++ consts = sparx5->data->consts; + + if (delta > -(NSEC_PER_SEC / 2) && delta < (NSEC_PER_SEC / 2)) { + unsigned long flags; +@@ -528,10 +538,10 @@ static int sparx5_ptp_adjtime(struct ptp + PTP_PTP_PIN_CFG_PTP_PIN_ACTION | + PTP_PTP_PIN_CFG_PTP_PIN_DOM | + PTP_PTP_PIN_CFG_PTP_PIN_SYNC, +- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); ++ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); + + spx5_wr(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(delta), +- sparx5, PTP_PTP_TOD_NSEC(TOD_ACC_PIN)); ++ sparx5, PTP_PTP_TOD_NSEC(consts->tod_pin)); + + /* Adjust time with the value of PTP_TOD_NSEC */ + spx5_rmw(PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(PTP_PIN_ACTION_DELTA) | +@@ -540,7 +550,7 @@ static int sparx5_ptp_adjtime(struct ptp + PTP_PTP_PIN_CFG_PTP_PIN_ACTION | + PTP_PTP_PIN_CFG_PTP_PIN_DOM | + PTP_PTP_PIN_CFG_PTP_PIN_SYNC, +- sparx5, PTP_PTP_PIN_CFG(TOD_ACC_PIN)); ++ sparx5, PTP_PTP_PIN_CFG(consts->tod_pin)); + + spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); + } else { +@@ -630,7 +640,7 @@ int sparx5_ptp_init(struct sparx5 *sparx + /* Enable master counters */ + spx5_wr(PTP_PTP_DOM_CFG_PTP_ENA_SET(0x7), sparx5, PTP_PTP_DOM_CFG); + +- for (i = 0; i < SPX5_PORTS; i++) { ++ for (i = 0; i < sparx5->data->consts->n_ports; i++) { + port = sparx5->ports[i]; + if (!port) + continue; +@@ -646,7 +656,7 @@ void sparx5_ptp_deinit(struct sparx5 *sp + struct sparx5_port *port; + int i; + +- for (i = 0; i < SPX5_PORTS; i++) { ++ for (i = 0; i < sparx5->data->consts->n_ports; i++) { + port = sparx5->ports[i]; + if (!port) + continue; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c +@@ -184,7 +184,7 @@ int sparx5_sdlb_group_get_by_rate(struct + + rate_bps = rate * 1000; + +- for (i = SPX5_SDLB_GROUP_CNT - 1; i >= 0; i--) { ++ for (i = sparx5->data->consts->n_lb_groups - 1; i >= 0; i--) { + group = &sdlb_groups[i]; + + count = sparx5_sdlb_group_get_count(sparx5, i); +@@ -208,7 +208,7 @@ int sparx5_sdlb_group_get_by_index(struc + u32 itr, next; + int i; + +- for (i = 0; i < SPX5_SDLB_GROUP_CNT; i++) { ++ for (i = 0; i < sparx5->data->consts->n_lb_groups; i++) { + if (sparx5_sdlb_group_is_empty(sparx5, i)) + continue; + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c +@@ -547,7 +547,7 @@ static int sparx5_handle_port_mdb_add(st + + /* Add any mrouter ports to the new entry */ + if (is_new && ether_addr_is_ip_mcast(v->addr)) +- for (i = 0; i < SPX5_PORTS; i++) ++ for (i = 0; i < spx5->data->consts->n_ports; i++) + if (spx5->ports[i] && spx5->ports[i]->is_mrouter) + sparx5_pgid_update_mask(spx5->ports[i], + entry->pgid_idx, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c +@@ -785,7 +785,9 @@ static int sparx5_tc_flower_psfp_setup(s + * allocate a stream gate that is always open. + */ + if (sg_idx < 0) { +- sg_idx = sparx5_pool_idx_to_id(SPX5_PSFP_SG_OPEN); ++ /* Always-open stream gate is always the last */ ++ sg_idx = sparx5_pool_idx_to_id(sparx5->data->consts->n_gates - ++ 1); + sg->ipv = 0; /* Disabled */ + sg->cycletime = SPX5_PSFP_SG_CYCLE_TIME_DEFAULT; + sg->num_entries = 1; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c +@@ -169,7 +169,7 @@ void sparx5_update_fwd(struct sparx5 *sp + } + + /* Update SRC masks */ +- for (port = 0; port < SPX5_PORTS; port++) { ++ for (port = 0; port < sparx5->data->consts->n_ports; port++) { + if (test_bit(port, sparx5->bridge_fwd_mask)) { + /* Allow to send to all bridged but self */ + bitmap_copy(workmask, sparx5->bridge_fwd_mask, SPX5_PORTS); diff --git a/target/linux/microchipsw/patches-6.12/0030-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-do-not.patch b/target/linux/microchipsw/patches-6.12/0030-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-do-not.patch new file mode 100644 index 0000000000..f311745f39 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0030-v6.13-net-sparx5-use-SPX5_CONST-for-constants-which-do-not.patch @@ -0,0 +1,60 @@ +From efdc2c3094cc2e8aca09c3a16f7a0f3a10d9a097 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:33 +0200 +Subject: [PATCH 35/82] net: sparx5: use SPX5_CONST for constants which do not + have a symbol + +Now that we have indentified all the chip constants, update the use of +them where a symbol is not defined for the constant. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -522,7 +522,7 @@ static int sparx5_init_coreclock(struct + sparx5, + LRN_AUTOAGE_CFG_1); + +- for (idx = 0; idx < 3; idx++) ++ for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++) + spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100), + GCB_SIO_CLOCK_SYS_CLK_PERIOD, + sparx5, +@@ -550,16 +550,21 @@ static u32 qlim_wm(struct sparx5 *sparx5 + + static int sparx5_qlim_set(struct sparx5 *sparx5) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + u32 res, dp, prio; + + for (res = 0; res < 2; res++) { + for (prio = 0; prio < 8; prio++) + spx5_wr(0xFFF, sparx5, +- QRES_RES_CFG(prio + 630 + res * 1024)); ++ QRES_RES_CFG(prio + ++ consts->qres_max_prio_idx + ++ res * 1024)); + + for (dp = 0; dp < 4; dp++) + spx5_wr(0xFFF, sparx5, +- QRES_RES_CFG(dp + 638 + res * 1024)); ++ QRES_RES_CFG(dp + ++ consts->qres_max_colour_idx + ++ res * 1024)); + } + + /* Set 80,90,95,100% of memory size for top watermarks */ +@@ -605,7 +610,7 @@ static int sparx5_start(struct sparx5 *s + int err; + + /* Setup own UPSIDs */ +- for (idx = 0; idx < 3; idx++) { ++ for (idx = 0; idx < consts->n_own_upsids; idx++) { + spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); + spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); + spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); diff --git a/target/linux/microchipsw/patches-6.12/0031-v6.13-net-sparx5-add-ops-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0031-v6.13-net-sparx5-add-ops-to-match-data.patch new file mode 100644 index 0000000000..0f213c8367 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0031-v6.13-net-sparx5-add-ops-to-match-data.patch @@ -0,0 +1,227 @@ +From 9a6d927f8d9386fcabe4b93aa1bf16a0796e69fb Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:34 +0200 +Subject: [PATCH 36/82] net: sparx5: add ops to match data + +Add new struct sparx5_ops, containing functions that needs to be +different as the implementation differs on Sparx5 and lan969x. Initially +we add functions for checking the port type (2g5, 5g, 10g or 25g) based +on the port number. Update the code to use the ops instead of the +platform specific functions. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../ethernet/microchip/sparx5/sparx5_main.c | 8 +++++ + .../ethernet/microchip/sparx5/sparx5_main.h | 8 +++++ + .../ethernet/microchip/sparx5/sparx5_port.c | 34 +++++++++++-------- + .../ethernet/microchip/sparx5/sparx5_port.h | 12 ++++--- + 4 files changed, 44 insertions(+), 18 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -982,12 +982,20 @@ static const struct sparx5_consts sparx5 + .tod_pin = 4, + }; + ++static const struct sparx5_ops sparx5_ops = { ++ .is_port_2g5 = &sparx5_port_is_2g5, ++ .is_port_5g = &sparx5_port_is_5g, ++ .is_port_10g = &sparx5_port_is_10g, ++ .is_port_25g = &sparx5_port_is_25g, ++}; ++ + static const struct sparx5_match_data sparx5_desc = { + .iomap = sparx5_main_iomap, + .iomap_size = ARRAY_SIZE(sparx5_main_iomap), + .ioranges = 3, + .regs = &sparx5_regs, + .consts = &sparx5_consts, ++ .ops = &sparx5_ops, + }; + + static const struct of_device_id mchp_sparx5_match[] = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -258,6 +258,13 @@ struct sparx5_consts { + u32 tod_pin; /* PTP TOD pin */ + }; + ++struct sparx5_ops { ++ bool (*is_port_2g5)(int portno); ++ bool (*is_port_5g)(int portno); ++ bool (*is_port_10g)(int portno); ++ bool (*is_port_25g)(int portno); ++}; ++ + struct sparx5_main_io_resource { + enum sparx5_target id; + phys_addr_t offset; +@@ -267,6 +274,7 @@ struct sparx5_main_io_resource { + struct sparx5_match_data { + const struct sparx5_regs *regs; + const struct sparx5_consts *consts; ++ const struct sparx5_ops *ops; + const struct sparx5_main_io_resource *iomap; + int ioranges; + int iomap_size; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -213,11 +213,13 @@ static int sparx5_port_verify_speed(stru + struct sparx5_port *port, + struct sparx5_port_config *conf) + { +- if ((sparx5_port_is_2g5(port->portno) && ++ const struct sparx5_ops *ops = sparx5->data->ops; ++ ++ if ((ops->is_port_2g5(port->portno) && + conf->speed > SPEED_2500) || +- (sparx5_port_is_5g(port->portno) && ++ (ops->is_port_5g(port->portno) && + conf->speed > SPEED_5000) || +- (sparx5_port_is_10g(port->portno) && ++ (ops->is_port_10g(port->portno) && + conf->speed > SPEED_10000)) + return sparx5_port_error(port, conf, SPX5_PERR_SPEED); + +@@ -226,14 +228,14 @@ static int sparx5_port_verify_speed(stru + return -EINVAL; + case PHY_INTERFACE_MODE_1000BASEX: + if (conf->speed != SPEED_1000 || +- sparx5_port_is_2g5(port->portno)) ++ ops->is_port_2g5(port->portno)) + return sparx5_port_error(port, conf, SPX5_PERR_SPEED); +- if (sparx5_port_is_2g5(port->portno)) ++ if (ops->is_port_2g5(port->portno)) + return sparx5_port_error(port, conf, SPX5_PERR_IFTYPE); + break; + case PHY_INTERFACE_MODE_2500BASEX: + if (conf->speed != SPEED_2500 || +- sparx5_port_is_2g5(port->portno)) ++ ops->is_port_2g5(port->portno)) + return sparx5_port_error(port, conf, SPX5_PERR_SPEED); + break; + case PHY_INTERFACE_MODE_QSGMII: +@@ -320,6 +322,7 @@ static int sparx5_port_disable(struct sp + u32 dev = high_spd_dev ? + sparx5_to_high_dev(sparx5, port->portno) : TARGET_DEV2G5; + void __iomem *devinst = spx5_inst_get(sparx5, dev, tinst); ++ const struct sparx5_ops *ops = sparx5->data->ops; + u32 spd = port->conf.speed; + u32 spd_prm; + int err; +@@ -436,7 +439,7 @@ static int sparx5_port_disable(struct sp + pcsinst, + PCS10G_BR_PCS_CFG(0)); + +- if (sparx5_port_is_25g(port->portno)) ++ if (ops->is_port_25g(port->portno)) + /* Disable 25G PCS */ + spx5_rmw(DEV25G_PCS25G_CFG_PCS25G_ENA_SET(0), + DEV25G_PCS25G_CFG_PCS25G_ENA, +@@ -561,6 +564,7 @@ static int sparx5_port_max_tags_set(stru + u32 dev = sparx5_to_high_dev(sparx5, port->portno); + u32 tinst = sparx5_port_dev_index(sparx5, port->portno); + void __iomem *inst = spx5_inst_get(sparx5, dev, tinst); ++ const struct sparx5_ops *ops = sparx5->data->ops; + u32 etype; + + etype = (vlan_type == SPX5_VLAN_PORT_TYPE_S_CUSTOM ? +@@ -575,7 +579,7 @@ static int sparx5_port_max_tags_set(stru + sparx5, + DEV2G5_MAC_TAGS_CFG(port->portno)); + +- if (sparx5_port_is_2g5(port->portno)) ++ if (ops->is_port_2g5(port->portno)) + return 0; + + spx5_inst_rmw(DEV10G_MAC_TAGS_CFG_TAG_ID_SET(etype) | +@@ -844,18 +848,19 @@ static int sparx5_port_pcs_high_set(stru + static void sparx5_dev_switch(struct sparx5 *sparx5, int port, bool hsd) + { + int bt_indx = BIT(sparx5_port_dev_index(sparx5, port)); ++ const struct sparx5_ops *ops = sparx5->data->ops; + +- if (sparx5_port_is_5g(port)) { ++ if (ops->is_port_5g(port)) { + spx5_rmw(hsd ? 0 : bt_indx, + bt_indx, + sparx5, + PORT_CONF_DEV5G_MODES); +- } else if (sparx5_port_is_10g(port)) { ++ } else if (ops->is_port_10g(port)) { + spx5_rmw(hsd ? 0 : bt_indx, + bt_indx, + sparx5, + PORT_CONF_DEV10G_MODES); +- } else if (sparx5_port_is_25g(port)) { ++ } else if (ops->is_port_25g(port)) { + spx5_rmw(hsd ? 0 : bt_indx, + bt_indx, + sparx5, +@@ -1016,6 +1021,7 @@ int sparx5_port_init(struct sparx5 *spar + { + u32 pause_start = sparx5_wm_enc(6 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); + u32 atop = sparx5_wm_enc(20 * (ETH_MAXLEN / SPX5_BUFFER_CELL_SZ)); ++ const struct sparx5_ops *ops = sparx5->data->ops; + u32 devhigh = sparx5_to_high_dev(sparx5, port->portno); + u32 pix = sparx5_port_dev_index(sparx5, port->portno); + u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); +@@ -1082,7 +1088,7 @@ int sparx5_port_init(struct sparx5 *spar + if (err) + return err; + +- if (!sparx5_port_is_2g5(port->portno)) ++ if (!ops->is_port_2g5(port->portno)) + /* Enable shadow device */ + spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1), + DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, +@@ -1105,7 +1111,7 @@ int sparx5_port_init(struct sparx5 *spar + sparx5, + DEV2G5_MAC_IFG_CFG(port->portno)); + +- if (sparx5_port_is_2g5(port->portno)) ++ if (ops->is_port_2g5(port->portno)) + return 0; /* Low speed device only - return */ + + /* Now setup the high speed device */ +@@ -1128,7 +1134,7 @@ int sparx5_port_init(struct sparx5 *spar + pcsinst, + PCS10G_BR_PCS_SD_CFG(0)); + +- if (sparx5_port_is_25g(port->portno)) { ++ if (ops->is_port_25g(port->portno)) { + /* Handle Signal Detect in 25G PCS */ + spx5_wr(DEV25G_PCS25G_SD_CFG_SD_POL_SET(sd_pol) | + DEV25G_PCS25G_SD_CFG_SD_SEL_SET(sd_sel) | +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h +@@ -42,18 +42,22 @@ static inline bool sparx5_port_is_25g(in + + static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) + { +- if (sparx5_port_is_5g(port)) ++ const struct sparx5_ops *ops = sparx5->data->ops; ++ ++ if (ops->is_port_5g(port)) + return TARGET_DEV5G; +- if (sparx5_port_is_10g(port)) ++ if (ops->is_port_10g(port)) + return TARGET_DEV10G; + return TARGET_DEV25G; + } + + static inline u32 sparx5_to_pcs_dev(struct sparx5 *sparx5, int port) + { +- if (sparx5_port_is_5g(port)) ++ const struct sparx5_ops *ops = sparx5->data->ops; ++ ++ if (ops->is_port_5g(port)) + return TARGET_PCS5G_BR; +- if (sparx5_port_is_10g(port)) ++ if (ops->is_port_10g(port)) + return TARGET_PCS10G_BR; + return TARGET_PCS25G_BR; + } diff --git a/target/linux/microchipsw/patches-6.12/0032-v6.13-net-sparx5-ops-out-chip-port-to-device-index-bit-fun.patch b/target/linux/microchipsw/patches-6.12/0032-v6.13-net-sparx5-ops-out-chip-port-to-device-index-bit-fun.patch new file mode 100644 index 0000000000..5a201dedb2 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0032-v6.13-net-sparx5-ops-out-chip-port-to-device-index-bit-fun.patch @@ -0,0 +1,80 @@ +From cc1814ae3a2cd34a345c7d638f5da991d8d22d33 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:35 +0200 +Subject: [PATCH 37/82] net: sparx5: ops out chip port to device index/bit + functions + +The chip port device index and mode bit can be obtained using the port +number. However the mapping of port number to chip device index and +mode bit differs on Sparx5 and lan969x. Therefore ops out the function. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 2 ++ + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 2 ++ + drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 4 +++- + drivers/net/ethernet/microchip/sparx5/sparx5_port.h | 7 ++++++- + 4 files changed, 13 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -987,6 +987,8 @@ static const struct sparx5_ops sparx5_op + .is_port_5g = &sparx5_port_is_5g, + .is_port_10g = &sparx5_port_is_10g, + .is_port_25g = &sparx5_port_is_25g, ++ .get_port_dev_index = &sparx5_port_dev_mapping, ++ .get_port_dev_bit = &sparx5_port_dev_mapping, + }; + + static const struct sparx5_match_data sparx5_desc = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -263,6 +263,8 @@ struct sparx5_ops { + bool (*is_port_5g)(int portno); + bool (*is_port_10g)(int portno); + bool (*is_port_25g)(int portno); ++ u32 (*get_port_dev_index)(struct sparx5 *sparx5, int port); ++ u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); + }; + + struct sparx5_main_io_resource { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -847,8 +847,10 @@ static int sparx5_port_pcs_high_set(stru + /* Switch between 1G/2500 and 5G/10G/25G devices */ + static void sparx5_dev_switch(struct sparx5 *sparx5, int port, bool hsd) + { +- int bt_indx = BIT(sparx5_port_dev_index(sparx5, port)); + const struct sparx5_ops *ops = sparx5->data->ops; ++ int bt_indx; ++ ++ bt_indx = BIT(ops->get_port_dev_bit(sparx5, port)); + + if (ops->is_port_5g(port)) { + spx5_rmw(hsd ? 0 : bt_indx, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h +@@ -62,7 +62,7 @@ static inline u32 sparx5_to_pcs_dev(stru + return TARGET_PCS25G_BR; + } + +-static inline int sparx5_port_dev_index(struct sparx5 *sparx5, int port) ++static inline u32 sparx5_port_dev_mapping(struct sparx5 *sparx5, int port) + { + if (sparx5_port_is_2g5(port)) + return port; +@@ -74,6 +74,11 @@ static inline int sparx5_port_dev_index( + return (port - 56); + } + ++static inline u32 sparx5_port_dev_index(struct sparx5 *sparx5, int port) ++{ ++ return sparx5->data->ops->get_port_dev_index(sparx5, port); ++} ++ + int sparx5_port_init(struct sparx5 *sparx5, + struct sparx5_port *spx5_port, + struct sparx5_port_config *conf); diff --git a/target/linux/microchipsw/patches-6.12/0033-v6.13-net-sparx5-ops-out-functions-for-getting-certain-arr.patch b/target/linux/microchipsw/patches-6.12/0033-v6.13-net-sparx5-ops-out-functions-for-getting-certain-arr.patch new file mode 100644 index 0000000000..71fff9c8db --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0033-v6.13-net-sparx5-ops-out-functions-for-getting-certain-arr.patch @@ -0,0 +1,170 @@ +From 54a152e60ab7b7fb64211ee6a3defec095fb796e Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:36 +0200 +Subject: [PATCH 38/82] net: sparx5: ops out functions for getting certain + array values + +Add getters for getting values in arrays: sdlb_groups and +sparx5_hsch_max_group_rate and ops out the getters, as these arrays will +differ on lan969x. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 2 ++ + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 3 +++ + drivers/net/ethernet/microchip/sparx5/sparx5_police.c | 3 ++- + drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c | 3 ++- + drivers/net/ethernet/microchip/sparx5/sparx5_qos.c | 8 +++++++- + drivers/net/ethernet/microchip/sparx5/sparx5_qos.h | 2 ++ + drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c | 11 +++++++++-- + 7 files changed, 27 insertions(+), 5 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -989,6 +989,8 @@ static const struct sparx5_ops sparx5_op + .is_port_25g = &sparx5_port_is_25g, + .get_port_dev_index = &sparx5_port_dev_mapping, + .get_port_dev_bit = &sparx5_port_dev_mapping, ++ .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, ++ .get_sdlb_group = &sparx5_get_sdlb_group, + }; + + static const struct sparx5_match_data sparx5_desc = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -265,6 +265,8 @@ struct sparx5_ops { + bool (*is_port_25g)(int portno); + u32 (*get_port_dev_index)(struct sparx5 *sparx5, int port); + u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); ++ u32 (*get_hsch_max_group_rate)(int grp); ++ struct sparx5_sdlb_group *(*get_sdlb_group)(int idx); + }; + + struct sparx5_main_io_resource { +@@ -501,6 +503,7 @@ struct sparx5_sdlb_group { + }; + + extern struct sparx5_sdlb_group sdlb_groups[SPX5_SDLB_GROUP_CNT]; ++struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx); + int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, + u64 rate); + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_police.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_police.c +@@ -11,10 +11,11 @@ static int sparx5_policer_service_conf_s + struct sparx5_policer *pol) + { + u32 idx, pup_tokens, max_pup_tokens, burst, thres; ++ const struct sparx5_ops *ops = sparx5->data->ops; + struct sparx5_sdlb_group *g; + u64 rate; + +- g = &sdlb_groups[pol->group]; ++ g = ops->get_sdlb_group(pol->group); + idx = pol->idx; + + rate = pol->rate * 1000; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_psfp.c +@@ -319,11 +319,12 @@ int sparx5_psfp_fm_del(struct sparx5 *sp + + void sparx5_psfp_init(struct sparx5 *sparx5) + { ++ const struct sparx5_ops *ops = sparx5->data->ops; + const struct sparx5_sdlb_group *group; + int i; + + for (i = 0; i < sparx5->data->consts->n_lb_groups; i++) { +- group = &sdlb_groups[i]; ++ group = ops->get_sdlb_group(i); + sparx5_sdlb_group_init(sparx5, group->max_rate, + group->min_burst, group->frame_size, i); + } +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c +@@ -74,6 +74,11 @@ static const u32 spx5_hsch_max_group_rat + 26214200 /* 26.214 Gbps */ + }; + ++u32 sparx5_get_hsch_max_group_rate(int grp) ++{ ++ return spx5_hsch_max_group_rate[grp]; ++} ++ + static struct sparx5_layer layers[SPX5_HSCH_LAYER_CNT]; + + static u32 sparx5_lg_get_leak_time(struct sparx5 *sparx5, u32 layer, u32 group) +@@ -385,6 +390,7 @@ static int sparx5_dwrr_conf_set(struct s + + static int sparx5_leak_groups_init(struct sparx5 *sparx5) + { ++ const struct sparx5_ops *ops = sparx5->data->ops; + struct sparx5_layer *layer; + u32 sys_clk_per_100ps; + struct sparx5_lg *lg; +@@ -397,7 +403,7 @@ static int sparx5_leak_groups_init(struc + layer = &layers[i]; + for (ii = 0; ii < SPX5_HSCH_LEAK_GRP_CNT; ii++) { + lg = &layer->leak_groups[ii]; +- lg->max_rate = spx5_hsch_max_group_rate[ii]; ++ lg->max_rate = ops->get_hsch_max_group_rate(i); + + /* Calculate the leak time in us, to serve a maximum + * rate of 'max_rate' for this group +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.h +@@ -79,4 +79,6 @@ int sparx5_tc_ets_add(struct sparx5_port + + int sparx5_tc_ets_del(struct sparx5_port *port); + ++u32 sparx5_get_hsch_max_group_rate(int grp); ++ + #endif /* __SPARX5_QOS_H__ */ +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c +@@ -20,6 +20,11 @@ struct sparx5_sdlb_group sdlb_groups[SPX + { 5000000ULL, 8192 / 8, 64 } /* 5 M */ + }; + ++struct sparx5_sdlb_group *sparx5_get_sdlb_group(int idx) ++{ ++ return &sdlb_groups[idx]; ++} ++ + int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) + { + u32 clk_per_100ps; +@@ -178,6 +183,7 @@ static int sparx5_sdlb_group_get_count(s + + int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst) + { ++ const struct sparx5_ops *ops = sparx5->data->ops; + const struct sparx5_sdlb_group *group; + u64 rate_bps; + int i, count; +@@ -185,7 +191,7 @@ int sparx5_sdlb_group_get_by_rate(struct + rate_bps = rate * 1000; + + for (i = sparx5->data->consts->n_lb_groups - 1; i >= 0; i--) { +- group = &sdlb_groups[i]; ++ group = ops->get_sdlb_group(i); + + count = sparx5_sdlb_group_get_count(sparx5, i); + +@@ -303,11 +309,12 @@ int sparx5_sdlb_group_del(struct sparx5 + void sparx5_sdlb_group_init(struct sparx5 *sparx5, u64 max_rate, u32 min_burst, + u32 frame_size, u32 idx) + { ++ const struct sparx5_ops *ops = sparx5->data->ops; + u32 thres_shift, mask = 0x01, power = 0; + struct sparx5_sdlb_group *group; + u64 max_token; + +- group = &sdlb_groups[idx]; ++ group = ops->get_sdlb_group(idx); + + /* Number of positions to right-shift LB's threshold value. */ + while ((min_burst & mask) == 0) { diff --git a/target/linux/microchipsw/patches-6.12/0034-v6.13-net-sparx5-ops-out-function-for-setting-the-port-mux.patch b/target/linux/microchipsw/patches-6.12/0034-v6.13-net-sparx5-ops-out-function-for-setting-the-port-mux.patch new file mode 100644 index 0000000000..44443b8e2d --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0034-v6.13-net-sparx5-ops-out-function-for-setting-the-port-mux.patch @@ -0,0 +1,74 @@ +From def4582837fa546a00860649a253c47107123060 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:37 +0200 +Subject: [PATCH 39/82] net: sparx5: ops out function for setting the port mux + +Port muxing is configured based on the supported port modes. As these +modes can differ on Sparx5 and lan969x we ops out the port muxing +function. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 1 + + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 6 ++++++ + drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 7 +++---- + 3 files changed, 10 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -991,6 +991,7 @@ static const struct sparx5_ops sparx5_op + .get_port_dev_bit = &sparx5_port_dev_mapping, + .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, + .get_sdlb_group = &sparx5_get_sdlb_group, ++ .set_port_mux = &sparx5_port_mux_set, + }; + + static const struct sparx5_match_data sparx5_desc = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -267,6 +267,8 @@ struct sparx5_ops { + u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); + u32 (*get_hsch_max_group_rate)(int grp); + struct sparx5_sdlb_group *(*get_sdlb_group)(int idx); ++ int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port, ++ struct sparx5_port_config *conf); + }; + + struct sparx5_main_io_resource { +@@ -485,6 +487,10 @@ int sparx5_pool_get(struct sparx5_pool_e + int sparx5_pool_get_with_idx(struct sparx5_pool_entry *pool, int size, u32 idx, + u32 *id); + ++/* sparx5_port.c */ ++int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, ++ struct sparx5_port_config *conf); ++ + /* sparx5_sdlb.c */ + #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF + #define SPX5_SDLB_PUP_TOKEN_MAX (SPX5_SDLB_PUP_TOKEN_DISABLE - 1) +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -516,9 +516,8 @@ static int sparx5_port_fifo_sz(struct sp + /* Configure port muxing: + * QSGMII: 4x2G5 devices + */ +-static int sparx5_port_mux_set(struct sparx5 *sparx5, +- struct sparx5_port *port, +- struct sparx5_port_config *conf) ++int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, ++ struct sparx5_port_config *conf) + { + u32 portno = port->portno; + u32 inst; +@@ -1039,7 +1038,7 @@ int sparx5_port_init(struct sparx5 *spar + pcsinst = spx5_inst_get(sparx5, pcs, pix); + + /* Set the mux port mode */ +- err = sparx5_port_mux_set(sparx5, port, conf); ++ err = ops->set_port_mux(sparx5, port, conf); + if (err) + return err; + diff --git a/target/linux/microchipsw/patches-6.12/0035-v6.13-net-sparx5-ops-out-PTP-IRQ-handler.patch b/target/linux/microchipsw/patches-6.12/0035-v6.13-net-sparx5-ops-out-PTP-IRQ-handler.patch new file mode 100644 index 0000000000..455c332bc2 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0035-v6.13-net-sparx5-ops-out-PTP-IRQ-handler.patch @@ -0,0 +1,56 @@ +From 6802dd4ba13b3487fb4e57dce38c53edf2ba63a2 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:38 +0200 +Subject: [PATCH 40/82] net: sparx5: ops out PTP IRQ handler + +The PTP registers are located in two different register targets on +Sparx5 and lan969x. We can't handle this with the register macros, so +ops out the handler. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 4 +++- + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 2 ++ + 2 files changed, 5 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -605,6 +605,7 @@ static int sparx5_start(struct sparx5 *s + { + u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; + const struct sparx5_consts *consts = sparx5->data->consts; ++ const struct sparx5_ops *ops = sparx5->data->ops; + char queue_name[32]; + u32 idx; + int err; +@@ -728,7 +729,7 @@ static int sparx5_start(struct sparx5 *s + + if (sparx5->ptp_irq >= 0) { + err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, +- NULL, sparx5_ptp_irq_handler, ++ NULL, ops->ptp_irq_handler, + IRQF_ONESHOT, "sparx5-ptp", + sparx5); + if (err) +@@ -992,6 +993,7 @@ static const struct sparx5_ops sparx5_op + .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, + .get_sdlb_group = &sparx5_get_sdlb_group, + .set_port_mux = &sparx5_port_mux_set, ++ .ptp_irq_handler = &sparx5_ptp_irq_handler, + }; + + static const struct sparx5_match_data sparx5_desc = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -269,6 +269,8 @@ struct sparx5_ops { + struct sparx5_sdlb_group *(*get_sdlb_group)(int idx); + int (*set_port_mux)(struct sparx5 *sparx5, struct sparx5_port *port, + struct sparx5_port_config *conf); ++ ++ irqreturn_t (*ptp_irq_handler)(int irq, void *args); + }; + + struct sparx5_main_io_resource { diff --git a/target/linux/microchipsw/patches-6.12/0036-v6.13-net-sparx5-ops-out-function-for-DSM-calendar-calcula.patch b/target/linux/microchipsw/patches-6.12/0036-v6.13-net-sparx5-ops-out-function-for-DSM-calendar-calcula.patch new file mode 100644 index 0000000000..44523d9011 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0036-v6.13-net-sparx5-ops-out-function-for-DSM-calendar-calcula.patch @@ -0,0 +1,137 @@ +From e8df6924d6e793aca572b8fa766779354d20adae Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:39 +0200 +Subject: [PATCH 41/82] net: sparx5: ops out function for DSM calendar + calculation + +The DSM (Disassembler) calendar grants each port access to internal +busses. The configuration of the calendar is done differently on Sparx5 +and lan969x. Therefore ops out the function that calculates the +calendar. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../microchip/sparx5/sparx5_calendar.c | 22 ++++--------------- + .../ethernet/microchip/sparx5/sparx5_main.c | 1 + + .../ethernet/microchip/sparx5/sparx5_main.h | 21 ++++++++++++++++++ + 3 files changed, 26 insertions(+), 18 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +@@ -15,9 +15,7 @@ + #define SPX5_CALBITS_PER_PORT 3 /* Bit per port in calendar register */ + + /* DSM calendar information */ +-#define SPX5_DSM_CAL_LEN 64 + #define SPX5_DSM_CAL_EMPTY 0xFFFF +-#define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 + #define SPX5_DSM_CAL_TAXIS 8 + #define SPX5_DSM_CAL_BW_LOSS 553 + +@@ -37,19 +35,6 @@ static u32 sparx5_taxi_ports[SPX5_DSM_CA + {64, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99, 99}, + }; + +-struct sparx5_calendar_data { +- u32 schedule[SPX5_DSM_CAL_LEN]; +- u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; +- u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; +- u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; +- u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; +- u32 new_slots[SPX5_DSM_CAL_LEN]; +- u32 temp_sched[SPX5_DSM_CAL_LEN]; +- u32 indices[SPX5_DSM_CAL_LEN]; +- u32 short_list[SPX5_DSM_CAL_LEN]; +- u32 long_list[SPX5_DSM_CAL_LEN]; +-}; +- + static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) + { + switch (sparx5->target_ct) { +@@ -279,8 +264,8 @@ static u32 sparx5_dsm_cp_cal(u32 *sched) + return SPX5_DSM_CAL_EMPTY; + } + +-static int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, +- struct sparx5_calendar_data *data) ++int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, ++ struct sparx5_calendar_data *data) + { + bool slow_mode; + u32 gcd, idx, sum, min, factor; +@@ -566,6 +551,7 @@ update_err: + /* Configure the DSM calendar based on port configuration */ + int sparx5_config_dsm_calendar(struct sparx5 *sparx5) + { ++ const struct sparx5_ops *ops = sparx5->data->ops; + int taxi; + struct sparx5_calendar_data *data; + int err = 0; +@@ -575,7 +561,7 @@ int sparx5_config_dsm_calendar(struct sp + return -ENOMEM; + + for (taxi = 0; taxi < sparx5->data->consts->n_dsm_cal_taxis; ++taxi) { +- err = sparx5_dsm_calendar_calc(sparx5, taxi, data); ++ err = ops->dsm_calendar_calc(sparx5, taxi, data); + if (err) { + dev_err(sparx5->dev, "DSM calendar calculation failed\n"); + goto cal_out; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -994,6 +994,7 @@ static const struct sparx5_ops sparx5_op + .get_sdlb_group = &sparx5_get_sdlb_group, + .set_port_mux = &sparx5_port_mux_set, + .ptp_irq_handler = &sparx5_ptp_irq_handler, ++ .dsm_calendar_calc = &sparx5_dsm_calendar_calc, + }; + + static const struct sparx5_match_data sparx5_desc = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -101,8 +101,24 @@ enum sparx5_vlan_port_type { + #define IFH_PDU_TYPE_IPV4_UDP_PTP 0x6 + #define IFH_PDU_TYPE_IPV6_UDP_PTP 0x7 + ++#define SPX5_DSM_CAL_LEN 64 ++#define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 ++ + struct sparx5; + ++struct sparx5_calendar_data { ++ u32 schedule[SPX5_DSM_CAL_LEN]; ++ u32 avg_dist[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; ++ u32 taxi_ports[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; ++ u32 taxi_speeds[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; ++ u32 dev_slots[SPX5_DSM_CAL_MAX_DEVS_PER_TAXI]; ++ u32 new_slots[SPX5_DSM_CAL_LEN]; ++ u32 temp_sched[SPX5_DSM_CAL_LEN]; ++ u32 indices[SPX5_DSM_CAL_LEN]; ++ u32 short_list[SPX5_DSM_CAL_LEN]; ++ u32 long_list[SPX5_DSM_CAL_LEN]; ++}; ++ + /* Frame DMA receive state: + * For each DB, there is a SKB, and the skb data pointer is mapped in + * the DB. Once a frame is received the skb is given to the upper layers +@@ -271,6 +287,8 @@ struct sparx5_ops { + struct sparx5_port_config *conf); + + irqreturn_t (*ptp_irq_handler)(int irq, void *args); ++ int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi, ++ struct sparx5_calendar_data *data); + }; + + struct sparx5_main_io_resource { +@@ -418,6 +436,9 @@ void sparx5_vlan_port_apply(struct sparx + /* sparx5_calendar.c */ + int sparx5_config_auto_calendar(struct sparx5 *sparx5); + int sparx5_config_dsm_calendar(struct sparx5 *sparx5); ++int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, ++ struct sparx5_calendar_data *data); ++ + + /* sparx5_ethtool.c */ + void sparx5_get_stats64(struct net_device *ndev, struct rtnl_link_stats64 *stats); diff --git a/target/linux/microchipsw/patches-6.12/0037-v6.13-net-sparx5-add-is_sparx5-macro-and-use-it-throughout.patch b/target/linux/microchipsw/patches-6.12/0037-v6.13-net-sparx5-add-is_sparx5-macro-and-use-it-throughout.patch new file mode 100644 index 0000000000..ab475ed860 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0037-v6.13-net-sparx5-add-is_sparx5-macro-and-use-it-throughout.patch @@ -0,0 +1,267 @@ +From 234d82beadb5fdf26dd9f469764e048f1ca4dd60 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:40 +0200 +Subject: [PATCH 42/82] net: sparx5: add is_sparx5 macro and use it throughout + +We dont want to ops out each time a function needs to do some platform +specifics. In particular we have a few places, where it would be +convenient to just branch out on the platform type. Add the function +is_sparx5() and, initially, use it for: + + - register writes that should only be done on Sparx5 (QSYS_CAL_CTRL, + CLKGEN_LCPLL1_CORE_CLK). + + - function calls that should only be done on Sparx5 + (ethtool_op_get_ts_info()) + + - register writes that are chip-exclusive (MASK_CFG1/2, PGID_CFG1/2, + these are replicated for n_ports >32 on Sparx5). + +The is_sparx5() function simply checks the target chip type, to +determine if this is a Sparx5 SKU or not. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jacob Keller +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../microchip/sparx5/sparx5_calendar.c | 7 +- + .../microchip/sparx5/sparx5_ethtool.c | 2 +- + .../ethernet/microchip/sparx5/sparx5_main.c | 88 ++++++++++++------- + .../ethernet/microchip/sparx5/sparx5_main.h | 3 + + .../ethernet/microchip/sparx5/sparx5_vlan.c | 42 ++++++--- + 5 files changed, 90 insertions(+), 52 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +@@ -194,9 +194,10 @@ int sparx5_config_auto_calendar(struct s + } + + /* Halt the calendar while changing it */ +- spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10), +- QSYS_CAL_CTRL_CAL_MODE, +- sparx5, QSYS_CAL_CTRL); ++ if (is_sparx5(sparx5)) ++ spx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10), ++ QSYS_CAL_CTRL_CAL_MODE, ++ sparx5, QSYS_CAL_CTRL); + + /* Assign port bandwidth to auto calendar */ + for (idx = 0; idx < consts->n_auto_cals; idx++) +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c +@@ -1189,7 +1189,7 @@ static int sparx5_get_ts_info(struct net + struct sparx5 *sparx5 = port->sparx5; + struct sparx5_phc *phc; + +- if (!sparx5->ptp) ++ if (!sparx5->ptp && is_sparx5(sparx5)) + return ethtool_op_get_ts_info(dev, info); + + phc = &sparx5->phc[SPARX5_PHC_PORT]; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -208,6 +208,25 @@ static const struct sparx5_main_io_resou + { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */ + }; + ++bool is_sparx5(struct sparx5 *sparx5) ++{ ++ switch (sparx5->target_ct) { ++ case SPX5_TARGET_CT_7546: ++ case SPX5_TARGET_CT_7549: ++ case SPX5_TARGET_CT_7552: ++ case SPX5_TARGET_CT_7556: ++ case SPX5_TARGET_CT_7558: ++ case SPX5_TARGET_CT_7546TSN: ++ case SPX5_TARGET_CT_7549TSN: ++ case SPX5_TARGET_CT_7552TSN: ++ case SPX5_TARGET_CT_7556TSN: ++ case SPX5_TARGET_CT_7558TSN: ++ return true; ++ default: ++ return false; ++ } ++} ++ + static int sparx5_create_targets(struct sparx5 *sparx5) + { + const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; +@@ -462,44 +481,45 @@ static int sparx5_init_coreclock(struct + return -ENODEV; + } + +- switch (freq) { +- case SPX5_CORE_CLOCK_250MHZ: +- clk_div = 10; +- pol_upd_int = 312; +- break; +- case SPX5_CORE_CLOCK_500MHZ: +- clk_div = 5; +- pol_upd_int = 624; +- break; +- case SPX5_CORE_CLOCK_625MHZ: +- clk_div = 4; +- pol_upd_int = 780; +- break; +- default: +- dev_err(sparx5->dev, "%d coreclock not supported on (%#04x)\n", +- sparx5->coreclock, sparx5->target_ct); +- return -EINVAL; ++ if (is_sparx5(sparx5)) { ++ switch (freq) { ++ case SPX5_CORE_CLOCK_250MHZ: ++ clk_div = 10; ++ pol_upd_int = 312; ++ break; ++ case SPX5_CORE_CLOCK_500MHZ: ++ clk_div = 5; ++ pol_upd_int = 624; ++ break; ++ case SPX5_CORE_CLOCK_625MHZ: ++ clk_div = 4; ++ pol_upd_int = 780; ++ break; ++ default: ++ dev_err(sparx5->dev, ++ "%d coreclock not supported on (%#04x)\n", ++ sparx5->coreclock, sparx5->target_ct); ++ return -EINVAL; ++ } ++ ++ /* Configure the LCPLL */ ++ spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | ++ CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, ++ sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); + } + + /* Update state with chosen frequency */ + sparx5->coreclock = freq; +- +- /* Configure the LCPLL */ +- spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1), +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | +- CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, +- sparx5, +- CLKGEN_LCPLL1_CORE_CLK_CFG); +- + clk_period = sparx5_clk_period(freq); + + spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -376,6 +376,9 @@ struct sparx5 { + const struct sparx5_match_data *data; + }; + ++/* sparx5_main.c */ ++bool is_sparx5(struct sparx5 *sparx5); ++ + /* sparx5_switchdev.c */ + int sparx5_register_notifier_blocks(struct sparx5 *sparx5); + void sparx5_unregister_notifier_blocks(struct sparx5 *sparx5); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c +@@ -16,8 +16,10 @@ static int sparx5_vlant_set_mask(struct + + /* Output mask to respective registers */ + spx5_wr(mask[0], sparx5, ANA_L3_VLAN_MASK_CFG(vid)); +- spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); +- spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); ++ if (is_sparx5(sparx5)) { ++ spx5_wr(mask[1], sparx5, ANA_L3_VLAN_MASK_CFG1(vid)); ++ spx5_wr(mask[2], sparx5, ANA_L3_VLAN_MASK_CFG2(vid)); ++ } + + return 0; + } +@@ -141,15 +143,19 @@ void sparx5_pgid_update_mask(struct spar + void sparx5_pgid_clear(struct sparx5 *spx5, int pgid) + { + spx5_wr(0, spx5, ANA_AC_PGID_CFG(pgid)); +- spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); +- spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); ++ if (is_sparx5(spx5)) { ++ spx5_wr(0, spx5, ANA_AC_PGID_CFG1(pgid)); ++ spx5_wr(0, spx5, ANA_AC_PGID_CFG2(pgid)); ++ } + } + + void sparx5_pgid_read_mask(struct sparx5 *spx5, int pgid, u32 portmask[3]) + { + portmask[0] = spx5_rd(spx5, ANA_AC_PGID_CFG(pgid)); +- portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid)); +- portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid)); ++ if (is_sparx5(spx5)) { ++ portmask[1] = spx5_rd(spx5, ANA_AC_PGID_CFG1(pgid)); ++ portmask[2] = spx5_rd(spx5, ANA_AC_PGID_CFG2(pgid)); ++ } + } + + void sparx5_update_fwd(struct sparx5 *sparx5) +@@ -164,8 +170,10 @@ void sparx5_update_fwd(struct sparx5 *sp + /* Update flood masks */ + for (port = PGID_UC_FLOOD; port <= PGID_BCAST; port++) { + spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); +- spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); +- spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); ++ if (is_sparx5(sparx5)) { ++ spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); ++ spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); ++ } + } + + /* Update SRC masks */ +@@ -176,12 +184,16 @@ void sparx5_update_fwd(struct sparx5 *sp + clear_bit(port, workmask); + bitmap_to_arr32(mask, workmask, SPX5_PORTS); + spx5_wr(mask[0], sparx5, ANA_AC_SRC_CFG(port)); +- spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port)); +- spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port)); ++ if (is_sparx5(sparx5)) { ++ spx5_wr(mask[1], sparx5, ANA_AC_SRC_CFG1(port)); ++ spx5_wr(mask[2], sparx5, ANA_AC_SRC_CFG2(port)); ++ } + } else { + spx5_wr(0, sparx5, ANA_AC_SRC_CFG(port)); +- spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port)); +- spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port)); ++ if (is_sparx5(sparx5)) { ++ spx5_wr(0, sparx5, ANA_AC_SRC_CFG1(port)); ++ spx5_wr(0, sparx5, ANA_AC_SRC_CFG2(port)); ++ } + } + } + +@@ -192,8 +204,10 @@ void sparx5_update_fwd(struct sparx5 *sp + + /* Apply learning mask */ + spx5_wr(mask[0], sparx5, ANA_L2_AUTO_LRN_CFG); +- spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1); +- spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2); ++ if (is_sparx5(sparx5)) { ++ spx5_wr(mask[1], sparx5, ANA_L2_AUTO_LRN_CFG1); ++ spx5_wr(mask[2], sparx5, ANA_L2_AUTO_LRN_CFG2); ++ } + } + + void sparx5_vlan_port_apply(struct sparx5 *sparx5, diff --git a/target/linux/microchipsw/patches-6.12/0038-v6.13-net-sparx5-redefine-internal-ports-and-PGID-s-as-off.patch b/target/linux/microchipsw/patches-6.12/0038-v6.13-net-sparx5-redefine-internal-ports-and-PGID-s-as-off.patch new file mode 100644 index 0000000000..3e0337237f --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0038-v6.13-net-sparx5-redefine-internal-ports-and-PGID-s-as-off.patch @@ -0,0 +1,351 @@ +From 976b85797451b92683f78af10334ceda13d5f1e0 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 4 Oct 2024 15:19:41 +0200 +Subject: [PATCH 43/82] net: sparx5: redefine internal ports and PGID's as + offsets + +Internal ports and PGID's are both defined relative to the number of +front ports on Sparx5. This will not work on lan969x. Instead make them +offsets to the number of front ports and add two helpers to retrieve +them. Use the helpers throughout. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../microchip/sparx5/sparx5_calendar.c | 14 +++++--- + .../ethernet/microchip/sparx5/sparx5_fdma.c | 4 ++- + .../microchip/sparx5/sparx5_mactable.c | 3 +- + .../ethernet/microchip/sparx5/sparx5_main.c | 14 ++++---- + .../ethernet/microchip/sparx5/sparx5_main.h | 34 +++++++++---------- + .../ethernet/microchip/sparx5/sparx5_netdev.c | 6 ++-- + .../ethernet/microchip/sparx5/sparx5_packet.c | 4 ++- + .../ethernet/microchip/sparx5/sparx5_pgid.c | 13 +++++-- + .../ethernet/microchip/sparx5/sparx5_port.c | 5 +++ + .../microchip/sparx5/sparx5_switchdev.c | 31 ++++++++++++----- + .../ethernet/microchip/sparx5/sparx5_vlan.c | 3 +- + 11 files changed, 86 insertions(+), 45 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +@@ -118,16 +118,22 @@ static enum sparx5_cal_bw sparx5_get_por + + if (portno >= sparx5->data->consts->n_ports) { + /* Internal ports */ +- if (portno == SPX5_PORT_CPU_0 || portno == SPX5_PORT_CPU_1) { ++ if (portno == ++ sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0) || ++ portno == ++ sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1)) { + /* Equals 1.25G */ + return SPX5_CAL_SPEED_2G5; +- } else if (portno == SPX5_PORT_VD0) { ++ } else if (portno == ++ sparx5_get_internal_port(sparx5, SPX5_PORT_VD0)) { + /* IPMC only idle BW */ + return SPX5_CAL_SPEED_NONE; +- } else if (portno == SPX5_PORT_VD1) { ++ } else if (portno == ++ sparx5_get_internal_port(sparx5, SPX5_PORT_VD1)) { + /* OAM only idle BW */ + return SPX5_CAL_SPEED_NONE; +- } else if (portno == SPX5_PORT_VD2) { ++ } else if (portno == ++ sparx5_get_internal_port(sparx5, SPX5_PORT_VD2)) { + /* IPinIP gets only idle BW */ + return SPX5_CAL_SPEED_NONE; + } +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c +@@ -364,7 +364,9 @@ static void sparx5_fdma_injection_mode(s + sparx5, QS_INJ_GRP_CFG(INJ_QUEUE)); + + /* CPU ports capture setup */ +- for (portno = SPX5_PORT_CPU_0; portno <= SPX5_PORT_CPU_1; portno++) { ++ for (portno = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); ++ portno <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); ++ portno++) { + /* ASM CPU port: No preamble, IFH, enable padding */ + spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) | + ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) | +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mactable.c +@@ -129,7 +129,8 @@ int sparx5_mc_sync(struct net_device *de + struct sparx5_port *port = netdev_priv(dev); + struct sparx5 *sparx5 = port->sparx5; + +- return sparx5_mact_learn(sparx5, PGID_CPU, addr, port->pvid); ++ return sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), ++ addr, port->pvid); + } + + static int sparx5_mact_get(struct sparx5 *sparx5, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -649,13 +649,14 @@ static int sparx5_start(struct sparx5 *s + sparx5_update_fwd(sparx5); + + /* CPU copy CPU pgids */ +- spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), +- sparx5, ANA_AC_PGID_MISC_CFG(PGID_CPU)); +- spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), +- sparx5, ANA_AC_PGID_MISC_CFG(PGID_BCAST)); ++ spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, ++ ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU))); ++ spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, ++ ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_BCAST))); + + /* Recalc injected frame FCS */ +- for (idx = SPX5_PORT_CPU_0; idx <= SPX5_PORT_CPU_1; idx++) ++ for (idx = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); ++ idx <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); idx++) + spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1), + ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, + sparx5, ANA_CL_FILTER_CTRL(idx)); +@@ -670,7 +671,8 @@ static int sparx5_start(struct sparx5 *s + sparx5_vlan_init(sparx5); + + /* Add host mode BC address (points only to CPU) */ +- sparx5_mact_learn(sparx5, PGID_CPU, broadcast, NULL_VID); ++ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), broadcast, ++ NULL_VID); + + /* Enable queue limitation watermarks */ + sparx5_qlim_set(sparx5); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -54,23 +54,21 @@ enum sparx5_vlan_port_type { + #define SPX5_PORTS 65 + #define SPX5_PORTS_ALL 70 /* Total number of ports */ + +-#define SPX5_PORT_CPU (SPX5_PORTS) /* Next port is CPU port */ +-#define SPX5_PORT_CPU_0 (SPX5_PORT_CPU + 0) /* CPU Port 65 */ +-#define SPX5_PORT_CPU_1 (SPX5_PORT_CPU + 1) /* CPU Port 66 */ +-#define SPX5_PORT_VD0 (SPX5_PORT_CPU + 2) /* VD0/Port 67 used for IPMC */ +-#define SPX5_PORT_VD1 (SPX5_PORT_CPU + 3) /* VD1/Port 68 used for AFI/OAM */ +-#define SPX5_PORT_VD2 (SPX5_PORT_CPU + 4) /* VD2/Port 69 used for IPinIP*/ +- +-#define PGID_BASE SPX5_PORTS /* Starts after port PGIDs */ +-#define PGID_UC_FLOOD (PGID_BASE + 0) +-#define PGID_MC_FLOOD (PGID_BASE + 1) +-#define PGID_IPV4_MC_DATA (PGID_BASE + 2) +-#define PGID_IPV4_MC_CTRL (PGID_BASE + 3) +-#define PGID_IPV6_MC_DATA (PGID_BASE + 4) +-#define PGID_IPV6_MC_CTRL (PGID_BASE + 5) +-#define PGID_BCAST (PGID_BASE + 6) +-#define PGID_CPU (PGID_BASE + 7) +-#define PGID_MCAST_START (PGID_BASE + 8) ++#define SPX5_PORT_CPU_0 0 /* CPU Port 0 */ ++#define SPX5_PORT_CPU_1 1 /* CPU Port 1 */ ++#define SPX5_PORT_VD0 2 /* VD0/Port used for IPMC */ ++#define SPX5_PORT_VD1 3 /* VD1/Port used for AFI/OAM */ ++#define SPX5_PORT_VD2 4 /* VD2/Port used for IPinIP*/ ++ ++#define PGID_UC_FLOOD 0 ++#define PGID_MC_FLOOD 1 ++#define PGID_IPV4_MC_DATA 2 ++#define PGID_IPV4_MC_CTRL 3 ++#define PGID_IPV6_MC_DATA 4 ++#define PGID_IPV6_MC_CTRL 5 ++#define PGID_BCAST 6 ++#define PGID_CPU 7 ++#define PGID_MCAST_START 8 + + #define PGID_TABLE_SIZE 3290 + +@@ -500,6 +498,7 @@ enum sparx5_pgid_type { + void sparx5_pgid_init(struct sparx5 *spx5); + int sparx5_pgid_alloc_mcast(struct sparx5 *spx5, u16 *idx); + int sparx5_pgid_free(struct sparx5 *spx5, u16 idx); ++int sparx5_get_pgid(struct sparx5 *sparx5, int pgid); + + /* sparx5_pool.c */ + struct sparx5_pool_entry { +@@ -516,6 +515,7 @@ int sparx5_pool_get_with_idx(struct spar + /* sparx5_port.c */ + int sparx5_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, + struct sparx5_port_config *conf); ++int sparx5_get_internal_port(struct sparx5 *sparx5, int port); + + /* sparx5_sdlb.c */ + #define SPX5_SDLB_PUP_TOKEN_DISABLE 0x1FFF +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c +@@ -68,7 +68,8 @@ void sparx5_set_port_ifh(struct sparx5 * + /* MISC.PIPELINE_ACT */ + ifh_encode_bitfield(ifh_hdr, 1, 42, 3); + /* FWD.SRC_PORT = CPU */ +- ifh_encode_bitfield(ifh_hdr, SPX5_PORT_CPU, 46, 7); ++ ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), ++ 46, 7); + /* FWD.SFLOW_ID (disable SFlow sampling) */ + ifh_encode_bitfield(ifh_hdr, 124, 57, 7); + /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */ +@@ -190,7 +191,8 @@ static int sparx5_set_mac_address(struct + sparx5_mact_forget(sparx5, dev->dev_addr, port->pvid); + + /* Add new */ +- sparx5_mact_learn(sparx5, PGID_CPU, addr->sa_data, port->pvid); ++ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), ++ addr->sa_data, port->pvid); + + /* Record the address */ + eth_hw_addr_set(dev, addr->sa_data); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +@@ -317,7 +317,9 @@ int sparx5_manual_injection_mode(struct + sparx5, QS_INJ_GRP_CFG(INJ_QUEUE)); + + /* CPU ports capture setup */ +- for (portno = SPX5_PORT_CPU_0; portno <= SPX5_PORT_CPU_1; portno++) { ++ for (portno = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); ++ portno <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); ++ portno++) { + /* ASM CPU port: No preamble, IFH, enable padding */ + spx5_wr(ASM_PORT_CFG_PAD_ENA_SET(1) | + ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) | +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_pgid.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_pgid.c +@@ -11,7 +11,7 @@ void sparx5_pgid_init(struct sparx5 *spx + /* Reserved for unicast, flood control, broadcast, and CPU. + * These cannot be freed. + */ +- for (i = 0; i <= PGID_CPU; i++) ++ for (i = 0; i <= sparx5_get_pgid(spx5, PGID_CPU); i++) + spx5->pgid_map[i] = SPX5_PGID_RESERVED; + } + +@@ -22,7 +22,8 @@ int sparx5_pgid_alloc_mcast(struct sparx + /* The multicast area starts at index 65, but the first 7 + * are reserved for flood masks and CPU. Start alloc after that. + */ +- for (i = PGID_MCAST_START; i < spx5->data->consts->n_pgids; i++) { ++ for (i = sparx5_get_pgid(spx5, PGID_MCAST_START); ++ i < spx5->data->consts->n_pgids; i++) { + if (spx5->pgid_map[i] == SPX5_PGID_FREE) { + spx5->pgid_map[i] = SPX5_PGID_MULTICAST; + *idx = i; +@@ -35,7 +36,8 @@ int sparx5_pgid_alloc_mcast(struct sparx + + int sparx5_pgid_free(struct sparx5 *spx5, u16 idx) + { +- if (idx <= PGID_CPU || idx >= spx5->data->consts->n_pgids) ++ if (idx <= sparx5_get_pgid(spx5, PGID_CPU) || ++ idx >= spx5->data->consts->n_pgids) + return -EINVAL; + + if (spx5->pgid_map[idx] == SPX5_PGID_FREE) +@@ -44,3 +46,8 @@ int sparx5_pgid_free(struct sparx5 *spx5 + spx5->pgid_map[idx] = SPX5_PGID_FREE; + return 0; + } ++ ++int sparx5_get_pgid(struct sparx5 *sparx5, int pgid) ++{ ++ return sparx5->data->consts->n_ports + pgid; ++} +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -1352,3 +1352,8 @@ int sparx5_port_qos_default_set(const st + + return 0; + } ++ ++int sparx5_get_internal_port(struct sparx5 *sparx5, int port) ++{ ++ return sparx5->data->consts->n_ports + port; ++} +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c +@@ -32,24 +32,34 @@ static int sparx5_port_attr_pre_bridge_f + static void sparx5_port_update_mcast_ip_flood(struct sparx5_port *port, bool flood_flag) + { + bool should_flood = flood_flag || port->is_mrouter; ++ struct sparx5 *sparx5 = port->sparx5; + int pgid; + +- for (pgid = PGID_IPV4_MC_DATA; pgid <= PGID_IPV6_MC_CTRL; pgid++) ++ for (pgid = sparx5_get_pgid(sparx5, PGID_IPV4_MC_DATA); ++ pgid <= sparx5_get_pgid(sparx5, PGID_IPV6_MC_CTRL); pgid++) + sparx5_pgid_update_mask(port, pgid, should_flood); + } + + static void sparx5_port_attr_bridge_flags(struct sparx5_port *port, + struct switchdev_brport_flags flags) + { ++ struct sparx5 *sparx5 = port->sparx5; ++ + if (flags.mask & BR_MCAST_FLOOD) { +- sparx5_pgid_update_mask(port, PGID_MC_FLOOD, !!(flags.val & BR_MCAST_FLOOD)); ++ sparx5_pgid_update_mask(port, ++ sparx5_get_pgid(sparx5, PGID_MC_FLOOD), ++ !!(flags.val & BR_MCAST_FLOOD)); + sparx5_port_update_mcast_ip_flood(port, !!(flags.val & BR_MCAST_FLOOD)); + } + + if (flags.mask & BR_FLOOD) +- sparx5_pgid_update_mask(port, PGID_UC_FLOOD, !!(flags.val & BR_FLOOD)); ++ sparx5_pgid_update_mask(port, ++ sparx5_get_pgid(sparx5, PGID_UC_FLOOD), ++ !!(flags.val & BR_FLOOD)); + if (flags.mask & BR_BCAST_FLOOD) +- sparx5_pgid_update_mask(port, PGID_BCAST, !!(flags.val & BR_BCAST_FLOOD)); ++ sparx5_pgid_update_mask(port, ++ sparx5_get_pgid(sparx5, PGID_BCAST), ++ !!(flags.val & BR_BCAST_FLOOD)); + } + + static void sparx5_attr_stp_state_set(struct sparx5_port *port, +@@ -219,7 +229,8 @@ static void sparx5_port_bridge_leave(str + port->vid = NULL_VID; + + /* Forward frames to CPU */ +- sparx5_mact_learn(sparx5, PGID_CPU, port->ndev->dev_addr, 0); ++ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), ++ port->ndev->dev_addr, 0); + + /* Port enters in host more therefore restore mc list */ + __dev_mc_sync(port->ndev, sparx5_mc_sync, sparx5_mc_unsync); +@@ -254,7 +265,8 @@ static int sparx5_port_add_addr(struct n + u16 vid = port->pvid; + + if (up) +- sparx5_mact_learn(sparx5, PGID_CPU, port->ndev->dev_addr, vid); ++ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), ++ port->ndev->dev_addr, vid); + else + sparx5_mact_forget(sparx5, port->ndev->dev_addr, vid); + +@@ -330,7 +342,8 @@ static void sparx5_switchdev_bridge_fdb_ + switch (switchdev_work->event) { + case SWITCHDEV_FDB_ADD_TO_DEVICE: + if (host_addr) +- sparx5_add_mact_entry(sparx5, dev, PGID_CPU, ++ sparx5_add_mact_entry(sparx5, dev, ++ sparx5_get_pgid(sparx5, PGID_CPU), + fdb_info->addr, vid); + else + sparx5_add_mact_entry(sparx5, port->ndev, port->portno, +@@ -418,8 +431,8 @@ static int sparx5_handle_port_vlan_add(s + switchdev_blocking_nb); + + /* Flood broadcast to CPU */ +- sparx5_mact_learn(sparx5, PGID_BCAST, dev->broadcast, +- v->vid); ++ sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_BCAST), ++ dev->broadcast, v->vid); + return 0; + } + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c +@@ -168,7 +168,8 @@ void sparx5_update_fwd(struct sparx5 *sp + bitmap_to_arr32(mask, sparx5->bridge_fwd_mask, SPX5_PORTS); + + /* Update flood masks */ +- for (port = PGID_UC_FLOOD; port <= PGID_BCAST; port++) { ++ for (port = sparx5_get_pgid(sparx5, PGID_UC_FLOOD); ++ port <= sparx5_get_pgid(sparx5, PGID_BCAST); port++) { + spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); + if (is_sparx5(sparx5)) { + spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); diff --git a/target/linux/microchipsw/patches-6.12/0039-v6.13-net-sparx5-add-support-for-lan969x-targets-and-core-.patch b/target/linux/microchipsw/patches-6.12/0039-v6.13-net-sparx5-add-support-for-lan969x-targets-and-core-.patch new file mode 100644 index 0000000000..be9c440c6f --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0039-v6.13-net-sparx5-add-support-for-lan969x-targets-and-core-.patch @@ -0,0 +1,169 @@ +From 3ba2228de3c42509cddd592fd7e61e1f2738b95e Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:20 +0200 +Subject: [PATCH 44/82] net: sparx5: add support for lan969x targets and core + clock + +In preparation for lan969x, add lan969x targets to +sparx5_target_chiptype and set the core clock frequency for these +throughout. Lan969x only supports a core clock frequency of 328MHz. + +Also, set the policer update internal (pol_upd_int) matching the 328 MHz +frequency of the lan969x targets. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-1-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../microchip/sparx5/sparx5_calendar.c | 17 +++++++++ + .../ethernet/microchip/sparx5/sparx5_main.c | 16 +++++++++ + .../ethernet/microchip/sparx5/sparx5_main.h | 35 +++++++++++++------ + .../ethernet/microchip/sparx5/sparx5_ptp.c | 6 ++++ + 4 files changed, 64 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +@@ -53,6 +53,22 @@ static u32 sparx5_target_bandwidth(struc + case SPX5_TARGET_CT_7558: + case SPX5_TARGET_CT_7558TSN: + return 201000; ++ case SPX5_TARGET_CT_LAN9691VAO: ++ return 46000; ++ case SPX5_TARGET_CT_LAN9694RED: ++ case SPX5_TARGET_CT_LAN9694TSN: ++ case SPX5_TARGET_CT_LAN9694: ++ return 68000; ++ case SPX5_TARGET_CT_LAN9696RED: ++ case SPX5_TARGET_CT_LAN9696TSN: ++ case SPX5_TARGET_CT_LAN9692VAO: ++ case SPX5_TARGET_CT_LAN9696: ++ return 88000; ++ case SPX5_TARGET_CT_LAN9698RED: ++ case SPX5_TARGET_CT_LAN9698TSN: ++ case SPX5_TARGET_CT_LAN9693VAO: ++ case SPX5_TARGET_CT_LAN9698: ++ return 101000; + default: + return 0; + } +@@ -74,6 +90,7 @@ static u32 sparx5_clk_to_bandwidth(enum + { + switch (cclock) { + case SPX5_CORE_CLOCK_250MHZ: return 83000; /* 250000 / 3 */ ++ case SPX5_CORE_CLOCK_328MHZ: return 109375; /* 328000 / 3 */ + case SPX5_CORE_CLOCK_500MHZ: return 166000; /* 500000 / 3 */ + case SPX5_CORE_CLOCK_625MHZ: return 208000; /* 625000 / 3 */ + default: return 0; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -475,6 +475,20 @@ static int sparx5_init_coreclock(struct + else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) + freq = 0; /* Not supported */ + break; ++ case SPX5_TARGET_CT_LAN9694: ++ case SPX5_TARGET_CT_LAN9691VAO: ++ case SPX5_TARGET_CT_LAN9694TSN: ++ case SPX5_TARGET_CT_LAN9694RED: ++ case SPX5_TARGET_CT_LAN9696: ++ case SPX5_TARGET_CT_LAN9692VAO: ++ case SPX5_TARGET_CT_LAN9696TSN: ++ case SPX5_TARGET_CT_LAN9696RED: ++ case SPX5_TARGET_CT_LAN9698: ++ case SPX5_TARGET_CT_LAN9693VAO: ++ case SPX5_TARGET_CT_LAN9698TSN: ++ case SPX5_TARGET_CT_LAN9698RED: ++ freq = SPX5_CORE_CLOCK_328MHZ; ++ break; + default: + dev_err(sparx5->dev, "Target (%#04x) not supported\n", + sparx5->target_ct); +@@ -516,6 +530,8 @@ static int sparx5_init_coreclock(struct + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA | + CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, + sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); ++ } else { ++ pol_upd_int = 820; // SPX5_CORE_CLOCK_328MHZ + } + + /* Update state with chosen frequency */ +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -26,16 +26,28 @@ + + /* Target chip type */ + enum spx5_target_chiptype { +- SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ +- SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ +- SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ +- SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ +- SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ +- SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ +- SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ +- SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ +- SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ +- SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ ++ SPX5_TARGET_CT_7546 = 0x7546, /* SparX-5-64 Enterprise */ ++ SPX5_TARGET_CT_7549 = 0x7549, /* SparX-5-90 Enterprise */ ++ SPX5_TARGET_CT_7552 = 0x7552, /* SparX-5-128 Enterprise */ ++ SPX5_TARGET_CT_7556 = 0x7556, /* SparX-5-160 Enterprise */ ++ SPX5_TARGET_CT_7558 = 0x7558, /* SparX-5-200 Enterprise */ ++ SPX5_TARGET_CT_7546TSN = 0x47546, /* SparX-5-64i Industrial */ ++ SPX5_TARGET_CT_7549TSN = 0x47549, /* SparX-5-90i Industrial */ ++ SPX5_TARGET_CT_7552TSN = 0x47552, /* SparX-5-128i Industrial */ ++ SPX5_TARGET_CT_7556TSN = 0x47556, /* SparX-5-160i Industrial */ ++ SPX5_TARGET_CT_7558TSN = 0x47558, /* SparX-5-200i Industrial */ ++ SPX5_TARGET_CT_LAN9694 = 0x9694, /* lan969x-40 */ ++ SPX5_TARGET_CT_LAN9691VAO = 0x9691, /* lan969x-40-VAO */ ++ SPX5_TARGET_CT_LAN9694TSN = 0x9695, /* lan969x-40-TSN */ ++ SPX5_TARGET_CT_LAN9694RED = 0x969A, /* lan969x-40-RED */ ++ SPX5_TARGET_CT_LAN9696 = 0x9696, /* lan969x-60 */ ++ SPX5_TARGET_CT_LAN9692VAO = 0x9692, /* lan969x-65-VAO */ ++ SPX5_TARGET_CT_LAN9696TSN = 0x9697, /* lan969x-60-TSN */ ++ SPX5_TARGET_CT_LAN9696RED = 0x969B, /* lan969x-60-RED */ ++ SPX5_TARGET_CT_LAN9698 = 0x9698, /* lan969x-100 */ ++ SPX5_TARGET_CT_LAN9693VAO = 0x9693, /* lan969x-100-VAO */ ++ SPX5_TARGET_CT_LAN9698TSN = 0x9699, /* lan969x-100-TSN */ ++ SPX5_TARGET_CT_LAN9698RED = 0x969C, /* lan969x-100-RED */ + }; + + enum sparx5_port_max_tags { +@@ -192,6 +204,7 @@ struct sparx5_port { + enum sparx5_core_clockfreq { + SPX5_CORE_CLOCK_DEFAULT, /* Defaults to the highest supported frequency */ + SPX5_CORE_CLOCK_250MHZ, /* 250MHZ core clock frequency */ ++ SPX5_CORE_CLOCK_328MHZ, /* 328MHZ core clock frequency */ + SPX5_CORE_CLOCK_500MHZ, /* 500MHZ core clock frequency */ + SPX5_CORE_CLOCK_625MHZ, /* 625MHZ core clock frequency */ + }; +@@ -641,6 +654,8 @@ static inline u32 sparx5_clk_period(enum + switch (cclock) { + case SPX5_CORE_CLOCK_250MHZ: + return 4000; ++ case SPX5_CORE_CLOCK_328MHZ: ++ return 3048; + case SPX5_CORE_CLOCK_500MHZ: + return 2000; + case SPX5_CORE_CLOCK_625MHZ: +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c +@@ -38,6 +38,9 @@ static u64 sparx5_ptp_get_1ppm(struct sp + case SPX5_CORE_CLOCK_250MHZ: + res = 2301339409586; + break; ++ case SPX5_CORE_CLOCK_328MHZ: ++ res = 1756832768924; ++ break; + case SPX5_CORE_CLOCK_500MHZ: + res = 1150669704793; + break; +@@ -60,6 +63,9 @@ static u64 sparx5_ptp_get_nominal_value( + case SPX5_CORE_CLOCK_250MHZ: + res = 0x1FF0000000000000; + break; ++ case SPX5_CORE_CLOCK_328MHZ: ++ res = 0x18604697DD0F9B5B; ++ break; + case SPX5_CORE_CLOCK_500MHZ: + res = 0x0FF8000000000000; + break; diff --git a/target/linux/microchipsw/patches-6.12/0040-v6.13-net-sparx5-change-spx5_wr-to-spx5_rmw-in-cal-update.patch b/target/linux/microchipsw/patches-6.12/0040-v6.13-net-sparx5-change-spx5_wr-to-spx5_rmw-in-cal-update.patch new file mode 100644 index 0000000000..e000abdaa2 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0040-v6.13-net-sparx5-change-spx5_wr-to-spx5_rmw-in-cal-update.patch @@ -0,0 +1,48 @@ +From 4feb1d4bb1cc58d86ef8c19091ba4b2785784e08 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:21 +0200 +Subject: [PATCH 45/82] net: sparx5: change spx5_wr to spx5_rmw in cal update() + +In preparation for lan969x, use spx5_rmw() for enabling the update of +the calendar. This is required to not overwrite the DSM_TAXI_CAL_CFG +register, as an additional write will be added before this one, in a +subsequent patch. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-2-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../ethernet/microchip/sparx5/sparx5_calendar.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +@@ -546,9 +546,10 @@ static int sparx5_dsm_calendar_update(st + u32 idx; + u32 cal_len = sparx5_dsm_cal_len(data->schedule), len; + +- spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), +- sparx5, +- DSM_TAXI_CAL_CFG(taxi)); ++ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), ++ DSM_TAXI_CAL_CFG_CAL_PGM_ENA, ++ sparx5, ++ DSM_TAXI_CAL_CFG(taxi)); + for (idx = 0; idx < cal_len; idx++) { + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(idx), + DSM_TAXI_CAL_CFG_CAL_IDX, +@@ -559,9 +560,10 @@ static int sparx5_dsm_calendar_update(st + sparx5, + DSM_TAXI_CAL_CFG(taxi)); + } +- spx5_wr(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), +- sparx5, +- DSM_TAXI_CAL_CFG(taxi)); ++ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0), ++ DSM_TAXI_CAL_CFG_CAL_PGM_ENA, ++ sparx5, ++ DSM_TAXI_CAL_CFG(taxi)); + len = DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(spx5_rd(sparx5, + DSM_TAXI_CAL_CFG(taxi))); + if (len != cal_len - 1) diff --git a/target/linux/microchipsw/patches-6.12/0041-v6.13-net-sparx5-change-frequency-calculation-for-SDLB-s.patch b/target/linux/microchipsw/patches-6.12/0041-v6.13-net-sparx5-change-frequency-calculation-for-SDLB-s.patch new file mode 100644 index 0000000000..adc46b6c12 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0041-v6.13-net-sparx5-change-frequency-calculation-for-SDLB-s.patch @@ -0,0 +1,55 @@ +From 6e50593002ad4886e2d74e99b67e735cbab0c606 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:22 +0200 +Subject: [PATCH 46/82] net: sparx5: change frequency calculation for SDLB's + +In preparation for lan969x, rework the function that calculates the SDLB +(Service Dual Leacky Bucket) clock. This is required, as the +HSCH_SYS_CLK_PER register is Sparx5-exclusive. Instead derive the clock +from the core clock, using the sparx5_clk_period() function. The clock +stays the same before and after this patch, only now, +sparx5_sdlb_clk_hz_get() can be used for lan969x too. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-3-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 2 +- + drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c | 10 +++------- + 2 files changed, 4 insertions(+), 8 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -552,7 +552,7 @@ struct sparx5_sdlb_group *sparx5_get_sdl + int sparx5_sdlb_pup_token_get(struct sparx5 *sparx5, u32 pup_interval, + u64 rate); + +-int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); ++u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5); + int sparx5_sdlb_group_get_by_rate(struct sparx5 *sparx5, u32 rate, u32 burst); + int sparx5_sdlb_group_get_by_index(struct sparx5 *sparx5, u32 idx, u32 *group); + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_sdlb.c +@@ -25,17 +25,13 @@ struct sparx5_sdlb_group *sparx5_get_sdl + return &sdlb_groups[idx]; + } + +-int sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) ++u64 sparx5_sdlb_clk_hz_get(struct sparx5 *sparx5) + { +- u32 clk_per_100ps; + u64 clk_hz; + +- clk_per_100ps = HSCH_SYS_CLK_PER_100PS_GET(spx5_rd(sparx5, +- HSCH_SYS_CLK_PER)); +- if (!clk_per_100ps) +- clk_per_100ps = SPX5_CLK_PER_100PS_DEFAULT; ++ clk_hz = (10 * 1000 * 1000) / ++ (sparx5_clk_period(sparx5->coreclock) / 100); + +- clk_hz = (10 * 1000 * 1000) / clk_per_100ps; + return clk_hz *= 1000; + } + diff --git a/target/linux/microchipsw/patches-6.12/0042-v6.13-net-sparx5-add-sparx5-context-pointer-to-a-few-funct.patch b/target/linux/microchipsw/patches-6.12/0042-v6.13-net-sparx5-add-sparx5-context-pointer-to-a-few-funct.patch new file mode 100644 index 0000000000..2ea8da484c --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0042-v6.13-net-sparx5-add-sparx5-context-pointer-to-a-few-funct.patch @@ -0,0 +1,122 @@ +From 6e84c752630600be74db11feae869d333c55fe1c Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:23 +0200 +Subject: [PATCH 47/82] net: sparx5: add sparx5 context pointer to a few + functions + +In preparation for lan969x, add the sparx5 context pointer to certain +IFH (Internal Frame Header) functions. This is required, as the +is_sparx5() function will be used here in a subsequent patch. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-4-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c | 2 +- + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 11 +++++++---- + .../net/ethernet/microchip/sparx5/sparx5_netdev.c | 9 ++++++--- + .../net/ethernet/microchip/sparx5/sparx5_packet.c | 13 ++++++++----- + 4 files changed, 22 insertions(+), 13 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c +@@ -154,7 +154,7 @@ static bool sparx5_fdma_rx_get_frame(str + skb = rx->skb[fdma->dcb_index][fdma->db_index]; + skb_put(skb, fdma_db_len_get(db_hw)); + /* Now do the normal processing of the skb */ +- sparx5_ifh_parse((u32 *)skb->data, &fi); ++ sparx5_ifh_parse(sparx5, (u32 *)skb->data, &fi); + /* Map to port netdev */ + port = fi.src_port < sparx5->data->consts->n_ports ? + sparx5->ports[fi.src_port] : +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -401,7 +401,7 @@ struct frame_info { + }; + + void sparx5_xtr_flush(struct sparx5 *sparx5, u8 grp); +-void sparx5_ifh_parse(u32 *ifh, struct frame_info *info); ++void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info); + irqreturn_t sparx5_xtr_handler(int irq, void *_priv); + netdev_tx_t sparx5_port_xmit_impl(struct sk_buff *skb, struct net_device *dev); + int sparx5_manual_injection_mode(struct sparx5 *sparx5); +@@ -469,10 +469,13 @@ static inline int sparx5_dcb_init(struct + #endif + + /* sparx5_netdev.c */ +-void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp); ++void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, ++ u64 timestamp); + void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op); +-void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type); +-void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset); ++void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, ++ u32 pdu_type); ++void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, ++ u32 pdu_w16_offset); + void sparx5_set_port_ifh(struct sparx5 *sparx5, void *ifh_hdr, u16 portno); + bool sparx5_netdevice_check(const struct net_device *dev); + struct net_device *sparx5_create_netdev(struct sparx5 *sparx5, u32 portno); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c +@@ -81,17 +81,20 @@ void sparx5_set_port_ifh_rew_op(void *if + ifh_encode_bitfield(ifh_hdr, rew_op, VSTAX + 32, 10); + } + +-void sparx5_set_port_ifh_pdu_type(void *ifh_hdr, u32 pdu_type) ++void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, ++ u32 pdu_type) + { + ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4); + } + +-void sparx5_set_port_ifh_pdu_w16_offset(void *ifh_hdr, u32 pdu_w16_offset) ++void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, ++ u32 pdu_w16_offset) + { + ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6); + } + +-void sparx5_set_port_ifh_timestamp(void *ifh_hdr, u64 timestamp) ++void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, ++ u64 timestamp) + { + ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); + } +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +@@ -32,7 +32,7 @@ void sparx5_xtr_flush(struct sparx5 *spa + spx5_wr(0, sparx5, QS_XTR_FLUSH); + } + +-void sparx5_ifh_parse(u32 *ifh, struct frame_info *info) ++void sparx5_ifh_parse(struct sparx5 *sparx5, u32 *ifh, struct frame_info *info) + { + u8 *xtr_hdr = (u8 *)ifh; + +@@ -72,7 +72,7 @@ static void sparx5_xtr_grp(struct sparx5 + ifh[i] = spx5_rd(sparx5, QS_XTR_RD(grp)); + + /* Decode IFH (what's needed) */ +- sparx5_ifh_parse(ifh, &fi); ++ sparx5_ifh_parse(sparx5, ifh, &fi); + + /* Map to port netdev */ + port = fi.src_port < sparx5->data->consts->n_ports ? +@@ -242,9 +242,12 @@ netdev_tx_t sparx5_port_xmit_impl(struct + return NETDEV_TX_BUSY; + + sparx5_set_port_ifh_rew_op(ifh, SPARX5_SKB_CB(skb)->rew_op); +- sparx5_set_port_ifh_pdu_type(ifh, SPARX5_SKB_CB(skb)->pdu_type); +- sparx5_set_port_ifh_pdu_w16_offset(ifh, SPARX5_SKB_CB(skb)->pdu_w16_offset); +- sparx5_set_port_ifh_timestamp(ifh, SPARX5_SKB_CB(skb)->ts_id); ++ sparx5_set_port_ifh_pdu_type(sparx5, ifh, ++ SPARX5_SKB_CB(skb)->pdu_type); ++ sparx5_set_port_ifh_pdu_w16_offset(sparx5, ifh, ++ SPARX5_SKB_CB(skb)->pdu_w16_offset); ++ sparx5_set_port_ifh_timestamp(sparx5, ifh, ++ SPARX5_SKB_CB(skb)->ts_id); + } + + skb_tx_timestamp(skb); diff --git a/target/linux/microchipsw/patches-6.12/0043-v6.13-net-sparx5-add-registers-required-by-lan969x.patch b/target/linux/microchipsw/patches-6.12/0043-v6.13-net-sparx5-add-registers-required-by-lan969x.patch new file mode 100644 index 0000000000..58df536635 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0043-v6.13-net-sparx5-add-registers-required-by-lan969x.patch @@ -0,0 +1,185 @@ +From 79009c7ee726a104e4d67c99ef5b53db31a39549 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:24 +0200 +Subject: [PATCH 48/82] net: sparx5: add registers required by lan969x + +Lan969x will require a few additional registers for certain operations. +Some are shared, some are not. Add these. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-5-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../microchip/sparx5/sparx5_main_regs.h | 132 ++++++++++++++++++ + 1 file changed, 132 insertions(+) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h +@@ -2666,6 +2666,44 @@ extern const struct sparx5_regs *regs; + #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\ + FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x) + ++/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ ++#define DEV2G5_PHAD_CTRL(t, g) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ ++ regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) ++ ++#define DEV2G5_PHAD_CTRL_PHAD_ENA\ ++ BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) ++#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ ++ spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) ++#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ ++ spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) ++ ++/* LAN969X ONLY */ ++#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) ++#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ ++ FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) ++#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ ++ FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) ++ ++/* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */ ++#define DEV2G5_PHAD_CTRL(t, g) \ ++ __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2, \ ++ regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4) ++ ++#define DEV2G5_PHAD_CTRL_PHAD_ENA\ ++ BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA]) ++#define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\ ++ spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x) ++#define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\ ++ spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x) ++ ++/* LAN969X ONLY */ ++#define DEV2G5_PHAD_CTRL_DIV_CFG GENMASK(11, 9) ++#define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\ ++ FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x) ++#define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\ ++ FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x) ++ + /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */ + #define DEV10G_MAC_ENA_CFG(t) \ + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1, \ +@@ -2869,6 +2907,11 @@ extern const struct sparx5_regs *regs; + #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ + FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x) + ++/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ ++#define DEV10G_PTP_STAMPER_CFG(t) \ ++ __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 20, 0, \ ++ 1, 4) ++ + /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */ + #define DEV10G_PCS25G_CFG(t) \ + __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\ +@@ -4267,6 +4310,11 @@ extern const struct sparx5_regs *regs; + #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\ + FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x) + ++/* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */ ++#define DEV5G_PTP_STAMPER_CFG(t) \ ++ __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 20, 0, 1, \ ++ 4) ++ + /* DSM:RAM_CTRL:RAM_INIT */ + #define DSM_RAM_INIT \ + __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4) +@@ -4444,6 +4492,27 @@ extern const struct sparx5_regs *regs; + #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\ + FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x) + ++/* LAN969X ONLY */ ++#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT BIT(23) ++#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\ ++ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) ++#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\ ++ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x) ++ ++/* LAN969X ONLY */ ++#define DSM_TAXI_CAL_CFG_CAL_SWITCH BIT(22) ++#define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\ ++ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) ++#define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\ ++ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x) ++ ++/* LAN969X ONLY */ ++#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL BIT(21) ++#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\ ++ FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) ++#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\ ++ FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x) ++ + /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */ + #define EACL_VCAP_ES2_KEY_SEL(g, r) \ + __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE], \ +@@ -6720,6 +6789,69 @@ extern const struct sparx5_regs *regs; + regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL], \ + regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4) + ++/* LAN969X ONLY */ ++/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */ ++#define PTP_TWOSTEP_CTRL \ ++ __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 0, 0, 1, 4) ++ ++#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA BIT(12) ++#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\ ++ FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) ++#define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\ ++ FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x) ++ ++#define PTP_TWOSTEP_CTRL_PTP_NXT BIT(11) ++#define PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\ ++ FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_NXT, x) ++#define PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\ ++ FIELD_GET(PTP_TWOSTEP_CTRL_PTP_NXT, x) ++ ++#define PTP_TWOSTEP_CTRL_PTP_VLD BIT(10) ++#define PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\ ++ FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_VLD, x) ++#define PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\ ++ FIELD_GET(PTP_TWOSTEP_CTRL_PTP_VLD, x) ++ ++#define PTP_TWOSTEP_CTRL_STAMP_TX BIT(9) ++#define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\ ++ FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x) ++#define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\ ++ FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x) ++ ++#define PTP_TWOSTEP_CTRL_STAMP_PORT GENMASK(8, 1) ++#define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\ ++ FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x) ++#define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\ ++ FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x) ++ ++#define PTP_TWOSTEP_CTRL_PTP_OVFL BIT(0) ++#define PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\ ++ FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVFL, x) ++#define PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\ ++ FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVFL, x) ++ ++/* LAN969X ONLY */ ++/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_NSEC */ ++#define PTP_TWOSTEP_STAMP_NSEC \ ++ __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 4, 0, 1, 4) ++ ++#define PTP_TWOSTEP_STAMP_NSEC_NS GENMASK(29, 0) ++#define PTP_TWOSTEP_STAMP_NSEC_NS_SET(x)\ ++ FIELD_PREP(PTP_TWOSTEP_STAMP_NSEC_NS, x) ++#define PTP_TWOSTEP_STAMP_NSEC_NS_GET(x)\ ++ FIELD_GET(PTP_TWOSTEP_STAMP_NSEC_NS, x) ++ ++/* LAN969X ONLY */ ++/* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_SUBNS */ ++#define PTP_TWOSTEP_STAMP_SUBNS \ ++ __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 8, 0, 1, 4) ++ ++#define PTP_TWOSTEP_STAMP_SUBNS_NS GENMASK(7, 0) ++#define PTP_TWOSTEP_STAMP_SUBNS_NS_SET(x)\ ++ FIELD_PREP(PTP_TWOSTEP_STAMP_SUBNS_NS, x) ++#define PTP_TWOSTEP_STAMP_SUBNS_NS_GET(x)\ ++ FIELD_GET(PTP_TWOSTEP_STAMP_SUBNS_NS, x) ++ + /* QFWD:SYSTEM:SWITCH_PORT_MODE */ + #define QFWD_SWITCH_PORT_MODE(r) \ + __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \ diff --git a/target/linux/microchipsw/patches-6.12/0044-v6.13-net-lan969x-add-match-data-for-lan969x.patch b/target/linux/microchipsw/patches-6.12/0044-v6.13-net-lan969x-add-match-data-for-lan969x.patch new file mode 100644 index 0000000000..659e8d053f --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0044-v6.13-net-lan969x-add-match-data-for-lan969x.patch @@ -0,0 +1,216 @@ +From 033defe6fd3cc5b5b90c31d7bf0effe27772adbd Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:25 +0200 +Subject: [PATCH 49/82] net: lan969x: add match data for lan969x + +Add match data for lan969x, with initial fields for iomap, iomap_size +and ioranges. Add new Kconfig symbol CONFIG_LAN969X_CONFIG for compiling +the lan969x driver. + +It has been decided to give lan969x its own Kconfig symbol, as a +considerable amount of code is needed, beside the Sparx5 code, to add +full chip support (and more will be added in future series). Also this +makes it possible to compile Sparx5 without lan969x. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-6-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + MAINTAINERS | 7 ++ + drivers/net/ethernet/microchip/Kconfig | 1 + + drivers/net/ethernet/microchip/Makefile | 1 + + .../net/ethernet/microchip/lan969x/Kconfig | 5 + + .../net/ethernet/microchip/lan969x/Makefile | 12 ++ + .../net/ethernet/microchip/lan969x/lan969x.c | 104 ++++++++++++++++++ + .../net/ethernet/microchip/lan969x/lan969x.h | 15 +++ + 7 files changed, 145 insertions(+) + create mode 100644 drivers/net/ethernet/microchip/lan969x/Kconfig + create mode 100644 drivers/net/ethernet/microchip/lan969x/Makefile + create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x.c + create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x.h + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -15147,6 +15147,13 @@ S: Maintained + F: Documentation/devicetree/bindings/interrupt-controller/microchip,lan966x-oic.yaml + F: drivers/irqchip/irq-lan966x-oic.c + ++MICROCHIP LAN969X ETHERNET DRIVER ++M: Daniel Machon ++M: UNGLinuxDriver@microchip.com ++L: netdev@vger.kernel.org ++S: Maintained ++F: drivers/net/ethernet/microchip/lan969x/* ++ + MICROCHIP LCDFB DRIVER + M: Nicolas Ferre + L: linux-fbdev@vger.kernel.org +--- a/drivers/net/ethernet/microchip/Kconfig ++++ b/drivers/net/ethernet/microchip/Kconfig +@@ -59,6 +59,7 @@ config LAN743X + + source "drivers/net/ethernet/microchip/lan865x/Kconfig" + source "drivers/net/ethernet/microchip/lan966x/Kconfig" ++source "drivers/net/ethernet/microchip/lan969x/Kconfig" + source "drivers/net/ethernet/microchip/sparx5/Kconfig" + source "drivers/net/ethernet/microchip/vcap/Kconfig" + source "drivers/net/ethernet/microchip/fdma/Kconfig" +--- a/drivers/net/ethernet/microchip/Makefile ++++ b/drivers/net/ethernet/microchip/Makefile +@@ -11,6 +11,7 @@ lan743x-objs := lan743x_main.o lan743x_e + + obj-$(CONFIG_LAN865X) += lan865x/ + obj-$(CONFIG_LAN966X_SWITCH) += lan966x/ ++obj-$(CONFIG_LAN969X_SWITCH) += lan969x/ + obj-$(CONFIG_SPARX5_SWITCH) += sparx5/ + obj-$(CONFIG_VCAP) += vcap/ + obj-$(CONFIG_FDMA) += fdma/ +--- /dev/null ++++ b/drivers/net/ethernet/microchip/lan969x/Kconfig +@@ -0,0 +1,5 @@ ++config LAN969X_SWITCH ++ tristate "Lan969x switch driver" ++ depends on SPARX5_SWITCH ++ help ++ This driver supports the lan969x family of network switch devices. +--- /dev/null ++++ b/drivers/net/ethernet/microchip/lan969x/Makefile +@@ -0,0 +1,12 @@ ++# SPDX-License-Identifier: GPL-2.0-only ++# ++# Makefile for the Microchip lan969x network device drivers. ++# ++ ++obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o ++ ++lan969x-switch-y := lan969x.o ++ ++# Provide include files ++ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma ++ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap +--- /dev/null ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c +@@ -0,0 +1,104 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. ++ */ ++ ++#include "lan969x.h" ++ ++static const struct sparx5_main_io_resource lan969x_main_iomap[] = { ++ { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ ++ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ ++ { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */ ++ { TARGET_QS, 0x2030000, 1 }, /* 0xe2030000 */ ++ { TARGET_PTP, 0x2040000, 1 }, /* 0xe2040000 */ ++ { TARGET_ANA_ACL, 0x2050000, 1 }, /* 0xe2050000 */ ++ { TARGET_LRN, 0x2060000, 1 }, /* 0xe2060000 */ ++ { TARGET_VCAP_SUPER, 0x2080000, 1 }, /* 0xe2080000 */ ++ { TARGET_QSYS, 0x20a0000, 1 }, /* 0xe20a0000 */ ++ { TARGET_QFWD, 0x20b0000, 1 }, /* 0xe20b0000 */ ++ { TARGET_XQS, 0x20c0000, 1 }, /* 0xe20c0000 */ ++ { TARGET_VCAP_ES2, 0x20d0000, 1 }, /* 0xe20d0000 */ ++ { TARGET_VCAP_ES0, 0x20e0000, 1 }, /* 0xe20e0000 */ ++ { TARGET_ANA_AC_POL, 0x2200000, 1 }, /* 0xe2200000 */ ++ { TARGET_QRES, 0x2280000, 1 }, /* 0xe2280000 */ ++ { TARGET_EACL, 0x22c0000, 1 }, /* 0xe22c0000 */ ++ { TARGET_ANA_CL, 0x2400000, 1 }, /* 0xe2400000 */ ++ { TARGET_ANA_L3, 0x2480000, 1 }, /* 0xe2480000 */ ++ { TARGET_ANA_AC_SDLB, 0x2500000, 1 }, /* 0xe2500000 */ ++ { TARGET_HSCH, 0x2580000, 1 }, /* 0xe2580000 */ ++ { TARGET_REW, 0x2600000, 1 }, /* 0xe2600000 */ ++ { TARGET_ANA_L2, 0x2800000, 1 }, /* 0xe2800000 */ ++ { TARGET_ANA_AC, 0x2900000, 1 }, /* 0xe2900000 */ ++ { TARGET_VOP, 0x2a00000, 1 }, /* 0xe2a00000 */ ++ { TARGET_DEV2G5, 0x3004000, 1 }, /* 0xe3004000 */ ++ { TARGET_DEV10G, 0x3008000, 1 }, /* 0xe3008000 */ ++ { TARGET_PCS10G_BR, 0x300c000, 1 }, /* 0xe300c000 */ ++ { TARGET_DEV2G5 + 1, 0x3010000, 1 }, /* 0xe3010000 */ ++ { TARGET_DEV2G5 + 2, 0x3014000, 1 }, /* 0xe3014000 */ ++ { TARGET_DEV2G5 + 3, 0x3018000, 1 }, /* 0xe3018000 */ ++ { TARGET_DEV2G5 + 4, 0x301c000, 1 }, /* 0xe301c000 */ ++ { TARGET_DEV10G + 1, 0x3020000, 1 }, /* 0xe3020000 */ ++ { TARGET_PCS10G_BR + 1, 0x3024000, 1 }, /* 0xe3024000 */ ++ { TARGET_DEV2G5 + 5, 0x3028000, 1 }, /* 0xe3028000 */ ++ { TARGET_DEV2G5 + 6, 0x302c000, 1 }, /* 0xe302c000 */ ++ { TARGET_DEV2G5 + 7, 0x3030000, 1 }, /* 0xe3030000 */ ++ { TARGET_DEV2G5 + 8, 0x3034000, 1 }, /* 0xe3034000 */ ++ { TARGET_DEV10G + 2, 0x3038000, 1 }, /* 0xe3038000 */ ++ { TARGET_PCS10G_BR + 2, 0x303c000, 1 }, /* 0xe303c000 */ ++ { TARGET_DEV2G5 + 9, 0x3040000, 1 }, /* 0xe3040000 */ ++ { TARGET_DEV5G, 0x3044000, 1 }, /* 0xe3044000 */ ++ { TARGET_PCS5G_BR, 0x3048000, 1 }, /* 0xe3048000 */ ++ { TARGET_DEV2G5 + 10, 0x304c000, 1 }, /* 0xe304c000 */ ++ { TARGET_DEV2G5 + 11, 0x3050000, 1 }, /* 0xe3050000 */ ++ { TARGET_DEV2G5 + 12, 0x3054000, 1 }, /* 0xe3054000 */ ++ { TARGET_DEV10G + 3, 0x3058000, 1 }, /* 0xe3058000 */ ++ { TARGET_PCS10G_BR + 3, 0x305c000, 1 }, /* 0xe305c000 */ ++ { TARGET_DEV2G5 + 13, 0x3060000, 1 }, /* 0xe3060000 */ ++ { TARGET_DEV5G + 1, 0x3064000, 1 }, /* 0xe3064000 */ ++ { TARGET_PCS5G_BR + 1, 0x3068000, 1 }, /* 0xe3068000 */ ++ { TARGET_DEV2G5 + 14, 0x306c000, 1 }, /* 0xe306c000 */ ++ { TARGET_DEV2G5 + 15, 0x3070000, 1 }, /* 0xe3070000 */ ++ { TARGET_DEV2G5 + 16, 0x3074000, 1 }, /* 0xe3074000 */ ++ { TARGET_DEV10G + 4, 0x3078000, 1 }, /* 0xe3078000 */ ++ { TARGET_PCS10G_BR + 4, 0x307c000, 1 }, /* 0xe307c000 */ ++ { TARGET_DEV2G5 + 17, 0x3080000, 1 }, /* 0xe3080000 */ ++ { TARGET_DEV5G + 2, 0x3084000, 1 }, /* 0xe3084000 */ ++ { TARGET_PCS5G_BR + 2, 0x3088000, 1 }, /* 0xe3088000 */ ++ { TARGET_DEV2G5 + 18, 0x308c000, 1 }, /* 0xe308c000 */ ++ { TARGET_DEV2G5 + 19, 0x3090000, 1 }, /* 0xe3090000 */ ++ { TARGET_DEV2G5 + 20, 0x3094000, 1 }, /* 0xe3094000 */ ++ { TARGET_DEV10G + 5, 0x3098000, 1 }, /* 0xe3098000 */ ++ { TARGET_PCS10G_BR + 5, 0x309c000, 1 }, /* 0xe309c000 */ ++ { TARGET_DEV2G5 + 21, 0x30a0000, 1 }, /* 0xe30a0000 */ ++ { TARGET_DEV5G + 3, 0x30a4000, 1 }, /* 0xe30a4000 */ ++ { TARGET_PCS5G_BR + 3, 0x30a8000, 1 }, /* 0xe30a8000 */ ++ { TARGET_DEV2G5 + 22, 0x30ac000, 1 }, /* 0xe30ac000 */ ++ { TARGET_DEV2G5 + 23, 0x30b0000, 1 }, /* 0xe30b0000 */ ++ { TARGET_DEV2G5 + 24, 0x30b4000, 1 }, /* 0xe30b4000 */ ++ { TARGET_DEV10G + 6, 0x30b8000, 1 }, /* 0xe30b8000 */ ++ { TARGET_PCS10G_BR + 6, 0x30bc000, 1 }, /* 0xe30bc000 */ ++ { TARGET_DEV2G5 + 25, 0x30c0000, 1 }, /* 0xe30c0000 */ ++ { TARGET_DEV10G + 7, 0x30c4000, 1 }, /* 0xe30c4000 */ ++ { TARGET_PCS10G_BR + 7, 0x30c8000, 1 }, /* 0xe30c8000 */ ++ { TARGET_DEV2G5 + 26, 0x30cc000, 1 }, /* 0xe30cc000 */ ++ { TARGET_DEV10G + 8, 0x30d0000, 1 }, /* 0xe30d0000 */ ++ { TARGET_PCS10G_BR + 8, 0x30d4000, 1 }, /* 0xe30d4000 */ ++ { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ ++ { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ ++ { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ ++ { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ ++ { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ ++ { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ ++}; ++ ++const struct sparx5_match_data lan969x_desc = { ++ .iomap = lan969x_main_iomap, ++ .iomap_size = ARRAY_SIZE(lan969x_main_iomap), ++ .ioranges = 2, ++}; ++EXPORT_SYMBOL_GPL(lan969x_desc); ++ ++MODULE_DESCRIPTION("Microchip lan969x switch driver"); ++MODULE_AUTHOR("Daniel Machon "); ++MODULE_LICENSE("Dual MIT/GPL"); +--- /dev/null ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h +@@ -0,0 +1,15 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. ++ */ ++ ++#ifndef __LAN969X_H__ ++#define __LAN969X_H__ ++ ++#include "../sparx5/sparx5_main.h" ++ ++/* lan969x.c */ ++extern const struct sparx5_match_data lan969x_desc; ++ ++#endif diff --git a/target/linux/microchipsw/patches-6.12/0045-v6.13-net-lan969x-add-register-diffs-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0045-v6.13-net-lan969x-add-register-diffs-to-match-data.patch new file mode 100644 index 0000000000..059faf0f04 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0045-v6.13-net-lan969x-add-register-diffs-to-match-data.patch @@ -0,0 +1,365 @@ +From d68c6bbfd6ba14f5c2987a59f1d6fb4a4688204e Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:26 +0200 +Subject: [PATCH 50/82] net: lan969x: add register diffs to match data + +Add new file lan969x_regs.c that defines all the register differences +for lan969x, and add it to the lan969x match data. + +GW_DEV2G5_PHASE_DETECTOR_CTRL, FP_DEV2G5_PHAD_CTRL_PHAD_ENA and +FP_DEV2G5_PHAD_CTRL_PHAD_FAILED are required by the new register macros +which was introduced earlier. Add these for Sparx5 also. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-7-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/microchip/lan969x/Makefile | 2 +- + .../net/ethernet/microchip/lan969x/lan969x.c | 12 + + .../net/ethernet/microchip/lan969x/lan969x.h | 11 + + .../ethernet/microchip/lan969x/lan969x_regs.c | 222 ++++++++++++++++++ + .../ethernet/microchip/sparx5/sparx5_regs.c | 5 +- + .../ethernet/microchip/sparx5/sparx5_regs.h | 5 +- + 6 files changed, 254 insertions(+), 3 deletions(-) + create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x_regs.c + +--- a/drivers/net/ethernet/microchip/lan969x/Makefile ++++ b/drivers/net/ethernet/microchip/lan969x/Makefile +@@ -5,7 +5,7 @@ + + obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o + +-lan969x-switch-y := lan969x.o ++lan969x-switch-y := lan969x_regs.o lan969x.o + + # Provide include files + ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c +@@ -92,10 +92,22 @@ static const struct sparx5_main_io_resou + { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ + }; + ++static const struct sparx5_regs lan969x_regs = { ++ .tsize = lan969x_tsize, ++ .gaddr = lan969x_gaddr, ++ .gcnt = lan969x_gcnt, ++ .gsize = lan969x_gsize, ++ .raddr = lan969x_raddr, ++ .rcnt = lan969x_rcnt, ++ .fpos = lan969x_fpos, ++ .fsize = lan969x_fsize, ++}; ++ + const struct sparx5_match_data lan969x_desc = { + .iomap = lan969x_main_iomap, + .iomap_size = ARRAY_SIZE(lan969x_main_iomap), + .ioranges = 2, ++ .regs = &lan969x_regs, + }; + EXPORT_SYMBOL_GPL(lan969x_desc); + +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.h ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h +@@ -8,8 +8,19 @@ + #define __LAN969X_H__ + + #include "../sparx5/sparx5_main.h" ++#include "../sparx5/sparx5_regs.h" + + /* lan969x.c */ + extern const struct sparx5_match_data lan969x_desc; + ++/* lan969x_regs.c */ ++extern const unsigned int lan969x_tsize[TSIZE_LAST]; ++extern const unsigned int lan969x_raddr[RADDR_LAST]; ++extern const unsigned int lan969x_rcnt[RCNT_LAST]; ++extern const unsigned int lan969x_gaddr[GADDR_LAST]; ++extern const unsigned int lan969x_gcnt[GCNT_LAST]; ++extern const unsigned int lan969x_gsize[GSIZE_LAST]; ++extern const unsigned int lan969x_fpos[FPOS_LAST]; ++extern const unsigned int lan969x_fsize[FSIZE_LAST]; ++ + #endif +--- /dev/null ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c +@@ -0,0 +1,222 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. ++ */ ++ ++/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. ++ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b ++ */ ++ ++#include "lan969x.h" ++ ++const unsigned int lan969x_tsize[TSIZE_LAST] = { ++ [TC_DEV10G] = 10, ++ [TC_DEV2G5] = 28, ++ [TC_DEV5G] = 4, ++ [TC_PCS10G_BR] = 10, ++ [TC_PCS5G_BR] = 4, ++}; ++ ++const unsigned int lan969x_raddr[RADDR_LAST] = { ++ [RA_CPU_PROC_CTRL] = 160, ++ [RA_GCB_SOFT_RST] = 12, ++ [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20, ++}; ++ ++const unsigned int lan969x_rcnt[RCNT_LAST] = { ++ [RC_ANA_AC_OWN_UPSID] = 1, ++ [RC_ANA_ACL_VCAP_S2_CFG] = 35, ++ [RC_ANA_ACL_OWN_UPSID] = 1, ++ [RC_ANA_CL_OWN_UPSID] = 1, ++ [RC_ANA_L2_OWN_UPSID] = 1, ++ [RC_ASM_PORT_CFG] = 32, ++ [RC_DSM_BUF_CFG] = 32, ++ [RC_DSM_DEV_TX_STOP_WM_CFG] = 32, ++ [RC_DSM_RX_PAUSE_CFG] = 32, ++ [RC_DSM_MAC_CFG] = 32, ++ [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30, ++ [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30, ++ [RC_DSM_TAXI_CAL_CFG] = 6, ++ [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30, ++ [RC_HSCH_PORT_MODE] = 35, ++ [RC_QFWD_SWITCH_PORT_MODE] = 35, ++ [RC_QSYS_PAUSE_CFG] = 35, ++ [RC_QSYS_ATOP] = 35, ++ [RC_QSYS_FWD_PRESSURE] = 35, ++ [RC_QSYS_CAL_AUTO] = 4, ++ [RC_REW_OWN_UPSID] = 1, ++ [RC_REW_RTAG_ETAG_CTRL] = 35, ++}; ++ ++const unsigned int lan969x_gaddr[GADDR_LAST] = { ++ [GA_ANA_AC_RAM_CTRL] = 202000, ++ [GA_ANA_AC_PS_COMMON] = 202880, ++ [GA_ANA_AC_MIRROR_PROBE] = 203232, ++ [GA_ANA_AC_SRC] = 201728, ++ [GA_ANA_AC_PGID] = 131072, ++ [GA_ANA_AC_TSN_SF] = 202028, ++ [GA_ANA_AC_TSN_SF_CFG] = 148480, ++ [GA_ANA_AC_TSN_SF_STATUS] = 147936, ++ [GA_ANA_AC_SG_ACCESS] = 202032, ++ [GA_ANA_AC_SG_CONFIG] = 202752, ++ [GA_ANA_AC_SG_STATUS] = 147952, ++ [GA_ANA_AC_SG_STATUS_STICKY] = 202044, ++ [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048, ++ [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800, ++ [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068, ++ [GA_ANA_ACL_COMMON] = 8192, ++ [GA_ANA_ACL_KEY_SEL] = 9204, ++ [GA_ANA_ACL_CNT_B] = 4096, ++ [GA_ANA_ACL_STICKY] = 10852, ++ [GA_ANA_AC_POL_POL_ALL_CFG] = 17504, ++ [GA_ANA_AC_POL_COMMON_BDLB] = 19464, ++ [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472, ++ [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788, ++ [GA_ANA_CL_PORT] = 65536, ++ [GA_ANA_CL_COMMON] = 87040, ++ [GA_ANA_L2_COMMON] = 561928, ++ [GA_ANA_L3_COMMON] = 370752, ++ [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580, ++ [GA_ASM_CFG] = 18304, ++ [GA_ASM_PFC_TIMER_CFG] = 15568, ++ [GA_ASM_LBK_WM_CFG] = 15596, ++ [GA_ASM_LBK_MISC_CFG] = 15608, ++ [GA_ASM_RAM_CTRL] = 15684, ++ [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864, ++ [GA_EACL_CNT_TBL] = 30720, ++ [GA_EACL_POL_CFG] = 38400, ++ [GA_EACL_ES2_STICKY] = 29072, ++ [GA_EACL_RAM_CTRL] = 29112, ++ [GA_GCB_SIO_CTRL] = 560, ++ [GA_HSCH_HSCH_DWRR] = 36480, ++ [GA_HSCH_HSCH_MISC] = 36608, ++ [GA_HSCH_HSCH_LEAK_LISTS] = 37256, ++ [GA_HSCH_SYSTEM] = 37384, ++ [GA_HSCH_MMGT] = 36260, ++ [GA_HSCH_TAS_CONFIG] = 37696, ++ [GA_PTP_PTP_CFG] = 512, ++ [GA_PTP_PTP_TOD_DOMAINS] = 528, ++ [GA_PTP_PHASE_DETECTOR_CTRL] = 628, ++ [GA_QSYS_CALCFG] = 2164, ++ [GA_QSYS_RAM_CTRL] = 2204, ++ [GA_REW_COMMON] = 98304, ++ [GA_REW_PORT] = 49152, ++ [GA_REW_VOE_PORT_LM_CNT] = 90112, ++ [GA_REW_RAM_CTRL] = 93992, ++ [GA_VOP_RAM_CTRL] = 16368, ++ [GA_XQS_SYSTEM] = 5744, ++ [GA_XQS_QLIMIT_SHR] = 6912, ++}; ++ ++const unsigned int lan969x_gcnt[GCNT_LAST] = { ++ [GC_ANA_AC_SRC] = 67, ++ [GC_ANA_AC_PGID] = 1054, ++ [GC_ANA_AC_TSN_SF_CFG] = 256, ++ [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35, ++ [GC_ANA_ACL_KEY_SEL] = 99, ++ [GC_ANA_ACL_CNT_A] = 1024, ++ [GC_ANA_ACL_CNT_B] = 1024, ++ [GC_ANA_AC_SDLB_LBGRP_TBL] = 5, ++ [GC_ANA_AC_SDLB_LBSET_TBL] = 496, ++ [GC_ANA_CL_PORT] = 35, ++ [GC_ANA_L2_ISDX_LIMIT] = 256, ++ [GC_ANA_L2_ISDX] = 1024, ++ [GC_ANA_L3_VLAN] = 4608, ++ [GC_ASM_DEV_STATISTICS] = 30, ++ [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68, ++ [GC_EACL_CNT_TBL] = 512, ++ [GC_GCB_SIO_CTRL] = 1, ++ [GC_HSCH_HSCH_CFG] = 1120, ++ [GC_HSCH_HSCH_DWRR] = 32, ++ [GC_PTP_PTP_PINS] = 8, ++ [GC_PTP_PHASE_DETECTOR_CTRL] = 8, ++ [GC_REW_PORT] = 35, ++ [GC_REW_VOE_PORT_LM_CNT] = 240, ++}; ++ ++const unsigned int lan969x_gsize[GSIZE_LAST] = { ++ [GW_ANA_AC_SRC] = 4, ++ [GW_ANA_L2_COMMON] = 712, ++ [GW_ASM_CFG] = 1092, ++ [GW_CPU_CPU_REGS] = 180, ++ [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12, ++ [GW_FDMA_FDMA] = 448, ++ [GW_GCB_CHIP_REGS] = 180, ++ [GW_HSCH_TAS_CONFIG] = 16, ++ [GW_PTP_PHASE_DETECTOR_CTRL] = 12, ++ [GW_QSYS_PAUSE_CFG] = 988, ++}; ++ ++const unsigned int lan969x_fpos[FPOS_LAST] = { ++ [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7, ++ [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6, ++ [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5, ++ [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4, ++ [FP_CPU_PROC_CTRL_VINITHI] = 3, ++ [FP_CPU_PROC_CTRL_CFGTE] = 2, ++ [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1, ++ [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0, ++ [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8, ++ [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5, ++ [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3, ++ [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5, ++ [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4, ++ [FP_FDMA_CH_CFG_CH_INJ_PORT] = 3, ++ [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27, ++ [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25, ++ [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24, ++ [FP_PTP_PHAD_CTRL_PHAD_ENA] = 5, ++ [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3, ++}; ++ ++const unsigned int lan969x_fsize[FSIZE_LAST] = { ++ [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30, ++ [FW_ANA_AC_SRC_CFG_PORT_MASK] = 30, ++ [FW_ANA_AC_PGID_CFG_PORT_MASK] = 30, ++ [FW_ANA_AC_TSN_SF_PORT_NUM] = 7, ++ [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8, ++ [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8, ++ [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8, ++ [FW_ANA_AC_PORT_SGE_CFG_MASK] = 17, ++ [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9, ++ [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3, ++ [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9, ++ [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9, ++ [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3, ++ [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9, ++ [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30, ++ [FW_ANA_L2_DLB_CFG_DLB_IDX] = 9, ++ [FW_ANA_L2_TSN_CFG_TSN_SFID] = 8, ++ [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30, ++ [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2, ++ [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7, ++ [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5, ++ [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14, ++ [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6, ++ [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11, ++ [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14, ++ [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6, ++ [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14, ++ [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13, ++ [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8, ++ [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13, ++ [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8, ++ [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8, ++ [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8, ++ [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3, ++ [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6, ++ [FW_QRES_RES_CFG_WM_HIGH] = 11, ++ [FW_QRES_RES_STAT_MAXUSE] = 19, ++ [FW_QRES_RES_STAT_CUR_INUSE] = 19, ++ [FW_QSYS_PAUSE_CFG_PAUSE_START] = 11, ++ [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11, ++ [FW_QSYS_ATOP_ATOP] = 11, ++ [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11, ++ [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6, ++ [FW_XQS_STAT_CFG_STAT_VIEW] = 10, ++ [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14, ++ [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14, ++ [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14, ++ [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14, ++}; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.c +@@ -4,7 +4,7 @@ + * Copyright (c) 2024 Microchip Technology Inc. + */ + +-/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. ++/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. + * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b + */ + +@@ -140,6 +140,7 @@ const unsigned int sparx5_gsize[GSIZE_LA + [GW_ANA_L2_COMMON] = 700, + [GW_ASM_CFG] = 1088, + [GW_CPU_CPU_REGS] = 204, ++ [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 8, + [GW_FDMA_FDMA] = 428, + [GW_GCB_CHIP_REGS] = 424, + [GW_HSCH_TAS_CONFIG] = 12, +@@ -157,6 +158,8 @@ const unsigned int sparx5_fpos[FPOS_LAST + [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 6, + [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 5, + [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 1, ++ [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 7, ++ [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 6, + [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 7, + [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 6, + [FP_FDMA_CH_CFG_CH_INJ_PORT] = 5, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_regs.h +@@ -4,7 +4,7 @@ + * Copyright (c) 2024 Microchip Technology Inc. + */ + +-/* This file is autogenerated by cml-utils 2024-09-24 14:02:24 +0200. ++/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. + * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b + */ + +@@ -151,6 +151,7 @@ enum sparx5_gsize_enum { + GW_ANA_L2_COMMON, + GW_ASM_CFG, + GW_CPU_CPU_REGS, ++ GW_DEV2G5_PHASE_DETECTOR_CTRL, + GW_FDMA_FDMA, + GW_GCB_CHIP_REGS, + GW_HSCH_TAS_CONFIG, +@@ -169,6 +170,8 @@ enum sparx5_fpos_enum { + FP_CPU_PROC_CTRL_CP15S_DISABLE, + FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, + FP_CPU_PROC_CTRL_L2_FLUSH_REQ, ++ FP_DEV2G5_PHAD_CTRL_PHAD_ENA, ++ FP_DEV2G5_PHAD_CTRL_PHAD_FAILED, + FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE, + FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, + FP_FDMA_CH_CFG_CH_INJ_PORT, diff --git a/target/linux/microchipsw/patches-6.12/0046-v6.13-net-lan969x-add-constants-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0046-v6.13-net-lan969x-add-constants-to-match-data.patch new file mode 100644 index 0000000000..eb9b597aa7 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0046-v6.13-net-lan969x-add-constants-to-match-data.patch @@ -0,0 +1,54 @@ +From df0ae12e09264cb432472c707ccb33ececc65935 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:27 +0200 +Subject: [PATCH 51/82] net: lan969x: add constants to match data + +Add the lan969x constants to match data. These are already used +throughout the Sparx5 code (introduced in earlier series [1]), so no +need to update any code use. + +[1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver-v2-0-d3290f581663@microchip.com/ + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-8-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/microchip/lan969x/lan969x.c | 21 +++++++++++++++++++ + 1 file changed, 21 insertions(+) + +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c +@@ -103,11 +103,32 @@ static const struct sparx5_regs lan969x_ + .fsize = lan969x_fsize, + }; + ++static const struct sparx5_consts lan969x_consts = { ++ .n_ports = 30, ++ .n_ports_all = 35, ++ .n_hsch_l1_elems = 32, ++ .n_hsch_queues = 4, ++ .n_lb_groups = 5, ++ .n_pgids = 1054, /* (1024 + n_ports) */ ++ .n_sio_clks = 1, ++ .n_own_upsids = 1, ++ .n_auto_cals = 4, ++ .n_filters = 256, ++ .n_gates = 256, ++ .n_sdlbs = 496, ++ .n_dsm_cal_taxis = 5, ++ .buf_size = 1572864, ++ .qres_max_prio_idx = 315, ++ .qres_max_colour_idx = 323, ++ .tod_pin = 4, ++}; ++ + const struct sparx5_match_data lan969x_desc = { + .iomap = lan969x_main_iomap, + .iomap_size = ARRAY_SIZE(lan969x_main_iomap), + .ioranges = 2, + .regs = &lan969x_regs, ++ .consts = &lan969x_consts, + }; + EXPORT_SYMBOL_GPL(lan969x_desc); + diff --git a/target/linux/microchipsw/patches-6.12/0047-v6.13-net-lan969x-add-lan969x-ops-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0047-v6.13-net-lan969x-add-lan969x-ops-to-match-data.patch new file mode 100644 index 0000000000..7cabd2ca39 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0047-v6.13-net-lan969x-add-lan969x-ops-to-match-data.patch @@ -0,0 +1,205 @@ +From 487d962349a2be3de1c3dc556b9d2a3529837f3a Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:28 +0200 +Subject: [PATCH 52/82] net: lan969x: add lan969x ops to match data + +Add a bunch of small lan969x ops in bulk. These ops are explained in +detail in a previous series [1]. + +[1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver-v2-8-d3290f581663@microchip.com/ + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-9-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/microchip/lan969x/lan969x.c | 122 ++++++++++++++++++ + .../net/ethernet/microchip/lan969x/lan969x.h | 28 ++++ + 2 files changed, 150 insertions(+) + +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c +@@ -6,6 +6,9 @@ + + #include "lan969x.h" + ++#define LAN969X_SDLB_GRP_CNT 5 ++#define LAN969X_HSCH_LEAK_GRP_CNT 4 ++ + static const struct sparx5_main_io_resource lan969x_main_iomap[] = { + { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ + { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ +@@ -92,6 +95,112 @@ static const struct sparx5_main_io_resou + { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ + }; + ++static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { ++ { 1000000000, 8192 / 2, 64 }, /* 1 G */ ++ { 500000000, 8192 / 2, 64 }, /* 500 M */ ++ { 100000000, 8192 / 4, 64 }, /* 100 M */ ++ { 50000000, 8192 / 4, 64 }, /* 50 M */ ++ { 5000000, 8192 / 8, 64 }, /* 10 M */ ++}; ++ ++static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = { ++ 655355, 1048568, 6553550, 10485680 ++}; ++ ++static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx) ++{ ++ return &lan969x_sdlb_groups[idx]; ++} ++ ++static u32 lan969x_get_hsch_max_group_rate(int grp) ++{ ++ return lan969x_hsch_max_group_rate[grp]; ++} ++ ++static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) ++{ ++ if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port)) ++ return port; ++ ++ /* 10G */ ++ switch (port) { ++ case 0: ++ return 12; ++ case 4: ++ return 13; ++ case 8: ++ return 14; ++ case 12: ++ return 0; ++ default: ++ return port; ++ } ++} ++ ++static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) ++{ ++ if (lan969x_port_is_5g(port)) { ++ switch (port) { ++ case 9: ++ return 0; ++ case 13: ++ return 1; ++ case 17: ++ return 2; ++ case 21: ++ return 3; ++ } ++ } ++ ++ if (lan969x_port_is_10g(port)) { ++ switch (port) { ++ case 0: ++ return 0; ++ case 4: ++ return 1; ++ case 8: ++ return 2; ++ case 12: ++ return 3; ++ case 16: ++ return 4; ++ case 20: ++ return 5; ++ case 24: ++ return 6; ++ case 25: ++ return 7; ++ case 26: ++ return 8; ++ case 27: ++ return 9; ++ } ++ } ++ ++ /* 2g5 port */ ++ return port; ++} ++ ++static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, ++ struct sparx5_port_config *conf) ++{ ++ u32 portno = port->portno; ++ u32 inst; ++ ++ if (port->conf.portmode == conf->portmode) ++ return 0; /* Nothing to do */ ++ ++ switch (conf->portmode) { ++ case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q' */ ++ inst = (portno - portno % 4) / 4; ++ spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); ++ break; ++ default: ++ break; ++ } ++ return 0; ++} ++ + static const struct sparx5_regs lan969x_regs = { + .tsize = lan969x_tsize, + .gaddr = lan969x_gaddr, +@@ -123,12 +232,25 @@ static const struct sparx5_consts lan969 + .tod_pin = 4, + }; + ++static const struct sparx5_ops lan969x_ops = { ++ .is_port_2g5 = &lan969x_port_is_2g5, ++ .is_port_5g = &lan969x_port_is_5g, ++ .is_port_10g = &lan969x_port_is_10g, ++ .is_port_25g = &lan969x_port_is_25g, ++ .get_port_dev_index = &lan969x_port_dev_mapping, ++ .get_port_dev_bit = &lan969x_get_dev_mode_bit, ++ .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, ++ .get_sdlb_group = &lan969x_get_sdlb_group, ++ .set_port_mux = &lan969x_port_mux_set, ++}; ++ + const struct sparx5_match_data lan969x_desc = { + .iomap = lan969x_main_iomap, + .iomap_size = ARRAY_SIZE(lan969x_main_iomap), + .ioranges = 2, + .regs = &lan969x_regs, + .consts = &lan969x_consts, ++ .ops = &lan969x_ops, + }; + EXPORT_SYMBOL_GPL(lan969x_desc); + +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.h ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h +@@ -23,4 +23,32 @@ extern const unsigned int lan969x_gsize[ + extern const unsigned int lan969x_fpos[FPOS_LAST]; + extern const unsigned int lan969x_fsize[FSIZE_LAST]; + ++static inline bool lan969x_port_is_2g5(int portno) ++{ ++ return portno == 1 || portno == 2 || portno == 3 || ++ portno == 5 || portno == 6 || portno == 7 || ++ portno == 10 || portno == 11 || portno == 14 || ++ portno == 15 || portno == 18 || portno == 19 || ++ portno == 22 || portno == 23; ++} ++ ++static inline bool lan969x_port_is_5g(int portno) ++{ ++ return portno == 9 || portno == 13 || portno == 17 || ++ portno == 21; ++} ++ ++static inline bool lan969x_port_is_10g(int portno) ++{ ++ return portno == 0 || portno == 4 || portno == 8 || ++ portno == 12 || portno == 16 || portno == 20 || ++ portno == 24 || portno == 25 || portno == 26 || ++ portno == 27; ++} ++ ++static inline bool lan969x_port_is_25g(int portno) ++{ ++ return false; ++} ++ + #endif diff --git a/target/linux/microchipsw/patches-6.12/0048-v6.13-net-lan969x-add-PTP-handler-function.patch b/target/linux/microchipsw/patches-6.12/0048-v6.13-net-lan969x-add-PTP-handler-function.patch new file mode 100644 index 0000000000..c93431f891 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0048-v6.13-net-lan969x-add-PTP-handler-function.patch @@ -0,0 +1,180 @@ +From a84b19eaf3ede71d2e4075dddffc71a529ccbdd9 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:29 +0200 +Subject: [PATCH 53/82] net: lan969x: add PTP handler function + +Add PTP IRQ handler for lan969x. This is required, as the PTP registers +are placed in two different targets on Sparx5 and lan969x. The +implementation is otherwise the same as on Sparx5. + +Also, expose sparx5_get_hwtimestamp() for use by lan969x. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-10-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/microchip/lan969x/lan969x.c | 90 +++++++++++++++++++ + .../ethernet/microchip/sparx5/sparx5_main.h | 5 ++ + .../ethernet/microchip/sparx5/sparx5_ptp.c | 9 +- + 3 files changed, 99 insertions(+), 5 deletions(-) + +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c +@@ -201,6 +201,95 @@ static int lan969x_port_mux_set(struct s + return 0; + } + ++static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args) ++{ ++ int budget = SPARX5_MAX_PTP_ID; ++ struct sparx5 *sparx5 = args; ++ ++ while (budget--) { ++ struct sk_buff *skb, *skb_tmp, *skb_match = NULL; ++ struct skb_shared_hwtstamps shhwtstamps; ++ struct sparx5_port *port; ++ struct timespec64 ts; ++ unsigned long flags; ++ u32 val, id, txport; ++ u32 delay; ++ ++ val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); ++ ++ /* Check if a timestamp can be retrieved */ ++ if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) ++ break; ++ ++ WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL); ++ ++ if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX)) ++ continue; ++ ++ /* Retrieve the ts Tx port */ ++ txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val); ++ ++ /* Retrieve its associated skb */ ++ port = sparx5->ports[txport]; ++ ++ /* Retrieve the delay */ ++ delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); ++ delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay); ++ ++ /* Get next timestamp from fifo, which needs to be the ++ * rx timestamp which represents the id of the frame ++ */ ++ spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), ++ PTP_TWOSTEP_CTRL_PTP_NXT, ++ sparx5, PTP_TWOSTEP_CTRL); ++ ++ val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); ++ ++ /* Check if a timestamp can be retrieved */ ++ if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) ++ break; ++ ++ /* Read RX timestamping to get the ID */ ++ id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); ++ id <<= 8; ++ id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS); ++ ++ spin_lock_irqsave(&port->tx_skbs.lock, flags); ++ skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { ++ if (SPARX5_SKB_CB(skb)->ts_id != id) ++ continue; ++ ++ __skb_unlink(skb, &port->tx_skbs); ++ skb_match = skb; ++ break; ++ } ++ spin_unlock_irqrestore(&port->tx_skbs.lock, flags); ++ ++ /* Next ts */ ++ spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), ++ PTP_TWOSTEP_CTRL_PTP_NXT, ++ sparx5, PTP_TWOSTEP_CTRL); ++ ++ if (WARN_ON(!skb_match)) ++ continue; ++ ++ spin_lock(&sparx5->ptp_ts_id_lock); ++ sparx5->ptp_skbs--; ++ spin_unlock(&sparx5->ptp_ts_id_lock); ++ ++ /* Get the h/w timestamp */ ++ sparx5_get_hwtimestamp(sparx5, &ts, delay); ++ ++ /* Set the timestamp in the skb */ ++ shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); ++ skb_tstamp_tx(skb_match, &shhwtstamps); ++ ++ dev_kfree_skb_any(skb_match); ++ } ++ ++ return IRQ_HANDLED; ++} ++ + static const struct sparx5_regs lan969x_regs = { + .tsize = lan969x_tsize, + .gaddr = lan969x_gaddr, +@@ -242,6 +331,7 @@ static const struct sparx5_ops lan969x_o + .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, + .get_sdlb_group = &lan969x_get_sdlb_group, + .set_port_mux = &lan969x_port_mux_set, ++ .ptp_irq_handler = &lan969x_ptp_irq_handler, + }; + + const struct sparx5_match_data lan969x_desc = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -114,6 +114,8 @@ enum sparx5_vlan_port_type { + #define SPX5_DSM_CAL_LEN 64 + #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 + ++#define SPARX5_MAX_PTP_ID 512 ++ + struct sparx5; + + struct sparx5_calendar_data { +@@ -499,6 +501,9 @@ void sparx5_ptp_txtstamp_release(struct + struct sk_buff *skb); + irqreturn_t sparx5_ptp_irq_handler(int irq, void *args); + int sparx5_ptp_gettime64(struct ptp_clock_info *ptp, struct timespec64 *ts); ++void sparx5_get_hwtimestamp(struct sparx5 *sparx5, ++ struct timespec64 *ts, ++ u32 nsec); + + /* sparx5_vcap_impl.c */ + int sparx5_vcap_init(struct sparx5 *sparx5); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c +@@ -11,8 +11,6 @@ + #include "sparx5_main_regs.h" + #include "sparx5_main.h" + +-#define SPARX5_MAX_PTP_ID 512 +- + #define TOD_ACC_PIN 0x4 + + enum { +@@ -275,9 +273,9 @@ void sparx5_ptp_txtstamp_release(struct + spin_unlock_irqrestore(&sparx5->ptp_ts_id_lock, flags); + } + +-static void sparx5_get_hwtimestamp(struct sparx5 *sparx5, +- struct timespec64 *ts, +- u32 nsec) ++void sparx5_get_hwtimestamp(struct sparx5 *sparx5, ++ struct timespec64 *ts, ++ u32 nsec) + { + /* Read current PTP time to get seconds */ + const struct sparx5_consts *consts = sparx5->data->consts; +@@ -305,6 +303,7 @@ static void sparx5_get_hwtimestamp(struc + + spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); + } ++EXPORT_SYMBOL_GPL(sparx5_get_hwtimestamp); + + irqreturn_t sparx5_ptp_irq_handler(int irq, void *args) + { diff --git a/target/linux/microchipsw/patches-6.12/0049-v6.13-net-lan969x-add-function-for-calculating-the-DSM-cal.patch b/target/linux/microchipsw/patches-6.12/0049-v6.13-net-lan969x-add-function-for-calculating-the-DSM-cal.patch new file mode 100644 index 0000000000..ebfc1fc4e6 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0049-v6.13-net-lan969x-add-function-for-calculating-the-DSM-cal.patch @@ -0,0 +1,359 @@ +From bb44231712c296fa992cf7e0f7206b0798a1b84c Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:30 +0200 +Subject: [PATCH 54/82] net: lan969x: add function for calculating the DSM + calendar + +Lan969x has support for RedBox / HSR / PRP (not implemented yet). In +order to accommodate for this in the future, we need to give lan969x it's +own function for calculating the DSM calendar. + +The function calculates the calendar for each taxi bus. The calendar is +used for bandwidth allocation towards the ports attached to the taxi +bus. A calendar configuration consists of up-to 64 slots, which may be +allocated to ports or left unused. Each slot accounts for 1 clock cycle. + +Also expose sparx5_cal_speed_to_value(), sparx5_get_port_cal_speed, +sparx5_cal_bw and SPX5_DSM_CAL_EMPTY for use by lan969x. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-11-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/microchip/lan969x/Makefile | 2 +- + .../net/ethernet/microchip/lan969x/lan969x.c | 1 + + .../net/ethernet/microchip/lan969x/lan969x.h | 3 + + .../microchip/lan969x/lan969x_calendar.c | 191 ++++++++++++++++++ + .../microchip/sparx5/sparx5_calendar.c | 20 +- + .../ethernet/microchip/sparx5/sparx5_main.h | 15 ++ + 6 files changed, 215 insertions(+), 17 deletions(-) + create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c + +--- a/drivers/net/ethernet/microchip/lan969x/Makefile ++++ b/drivers/net/ethernet/microchip/lan969x/Makefile +@@ -5,7 +5,7 @@ + + obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o + +-lan969x-switch-y := lan969x_regs.o lan969x.o ++lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o + + # Provide include files + ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c +@@ -332,6 +332,7 @@ static const struct sparx5_ops lan969x_o + .get_sdlb_group = &lan969x_get_sdlb_group, + .set_port_mux = &lan969x_port_mux_set, + .ptp_irq_handler = &lan969x_ptp_irq_handler, ++ .dsm_calendar_calc = &lan969x_dsm_calendar_calc, + }; + + const struct sparx5_match_data lan969x_desc = { +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.h ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h +@@ -51,4 +51,7 @@ static inline bool lan969x_port_is_25g(i + return false; + } + ++/* lan969x_calendar.c */ ++int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, ++ struct sparx5_calendar_data *data); + #endif +--- /dev/null ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c +@@ -0,0 +1,191 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. ++ */ ++ ++#include "lan969x.h" ++ ++#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10 ++#define LAN969X_DSM_CAL_TAXIS 5 ++ ++enum lan969x_dsm_cal_dev { ++ DSM_CAL_DEV_2G5, ++ DSM_CAL_DEV_5G, ++ DSM_CAL_DEV_10G, ++ DSM_CAL_DEV_OTHER, /* 1G or less */ ++ DSM_CAL_DEV_MAX ++}; ++ ++/* Each entry in the following struct defines properties for a given speed ++ * (10G, 5G, 2.5G, or 1G or less). ++ */ ++struct lan969x_dsm_cal_dev_speed { ++ /* Number of devices that requires this speed. */ ++ u32 n_devs; ++ ++ /* Array of devices that requires this speed. */ ++ u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI]; ++ ++ /* Number of slots required for one device running this speed. */ ++ u32 n_slots; ++ ++ /* Gap between two slots for one device running this speed. */ ++ u32 gap; ++}; ++ ++static u32 ++lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = { ++ { 0, 4, 1, 2, 3, 5, 6, 7, 28, 29 }, ++ { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 }, ++ { 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 }, ++ { 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 }, ++ { 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 } ++}; ++ ++static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx) ++{ ++ if (*cal_idx >= cal_len) ++ return -EINVAL; ++ ++ do { ++ if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY) ++ return 0; ++ ++ (*cal_idx)++; ++ } while (*cal_idx < cal_len); ++ ++ return -ENOENT; ++} ++ ++static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) ++{ ++ return (speed == 10000 ? DSM_CAL_DEV_10G : ++ speed == 5000 ? DSM_CAL_DEV_5G : ++ speed == 2500 ? DSM_CAL_DEV_2G5 : ++ DSM_CAL_DEV_OTHER); ++} ++ ++static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev) ++{ ++ return (dev == DSM_CAL_DEV_10G ? 10000 : ++ dev == DSM_CAL_DEV_5G ? 5000 : ++ dev == DSM_CAL_DEV_2G5 ? 2500 : ++ 1000); ++} ++ ++int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, ++ struct sparx5_calendar_data *data) ++{ ++ struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {}; ++ u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw = 0; ++ struct lan969x_dsm_cal_dev_speed *speed; ++ int err; ++ ++ /* Maximum bandwidth for this taxi */ ++ taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); ++ ++ memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], ++ LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32)); ++ ++ for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { ++ u32 portno = data->taxi_ports[i]; ++ enum sparx5_cal_bw bw; ++ ++ bw = sparx5_get_port_cal_speed(sparx5, portno); ++ ++ if (portno < sparx5->data->consts->n_ports_all) ++ data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw); ++ else ++ data->taxi_speeds[i] = 0; ++ } ++ ++ /* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the ++ * this taxi map. ++ */ ++ for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { ++ u32 taxi_speed = data->taxi_speeds[i]; ++ enum lan969x_dsm_cal_dev dev; ++ ++ if (taxi_speed == 0) ++ continue; ++ ++ required_bw += taxi_speed; ++ ++ dev = lan969x_dsm_cal_get_dev(taxi_speed); ++ speed = &dev_speeds[dev]; ++ speed->devs[speed->n_devs++] = i; ++ n_devs++; ++ } ++ ++ if (required_bw > taxi_bw) { ++ pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u", ++ required_bw, taxi_bw); ++ return -EINVAL; ++ } ++ ++ if (n_devs == 0) { ++ data->schedule[0] = SPX5_DSM_CAL_EMPTY; ++ return 0; ++ } ++ ++ cal_len = n_devs; ++ ++ /* Search for a calendar length that fits all active devices. */ ++ while (cal_len < SPX5_DSM_CAL_LEN) { ++ u32 bw_per_slot = taxi_bw / cal_len; ++ ++ n_slots = 0; ++ ++ for (int i = 0; i < DSM_CAL_DEV_MAX; i++) { ++ speed = &dev_speeds[i]; ++ ++ if (speed->n_devs == 0) ++ continue; ++ ++ required_bw = lan969x_dsm_cal_get_speed(i); ++ speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot); ++ ++ if (speed->n_slots) ++ speed->gap = DIV_ROUND_UP(cal_len, ++ speed->n_slots); ++ else ++ speed->gap = 0; ++ ++ n_slots += speed->n_slots * speed->n_devs; ++ } ++ ++ if (n_slots <= cal_len) ++ break; /* Found a suitable calendar length. */ ++ ++ /* Not good enough yet. */ ++ cal_len = n_slots; ++ } ++ ++ if (cal_len > SPX5_DSM_CAL_LEN) { ++ pr_err("Invalid length: %u for taxi: %u", cal_len, taxi); ++ return -EINVAL; ++ } ++ ++ for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++) ++ data->schedule[i] = SPX5_DSM_CAL_EMPTY; ++ ++ /* Place the remaining devices */ ++ for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) { ++ speed = &dev_speeds[i]; ++ for (u32 dev = 0; dev < speed->n_devs; dev++) { ++ u32 idx = 0; ++ ++ for (n_slots = 0; n_slots < speed->n_slots; n_slots++) { ++ err = lan969x_dsm_cal_idx_get(data->schedule, ++ cal_len, &idx); ++ if (err) ++ return err; ++ data->schedule[idx] = speed->devs[dev]; ++ idx += speed->gap; ++ } ++ } ++ } ++ ++ return 0; ++} +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +@@ -15,7 +15,6 @@ + #define SPX5_CALBITS_PER_PORT 3 /* Bit per port in calendar register */ + + /* DSM calendar information */ +-#define SPX5_DSM_CAL_EMPTY 0xFFFF + #define SPX5_DSM_CAL_TAXIS 8 + #define SPX5_DSM_CAL_BW_LOSS 553 + +@@ -74,18 +73,6 @@ static u32 sparx5_target_bandwidth(struc + } + } + +-/* This is used in calendar configuration */ +-enum sparx5_cal_bw { +- SPX5_CAL_SPEED_NONE = 0, +- SPX5_CAL_SPEED_1G = 1, +- SPX5_CAL_SPEED_2G5 = 2, +- SPX5_CAL_SPEED_5G = 3, +- SPX5_CAL_SPEED_10G = 4, +- SPX5_CAL_SPEED_25G = 5, +- SPX5_CAL_SPEED_0G5 = 6, +- SPX5_CAL_SPEED_12G5 = 7 +-}; +- + static u32 sparx5_clk_to_bandwidth(enum sparx5_core_clockfreq cclock) + { + switch (cclock) { +@@ -98,7 +85,7 @@ static u32 sparx5_clk_to_bandwidth(enum + return 0; + } + +-static u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed) ++u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed) + { + switch (speed) { + case SPX5_CAL_SPEED_1G: return 1000; +@@ -111,6 +98,7 @@ static u32 sparx5_cal_speed_to_value(enu + default: return 0; + } + } ++EXPORT_SYMBOL_GPL(sparx5_cal_speed_to_value); + + static u32 sparx5_bandwidth_to_calendar(u32 bw) + { +@@ -128,8 +116,7 @@ static u32 sparx5_bandwidth_to_calendar( + } + } + +-static enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, +- u32 portno) ++enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno) + { + struct sparx5_port *port; + +@@ -163,6 +150,7 @@ static enum sparx5_cal_bw sparx5_get_por + return SPX5_CAL_SPEED_NONE; + return sparx5_bandwidth_to_calendar(port->conf.bandwidth); + } ++EXPORT_SYMBOL_GPL(sparx5_get_port_cal_speed); + + /* Auto configure the QSYS calendar based on port configuration */ + int sparx5_config_auto_calendar(struct sparx5 *sparx5) +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -63,6 +63,18 @@ enum sparx5_vlan_port_type { + SPX5_VLAN_PORT_TYPE_S_CUSTOM /* S-port using custom type */ + }; + ++/* This is used in calendar configuration */ ++enum sparx5_cal_bw { ++ SPX5_CAL_SPEED_NONE = 0, ++ SPX5_CAL_SPEED_1G = 1, ++ SPX5_CAL_SPEED_2G5 = 2, ++ SPX5_CAL_SPEED_5G = 3, ++ SPX5_CAL_SPEED_10G = 4, ++ SPX5_CAL_SPEED_25G = 5, ++ SPX5_CAL_SPEED_0G5 = 6, ++ SPX5_CAL_SPEED_12G5 = 7 ++}; ++ + #define SPX5_PORTS 65 + #define SPX5_PORTS_ALL 70 /* Total number of ports */ + +@@ -113,6 +125,7 @@ enum sparx5_vlan_port_type { + + #define SPX5_DSM_CAL_LEN 64 + #define SPX5_DSM_CAL_MAX_DEVS_PER_TAXI 13 ++#define SPX5_DSM_CAL_EMPTY 0xFFFF + + #define SPARX5_MAX_PTP_ID 512 + +@@ -454,6 +467,8 @@ int sparx5_config_auto_calendar(struct s + int sparx5_config_dsm_calendar(struct sparx5 *sparx5); + int sparx5_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, + struct sparx5_calendar_data *data); ++u32 sparx5_cal_speed_to_value(enum sparx5_cal_bw speed); ++enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno); + + + /* sparx5_ethtool.c */ diff --git a/target/linux/microchipsw/patches-6.12/0050-v6.13-net-sparx5-use-is_sparx5-macro-throughout.patch b/target/linux/microchipsw/patches-6.12/0050-v6.13-net-sparx5-use-is_sparx5-macro-throughout.patch new file mode 100644 index 0000000000..ab2c53a165 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0050-v6.13-net-sparx5-use-is_sparx5-macro-throughout.patch @@ -0,0 +1,306 @@ +From ad3d33e6ac44359d2414f11bcaf1ebb8ba64346d Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:31 +0200 +Subject: [PATCH 55/82] net: sparx5: use is_sparx5() macro throughout + +Use the is_sparx5() macro (introduced in earlier series [1]), in places +where we need to handle things a bit differently on lan969x. + +These places are: + + - in sparx5_dsm_calendar_update() we need to switch the calendar + from a to b on lan969x. + + - in sparx5_start() we need to make sure the HSCH_SYS_CLK_PER + register is only touched on Sparx5. + + - in sparx5_start() we need to disable VCAP and FDMA for lan969x + (will come in later series). + + - in sparx5_mirror_port_get() we must make sure the + ANA_AC_PROBE_PORT_CFG1 register is only read on Sparx5. + + - sparx5_netdev.c and sparx5_packet.c we need to use different IFH + (Internal Frame Header) offsets for lan969x. + + - in sparx5_port_fifo_sz() we must bail out on lan969x. + + - in sparx5_port_config_low_set() we must configure the phase + detection registers. + + - in sparx5_port_config() and sparx5_port_init() we must do some + additional configuration of the port devices. + + - in sparx5_dwrr_conf_set() we must derive the scheduling layer + +[1] https://lore.kernel.org/netdev/20241004-b4-sparx5-lan969x-switch-driver-v2-8-d3290f581663@microchip.com/ + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-12-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../microchip/sparx5/sparx5_calendar.c | 21 ++++++++- + .../ethernet/microchip/sparx5/sparx5_main.c | 21 +++++---- + .../ethernet/microchip/sparx5/sparx5_mirror.c | 10 +++- + .../ethernet/microchip/sparx5/sparx5_netdev.c | 17 ++++--- + .../ethernet/microchip/sparx5/sparx5_packet.c | 3 +- + .../ethernet/microchip/sparx5/sparx5_port.c | 46 +++++++++++++++++++ + .../ethernet/microchip/sparx5/sparx5_qos.c | 3 +- + 7 files changed, 99 insertions(+), 22 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +@@ -531,8 +531,18 @@ check_err: + static int sparx5_dsm_calendar_update(struct sparx5 *sparx5, u32 taxi, + struct sparx5_calendar_data *data) + { +- u32 idx; +- u32 cal_len = sparx5_dsm_cal_len(data->schedule), len; ++ u32 cal_len = sparx5_dsm_cal_len(data->schedule), len, idx; ++ ++ if (!is_sparx5(sparx5)) { ++ u32 val, act; ++ ++ val = spx5_rd(sparx5, DSM_TAXI_CAL_CFG(taxi)); ++ act = DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(val); ++ ++ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!act), ++ DSM_TAXI_CAL_CFG_CAL_PGM_SEL, ++ sparx5, DSM_TAXI_CAL_CFG(taxi)); ++ } + + spx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1), + DSM_TAXI_CAL_CFG_CAL_PGM_ENA, +@@ -556,6 +566,13 @@ static int sparx5_dsm_calendar_update(st + DSM_TAXI_CAL_CFG(taxi))); + if (len != cal_len - 1) + goto update_err; ++ ++ if (!is_sparx5(sparx5)) { ++ spx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1), ++ DSM_TAXI_CAL_CFG_CAL_SWITCH, ++ sparx5, DSM_TAXI_CAL_CFG(taxi)); ++ } ++ + return 0; + update_err: + dev_err(sparx5->dev, "Incorrect calendar length: %u\n", len); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -538,10 +538,11 @@ static int sparx5_init_coreclock(struct + sparx5->coreclock = freq; + clk_period = sparx5_clk_period(freq); + +- spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), +- HSCH_SYS_CLK_PER_100PS, +- sparx5, +- HSCH_SYS_CLK_PER); ++ if (is_sparx5(sparx5)) ++ spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100), ++ HSCH_SYS_CLK_PER_100PS, ++ sparx5, ++ HSCH_SYS_CLK_PER); + + spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100), + ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, +@@ -731,15 +732,17 @@ static int sparx5_start(struct sparx5 *s + if (err) + return err; + +- err = sparx5_vcap_init(sparx5); +- if (err) { +- sparx5_unregister_notifier_blocks(sparx5); +- return err; ++ if (is_sparx5(sparx5)) { ++ err = sparx5_vcap_init(sparx5); ++ if (err) { ++ sparx5_unregister_notifier_blocks(sparx5); ++ return err; ++ } + } + + /* Start Frame DMA with fallback to register based INJ/XTR */ + err = -ENXIO; +- if (sparx5->fdma_irq >= 0) { ++ if (sparx5->fdma_irq >= 0 && is_sparx5(sparx5)) { + if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) + err = devm_request_irq(sparx5->dev, + sparx5->fdma_irq, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c +@@ -24,8 +24,14 @@ static u32 sparx5_mirror_to_dir(bool ing + /* Get ports belonging to this mirror */ + static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx) + { +- return (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32 | +- spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); ++ u64 val; ++ ++ val = spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); ++ ++ if (is_sparx5(sparx5)) ++ val |= (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32; ++ ++ return val; + } + + /* Add port to mirror (only front ports) */ +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_netdev.c +@@ -64,16 +64,16 @@ void sparx5_set_port_ifh(struct sparx5 * + /* MISC.CPU_MASK/DPORT = Destination port */ + ifh_encode_bitfield(ifh_hdr, portno, 29, 8); + /* MISC.PIPELINE_PT */ +- ifh_encode_bitfield(ifh_hdr, 16, 37, 5); ++ ifh_encode_bitfield(ifh_hdr, is_sparx5(sparx5) ? 16 : 17, 37, 5); + /* MISC.PIPELINE_ACT */ + ifh_encode_bitfield(ifh_hdr, 1, 42, 3); + /* FWD.SRC_PORT = CPU */ + ifh_encode_bitfield(ifh_hdr, sparx5_get_pgid(sparx5, SPX5_PORT_CPU_0), +- 46, 7); ++ 46, is_sparx5(sparx5) ? 7 : 6); + /* FWD.SFLOW_ID (disable SFlow sampling) */ +- ifh_encode_bitfield(ifh_hdr, 124, 57, 7); ++ ifh_encode_bitfield(ifh_hdr, 124, is_sparx5(sparx5) ? 57 : 56, 7); + /* FWD.UPDATE_FCS = Enable. Enforce update of FCS. */ +- ifh_encode_bitfield(ifh_hdr, 1, 67, 1); ++ ifh_encode_bitfield(ifh_hdr, 1, is_sparx5(sparx5) ? 67 : 66, 1); + } + + void sparx5_set_port_ifh_rew_op(void *ifh_hdr, u32 rew_op) +@@ -84,19 +84,22 @@ void sparx5_set_port_ifh_rew_op(void *if + void sparx5_set_port_ifh_pdu_type(struct sparx5 *sparx5, void *ifh_hdr, + u32 pdu_type) + { +- ifh_encode_bitfield(ifh_hdr, pdu_type, 191, 4); ++ ifh_encode_bitfield(ifh_hdr, pdu_type, is_sparx5(sparx5) ? 191 : 190, ++ 4); + } + + void sparx5_set_port_ifh_pdu_w16_offset(struct sparx5 *sparx5, void *ifh_hdr, + u32 pdu_w16_offset) + { +- ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, 195, 6); ++ ifh_encode_bitfield(ifh_hdr, pdu_w16_offset, ++ is_sparx5(sparx5) ? 195 : 194, 6); + } + + void sparx5_set_port_ifh_timestamp(struct sparx5 *sparx5, void *ifh_hdr, + u64 timestamp) + { +- ifh_encode_bitfield(ifh_hdr, timestamp, 232, 40); ++ ifh_encode_bitfield(ifh_hdr, timestamp, 232, ++ is_sparx5(sparx5) ? 40 : 38); + } + + static int sparx5_port_open(struct net_device *ndev) +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +@@ -43,7 +43,8 @@ void sparx5_ifh_parse(struct sparx5 *spa + ((u32)xtr_hdr[29] << 8) | + ((u32)xtr_hdr[30] << 0); + fwd = (fwd >> 5); +- info->src_port = FIELD_GET(GENMASK(7, 1), fwd); ++ info->src_port = spx5_field_get(GENMASK(is_sparx5(sparx5) ? 7 : 6, 1), ++ fwd); + + /* + * Bit 270-271 are occasionally unexpectedly set by the hardware, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -476,6 +476,9 @@ static int sparx5_port_fifo_sz(struct sp + u32 mac_width = 8; + u32 addition = 0; + ++ if (!is_sparx5(sparx5)) ++ return 0; ++ + switch (speed) { + case SPEED_25000: + return 0; +@@ -921,6 +924,20 @@ static int sparx5_port_config_low_set(st + sparx5, + DEV2G5_DEV_RST_CTRL(port->portno)); + ++ /* Enable PHAD_CTRL for better timestamping */ ++ if (!is_sparx5(sparx5)) { ++ for (int i = 0; i < 2; ++i) { ++ /* Divide the port clock by three for the two ++ * phase detection registers. ++ */ ++ spx5_rmw(DEV2G5_PHAD_CTRL_DIV_CFG_SET(3) | ++ DEV2G5_PHAD_CTRL_PHAD_ENA_SET(1), ++ DEV2G5_PHAD_CTRL_DIV_CFG | ++ DEV2G5_PHAD_CTRL_PHAD_ENA, ++ sparx5, DEV2G5_PHAD_CTRL(port->portno, i)); ++ } ++ } ++ + return 0; + } + +@@ -978,6 +995,7 @@ int sparx5_port_config(struct sparx5 *sp + struct sparx5_port_config *conf) + { + bool high_speed_dev = sparx5_is_baser(conf->portmode); ++ const struct sparx5_ops *ops = sparx5->data->ops; + int err, urgency, stop_wm; + + err = sparx5_port_verify_speed(sparx5, port, conf); +@@ -993,6 +1011,13 @@ int sparx5_port_config(struct sparx5 *sp + if (err) + return err; + ++ if (!is_sparx5(sparx5) && ops->is_port_10g(port->portno) && ++ conf->speed < SPEED_10000) ++ spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1), ++ DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, ++ sparx5, ++ DSM_DEV_TX_STOP_WM_CFG(port->portno)); ++ + /* Set the DSM stop watermark */ + stop_wm = sparx5_port_fifo_sz(sparx5, port->portno, conf->speed); + spx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(stop_wm), +@@ -1144,6 +1169,27 @@ int sparx5_port_init(struct sparx5 *spar + DEV25G_PCS25G_SD_CFG(pix)); + } + ++ if (!is_sparx5(sparx5)) { ++ void __iomem *inst; ++ u32 dev, tinst; ++ ++ if (ops->is_port_10g(port->portno)) { ++ dev = sparx5_to_high_dev(sparx5, port->portno); ++ tinst = sparx5_port_dev_index(sparx5, port->portno); ++ inst = spx5_inst_get(sparx5, dev, tinst); ++ ++ spx5_inst_wr(5, inst, ++ DEV10G_PTP_STAMPER_CFG(port->portno)); ++ } else if (ops->is_port_5g(port->portno)) { ++ dev = sparx5_to_high_dev(sparx5, port->portno); ++ tinst = sparx5_port_dev_index(sparx5, port->portno); ++ inst = spx5_inst_get(sparx5, dev, tinst); ++ ++ spx5_inst_wr(5, inst, ++ DEV5G_PTP_STAMPER_CFG(port->portno)); ++ } ++ } ++ + return 0; + } + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_qos.c +@@ -367,9 +367,10 @@ static u32 sparx5_weight_to_hw_cost(u32 + static int sparx5_dwrr_conf_set(struct sparx5_port *port, + struct sparx5_dwrr *dwrr) + { ++ u32 layer = is_sparx5(port->sparx5) ? 2 : 1; + int i; + +- spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(2) | ++ spx5_rmw(HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(layer) | + HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(port->portno), + HSCH_HSCH_CFG_CFG_HSCH_LAYER | HSCH_HSCH_CFG_CFG_CFG_SE_IDX, + port->sparx5, HSCH_HSCH_CFG_CFG); diff --git a/target/linux/microchipsw/patches-6.12/0051-v6.13-net-sparx5-add-compatible-string-for-lan969x.patch b/target/linux/microchipsw/patches-6.12/0051-v6.13-net-sparx5-add-compatible-string-for-lan969x.patch new file mode 100644 index 0000000000..a8416226fd --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0051-v6.13-net-sparx5-add-compatible-string-for-lan969x.patch @@ -0,0 +1,38 @@ +From a02276501dbc5ae015e56aad0176e9f40703aac9 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:33 +0200 +Subject: [PATCH 56/82] net: sparx5: add compatible string for lan969x + +Add lan9691-switch compatible string to mchp_sparx5_match. Guard it with +IS_ENABLED(CONFIG_LAN969X_SWITCH) to make sure Sparx5 can be compiled on +its own. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-14-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -24,6 +24,8 @@ + #include + #include + ++#include "../lan969x/lan969x.h" /* for lan969x match data */ ++ + #include "sparx5_main_regs.h" + #include "sparx5_main.h" + #include "sparx5_port.h" +@@ -1049,6 +1051,9 @@ static const struct sparx5_match_data sp + + static const struct of_device_id mchp_sparx5_match[] = { + { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, ++#if IS_ENABLED(CONFIG_LAN969X_SWITCH) ++ { .compatible = "microchip,lan9691-switch", .data = &lan969x_desc }, ++#endif + { } + }; + MODULE_DEVICE_TABLE(of, mchp_sparx5_match); diff --git a/target/linux/microchipsw/patches-6.12/0052-v6.13-net-sparx5-add-feature-support.patch b/target/linux/microchipsw/patches-6.12/0052-v6.13-net-sparx5-add-feature-support.patch new file mode 100644 index 0000000000..4601a14948 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0052-v6.13-net-sparx5-add-feature-support.patch @@ -0,0 +1,130 @@ +From 77520fd6b40f129f2b8d6d81d27bd311d30c3250 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 24 Oct 2024 00:01:34 +0200 +Subject: [PATCH 57/82] net: sparx5: add feature support + +Lan969x supports a number of different features, depending on the +target. Add new field sparx5->features and initialize the features based +on the target. Also add the function sparx5_has_feature() and use it +throughout. For now, we only need to handle features: PSFP and PTP - +more will come in the future. + +[1] https://www.microchip.com/en-us/product/lan9698 + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241024-sparx5-lan969x-switch-driver-2-v2-15-a0b5fae88a0f@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../ethernet/microchip/sparx5/sparx5_main.c | 40 ++++++++++++++++++- + .../ethernet/microchip/sparx5/sparx5_main.h | 7 ++++ + .../microchip/sparx5/sparx5_tc_flower.c | 5 +++ + 3 files changed, 51 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -229,6 +229,40 @@ bool is_sparx5(struct sparx5 *sparx5) + } + } + ++static void sparx5_init_features(struct sparx5 *sparx5) ++{ ++ switch (sparx5->target_ct) { ++ case SPX5_TARGET_CT_7546: ++ case SPX5_TARGET_CT_7549: ++ case SPX5_TARGET_CT_7552: ++ case SPX5_TARGET_CT_7556: ++ case SPX5_TARGET_CT_7558: ++ case SPX5_TARGET_CT_7546TSN: ++ case SPX5_TARGET_CT_7549TSN: ++ case SPX5_TARGET_CT_7552TSN: ++ case SPX5_TARGET_CT_7556TSN: ++ case SPX5_TARGET_CT_7558TSN: ++ case SPX5_TARGET_CT_LAN9691VAO: ++ case SPX5_TARGET_CT_LAN9694TSN: ++ case SPX5_TARGET_CT_LAN9694RED: ++ case SPX5_TARGET_CT_LAN9692VAO: ++ case SPX5_TARGET_CT_LAN9696TSN: ++ case SPX5_TARGET_CT_LAN9696RED: ++ case SPX5_TARGET_CT_LAN9693VAO: ++ case SPX5_TARGET_CT_LAN9698TSN: ++ case SPX5_TARGET_CT_LAN9698RED: ++ sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); ++ break; ++ default: ++ break; ++ } ++} ++ ++bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature) ++{ ++ return sparx5->features & feature; ++} ++ + static int sparx5_create_targets(struct sparx5 *sparx5) + { + const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; +@@ -770,7 +804,8 @@ static int sparx5_start(struct sparx5 *s + sparx5->xtr_irq = -ENXIO; + } + +- if (sparx5->ptp_irq >= 0) { ++ if (sparx5->ptp_irq >= 0 && ++ sparx5_has_feature(sparx5, SPX5_FEATURE_PTP)) { + err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, + NULL, ops->ptp_irq_handler, + IRQF_ONESHOT, "sparx5-ptp", +@@ -914,6 +949,9 @@ static int mchp_sparx5_probe(struct plat + sparx5->target_ct = (enum spx5_target_chiptype) + GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); + ++ /* Initialize the features based on the target */ ++ sparx5_init_features(sparx5); ++ + /* Initialize Switchcore and internal RAMs */ + err = sparx5_init_switchcore(sparx5); + if (err) { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -75,6 +75,11 @@ enum sparx5_cal_bw { + SPX5_CAL_SPEED_12G5 = 7 + }; + ++enum sparx5_feature { ++ SPX5_FEATURE_PSFP = BIT(0), ++ SPX5_FEATURE_PTP = BIT(1), ++}; ++ + #define SPX5_PORTS 65 + #define SPX5_PORTS_ALL 70 /* Total number of ports */ + +@@ -337,6 +342,7 @@ struct sparx5 { + struct device *dev; + u32 chip_id; + enum spx5_target_chiptype target_ct; ++ u32 features; + void __iomem *regs[NUM_TARGETS]; + int port_count; + struct mutex lock; /* MAC reg lock */ +@@ -404,6 +410,7 @@ struct sparx5 { + + /* sparx5_main.c */ + bool is_sparx5(struct sparx5 *sparx5); ++bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature); + + /* sparx5_switchdev.c */ + int sparx5_register_notifier_blocks(struct sparx5 *sparx5); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_tc_flower.c +@@ -1284,6 +1284,11 @@ static int sparx5_tc_flower_replace(stru + + /* Setup PSFP */ + if (tc_sg_idx >= 0 || tc_pol_idx >= 0) { ++ if (!sparx5_has_feature(sparx5, SPX5_FEATURE_PSFP)) { ++ err = -EOPNOTSUPP; ++ goto out; ++ } ++ + err = sparx5_tc_flower_psfp_setup(sparx5, vrule, tc_sg_idx, + tc_pol_idx, &sg, &fm, &sf); + if (err) diff --git a/target/linux/microchipsw/patches-6.12/0053-v6.13-net-sparx5-expose-some-sparx5-VCAP-symbols.patch b/target/linux/microchipsw/patches-6.12/0053-v6.13-net-sparx5-expose-some-sparx5-VCAP-symbols.patch new file mode 100644 index 0000000000..de7804c61b --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0053-v6.13-net-sparx5-expose-some-sparx5-VCAP-symbols.patch @@ -0,0 +1,116 @@ +From c7a8ba9eec856c3a1d134a09387df04a13efb163 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 1 Nov 2024 08:09:07 +0100 +Subject: [PATCH 58/82] net: sparx5: expose some sparx5 VCAP symbols +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +In preparation for lan969x VCAP support, expose the following symbols for +use by the lan969x VCAP implementation: + +- The symbols SPARX5_*_LOOKUPS defines the number of lookups in each + VCAP instance. These are the same for lan969x. Move them to the + header file. + +- The struct sparx5_vcap_inst encapsulates information about a single + VCAP instance. Move this struct to the header file and declare the + sparx5_vcap_inst_cfg as extern. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jens Emil Schulz Østergaard +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../microchip/sparx5/sparx5_vcap_impl.c | 18 +--------------- + .../microchip/sparx5/sparx5_vcap_impl.h | 21 +++++++++++++++++++ + 2 files changed, 22 insertions(+), 17 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c +@@ -17,7 +17,6 @@ + #define SUPER_VCAP_BLK_SIZE 3072 /* addresses per Super VCAP block */ + #define STREAMSIZE (64 * 4) /* bytes in the VCAP cache area */ + +-#define SPARX5_IS2_LOOKUPS 4 + #define VCAP_IS2_KEYSEL(_ena, _noneth, _v4_mc, _v4_uc, _v6_mc, _v6_uc, _arp) \ + (ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(_ena) | \ + ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(_noneth) | \ +@@ -27,7 +26,6 @@ + ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(_v6_uc) | \ + ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(_arp)) + +-#define SPARX5_IS0_LOOKUPS 6 + #define VCAP_IS0_KEYSEL(_ena, _etype, _ipv4, _ipv6, _mpls_uc, _mpls_mc, _mlbs) \ + (ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(_ena) | \ + ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(_etype) | \ +@@ -37,31 +35,17 @@ + ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(_mpls_mc) | \ + ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(_mlbs)) + +-#define SPARX5_ES0_LOOKUPS 1 + #define VCAP_ES0_KEYSEL(_key) (REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(_key)) + #define SPARX5_STAT_ESDX_GRN_PKTS 0x300 + #define SPARX5_STAT_ESDX_YEL_PKTS 0x301 + +-#define SPARX5_ES2_LOOKUPS 2 + #define VCAP_ES2_KEYSEL(_ena, _arp, _ipv4, _ipv6) \ + (EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(_ena) | \ + EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(_arp) | \ + EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(_ipv4) | \ + EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(_ipv6)) + +-static struct sparx5_vcap_inst { +- enum vcap_type vtype; /* type of vcap */ +- int vinst; /* instance number within the same type */ +- int lookups; /* number of lookups in this vcap type */ +- int lookups_per_instance; /* number of lookups in this instance */ +- int first_cid; /* first chain id in this vcap */ +- int last_cid; /* last chain id in this vcap */ +- int count; /* number of available addresses, not in super vcap */ +- int map_id; /* id in the super vcap block mapping (if applicable) */ +- int blockno; /* starting block in super vcap (if applicable) */ +- int blocks; /* number of blocks in super vcap (if applicable) */ +- bool ingress; /* is vcap in the ingress path */ +-} sparx5_vcap_inst_cfg[] = { ++const struct sparx5_vcap_inst sparx5_vcap_inst_cfg[] = { + { + .vtype = VCAP_TYPE_IS0, /* CLM-0 */ + .vinst = 0, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.h +@@ -16,6 +16,11 @@ + #include "vcap_api.h" + #include "vcap_api_client.h" + ++#define SPARX5_IS2_LOOKUPS 4 ++#define SPARX5_IS0_LOOKUPS 6 ++#define SPARX5_ES0_LOOKUPS 1 ++#define SPARX5_ES2_LOOKUPS 2 ++ + #define SPARX5_VCAP_CID_IS0_L0 VCAP_CID_INGRESS_L0 /* IS0/CLM lookup 0 */ + #define SPARX5_VCAP_CID_IS0_L1 VCAP_CID_INGRESS_L1 /* IS0/CLM lookup 1 */ + #define SPARX5_VCAP_CID_IS0_L2 VCAP_CID_INGRESS_L2 /* IS0/CLM lookup 2 */ +@@ -40,6 +45,22 @@ + #define SPARX5_VCAP_CID_ES2_MAX \ + (VCAP_CID_EGRESS_STAGE2_L1 + VCAP_CID_LOOKUP_SIZE - 1) /* ES2 Max */ + ++struct sparx5_vcap_inst { ++ enum vcap_type vtype; /* type of vcap */ ++ int vinst; /* instance number within the same type */ ++ int lookups; /* number of lookups in this vcap type */ ++ int lookups_per_instance; /* number of lookups in this instance */ ++ int first_cid; /* first chain id in this vcap */ ++ int last_cid; /* last chain id in this vcap */ ++ int count; /* number of available addresses, not in super vcap */ ++ int map_id; /* id in the super vcap block mapping (if applicable) */ ++ int blockno; /* starting block in super vcap (if applicable) */ ++ int blocks; /* number of blocks in super vcap (if applicable) */ ++ bool ingress; /* is vcap in the ingress path */ ++}; ++ ++extern const struct sparx5_vcap_inst sparx5_vcap_inst_cfg[]; ++ + /* IS0 port keyset selection control */ + + /* IS0 ethernet, IPv4, IPv6 traffic type keyset generation */ diff --git a/target/linux/microchipsw/patches-6.12/0054-v6.13-net-sparx5-replace-SPX5_PORTS-with-n_ports.patch b/target/linux/microchipsw/patches-6.12/0054-v6.13-net-sparx5-replace-SPX5_PORTS-with-n_ports.patch new file mode 100644 index 0000000000..039fc7e8a2 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0054-v6.13-net-sparx5-replace-SPX5_PORTS-with-n_ports.patch @@ -0,0 +1,143 @@ +From 847d70a1d4583e2a5c00faf48e54d8880d248310 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 1 Nov 2024 08:09:08 +0100 +Subject: [PATCH 59/82] net: sparx5: replace SPX5_PORTS with n_ports +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The Sparx5 VCAP implementation uses the SPX5_PORTS symbol to iterate over +the 65 front ports of Sparx5. Replace the use with the n_ports constant +from the match data, which translates to 65 of Sparx5 and 30 on lan969x. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jens Emil Schulz Østergaard +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../microchip/sparx5/sparx5_vcap_impl.c | 24 ++++++++++++------- + 1 file changed, 15 insertions(+), 9 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c +@@ -1777,6 +1777,7 @@ void sparx5_vcap_set_port_keyset(struct + static void sparx5_vcap_is0_port_key_selection(struct sparx5 *sparx5, + struct vcap_admin *admin) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + int portno, lookup; + u32 keysel; + +@@ -1788,7 +1789,7 @@ static void sparx5_vcap_is0_port_key_sel + VCAP_IS0_PS_MPLS_FOLLOW_ETYPE, + VCAP_IS0_PS_MLBS_FOLLOW_ETYPE); + for (lookup = 0; lookup < admin->lookups; ++lookup) { +- for (portno = 0; portno < SPX5_PORTS; ++portno) { ++ for (portno = 0; portno < consts->n_ports; ++portno) { + spx5_wr(keysel, sparx5, + ANA_CL_ADV_CL_CFG(portno, lookup)); + spx5_rmw(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, +@@ -1803,6 +1804,7 @@ static void sparx5_vcap_is0_port_key_sel + static void sparx5_vcap_is2_port_key_selection(struct sparx5 *sparx5, + struct vcap_admin *admin) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + int portno, lookup; + u32 keysel; + +@@ -1813,13 +1815,13 @@ static void sparx5_vcap_is2_port_key_sel + VCAP_IS2_PS_IPV6_UC_IP_7TUPLE, + VCAP_IS2_PS_ARP_ARP); + for (lookup = 0; lookup < admin->lookups; ++lookup) { +- for (portno = 0; portno < SPX5_PORTS; ++portno) { ++ for (portno = 0; portno < consts->n_ports; ++portno) { + spx5_wr(keysel, sparx5, + ANA_ACL_VCAP_S2_KEY_SEL(portno, lookup)); + } + } + /* IS2 lookups are in bit 0:3 */ +- for (portno = 0; portno < SPX5_PORTS; ++portno) ++ for (portno = 0; portno < consts->n_ports; ++portno) + spx5_rmw(ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(0xf), + ANA_ACL_VCAP_S2_CFG_SEC_ENA, + sparx5, +@@ -1830,11 +1832,12 @@ static void sparx5_vcap_is2_port_key_sel + static void sparx5_vcap_es0_port_key_selection(struct sparx5 *sparx5, + struct vcap_admin *admin) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + int portno; + u32 keysel; + + keysel = VCAP_ES0_KEYSEL(VCAP_ES0_PS_FORCE_ISDX_LOOKUPS); +- for (portno = 0; portno < SPX5_PORTS; ++portno) ++ for (portno = 0; portno < consts->n_ports; ++portno) + spx5_rmw(keysel, REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, + sparx5, REW_RTAG_ETAG_CTRL(portno)); + +@@ -1846,6 +1849,7 @@ static void sparx5_vcap_es0_port_key_sel + static void sparx5_vcap_es2_port_key_selection(struct sparx5 *sparx5, + struct vcap_admin *admin) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + int portno, lookup; + u32 keysel; + +@@ -1853,7 +1857,7 @@ static void sparx5_vcap_es2_port_key_sel + VCAP_ES2_PS_IPV4_IP4_TCP_UDP_OTHER, + VCAP_ES2_PS_IPV6_IP_7TUPLE); + for (lookup = 0; lookup < admin->lookups; ++lookup) +- for (portno = 0; portno < SPX5_PORTS; ++portno) ++ for (portno = 0; portno < consts->n_ports; ++portno) + spx5_wr(keysel, sparx5, + EACL_VCAP_ES2_KEY_SEL(portno, lookup)); + } +@@ -1885,19 +1889,20 @@ static void sparx5_vcap_port_key_selecti + static void sparx5_vcap_port_key_deselection(struct sparx5 *sparx5, + struct vcap_admin *admin) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + int portno, lookup; + + switch (admin->vtype) { + case VCAP_TYPE_IS0: + for (lookup = 0; lookup < admin->lookups; ++lookup) +- for (portno = 0; portno < SPX5_PORTS; ++portno) ++ for (portno = 0; portno < consts->n_ports; ++portno) + spx5_rmw(ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(0), + ANA_CL_ADV_CL_CFG_LOOKUP_ENA, + sparx5, + ANA_CL_ADV_CL_CFG(portno, lookup)); + break; + case VCAP_TYPE_IS2: +- for (portno = 0; portno < SPX5_PORTS; ++portno) ++ for (portno = 0; portno < consts->n_ports; ++portno) + spx5_rmw(ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(0), + ANA_ACL_VCAP_S2_CFG_SEC_ENA, + sparx5, +@@ -1909,7 +1914,7 @@ static void sparx5_vcap_port_key_deselec + break; + case VCAP_TYPE_ES2: + for (lookup = 0; lookup < admin->lookups; ++lookup) +- for (portno = 0; portno < SPX5_PORTS; ++portno) ++ for (portno = 0; portno < consts->n_ports; ++portno) + spx5_rmw(EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(0), + EACL_VCAP_ES2_KEY_SEL_KEY_ENA, + sparx5, +@@ -2026,6 +2031,7 @@ static void sparx5_vcap_block_alloc(stru + /* Allocate a vcap control and vcap instances and configure the system */ + int sparx5_vcap_init(struct sparx5 *sparx5) + { ++ const struct sparx5_consts *consts = sparx5->data->consts; + const struct sparx5_vcap_inst *cfg; + struct vcap_control *ctrl; + struct vcap_admin *admin; +@@ -2069,7 +2075,7 @@ int sparx5_vcap_init(struct sparx5 *spar + list_add_tail(&admin->list, &ctrl->list); + } + dir = vcap_debugfs(sparx5->dev, sparx5->debugfs_root, ctrl); +- for (idx = 0; idx < SPX5_PORTS; ++idx) ++ for (idx = 0; idx < consts->n_ports; ++idx) + if (sparx5->ports[idx]) + vcap_port_debugfs(sparx5->dev, dir, ctrl, + sparx5->ports[idx]->ndev); diff --git a/target/linux/microchipsw/patches-6.12/0055-v6.13-net-sparx5-add-new-VCAP-constants-to-match-data.patch b/target/linux/microchipsw/patches-6.12/0055-v6.13-net-sparx5-add-new-VCAP-constants-to-match-data.patch new file mode 100644 index 0000000000..1d5dbd437e --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0055-v6.13-net-sparx5-add-new-VCAP-constants-to-match-data.patch @@ -0,0 +1,97 @@ +From 6deea25857672a2ae9742499634b07f83508b35a Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 1 Nov 2024 08:09:09 +0100 +Subject: [PATCH 60/82] net: sparx5: add new VCAP constants to match data +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +In preparation for lan969x VCAP support, add the following three new +VCAP constants to match data: + + - vcaps_cfg (contains configuration data for each VCAP). + + - vcaps (contains auto-generated information about VCAP keys and + actions). + + - vcap_stats: (contains auto-generated string names of all the keys + and actions) + +Add these constants to the Sparx5 match data constants and use them to +initialize the VCAP's in sparx5_vcap_init(). + +Reviewed-by: Steen Hegelund +Reviewed-by: Jens Emil Schulz Østergaard +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++++ + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 3 +++ + drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h | 2 ++ + drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c | 6 +++--- + 4 files changed, 13 insertions(+), 3 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -30,6 +30,8 @@ + #include "sparx5_main.h" + #include "sparx5_port.h" + #include "sparx5_qos.h" ++#include "sparx5_vcap_ag_api.h" ++#include "sparx5_vcap_impl.h" + + const struct sparx5_regs *regs; + +@@ -1062,6 +1064,9 @@ static const struct sparx5_consts sparx5 + .qres_max_prio_idx = 630, + .qres_max_colour_idx = 638, + .tod_pin = 4, ++ .vcaps = sparx5_vcaps, ++ .vcaps_cfg = sparx5_vcap_inst_cfg, ++ .vcap_stats = &sparx5_vcap_stats, + }; + + static const struct sparx5_ops sparx5_ops = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -303,6 +303,9 @@ struct sparx5_consts { + u32 qres_max_prio_idx; /* Maximum QRES prio index */ + u32 qres_max_colour_idx; /* Maximum QRES colour index */ + u32 tod_pin; /* PTP TOD pin */ ++ const struct sparx5_vcap_inst *vcaps_cfg; ++ const struct vcap_info *vcaps; ++ const struct vcap_statistics *vcap_stats; + }; + + struct sparx5_ops { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h +@@ -10,6 +10,8 @@ + #ifndef __SPARX5_VCAP_AG_API_H__ + #define __SPARX5_VCAP_AG_API_H__ + ++#include "vcap_api.h" ++ + /* VCAPs */ + extern const struct vcap_info sparx5_vcaps[]; + extern const struct vcap_statistics sparx5_vcap_stats; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c +@@ -2053,14 +2053,14 @@ int sparx5_vcap_init(struct sparx5 *spar + + sparx5->vcap_ctrl = ctrl; + /* select the sparx5 VCAP model */ +- ctrl->vcaps = sparx5_vcaps; +- ctrl->stats = &sparx5_vcap_stats; ++ ctrl->vcaps = consts->vcaps; ++ ctrl->stats = consts->vcap_stats; + /* Setup callbacks to allow the API to use the VCAP HW */ + ctrl->ops = &sparx5_vcap_ops; + + INIT_LIST_HEAD(&ctrl->list); + for (idx = 0; idx < ARRAY_SIZE(sparx5_vcap_inst_cfg); ++idx) { +- cfg = &sparx5_vcap_inst_cfg[idx]; ++ cfg = &consts->vcaps_cfg[idx]; + admin = sparx5_vcap_admin_alloc(sparx5, ctrl, cfg); + if (IS_ERR(admin)) { + err = PTR_ERR(admin); diff --git a/target/linux/microchipsw/patches-6.12/0056-v6.13-net-sparx5-execute-sparx5_vcap_init-on-lan969x.patch b/target/linux/microchipsw/patches-6.12/0056-v6.13-net-sparx5-execute-sparx5_vcap_init-on-lan969x.patch new file mode 100644 index 0000000000..6df0092689 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0056-v6.13-net-sparx5-execute-sparx5_vcap_init-on-lan969x.patch @@ -0,0 +1,39 @@ +From 41742f746f4860ad7658484ec24a2971476a9d05 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 1 Nov 2024 08:09:10 +0100 +Subject: [PATCH 61/82] net: sparx5: execute sparx5_vcap_init() on lan969x +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The is_sparx5() check was introduced in an earlier series, to make sure +the sparx5_vcap_init() was not executed on lan969x, as it was not +implemented there yet. Now that it is, remove that check. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jens Emil Schulz Østergaard +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 10 ++++------ + 1 file changed, 4 insertions(+), 6 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -770,12 +770,10 @@ static int sparx5_start(struct sparx5 *s + if (err) + return err; + +- if (is_sparx5(sparx5)) { +- err = sparx5_vcap_init(sparx5); +- if (err) { +- sparx5_unregister_notifier_blocks(sparx5); +- return err; +- } ++ err = sparx5_vcap_init(sparx5); ++ if (err) { ++ sparx5_unregister_notifier_blocks(sparx5); ++ return err; + } + + /* Start Frame DMA with fallback to register based INJ/XTR */ diff --git a/target/linux/microchipsw/patches-6.12/0057-v6.13-net-lan969x-add-autogenerated-VCAP-information.patch b/target/linux/microchipsw/patches-6.12/0057-v6.13-net-lan969x-add-autogenerated-VCAP-information.patch new file mode 100644 index 0000000000..50eccb4af3 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0057-v6.13-net-lan969x-add-autogenerated-VCAP-information.patch @@ -0,0 +1,3916 @@ +From 1a3175837f88ce0d121bcaa4c8947872eb201a22 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 1 Nov 2024 08:09:11 +0100 +Subject: [PATCH 62/82] net: lan969x: add autogenerated VCAP information +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Platform VCAP data for each VCAP instance is auto-generated using an +internal Microchip tool. The generated VCAP data contains information +about keyfields, keyfield sets, actionfields, actionfield sets and +typegroups, which in combination are used to encode and decode rules in +the VCAP. + +Add the auto-generated VCAP file lan969x_vcap_ag_api.c and assign the +two structs: lan969x_vcaps and lan969x_vcap_stats to the match data. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jens Emil Schulz Østergaard +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/microchip/lan969x/Makefile | 3 +- + .../net/ethernet/microchip/lan969x/lan969x.c | 2 + + .../net/ethernet/microchip/lan969x/lan969x.h | 5 + + .../microchip/lan969x/lan969x_vcap_ag_api.c | 3843 +++++++++++++++++ + 4 files changed, 3852 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c + +--- a/drivers/net/ethernet/microchip/lan969x/Makefile ++++ b/drivers/net/ethernet/microchip/lan969x/Makefile +@@ -5,7 +5,8 @@ + + obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o + +-lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o ++lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \ ++ lan969x_vcap_ag_api.o + + # Provide include files + ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c +@@ -319,6 +319,8 @@ static const struct sparx5_consts lan969 + .qres_max_prio_idx = 315, + .qres_max_colour_idx = 323, + .tod_pin = 4, ++ .vcaps = lan969x_vcaps, ++ .vcap_stats = &lan969x_vcap_stats, + }; + + static const struct sparx5_ops lan969x_ops = { +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.h ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h +@@ -9,10 +9,15 @@ + + #include "../sparx5/sparx5_main.h" + #include "../sparx5/sparx5_regs.h" ++#include "../sparx5/sparx5_vcap_impl.h" + + /* lan969x.c */ + extern const struct sparx5_match_data lan969x_desc; + ++/* lan969x_vcap_ag_api.c */ ++extern const struct vcap_statistics lan969x_vcap_stats; ++extern const struct vcap_info lan969x_vcaps[]; ++ + /* lan969x_regs.c */ + extern const unsigned int lan969x_tsize[TSIZE_LAST]; + extern const unsigned int lan969x_raddr[RADDR_LAST]; +--- /dev/null ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c +@@ -0,0 +1,3843 @@ ++// SPDX-License-Identifier: BSD-3-Clause ++/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. ++ * Microchip VCAP API ++ */ ++ ++/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200. ++ * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391 ++ */ ++ ++#include ++#include ++ ++#include "lan969x.h" ++ ++/* keyfields */ ++static const struct vcap_field is0_normal_7tuple_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 1, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 2, ++ .width = 2, ++ }, ++ [VCAP_KF_LOOKUP_GEN_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 4, ++ .width = 10, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U72, ++ .offset = 16, ++ .width = 65, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 81, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 82, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 83, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_TPID0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 86, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 89, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 93, ++ .width = 12, ++ }, ++ [VCAP_KF_8021Q_TPID1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 105, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 108, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI1] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 111, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 112, ++ .width = 12, ++ }, ++ [VCAP_KF_8021Q_TPID2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 124, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 127, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI2] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 130, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 131, ++ .width = 12, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 144, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 192, ++ .width = 48, ++ }, ++ [VCAP_KF_IP_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 240, ++ .width = 1, ++ }, ++ [VCAP_KF_ETYPE_LEN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 241, ++ .width = 1, ++ }, ++ [VCAP_KF_ETYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 242, ++ .width = 16, ++ }, ++ [VCAP_KF_IP_SNAP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 258, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 259, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 260, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 262, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 263, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DSCP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 264, ++ .width = 6, ++ }, ++ [VCAP_KF_L3_IP6_DIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 270, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 398, ++ .width = 128, ++ }, ++ [VCAP_KF_TCP_UDP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 526, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 527, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 528, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 544, ++ .width = 8, ++ }, ++}; ++ ++static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 2, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 2, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 3, ++ .width = 2, ++ }, ++ [VCAP_KF_LOOKUP_GEN_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 10, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 15, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U72, ++ .offset = 17, ++ .width = 65, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 82, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 83, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_TPID0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 87, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 90, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 93, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 94, ++ .width = 12, ++ }, ++ [VCAP_KF_8021Q_TPID1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 106, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 109, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI1] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 112, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 113, ++ .width = 12, ++ }, ++ [VCAP_KF_8021Q_TPID2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 125, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 128, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI2] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 131, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 132, ++ .width = 12, ++ }, ++ [VCAP_KF_IP_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 145, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 146, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 147, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 149, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 150, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DSCP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 151, ++ .width = 6, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 157, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 189, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 221, ++ .width = 8, ++ }, ++ [VCAP_KF_TCP_UDP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 229, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 230, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 231, ++ .width = 8, ++ }, ++ [VCAP_KF_IP_PAYLOAD_5TUPLE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 239, ++ .width = 32, ++ }, ++}; ++ ++static const struct vcap_field is2_mac_etype_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 88, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 89, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 137, ++ .width = 48, ++ }, ++ [VCAP_KF_ETYPE_LEN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 185, ++ .width = 1, ++ }, ++ [VCAP_KF_ETYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 186, ++ .width = 16, ++ }, ++ [VCAP_KF_L2_PAYLOAD_ETYPE] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 202, ++ .width = 64, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 266, ++ .width = 16, ++ }, ++ [VCAP_KF_OAM_CCM_CNTS_EQ0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 282, ++ .width = 1, ++ }, ++ [VCAP_KF_OAM_Y1731_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 283, ++ .width = 1, ++ }, ++}; ++ ++static const struct vcap_field is2_arp_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 85, ++ .width = 48, ++ }, ++ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 133, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 134, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_LEN_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 135, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_TGT_MATCH_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 136, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_SENDER_MATCH_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 137, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 138, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_OPCODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 139, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 141, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 173, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 205, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 206, ++ .width = 16, ++ }, ++}; ++ ++static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 88, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 89, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 90, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 93, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 94, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 95, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 103, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 135, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 167, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 168, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_DPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 169, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 185, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 201, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 217, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 218, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_FIN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 219, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SYN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 220, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RST] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 221, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PSH] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 222, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_ACK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 223, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_URG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 224, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PAYLOAD] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 225, ++ .width = 64, ++ }, ++}; ++ ++static const struct vcap_field is2_ip4_other_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 88, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 89, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 90, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 93, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 94, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 95, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 103, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 135, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 167, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 168, ++ .width = 8, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 176, ++ .width = 16, ++ }, ++ [VCAP_KF_L3_PAYLOAD] = { ++ .type = VCAP_FIELD_U112, ++ .offset = 192, ++ .width = 96, ++ }, ++}; ++ ++static const struct vcap_field is2_ip6_std_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 89, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 90, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 218, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 219, ++ .width = 8, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 227, ++ .width = 16, ++ }, ++ [VCAP_KF_L3_PAYLOAD] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 243, ++ .width = 40, ++ }, ++}; ++ ++static const struct vcap_field is2_ip_7tuple_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 2, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 2, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 3, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 11, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 12, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U72, ++ .offset = 18, ++ .width = 65, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 83, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 85, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 98, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 111, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 112, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 115, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 118, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 119, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 120, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 168, ++ .width = 48, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 218, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 219, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 220, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP6_DIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 228, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 356, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 484, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_UDP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 485, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 486, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_DPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 487, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 503, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 519, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 535, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 536, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_FIN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 537, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SYN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 538, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RST] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 539, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PSH] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 540, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_ACK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 541, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_URG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 542, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PAYLOAD] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 543, ++ .width = 64, ++ }, ++}; ++ ++static const struct vcap_field es0_isdx_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_EGR_PORT_NO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 1, ++ .width = 6, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 7, ++ .width = 13, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_TPID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 23, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 27, ++ .width = 1, ++ }, ++ [VCAP_KF_PROT_ACTIVE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 28, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 38, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field es2_mac_etype_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 96, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 144, ++ .width = 48, ++ }, ++ [VCAP_KF_ETYPE_LEN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 192, ++ .width = 1, ++ }, ++ [VCAP_KF_ETYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 193, ++ .width = 16, ++ }, ++ [VCAP_KF_L2_PAYLOAD_ETYPE] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 209, ++ .width = 64, ++ }, ++ [VCAP_KF_OAM_CCM_CNTS_EQ0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 273, ++ .width = 1, ++ }, ++ [VCAP_KF_OAM_Y1731_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 274, ++ .width = 1, ++ }, ++}; ++ ++static const struct vcap_field es2_arp_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 95, ++ .width = 48, ++ }, ++ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 143, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 144, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_LEN_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 145, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_TGT_MATCH_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 146, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_SENDER_MATCH_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 147, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 148, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_OPCODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 149, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 151, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 183, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 215, ++ .width = 1, ++ }, ++}; ++ ++static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 96, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 97, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 99, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 100, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 101, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 109, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 141, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 173, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 174, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_DPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 175, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 191, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 207, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 223, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 224, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_FIN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 225, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SYN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 226, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RST] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 227, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PSH] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 228, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_ACK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 229, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_URG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 230, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PAYLOAD] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 231, ++ .width = 64, ++ }, ++}; ++ ++static const struct vcap_field es2_ip4_other_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 96, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 97, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 99, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 100, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 101, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 109, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 141, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 173, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 174, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_PAYLOAD] = { ++ .type = VCAP_FIELD_U112, ++ .offset = 182, ++ .width = 96, ++ }, ++}; ++ ++static const struct vcap_field es2_ip_7tuple_keyfield[] = { ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 10, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 11, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 12, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 13, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 23, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 25, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 38, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 73, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 74, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 85, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 88, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 89, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 93, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 141, ++ .width = 48, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 191, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 192, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 193, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP6_DIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 201, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 329, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 457, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_UDP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 458, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 459, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_DPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 460, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 476, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 492, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 508, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 509, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_FIN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 510, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SYN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 511, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RST] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 512, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PSH] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 513, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_ACK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 514, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_URG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 515, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PAYLOAD] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 516, ++ .width = 64, ++ }, ++}; ++ ++static const struct vcap_field es2_ip6_std_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 96, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 97, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 225, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 226, ++ .width = 8, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 234, ++ .width = 16, ++ }, ++ [VCAP_KF_L3_PAYLOAD] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 250, ++ .width = 40, ++ }, ++}; ++ ++/* keyfield_set */ ++static const struct vcap_set is0_keyfield_set[] = { ++ [VCAP_KFS_NORMAL_7TUPLE] = { ++ .type_id = 0, ++ .sw_per_item = 12, ++ .sw_cnt = 1, ++ }, ++ [VCAP_KFS_NORMAL_5TUPLE_IP4] = { ++ .type_id = 2, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++}; ++ ++static const struct vcap_set is2_keyfield_set[] = { ++ [VCAP_KFS_MAC_ETYPE] = { ++ .type_id = 0, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_ARP] = { ++ .type_id = 3, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP4_TCP_UDP] = { ++ .type_id = 4, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP4_OTHER] = { ++ .type_id = 5, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP6_STD] = { ++ .type_id = 6, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP_7TUPLE] = { ++ .type_id = 1, ++ .sw_per_item = 12, ++ .sw_cnt = 1, ++ }, ++}; ++ ++static const struct vcap_set es0_keyfield_set[] = { ++ [VCAP_KFS_ISDX] = { ++ .type_id = 0, ++ .sw_per_item = 1, ++ .sw_cnt = 1, ++ }, ++}; ++ ++static const struct vcap_set es2_keyfield_set[] = { ++ [VCAP_KFS_MAC_ETYPE] = { ++ .type_id = 0, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_ARP] = { ++ .type_id = 1, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP4_TCP_UDP] = { ++ .type_id = 2, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP4_OTHER] = { ++ .type_id = 3, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP_7TUPLE] = { ++ .type_id = -1, ++ .sw_per_item = 12, ++ .sw_cnt = 1, ++ }, ++ [VCAP_KFS_IP6_STD] = { ++ .type_id = 4, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++}; ++ ++/* keyfield_set map */ ++static const struct vcap_field *is0_keyfield_set_map[] = { ++ [VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield, ++ [VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield, ++}; ++ ++static const struct vcap_field *is2_keyfield_set_map[] = { ++ [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield, ++ [VCAP_KFS_ARP] = is2_arp_keyfield, ++ [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield, ++ [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield, ++ [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield, ++ [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield, ++}; ++ ++static const struct vcap_field *es0_keyfield_set_map[] = { ++ [VCAP_KFS_ISDX] = es0_isdx_keyfield, ++}; ++ ++static const struct vcap_field *es2_keyfield_set_map[] = { ++ [VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield, ++ [VCAP_KFS_ARP] = es2_arp_keyfield, ++ [VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield, ++ [VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield, ++ [VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield, ++ [VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield, ++}; ++ ++/* keyfield_set map sizes */ ++static int is0_keyfield_set_map_size[] = { ++ [VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield), ++ [VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield), ++}; ++ ++static int is2_keyfield_set_map_size[] = { ++ [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield), ++ [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield), ++ [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), ++ [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield), ++ [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield), ++ [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield), ++}; ++ ++static int es0_keyfield_set_map_size[] = { ++ [VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield), ++}; ++ ++static int es2_keyfield_set_map_size[] = { ++ [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield), ++ [VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield), ++ [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), ++ [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield), ++ [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield), ++ [VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield), ++}; ++ ++/* actionfields */ ++static const struct vcap_field is0_classification_actionfield[] = { ++ [VCAP_AF_TYPE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_AF_DSCP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 1, ++ .width = 1, ++ }, ++ [VCAP_AF_DSCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 2, ++ .width = 6, ++ }, ++ [VCAP_AF_QOS_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 12, ++ .width = 1, ++ }, ++ [VCAP_AF_QOS_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 13, ++ .width = 3, ++ }, ++ [VCAP_AF_DP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 16, ++ .width = 1, ++ }, ++ [VCAP_AF_DP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 17, ++ .width = 2, ++ }, ++ [VCAP_AF_DEI_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 19, ++ .width = 1, ++ }, ++ [VCAP_AF_DEI_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 20, ++ .width = 1, ++ }, ++ [VCAP_AF_PCP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 21, ++ .width = 1, ++ }, ++ [VCAP_AF_PCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 22, ++ .width = 3, ++ }, ++ [VCAP_AF_MAP_LOOKUP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 25, ++ .width = 2, ++ }, ++ [VCAP_AF_MAP_KEY] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 27, ++ .width = 3, ++ }, ++ [VCAP_AF_MAP_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 30, ++ .width = 7, ++ }, ++ [VCAP_AF_CLS_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 37, ++ .width = 3, ++ }, ++ [VCAP_AF_VID_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 43, ++ .width = 13, ++ }, ++ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 66, ++ .width = 1, ++ }, ++ [VCAP_AF_ISDX_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 10, ++ }, ++ [VCAP_AF_PAG_OVERRIDE_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 107, ++ .width = 8, ++ }, ++ [VCAP_AF_PAG_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 115, ++ .width = 8, ++ }, ++ [VCAP_AF_NXT_IDX_CTRL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 167, ++ .width = 3, ++ }, ++ [VCAP_AF_NXT_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 170, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field is0_full_actionfield[] = { ++ [VCAP_AF_DSCP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_AF_DSCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 1, ++ .width = 6, ++ }, ++ [VCAP_AF_QOS_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 11, ++ .width = 1, ++ }, ++ [VCAP_AF_QOS_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 12, ++ .width = 3, ++ }, ++ [VCAP_AF_DP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_AF_DP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 2, ++ }, ++ [VCAP_AF_DEI_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 18, ++ .width = 1, ++ }, ++ [VCAP_AF_DEI_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 19, ++ .width = 1, ++ }, ++ [VCAP_AF_PCP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 20, ++ .width = 1, ++ }, ++ [VCAP_AF_PCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 21, ++ .width = 3, ++ }, ++ [VCAP_AF_MAP_LOOKUP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 24, ++ .width = 2, ++ }, ++ [VCAP_AF_MAP_KEY] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 26, ++ .width = 3, ++ }, ++ [VCAP_AF_MAP_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 29, ++ .width = 7, ++ }, ++ [VCAP_AF_CLS_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 36, ++ .width = 3, ++ }, ++ [VCAP_AF_VID_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 42, ++ .width = 13, ++ }, ++ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 65, ++ .width = 1, ++ }, ++ [VCAP_AF_ISDX_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 66, ++ .width = 10, ++ }, ++ [VCAP_AF_MASK_MODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 76, ++ .width = 3, ++ }, ++ [VCAP_AF_PORT_MASK] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 79, ++ .width = 37, ++ }, ++ [VCAP_AF_PAG_OVERRIDE_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 174, ++ .width = 8, ++ }, ++ [VCAP_AF_PAG_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 182, ++ .width = 8, ++ }, ++ [VCAP_AF_NXT_IDX_CTRL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 266, ++ .width = 3, ++ }, ++ [VCAP_AF_NXT_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 269, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field is0_class_reduced_actionfield[] = { ++ [VCAP_AF_TYPE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_AF_QOS_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 5, ++ .width = 1, ++ }, ++ [VCAP_AF_QOS_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 6, ++ .width = 3, ++ }, ++ [VCAP_AF_DP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 9, ++ .width = 1, ++ }, ++ [VCAP_AF_DP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 10, ++ .width = 2, ++ }, ++ [VCAP_AF_MAP_LOOKUP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 12, ++ .width = 2, ++ }, ++ [VCAP_AF_MAP_KEY] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 3, ++ }, ++ [VCAP_AF_CLS_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 17, ++ .width = 3, ++ }, ++ [VCAP_AF_VID_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 23, ++ .width = 13, ++ }, ++ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 46, ++ .width = 1, ++ }, ++ [VCAP_AF_ISDX_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 47, ++ .width = 10, ++ }, ++ [VCAP_AF_NXT_IDX_CTRL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 89, ++ .width = 3, ++ }, ++ [VCAP_AF_NXT_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 92, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field is2_base_type_actionfield[] = { ++ [VCAP_AF_PIPELINE_FORCE_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 1, ++ .width = 1, ++ }, ++ [VCAP_AF_PIPELINE_PT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 2, ++ .width = 5, ++ }, ++ [VCAP_AF_HIT_ME_ONCE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 7, ++ .width = 1, ++ }, ++ [VCAP_AF_INTR_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 8, ++ .width = 1, ++ }, ++ [VCAP_AF_CPU_COPY_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 9, ++ .width = 1, ++ }, ++ [VCAP_AF_CPU_QUEUE_NUM] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 10, ++ .width = 3, ++ }, ++ [VCAP_AF_LRN_DIS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_AF_RT_DIS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 16, ++ .width = 1, ++ }, ++ [VCAP_AF_POLICE_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 17, ++ .width = 1, ++ }, ++ [VCAP_AF_POLICE_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 5, ++ }, ++ [VCAP_AF_IGNORE_PIPELINE_CTRL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 23, ++ .width = 1, ++ }, ++ [VCAP_AF_MASK_MODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 27, ++ .width = 3, ++ }, ++ [VCAP_AF_PORT_MASK] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 30, ++ .width = 37, ++ }, ++ [VCAP_AF_MIRROR_PROBE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 78, ++ .width = 2, ++ }, ++ [VCAP_AF_MATCH_ID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 131, ++ .width = 16, ++ }, ++ [VCAP_AF_MATCH_ID_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 147, ++ .width = 16, ++ }, ++ [VCAP_AF_CNT_ID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 163, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field es0_es0_actionfield[] = { ++ [VCAP_AF_PUSH_OUTER_TAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 2, ++ }, ++ [VCAP_AF_PUSH_INNER_TAG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 2, ++ .width = 1, ++ }, ++ [VCAP_AF_TAG_A_TPID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 3, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_A_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 6, ++ .width = 2, ++ }, ++ [VCAP_AF_TAG_A_PCP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 8, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_A_DEI_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 11, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_B_TPID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_B_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 17, ++ .width = 2, ++ }, ++ [VCAP_AF_TAG_B_PCP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 19, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_B_DEI_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 22, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_C_TPID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 25, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_C_PCP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_C_DEI_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 31, ++ .width = 3, ++ }, ++ [VCAP_AF_VID_A_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 34, ++ .width = 12, ++ }, ++ [VCAP_AF_PCP_A_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 46, ++ .width = 3, ++ }, ++ [VCAP_AF_DEI_A_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 49, ++ .width = 1, ++ }, ++ [VCAP_AF_VID_B_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 50, ++ .width = 12, ++ }, ++ [VCAP_AF_PCP_B_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 62, ++ .width = 3, ++ }, ++ [VCAP_AF_DEI_B_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 65, ++ .width = 1, ++ }, ++ [VCAP_AF_VID_C_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 66, ++ .width = 12, ++ }, ++ [VCAP_AF_PCP_C_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 78, ++ .width = 3, ++ }, ++ [VCAP_AF_DEI_C_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 81, ++ .width = 1, ++ }, ++ [VCAP_AF_POP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 82, ++ .width = 2, ++ }, ++ [VCAP_AF_UNTAG_VID_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_AF_PUSH_CUSTOMER_TAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 85, ++ .width = 2, ++ }, ++ [VCAP_AF_TAG_C_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 87, ++ .width = 2, ++ }, ++ [VCAP_AF_DSCP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 127, ++ .width = 3, ++ }, ++ [VCAP_AF_DSCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 130, ++ .width = 6, ++ }, ++ [VCAP_AF_ESDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 319, ++ .width = 10, ++ }, ++ [VCAP_AF_FWD_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 438, ++ .width = 2, ++ }, ++ [VCAP_AF_CPU_QU] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 440, ++ .width = 3, ++ }, ++ [VCAP_AF_PIPELINE_PT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 443, ++ .width = 2, ++ }, ++ [VCAP_AF_PIPELINE_ACT] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 445, ++ .width = 1, ++ }, ++ [VCAP_AF_SWAP_MACS_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 454, ++ .width = 1, ++ }, ++ [VCAP_AF_LOOP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 455, ++ .width = 1, ++ }, ++}; ++ ++static const struct vcap_field es2_base_type_actionfield[] = { ++ [VCAP_AF_HIT_ME_ONCE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_AF_INTR_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 1, ++ .width = 1, ++ }, ++ [VCAP_AF_FWD_MODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 2, ++ .width = 2, ++ }, ++ [VCAP_AF_COPY_QUEUE_NUM] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 4, ++ .width = 14, ++ }, ++ [VCAP_AF_COPY_PORT_NUM] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 6, ++ }, ++ [VCAP_AF_MIRROR_PROBE_ID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 24, ++ .width = 2, ++ }, ++ [VCAP_AF_CPU_COPY_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_AF_CPU_QUEUE_NUM] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 27, ++ .width = 3, ++ }, ++ [VCAP_AF_POLICE_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 30, ++ .width = 1, ++ }, ++ [VCAP_AF_POLICE_REMARK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 31, ++ .width = 1, ++ }, ++ [VCAP_AF_POLICE_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 32, ++ .width = 5, ++ }, ++ [VCAP_AF_ES2_REW_CMD] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 37, ++ .width = 3, ++ }, ++ [VCAP_AF_CNT_ID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 40, ++ .width = 9, ++ }, ++ [VCAP_AF_IGNORE_PIPELINE_CTRL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 49, ++ .width = 1, ++ }, ++}; ++ ++/* actionfield_set */ ++static const struct vcap_set is0_actionfield_set[] = { ++ [VCAP_AFS_CLASSIFICATION] = { ++ .type_id = 1, ++ .sw_per_item = 2, ++ .sw_cnt = 6, ++ }, ++ [VCAP_AFS_FULL] = { ++ .type_id = -1, ++ .sw_per_item = 3, ++ .sw_cnt = 4, ++ }, ++ [VCAP_AFS_CLASS_REDUCED] = { ++ .type_id = 1, ++ .sw_per_item = 1, ++ .sw_cnt = 12, ++ }, ++}; ++ ++static const struct vcap_set is2_actionfield_set[] = { ++ [VCAP_AFS_BASE_TYPE] = { ++ .type_id = -1, ++ .sw_per_item = 3, ++ .sw_cnt = 4, ++ }, ++}; ++ ++static const struct vcap_set es0_actionfield_set[] = { ++ [VCAP_AFS_ES0] = { ++ .type_id = -1, ++ .sw_per_item = 1, ++ .sw_cnt = 1, ++ }, ++}; ++ ++static const struct vcap_set es2_actionfield_set[] = { ++ [VCAP_AFS_BASE_TYPE] = { ++ .type_id = -1, ++ .sw_per_item = 3, ++ .sw_cnt = 4, ++ }, ++}; ++ ++/* actionfield_set map */ ++static const struct vcap_field *is0_actionfield_set_map[] = { ++ [VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield, ++ [VCAP_AFS_FULL] = is0_full_actionfield, ++ [VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield, ++}; ++ ++static const struct vcap_field *is2_actionfield_set_map[] = { ++ [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield, ++}; ++ ++static const struct vcap_field *es0_actionfield_set_map[] = { ++ [VCAP_AFS_ES0] = es0_es0_actionfield, ++}; ++ ++static const struct vcap_field *es2_actionfield_set_map[] = { ++ [VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield, ++}; ++ ++/* actionfield_set map size */ ++static int is0_actionfield_set_map_size[] = { ++ [VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield), ++ [VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield), ++ [VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield), ++}; ++ ++static int is2_actionfield_set_map_size[] = { ++ [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield), ++}; ++ ++static int es0_actionfield_set_map_size[] = { ++ [VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield), ++}; ++ ++static int es2_actionfield_set_map_size[] = { ++ [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield), ++}; ++ ++/* Type Groups */ ++static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 5, ++ .value = 16, ++ }, ++ { ++ .offset = 52, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 104, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 156, ++ .width = 3, ++ .value = 0, ++ }, ++ { ++ .offset = 208, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 260, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 312, ++ .width = 4, ++ .value = 0, ++ }, ++ { ++ .offset = 364, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 416, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 468, ++ .width = 3, ++ .value = 0, ++ }, ++ { ++ .offset = 520, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 572, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 4, ++ .value = 8, ++ }, ++ { ++ .offset = 52, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 104, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 156, ++ .width = 3, ++ .value = 0, ++ }, ++ { ++ .offset = 208, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 260, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 3, ++ .value = 4, ++ }, ++ { ++ .offset = 156, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 312, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 468, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 156, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 3, ++ .value = 4, ++ }, ++ { ++ .offset = 156, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 312, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 468, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 156, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = { ++ [12] = is0_x12_keyfield_set_typegroups, ++ [6] = is0_x6_keyfield_set_typegroups, ++ [3] = is0_x3_keyfield_set_typegroups, ++ [2] = is0_x2_keyfield_set_typegroups, ++ [1] = is0_x1_keyfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = { ++ [12] = is2_x12_keyfield_set_typegroups, ++ [6] = is2_x6_keyfield_set_typegroups, ++ [3] = is2_x3_keyfield_set_typegroups, ++ [1] = is2_x1_keyfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = { ++ [1] = es0_x1_keyfield_set_typegroups, ++ [2] = NULL, ++}; ++ ++static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = { ++ [12] = es2_x12_keyfield_set_typegroups, ++ [6] = es2_x6_keyfield_set_typegroups, ++ [3] = es2_x3_keyfield_set_typegroups, ++ [1] = es2_x1_keyfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 3, ++ .value = 4, ++ }, ++ { ++ .offset = 103, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 206, ++ .width = 2, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 103, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 1, ++ .value = 1, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 95, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 190, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 19, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 38, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = { ++ [3] = is0_x3_actionfield_set_typegroups, ++ [2] = is0_x2_actionfield_set_typegroups, ++ [1] = is0_x1_actionfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = { ++ [3] = is2_x3_actionfield_set_typegroups, ++ [1] = is2_x1_actionfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = { ++ [1] = es0_x1_actionfield_set_typegroups, ++ [2] = NULL, ++}; ++ ++static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = { ++ [3] = es2_x3_actionfield_set_typegroups, ++ [1] = es2_x1_actionfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++/* Keyfieldset names */ ++static const char * const vcap_keyfield_set_names[] = { ++ [VCAP_KFS_NO_VALUE] = "(None)", ++ [VCAP_KFS_ARP] = "VCAP_KFS_ARP", ++ [VCAP_KFS_ETAG] = "VCAP_KFS_ETAG", ++ [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER", ++ [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP", ++ [VCAP_KFS_IP4_VID] = "VCAP_KFS_IP4_VID", ++ [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER", ++ [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD", ++ [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP", ++ [VCAP_KFS_IP6_VID] = "VCAP_KFS_IP6_VID", ++ [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE", ++ [VCAP_KFS_ISDX] = "VCAP_KFS_ISDX", ++ [VCAP_KFS_LL_FULL] = "VCAP_KFS_LL_FULL", ++ [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE", ++ [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC", ++ [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP", ++ [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4", ++ [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE", ++ [VCAP_KFS_OAM] = "VCAP_KFS_OAM", ++ [VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4", ++ [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4", ++ [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6", ++}; ++ ++/* Actionfieldset names */ ++static const char * const vcap_actionfield_set_names[] = { ++ [VCAP_AFS_NO_VALUE] = "(None)", ++ [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE", ++ [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION", ++ [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED", ++ [VCAP_AFS_ES0] = "VCAP_AFS_ES0", ++ [VCAP_AFS_FULL] = "VCAP_AFS_FULL", ++ [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP", ++}; ++ ++/* Keyfield names */ ++static const char * const vcap_keyfield_names[] = { ++ [VCAP_KF_NO_VALUE] = "(None)", ++ [VCAP_KF_8021BR_ECID_BASE] = "8021BR_ECID_BASE", ++ [VCAP_KF_8021BR_ECID_EXT] = "8021BR_ECID_EXT", ++ [VCAP_KF_8021BR_E_TAGGED] = "8021BR_E_TAGGED", ++ [VCAP_KF_8021BR_GRP] = "8021BR_GRP", ++ [VCAP_KF_8021BR_IGR_ECID_BASE] = "8021BR_IGR_ECID_BASE", ++ [VCAP_KF_8021BR_IGR_ECID_EXT] = "8021BR_IGR_ECID_EXT", ++ [VCAP_KF_8021Q_DEI0] = "8021Q_DEI0", ++ [VCAP_KF_8021Q_DEI1] = "8021Q_DEI1", ++ [VCAP_KF_8021Q_DEI2] = "8021Q_DEI2", ++ [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS", ++ [VCAP_KF_8021Q_PCP0] = "8021Q_PCP0", ++ [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1", ++ [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2", ++ [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS", ++ [VCAP_KF_8021Q_TPID] = "8021Q_TPID", ++ [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0", ++ [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1", ++ [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2", ++ [VCAP_KF_8021Q_VID0] = "8021Q_VID0", ++ [VCAP_KF_8021Q_VID1] = "8021Q_VID1", ++ [VCAP_KF_8021Q_VID2] = "8021Q_VID2", ++ [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS", ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS", ++ [VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS", ++ [VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID", ++ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS", ++ [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS", ++ [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE", ++ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS", ++ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS", ++ [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS", ++ [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS", ++ [VCAP_KF_COSID_CLS] = "COSID_CLS", ++ [VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA", ++ [VCAP_KF_ETYPE] = "ETYPE", ++ [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS", ++ [VCAP_KF_HOST_MATCH] = "HOST_MATCH", ++ [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK", ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG", ++ [VCAP_KF_IF_EGR_PORT_NO] = "IF_EGR_PORT_NO", ++ [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT", ++ [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK", ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3", ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG", ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL", ++ [VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL", ++ [VCAP_KF_IP4_IS] = "IP4_IS", ++ [VCAP_KF_IP_MC_IS] = "IP_MC_IS", ++ [VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE", ++ [VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS", ++ [VCAP_KF_ISDX_CLS] = "ISDX_CLS", ++ [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS", ++ [VCAP_KF_L2_BC_IS] = "L2_BC_IS", ++ [VCAP_KF_L2_DMAC] = "L2_DMAC", ++ [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE", ++ [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS", ++ [VCAP_KF_L2_LLC] = "L2_LLC", ++ [VCAP_KF_L2_MC_IS] = "L2_MC_IS", ++ [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0", ++ [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1", ++ [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2", ++ [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE", ++ [VCAP_KF_L2_SMAC] = "L2_SMAC", ++ [VCAP_KF_L2_SNAP] = "L2_SNAP", ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS", ++ [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS", ++ [VCAP_KF_L3_DSCP] = "L3_DSCP", ++ [VCAP_KF_L3_DST_IS] = "L3_DST_IS", ++ [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT", ++ [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE", ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN", ++ [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0", ++ [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP", ++ [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP", ++ [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP", ++ [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP", ++ [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO", ++ [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS", ++ [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD", ++ [VCAP_KF_L3_RT_IS] = "L3_RT_IS", ++ [VCAP_KF_L3_TOS] = "L3_TOS", ++ [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0", ++ [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM", ++ [VCAP_KF_L4_1588_VER] = "L4_1588_VER", ++ [VCAP_KF_L4_ACK] = "L4_ACK", ++ [VCAP_KF_L4_DPORT] = "L4_DPORT", ++ [VCAP_KF_L4_FIN] = "L4_FIN", ++ [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD", ++ [VCAP_KF_L4_PSH] = "L4_PSH", ++ [VCAP_KF_L4_RNG] = "L4_RNG", ++ [VCAP_KF_L4_RST] = "L4_RST", ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS", ++ [VCAP_KF_L4_SPORT] = "L4_SPORT", ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS", ++ [VCAP_KF_L4_SYN] = "L4_SYN", ++ [VCAP_KF_L4_URG] = "L4_URG", ++ [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS", ++ [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX", ++ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL", ++ [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG", ++ [VCAP_KF_MIRROR_PROBE] = "MIRROR_PROBE", ++ [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0", ++ [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED", ++ [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS", ++ [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS", ++ [VCAP_KF_OAM_MEPID] = "OAM_MEPID", ++ [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE", ++ [VCAP_KF_OAM_VER] = "OAM_VER", ++ [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS", ++ [VCAP_KF_PROT_ACTIVE] = "PROT_ACTIVE", ++ [VCAP_KF_TCP_IS] = "TCP_IS", ++ [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS", ++ [VCAP_KF_TYPE] = "TYPE", ++}; ++ ++/* Actionfield names */ ++static const char * const vcap_actionfield_names[] = { ++ [VCAP_AF_NO_VALUE] = "(None)", ++ [VCAP_AF_ACL_ID] = "ACL_ID", ++ [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL", ++ [VCAP_AF_CNT_ID] = "CNT_ID", ++ [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM", ++ [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM", ++ [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA", ++ [VCAP_AF_CPU_QU] = "CPU_QU", ++ [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM", ++ [VCAP_AF_DEI_A_VAL] = "DEI_A_VAL", ++ [VCAP_AF_DEI_B_VAL] = "DEI_B_VAL", ++ [VCAP_AF_DEI_C_VAL] = "DEI_C_VAL", ++ [VCAP_AF_DEI_ENA] = "DEI_ENA", ++ [VCAP_AF_DEI_VAL] = "DEI_VAL", ++ [VCAP_AF_DP_ENA] = "DP_ENA", ++ [VCAP_AF_DP_VAL] = "DP_VAL", ++ [VCAP_AF_DSCP_ENA] = "DSCP_ENA", ++ [VCAP_AF_DSCP_SEL] = "DSCP_SEL", ++ [VCAP_AF_DSCP_VAL] = "DSCP_VAL", ++ [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD", ++ [VCAP_AF_ESDX] = "ESDX", ++ [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA", ++ [VCAP_AF_FWD_MODE] = "FWD_MODE", ++ [VCAP_AF_FWD_SEL] = "FWD_SEL", ++ [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE", ++ [VCAP_AF_HOST_MATCH] = "HOST_MATCH", ++ [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL", ++ [VCAP_AF_INTR_ENA] = "INTR_ENA", ++ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL", ++ [VCAP_AF_ISDX_ENA] = "ISDX_ENA", ++ [VCAP_AF_ISDX_VAL] = "ISDX_VAL", ++ [VCAP_AF_LOOP_ENA] = "LOOP_ENA", ++ [VCAP_AF_LRN_DIS] = "LRN_DIS", ++ [VCAP_AF_MAP_IDX] = "MAP_IDX", ++ [VCAP_AF_MAP_KEY] = "MAP_KEY", ++ [VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL", ++ [VCAP_AF_MASK_MODE] = "MASK_MODE", ++ [VCAP_AF_MATCH_ID] = "MATCH_ID", ++ [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK", ++ [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA", ++ [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE", ++ [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID", ++ [VCAP_AF_NXT_IDX] = "NXT_IDX", ++ [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL", ++ [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK", ++ [VCAP_AF_PAG_VAL] = "PAG_VAL", ++ [VCAP_AF_PCP_A_VAL] = "PCP_A_VAL", ++ [VCAP_AF_PCP_B_VAL] = "PCP_B_VAL", ++ [VCAP_AF_PCP_C_VAL] = "PCP_C_VAL", ++ [VCAP_AF_PCP_ENA] = "PCP_ENA", ++ [VCAP_AF_PCP_VAL] = "PCP_VAL", ++ [VCAP_AF_PIPELINE_ACT] = "PIPELINE_ACT", ++ [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA", ++ [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT", ++ [VCAP_AF_POLICE_ENA] = "POLICE_ENA", ++ [VCAP_AF_POLICE_IDX] = "POLICE_IDX", ++ [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK", ++ [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY", ++ [VCAP_AF_POP_VAL] = "POP_VAL", ++ [VCAP_AF_PORT_MASK] = "PORT_MASK", ++ [VCAP_AF_PUSH_CUSTOMER_TAG] = "PUSH_CUSTOMER_TAG", ++ [VCAP_AF_PUSH_INNER_TAG] = "PUSH_INNER_TAG", ++ [VCAP_AF_PUSH_OUTER_TAG] = "PUSH_OUTER_TAG", ++ [VCAP_AF_QOS_ENA] = "QOS_ENA", ++ [VCAP_AF_QOS_VAL] = "QOS_VAL", ++ [VCAP_AF_REW_OP] = "REW_OP", ++ [VCAP_AF_RT_DIS] = "RT_DIS", ++ [VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA", ++ [VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL", ++ [VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL", ++ [VCAP_AF_TAG_A_TPID_SEL] = "TAG_A_TPID_SEL", ++ [VCAP_AF_TAG_A_VID_SEL] = "TAG_A_VID_SEL", ++ [VCAP_AF_TAG_B_DEI_SEL] = "TAG_B_DEI_SEL", ++ [VCAP_AF_TAG_B_PCP_SEL] = "TAG_B_PCP_SEL", ++ [VCAP_AF_TAG_B_TPID_SEL] = "TAG_B_TPID_SEL", ++ [VCAP_AF_TAG_B_VID_SEL] = "TAG_B_VID_SEL", ++ [VCAP_AF_TAG_C_DEI_SEL] = "TAG_C_DEI_SEL", ++ [VCAP_AF_TAG_C_PCP_SEL] = "TAG_C_PCP_SEL", ++ [VCAP_AF_TAG_C_TPID_SEL] = "TAG_C_TPID_SEL", ++ [VCAP_AF_TAG_C_VID_SEL] = "TAG_C_VID_SEL", ++ [VCAP_AF_TYPE] = "TYPE", ++ [VCAP_AF_UNTAG_VID_ENA] = "UNTAG_VID_ENA", ++ [VCAP_AF_VID_A_VAL] = "VID_A_VAL", ++ [VCAP_AF_VID_B_VAL] = "VID_B_VAL", ++ [VCAP_AF_VID_C_VAL] = "VID_C_VAL", ++ [VCAP_AF_VID_VAL] = "VID_VAL", ++}; ++ ++/* VCAPs */ ++const struct vcap_info lan969x_vcaps[] = { ++ [VCAP_TYPE_IS0] = { ++ .name = "is0", ++ .rows = 256, ++ .sw_count = 12, ++ .sw_width = 52, ++ .sticky_width = 1, ++ .act_width = 103, ++ .default_cnt = 70, ++ .require_cnt_dis = 0, ++ .version = 1, ++ .keyfield_set = is0_keyfield_set, ++ .keyfield_set_size = ARRAY_SIZE(is0_keyfield_set), ++ .actionfield_set = is0_actionfield_set, ++ .actionfield_set_size = ARRAY_SIZE(is0_actionfield_set), ++ .keyfield_set_map = is0_keyfield_set_map, ++ .keyfield_set_map_size = is0_keyfield_set_map_size, ++ .actionfield_set_map = is0_actionfield_set_map, ++ .actionfield_set_map_size = is0_actionfield_set_map_size, ++ .keyfield_set_typegroups = is0_keyfield_set_typegroups, ++ .actionfield_set_typegroups = is0_actionfield_set_typegroups, ++ }, ++ [VCAP_TYPE_IS2] = { ++ .name = "is2", ++ .rows = 256, ++ .sw_count = 12, ++ .sw_width = 52, ++ .sticky_width = 1, ++ .act_width = 103, ++ .default_cnt = 38, ++ .require_cnt_dis = 0, ++ .version = 1, ++ .keyfield_set = is2_keyfield_set, ++ .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set), ++ .actionfield_set = is2_actionfield_set, ++ .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set), ++ .keyfield_set_map = is2_keyfield_set_map, ++ .keyfield_set_map_size = is2_keyfield_set_map_size, ++ .actionfield_set_map = is2_actionfield_set_map, ++ .actionfield_set_map_size = is2_actionfield_set_map_size, ++ .keyfield_set_typegroups = is2_keyfield_set_typegroups, ++ .actionfield_set_typegroups = is2_actionfield_set_typegroups, ++ }, ++ [VCAP_TYPE_ES0] = { ++ .name = "es0", ++ .rows = 1536, ++ .sw_count = 1, ++ .sw_width = 51, ++ .sticky_width = 1, ++ .act_width = 469, ++ .default_cnt = 35, ++ .require_cnt_dis = 0, ++ .version = 1, ++ .keyfield_set = es0_keyfield_set, ++ .keyfield_set_size = ARRAY_SIZE(es0_keyfield_set), ++ .actionfield_set = es0_actionfield_set, ++ .actionfield_set_size = ARRAY_SIZE(es0_actionfield_set), ++ .keyfield_set_map = es0_keyfield_set_map, ++ .keyfield_set_map_size = es0_keyfield_set_map_size, ++ .actionfield_set_map = es0_actionfield_set_map, ++ .actionfield_set_map_size = es0_actionfield_set_map_size, ++ .keyfield_set_typegroups = es0_keyfield_set_typegroups, ++ .actionfield_set_typegroups = es0_actionfield_set_typegroups, ++ }, ++ [VCAP_TYPE_ES2] = { ++ .name = "es2", ++ .rows = 256, ++ .sw_count = 12, ++ .sw_width = 52, ++ .sticky_width = 1, ++ .act_width = 19, ++ .default_cnt = 39, ++ .require_cnt_dis = 0, ++ .version = 1, ++ .keyfield_set = es2_keyfield_set, ++ .keyfield_set_size = ARRAY_SIZE(es2_keyfield_set), ++ .actionfield_set = es2_actionfield_set, ++ .actionfield_set_size = ARRAY_SIZE(es2_actionfield_set), ++ .keyfield_set_map = es2_keyfield_set_map, ++ .keyfield_set_map_size = es2_keyfield_set_map_size, ++ .actionfield_set_map = es2_actionfield_set_map, ++ .actionfield_set_map_size = es2_actionfield_set_map_size, ++ .keyfield_set_typegroups = es2_keyfield_set_typegroups, ++ .actionfield_set_typegroups = es2_actionfield_set_typegroups, ++ }, ++}; ++ ++const struct vcap_statistics lan969x_vcap_stats = { ++ .name = "lan969x", ++ .count = 4, ++ .keyfield_set_names = vcap_keyfield_set_names, ++ .actionfield_set_names = vcap_actionfield_set_names, ++ .keyfield_names = vcap_keyfield_names, ++ .actionfield_names = vcap_actionfield_names, ++}; diff --git a/target/linux/microchipsw/patches-6.12/0058-v6.13-net-lan969x-add-VCAP-configuration-data.patch b/target/linux/microchipsw/patches-6.12/0058-v6.13-net-lan969x-add-VCAP-configuration-data.patch new file mode 100644 index 0000000000..803c991d54 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0058-v6.13-net-lan969x-add-VCAP-configuration-data.patch @@ -0,0 +1,166 @@ +From 4a4336e333f869544dabc729812f57f99f5f2ff8 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 1 Nov 2024 08:09:12 +0100 +Subject: [PATCH 63/82] net: lan969x: add VCAP configuration data +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add configuration data (for consumption by the VCAP API) for the four +VCAP's that we are going to support. The following VCAP's will be +supported: + + - VCAP CLM: (also known as IS0) is part of the analyzer and enables + frame classification using VCAP functionality. + + - VCAP IS2: is part of ANA_ACL and enables access control lists, using + VCAP functionality. + + - VCAP ES0: is part of the rewriter and enables rewriting of frames + using VCAP functionality. + + - VCAP ES2: is part of EACL and enables egress access control lists + using VCAP functionality + +The two VCAP's: CLM and IS2 use shared resources from the SUPER VCAP. +The SUPER VCAP is a shared pool of 6 blocks that can be distributed +freely among CLM and IS2. Each block in the pool has 3,072 addresses +with entries, actions, and counters. ES0 and ES2 does not use shared +resources. + +In the configuration data for lan969x CLM uses blocks 2-4 with a total +of 6 lookups. IS2 uses blocks 0-1 with a total of 4 lookups. + +Reviewed-by: Steen Hegelund +Reviewed-by: Jens Emil Schulz Østergaard +Signed-off-by: Daniel Machon +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/microchip/lan969x/Makefile | 2 +- + .../net/ethernet/microchip/lan969x/lan969x.c | 1 + + .../net/ethernet/microchip/lan969x/lan969x.h | 3 + + .../microchip/lan969x/lan969x_vcap_impl.c | 85 +++++++++++++++++++ + 4 files changed, 90 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/microchip/lan969x/lan969x_vcap_impl.c + +--- a/drivers/net/ethernet/microchip/lan969x/Makefile ++++ b/drivers/net/ethernet/microchip/lan969x/Makefile +@@ -6,7 +6,7 @@ + obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o + + lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \ +- lan969x_vcap_ag_api.o ++ lan969x_vcap_ag_api.o lan969x_vcap_impl.o + + # Provide include files + ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.c +@@ -321,6 +321,7 @@ static const struct sparx5_consts lan969 + .tod_pin = 4, + .vcaps = lan969x_vcaps, + .vcap_stats = &lan969x_vcap_stats, ++ .vcaps_cfg = lan969x_vcap_inst_cfg, + }; + + static const struct sparx5_ops lan969x_ops = { +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.h ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x.h +@@ -18,6 +18,9 @@ extern const struct sparx5_match_data la + extern const struct vcap_statistics lan969x_vcap_stats; + extern const struct vcap_info lan969x_vcaps[]; + ++/* lan969x_vcap_impl.c */ ++extern const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[]; ++ + /* lan969x_regs.c */ + extern const unsigned int lan969x_tsize[TSIZE_LAST]; + extern const unsigned int lan969x_raddr[RADDR_LAST]; +--- /dev/null ++++ b/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_impl.c +@@ -0,0 +1,85 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include "vcap_api.h" ++#include "lan969x.h" ++ ++const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[] = { ++ { ++ .vtype = VCAP_TYPE_IS0, /* CLM-0 */ ++ .vinst = 0, ++ .map_id = 1, ++ .lookups = SPARX5_IS0_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, ++ .first_cid = SPARX5_VCAP_CID_IS0_L0, ++ .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1, ++ .blockno = 2, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_IS0, /* CLM-1 */ ++ .vinst = 1, ++ .map_id = 2, ++ .lookups = SPARX5_IS0_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, ++ .first_cid = SPARX5_VCAP_CID_IS0_L2, ++ .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1, ++ .blockno = 3, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_IS0, /* CLM-2 */ ++ .vinst = 2, ++ .map_id = 3, ++ .lookups = SPARX5_IS0_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, ++ .first_cid = SPARX5_VCAP_CID_IS0_L4, ++ .last_cid = SPARX5_VCAP_CID_IS0_MAX, ++ .blockno = 4, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_IS2, /* IS2-0 */ ++ .vinst = 0, ++ .map_id = 4, ++ .lookups = SPARX5_IS2_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, ++ .first_cid = SPARX5_VCAP_CID_IS2_L0, ++ .last_cid = SPARX5_VCAP_CID_IS2_L2 - 1, ++ .blockno = 0, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_IS2, /* IS2-1 */ ++ .vinst = 1, ++ .map_id = 5, ++ .lookups = SPARX5_IS2_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, ++ .first_cid = SPARX5_VCAP_CID_IS2_L2, ++ .last_cid = SPARX5_VCAP_CID_IS2_MAX, ++ .blockno = 1, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_ES0, ++ .lookups = SPARX5_ES0_LOOKUPS, ++ .lookups_per_instance = SPARX5_ES0_LOOKUPS, ++ .first_cid = SPARX5_VCAP_CID_ES0_L0, ++ .last_cid = SPARX5_VCAP_CID_ES0_MAX, ++ .count = 1536, ++ .ingress = false, ++ }, ++ { ++ .vtype = VCAP_TYPE_ES2, ++ .lookups = SPARX5_ES2_LOOKUPS, ++ .lookups_per_instance = SPARX5_ES2_LOOKUPS, ++ .first_cid = SPARX5_VCAP_CID_ES2_L0, ++ .last_cid = SPARX5_VCAP_CID_ES2_MAX, ++ .count = 1024, ++ .ingress = false, ++ }, ++}; diff --git a/target/linux/microchipsw/patches-6.12/0059-v6.13-net-sparx5-add-missing-lan969x-Kconfig-dependency.patch b/target/linux/microchipsw/patches-6.12/0059-v6.13-net-sparx5-add-missing-lan969x-Kconfig-dependency.patch new file mode 100644 index 0000000000..fb93fd7f74 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0059-v6.13-net-sparx5-add-missing-lan969x-Kconfig-dependency.patch @@ -0,0 +1,45 @@ +From e63e43479af9d5817eecd34e26af67a5064937b4 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann +Date: Wed, 13 Nov 2024 12:55:08 +0100 +Subject: [PATCH 64/82] net: sparx5: add missing lan969x Kconfig dependency + +The sparx5 switchdev driver can be built either with or without support +for the Lan969x switch. However, it cannot be built-in when the lan969x +driver is a loadable module because of a link-time dependency: + +arm-linux-gnueabi-ld: drivers/net/ethernet/microchip/sparx5/sparx5_main.o:(.rodata+0xd44): undefined reference to `lan969x_desc' + +Add a Kconfig dependency to reflect this in Kconfig, allowing all +the valid configurations but forcing sparx5 to be a loadable module +as well if lan969x is. + +Fixes: 98a01119608d ("net: sparx5: add compatible string for lan969x") +Signed-off-by: Arnd Bergmann +Reviewed-by: Daniel Machon +Link: https://patch.msgid.link/20241113115513.4132548-1-arnd@kernel.org +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/lan969x/Kconfig | 2 +- + drivers/net/ethernet/microchip/lan969x/Makefile | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/microchip/lan969x/Kconfig ++++ b/drivers/net/ethernet/microchip/lan969x/Kconfig +@@ -1,5 +1,5 @@ + config LAN969X_SWITCH +- tristate "Lan969x switch driver" ++ bool "Lan969x switch driver" + depends on SPARX5_SWITCH + help + This driver supports the lan969x family of network switch devices. +--- a/drivers/net/ethernet/microchip/lan969x/Makefile ++++ b/drivers/net/ethernet/microchip/lan969x/Makefile +@@ -3,7 +3,7 @@ + # Makefile for the Microchip lan969x network device drivers. + # + +-obj-$(CONFIG_LAN969X_SWITCH) += lan969x-switch.o ++obj-$(CONFIG_SPARX5_SWITCH) += lan969x-switch.o + + lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \ + lan969x_vcap_ag_api.o lan969x_vcap_impl.o diff --git a/target/linux/microchipsw/patches-6.12/0060-v6.13-net-lan969x-fix-cyclic-dependency-reported-by-depmod.patch b/target/linux/microchipsw/patches-6.12/0060-v6.13-net-lan969x-fix-cyclic-dependency-reported-by-depmod.patch new file mode 100644 index 0000000000..5c66df5c52 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0060-v6.13-net-lan969x-fix-cyclic-dependency-reported-by-depmod.patch @@ -0,0 +1,9733 @@ +From 8b097eba8b5e48efe73d5298ff2dce11cd9d16cb Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 5 Dec 2024 14:54:24 +0100 +Subject: [PATCH 65/82] net: lan969x: fix cyclic dependency reported by depmod + +Depmod reports a cyclic dependency between modules sparx5-switch.ko and +lan969x-switch.ko: + +depmod: ERROR: Cycle detected: lan969x_switch -> sparx5_switch -> lan969x_switch +depmod: ERROR: Found 2 modules in dependency cycles! +make[2]: *** [scripts/Makefile.modinst:132: depmod] Error 1 +make: *** [Makefile:224: __sub-make] Error 2 + +This makes sense, as they both require symbols from each other. + +Fix this by compiling lan969x support into the sparx5-switch.ko module. +In order to do this, in a sensible way, we move the lan969x/ dir into +the sparx5/ dir and do some code cleanup of code that is no longer +required. + +After this patch, depmod will no longer complain, as lan969x support is +compiled into the sparx5-swicth.ko module, and can no longer be compiled +as a standalone module. + +Fixes: 98a01119608d ("net: sparx5: add compatible string for lan969x") +Signed-off-by: Daniel Machon +Signed-off-by: David S. Miller +--- + MAINTAINERS | 2 +- + drivers/net/ethernet/microchip/Kconfig | 1 - + drivers/net/ethernet/microchip/Makefile | 1 - + drivers/net/ethernet/microchip/lan969x/Kconfig | 5 ----- + drivers/net/ethernet/microchip/lan969x/Makefile | 13 ------------- + drivers/net/ethernet/microchip/sparx5/Kconfig | 6 ++++++ + drivers/net/ethernet/microchip/sparx5/Makefile | 6 ++++++ + .../microchip/{ => sparx5}/lan969x/lan969x.c | 5 ----- + .../microchip/{ => sparx5}/lan969x/lan969x.h | 0 + .../{ => sparx5}/lan969x/lan969x_calendar.c | 0 + .../microchip/{ => sparx5}/lan969x/lan969x_regs.c | 0 + .../{ => sparx5}/lan969x/lan969x_vcap_ag_api.c | 0 + .../{ => sparx5}/lan969x/lan969x_vcap_impl.c | 0 + .../net/ethernet/microchip/sparx5/sparx5_calendar.c | 2 -- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 4 ++-- + drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c | 1 - + 16 files changed, 15 insertions(+), 31 deletions(-) + delete mode 100644 drivers/net/ethernet/microchip/lan969x/Kconfig + delete mode 100644 drivers/net/ethernet/microchip/lan969x/Makefile + rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x.c (98%) + rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x.h (100%) + rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_calendar.c (100%) + rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_regs.c (100%) + rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_vcap_ag_api.c (100%) + rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_vcap_impl.c (100%) + +--- a/MAINTAINERS ++++ b/MAINTAINERS +@@ -15152,7 +15152,7 @@ M: Daniel Machon +--- a/drivers/net/ethernet/microchip/Kconfig ++++ b/drivers/net/ethernet/microchip/Kconfig +@@ -59,7 +59,6 @@ config LAN743X + + source "drivers/net/ethernet/microchip/lan865x/Kconfig" + source "drivers/net/ethernet/microchip/lan966x/Kconfig" +-source "drivers/net/ethernet/microchip/lan969x/Kconfig" + source "drivers/net/ethernet/microchip/sparx5/Kconfig" + source "drivers/net/ethernet/microchip/vcap/Kconfig" + source "drivers/net/ethernet/microchip/fdma/Kconfig" +--- a/drivers/net/ethernet/microchip/Makefile ++++ b/drivers/net/ethernet/microchip/Makefile +@@ -11,7 +11,6 @@ lan743x-objs := lan743x_main.o lan743x_e + + obj-$(CONFIG_LAN865X) += lan865x/ + obj-$(CONFIG_LAN966X_SWITCH) += lan966x/ +-obj-$(CONFIG_LAN969X_SWITCH) += lan969x/ + obj-$(CONFIG_SPARX5_SWITCH) += sparx5/ + obj-$(CONFIG_VCAP) += vcap/ + obj-$(CONFIG_FDMA) += fdma/ +--- a/drivers/net/ethernet/microchip/lan969x/Kconfig ++++ /dev/null +@@ -1,5 +0,0 @@ +-config LAN969X_SWITCH +- bool "Lan969x switch driver" +- depends on SPARX5_SWITCH +- help +- This driver supports the lan969x family of network switch devices. +--- a/drivers/net/ethernet/microchip/lan969x/Makefile ++++ /dev/null +@@ -1,13 +0,0 @@ +-# SPDX-License-Identifier: GPL-2.0-only +-# +-# Makefile for the Microchip lan969x network device drivers. +-# +- +-obj-$(CONFIG_SPARX5_SWITCH) += lan969x-switch.o +- +-lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \ +- lan969x_vcap_ag_api.o lan969x_vcap_impl.o +- +-# Provide include files +-ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma +-ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap +--- a/drivers/net/ethernet/microchip/sparx5/Kconfig ++++ b/drivers/net/ethernet/microchip/sparx5/Kconfig +@@ -24,3 +24,9 @@ config SPARX5_DCB + DSCP and PCP. + + If unsure, set to Y. ++ ++config LAN969X_SWITCH ++ bool "Lan969x switch driver" ++ depends on SPARX5_SWITCH ++ help ++ This driver supports the lan969x family of network switch devices. +--- a/drivers/net/ethernet/microchip/sparx5/Makefile ++++ b/drivers/net/ethernet/microchip/sparx5/Makefile +@@ -16,6 +16,12 @@ sparx5-switch-y := sparx5_main.o sparx5 + sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o + sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o + ++sparx5-switch-$(CONFIG_LAN969X_SWITCH) += lan969x/lan969x_regs.o \ ++ lan969x/lan969x.o \ ++ lan969x/lan969x_calendar.o \ ++ lan969x/lan969x_vcap_ag_api.o \ ++ lan969x/lan969x_vcap_impl.o ++ + # Provide include files + ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap + ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.c ++++ /dev/null +@@ -1,353 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* Microchip lan969x Switch driver +- * +- * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. +- */ +- +-#include "lan969x.h" +- +-#define LAN969X_SDLB_GRP_CNT 5 +-#define LAN969X_HSCH_LEAK_GRP_CNT 4 +- +-static const struct sparx5_main_io_resource lan969x_main_iomap[] = { +- { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ +- { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ +- { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */ +- { TARGET_QS, 0x2030000, 1 }, /* 0xe2030000 */ +- { TARGET_PTP, 0x2040000, 1 }, /* 0xe2040000 */ +- { TARGET_ANA_ACL, 0x2050000, 1 }, /* 0xe2050000 */ +- { TARGET_LRN, 0x2060000, 1 }, /* 0xe2060000 */ +- { TARGET_VCAP_SUPER, 0x2080000, 1 }, /* 0xe2080000 */ +- { TARGET_QSYS, 0x20a0000, 1 }, /* 0xe20a0000 */ +- { TARGET_QFWD, 0x20b0000, 1 }, /* 0xe20b0000 */ +- { TARGET_XQS, 0x20c0000, 1 }, /* 0xe20c0000 */ +- { TARGET_VCAP_ES2, 0x20d0000, 1 }, /* 0xe20d0000 */ +- { TARGET_VCAP_ES0, 0x20e0000, 1 }, /* 0xe20e0000 */ +- { TARGET_ANA_AC_POL, 0x2200000, 1 }, /* 0xe2200000 */ +- { TARGET_QRES, 0x2280000, 1 }, /* 0xe2280000 */ +- { TARGET_EACL, 0x22c0000, 1 }, /* 0xe22c0000 */ +- { TARGET_ANA_CL, 0x2400000, 1 }, /* 0xe2400000 */ +- { TARGET_ANA_L3, 0x2480000, 1 }, /* 0xe2480000 */ +- { TARGET_ANA_AC_SDLB, 0x2500000, 1 }, /* 0xe2500000 */ +- { TARGET_HSCH, 0x2580000, 1 }, /* 0xe2580000 */ +- { TARGET_REW, 0x2600000, 1 }, /* 0xe2600000 */ +- { TARGET_ANA_L2, 0x2800000, 1 }, /* 0xe2800000 */ +- { TARGET_ANA_AC, 0x2900000, 1 }, /* 0xe2900000 */ +- { TARGET_VOP, 0x2a00000, 1 }, /* 0xe2a00000 */ +- { TARGET_DEV2G5, 0x3004000, 1 }, /* 0xe3004000 */ +- { TARGET_DEV10G, 0x3008000, 1 }, /* 0xe3008000 */ +- { TARGET_PCS10G_BR, 0x300c000, 1 }, /* 0xe300c000 */ +- { TARGET_DEV2G5 + 1, 0x3010000, 1 }, /* 0xe3010000 */ +- { TARGET_DEV2G5 + 2, 0x3014000, 1 }, /* 0xe3014000 */ +- { TARGET_DEV2G5 + 3, 0x3018000, 1 }, /* 0xe3018000 */ +- { TARGET_DEV2G5 + 4, 0x301c000, 1 }, /* 0xe301c000 */ +- { TARGET_DEV10G + 1, 0x3020000, 1 }, /* 0xe3020000 */ +- { TARGET_PCS10G_BR + 1, 0x3024000, 1 }, /* 0xe3024000 */ +- { TARGET_DEV2G5 + 5, 0x3028000, 1 }, /* 0xe3028000 */ +- { TARGET_DEV2G5 + 6, 0x302c000, 1 }, /* 0xe302c000 */ +- { TARGET_DEV2G5 + 7, 0x3030000, 1 }, /* 0xe3030000 */ +- { TARGET_DEV2G5 + 8, 0x3034000, 1 }, /* 0xe3034000 */ +- { TARGET_DEV10G + 2, 0x3038000, 1 }, /* 0xe3038000 */ +- { TARGET_PCS10G_BR + 2, 0x303c000, 1 }, /* 0xe303c000 */ +- { TARGET_DEV2G5 + 9, 0x3040000, 1 }, /* 0xe3040000 */ +- { TARGET_DEV5G, 0x3044000, 1 }, /* 0xe3044000 */ +- { TARGET_PCS5G_BR, 0x3048000, 1 }, /* 0xe3048000 */ +- { TARGET_DEV2G5 + 10, 0x304c000, 1 }, /* 0xe304c000 */ +- { TARGET_DEV2G5 + 11, 0x3050000, 1 }, /* 0xe3050000 */ +- { TARGET_DEV2G5 + 12, 0x3054000, 1 }, /* 0xe3054000 */ +- { TARGET_DEV10G + 3, 0x3058000, 1 }, /* 0xe3058000 */ +- { TARGET_PCS10G_BR + 3, 0x305c000, 1 }, /* 0xe305c000 */ +- { TARGET_DEV2G5 + 13, 0x3060000, 1 }, /* 0xe3060000 */ +- { TARGET_DEV5G + 1, 0x3064000, 1 }, /* 0xe3064000 */ +- { TARGET_PCS5G_BR + 1, 0x3068000, 1 }, /* 0xe3068000 */ +- { TARGET_DEV2G5 + 14, 0x306c000, 1 }, /* 0xe306c000 */ +- { TARGET_DEV2G5 + 15, 0x3070000, 1 }, /* 0xe3070000 */ +- { TARGET_DEV2G5 + 16, 0x3074000, 1 }, /* 0xe3074000 */ +- { TARGET_DEV10G + 4, 0x3078000, 1 }, /* 0xe3078000 */ +- { TARGET_PCS10G_BR + 4, 0x307c000, 1 }, /* 0xe307c000 */ +- { TARGET_DEV2G5 + 17, 0x3080000, 1 }, /* 0xe3080000 */ +- { TARGET_DEV5G + 2, 0x3084000, 1 }, /* 0xe3084000 */ +- { TARGET_PCS5G_BR + 2, 0x3088000, 1 }, /* 0xe3088000 */ +- { TARGET_DEV2G5 + 18, 0x308c000, 1 }, /* 0xe308c000 */ +- { TARGET_DEV2G5 + 19, 0x3090000, 1 }, /* 0xe3090000 */ +- { TARGET_DEV2G5 + 20, 0x3094000, 1 }, /* 0xe3094000 */ +- { TARGET_DEV10G + 5, 0x3098000, 1 }, /* 0xe3098000 */ +- { TARGET_PCS10G_BR + 5, 0x309c000, 1 }, /* 0xe309c000 */ +- { TARGET_DEV2G5 + 21, 0x30a0000, 1 }, /* 0xe30a0000 */ +- { TARGET_DEV5G + 3, 0x30a4000, 1 }, /* 0xe30a4000 */ +- { TARGET_PCS5G_BR + 3, 0x30a8000, 1 }, /* 0xe30a8000 */ +- { TARGET_DEV2G5 + 22, 0x30ac000, 1 }, /* 0xe30ac000 */ +- { TARGET_DEV2G5 + 23, 0x30b0000, 1 }, /* 0xe30b0000 */ +- { TARGET_DEV2G5 + 24, 0x30b4000, 1 }, /* 0xe30b4000 */ +- { TARGET_DEV10G + 6, 0x30b8000, 1 }, /* 0xe30b8000 */ +- { TARGET_PCS10G_BR + 6, 0x30bc000, 1 }, /* 0xe30bc000 */ +- { TARGET_DEV2G5 + 25, 0x30c0000, 1 }, /* 0xe30c0000 */ +- { TARGET_DEV10G + 7, 0x30c4000, 1 }, /* 0xe30c4000 */ +- { TARGET_PCS10G_BR + 7, 0x30c8000, 1 }, /* 0xe30c8000 */ +- { TARGET_DEV2G5 + 26, 0x30cc000, 1 }, /* 0xe30cc000 */ +- { TARGET_DEV10G + 8, 0x30d0000, 1 }, /* 0xe30d0000 */ +- { TARGET_PCS10G_BR + 8, 0x30d4000, 1 }, /* 0xe30d4000 */ +- { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ +- { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ +- { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ +- { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ +- { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ +- { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ +-}; +- +-static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { +- { 1000000000, 8192 / 2, 64 }, /* 1 G */ +- { 500000000, 8192 / 2, 64 }, /* 500 M */ +- { 100000000, 8192 / 4, 64 }, /* 100 M */ +- { 50000000, 8192 / 4, 64 }, /* 50 M */ +- { 5000000, 8192 / 8, 64 }, /* 10 M */ +-}; +- +-static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = { +- 655355, 1048568, 6553550, 10485680 +-}; +- +-static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx) +-{ +- return &lan969x_sdlb_groups[idx]; +-} +- +-static u32 lan969x_get_hsch_max_group_rate(int grp) +-{ +- return lan969x_hsch_max_group_rate[grp]; +-} +- +-static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) +-{ +- if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port)) +- return port; +- +- /* 10G */ +- switch (port) { +- case 0: +- return 12; +- case 4: +- return 13; +- case 8: +- return 14; +- case 12: +- return 0; +- default: +- return port; +- } +-} +- +-static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) +-{ +- if (lan969x_port_is_5g(port)) { +- switch (port) { +- case 9: +- return 0; +- case 13: +- return 1; +- case 17: +- return 2; +- case 21: +- return 3; +- } +- } +- +- if (lan969x_port_is_10g(port)) { +- switch (port) { +- case 0: +- return 0; +- case 4: +- return 1; +- case 8: +- return 2; +- case 12: +- return 3; +- case 16: +- return 4; +- case 20: +- return 5; +- case 24: +- return 6; +- case 25: +- return 7; +- case 26: +- return 8; +- case 27: +- return 9; +- } +- } +- +- /* 2g5 port */ +- return port; +-} +- +-static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, +- struct sparx5_port_config *conf) +-{ +- u32 portno = port->portno; +- u32 inst; +- +- if (port->conf.portmode == conf->portmode) +- return 0; /* Nothing to do */ +- +- switch (conf->portmode) { +- case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q' */ +- inst = (portno - portno % 4) / 4; +- spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); +- break; +- default: +- break; +- } +- return 0; +-} +- +-static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args) +-{ +- int budget = SPARX5_MAX_PTP_ID; +- struct sparx5 *sparx5 = args; +- +- while (budget--) { +- struct sk_buff *skb, *skb_tmp, *skb_match = NULL; +- struct skb_shared_hwtstamps shhwtstamps; +- struct sparx5_port *port; +- struct timespec64 ts; +- unsigned long flags; +- u32 val, id, txport; +- u32 delay; +- +- val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); +- +- /* Check if a timestamp can be retrieved */ +- if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) +- break; +- +- WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL); +- +- if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX)) +- continue; +- +- /* Retrieve the ts Tx port */ +- txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val); +- +- /* Retrieve its associated skb */ +- port = sparx5->ports[txport]; +- +- /* Retrieve the delay */ +- delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); +- delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay); +- +- /* Get next timestamp from fifo, which needs to be the +- * rx timestamp which represents the id of the frame +- */ +- spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), +- PTP_TWOSTEP_CTRL_PTP_NXT, +- sparx5, PTP_TWOSTEP_CTRL); +- +- val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); +- +- /* Check if a timestamp can be retrieved */ +- if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) +- break; +- +- /* Read RX timestamping to get the ID */ +- id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); +- id <<= 8; +- id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS); +- +- spin_lock_irqsave(&port->tx_skbs.lock, flags); +- skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { +- if (SPARX5_SKB_CB(skb)->ts_id != id) +- continue; +- +- __skb_unlink(skb, &port->tx_skbs); +- skb_match = skb; +- break; +- } +- spin_unlock_irqrestore(&port->tx_skbs.lock, flags); +- +- /* Next ts */ +- spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), +- PTP_TWOSTEP_CTRL_PTP_NXT, +- sparx5, PTP_TWOSTEP_CTRL); +- +- if (WARN_ON(!skb_match)) +- continue; +- +- spin_lock(&sparx5->ptp_ts_id_lock); +- sparx5->ptp_skbs--; +- spin_unlock(&sparx5->ptp_ts_id_lock); +- +- /* Get the h/w timestamp */ +- sparx5_get_hwtimestamp(sparx5, &ts, delay); +- +- /* Set the timestamp in the skb */ +- shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); +- skb_tstamp_tx(skb_match, &shhwtstamps); +- +- dev_kfree_skb_any(skb_match); +- } +- +- return IRQ_HANDLED; +-} +- +-static const struct sparx5_regs lan969x_regs = { +- .tsize = lan969x_tsize, +- .gaddr = lan969x_gaddr, +- .gcnt = lan969x_gcnt, +- .gsize = lan969x_gsize, +- .raddr = lan969x_raddr, +- .rcnt = lan969x_rcnt, +- .fpos = lan969x_fpos, +- .fsize = lan969x_fsize, +-}; +- +-static const struct sparx5_consts lan969x_consts = { +- .n_ports = 30, +- .n_ports_all = 35, +- .n_hsch_l1_elems = 32, +- .n_hsch_queues = 4, +- .n_lb_groups = 5, +- .n_pgids = 1054, /* (1024 + n_ports) */ +- .n_sio_clks = 1, +- .n_own_upsids = 1, +- .n_auto_cals = 4, +- .n_filters = 256, +- .n_gates = 256, +- .n_sdlbs = 496, +- .n_dsm_cal_taxis = 5, +- .buf_size = 1572864, +- .qres_max_prio_idx = 315, +- .qres_max_colour_idx = 323, +- .tod_pin = 4, +- .vcaps = lan969x_vcaps, +- .vcap_stats = &lan969x_vcap_stats, +- .vcaps_cfg = lan969x_vcap_inst_cfg, +-}; +- +-static const struct sparx5_ops lan969x_ops = { +- .is_port_2g5 = &lan969x_port_is_2g5, +- .is_port_5g = &lan969x_port_is_5g, +- .is_port_10g = &lan969x_port_is_10g, +- .is_port_25g = &lan969x_port_is_25g, +- .get_port_dev_index = &lan969x_port_dev_mapping, +- .get_port_dev_bit = &lan969x_get_dev_mode_bit, +- .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, +- .get_sdlb_group = &lan969x_get_sdlb_group, +- .set_port_mux = &lan969x_port_mux_set, +- .ptp_irq_handler = &lan969x_ptp_irq_handler, +- .dsm_calendar_calc = &lan969x_dsm_calendar_calc, +-}; +- +-const struct sparx5_match_data lan969x_desc = { +- .iomap = lan969x_main_iomap, +- .iomap_size = ARRAY_SIZE(lan969x_main_iomap), +- .ioranges = 2, +- .regs = &lan969x_regs, +- .consts = &lan969x_consts, +- .ops = &lan969x_ops, +-}; +-EXPORT_SYMBOL_GPL(lan969x_desc); +- +-MODULE_DESCRIPTION("Microchip lan969x switch driver"); +-MODULE_AUTHOR("Daniel Machon "); +-MODULE_LICENSE("Dual MIT/GPL"); +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c +@@ -0,0 +1,348 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. ++ */ ++ ++#include "lan969x.h" ++ ++#define LAN969X_SDLB_GRP_CNT 5 ++#define LAN969X_HSCH_LEAK_GRP_CNT 4 ++ ++static const struct sparx5_main_io_resource lan969x_main_iomap[] = { ++ { TARGET_CPU, 0xc0000, 0 }, /* 0xe00c0000 */ ++ { TARGET_FDMA, 0xc0400, 0 }, /* 0xe00c0400 */ ++ { TARGET_GCB, 0x2010000, 1 }, /* 0xe2010000 */ ++ { TARGET_QS, 0x2030000, 1 }, /* 0xe2030000 */ ++ { TARGET_PTP, 0x2040000, 1 }, /* 0xe2040000 */ ++ { TARGET_ANA_ACL, 0x2050000, 1 }, /* 0xe2050000 */ ++ { TARGET_LRN, 0x2060000, 1 }, /* 0xe2060000 */ ++ { TARGET_VCAP_SUPER, 0x2080000, 1 }, /* 0xe2080000 */ ++ { TARGET_QSYS, 0x20a0000, 1 }, /* 0xe20a0000 */ ++ { TARGET_QFWD, 0x20b0000, 1 }, /* 0xe20b0000 */ ++ { TARGET_XQS, 0x20c0000, 1 }, /* 0xe20c0000 */ ++ { TARGET_VCAP_ES2, 0x20d0000, 1 }, /* 0xe20d0000 */ ++ { TARGET_VCAP_ES0, 0x20e0000, 1 }, /* 0xe20e0000 */ ++ { TARGET_ANA_AC_POL, 0x2200000, 1 }, /* 0xe2200000 */ ++ { TARGET_QRES, 0x2280000, 1 }, /* 0xe2280000 */ ++ { TARGET_EACL, 0x22c0000, 1 }, /* 0xe22c0000 */ ++ { TARGET_ANA_CL, 0x2400000, 1 }, /* 0xe2400000 */ ++ { TARGET_ANA_L3, 0x2480000, 1 }, /* 0xe2480000 */ ++ { TARGET_ANA_AC_SDLB, 0x2500000, 1 }, /* 0xe2500000 */ ++ { TARGET_HSCH, 0x2580000, 1 }, /* 0xe2580000 */ ++ { TARGET_REW, 0x2600000, 1 }, /* 0xe2600000 */ ++ { TARGET_ANA_L2, 0x2800000, 1 }, /* 0xe2800000 */ ++ { TARGET_ANA_AC, 0x2900000, 1 }, /* 0xe2900000 */ ++ { TARGET_VOP, 0x2a00000, 1 }, /* 0xe2a00000 */ ++ { TARGET_DEV2G5, 0x3004000, 1 }, /* 0xe3004000 */ ++ { TARGET_DEV10G, 0x3008000, 1 }, /* 0xe3008000 */ ++ { TARGET_PCS10G_BR, 0x300c000, 1 }, /* 0xe300c000 */ ++ { TARGET_DEV2G5 + 1, 0x3010000, 1 }, /* 0xe3010000 */ ++ { TARGET_DEV2G5 + 2, 0x3014000, 1 }, /* 0xe3014000 */ ++ { TARGET_DEV2G5 + 3, 0x3018000, 1 }, /* 0xe3018000 */ ++ { TARGET_DEV2G5 + 4, 0x301c000, 1 }, /* 0xe301c000 */ ++ { TARGET_DEV10G + 1, 0x3020000, 1 }, /* 0xe3020000 */ ++ { TARGET_PCS10G_BR + 1, 0x3024000, 1 }, /* 0xe3024000 */ ++ { TARGET_DEV2G5 + 5, 0x3028000, 1 }, /* 0xe3028000 */ ++ { TARGET_DEV2G5 + 6, 0x302c000, 1 }, /* 0xe302c000 */ ++ { TARGET_DEV2G5 + 7, 0x3030000, 1 }, /* 0xe3030000 */ ++ { TARGET_DEV2G5 + 8, 0x3034000, 1 }, /* 0xe3034000 */ ++ { TARGET_DEV10G + 2, 0x3038000, 1 }, /* 0xe3038000 */ ++ { TARGET_PCS10G_BR + 2, 0x303c000, 1 }, /* 0xe303c000 */ ++ { TARGET_DEV2G5 + 9, 0x3040000, 1 }, /* 0xe3040000 */ ++ { TARGET_DEV5G, 0x3044000, 1 }, /* 0xe3044000 */ ++ { TARGET_PCS5G_BR, 0x3048000, 1 }, /* 0xe3048000 */ ++ { TARGET_DEV2G5 + 10, 0x304c000, 1 }, /* 0xe304c000 */ ++ { TARGET_DEV2G5 + 11, 0x3050000, 1 }, /* 0xe3050000 */ ++ { TARGET_DEV2G5 + 12, 0x3054000, 1 }, /* 0xe3054000 */ ++ { TARGET_DEV10G + 3, 0x3058000, 1 }, /* 0xe3058000 */ ++ { TARGET_PCS10G_BR + 3, 0x305c000, 1 }, /* 0xe305c000 */ ++ { TARGET_DEV2G5 + 13, 0x3060000, 1 }, /* 0xe3060000 */ ++ { TARGET_DEV5G + 1, 0x3064000, 1 }, /* 0xe3064000 */ ++ { TARGET_PCS5G_BR + 1, 0x3068000, 1 }, /* 0xe3068000 */ ++ { TARGET_DEV2G5 + 14, 0x306c000, 1 }, /* 0xe306c000 */ ++ { TARGET_DEV2G5 + 15, 0x3070000, 1 }, /* 0xe3070000 */ ++ { TARGET_DEV2G5 + 16, 0x3074000, 1 }, /* 0xe3074000 */ ++ { TARGET_DEV10G + 4, 0x3078000, 1 }, /* 0xe3078000 */ ++ { TARGET_PCS10G_BR + 4, 0x307c000, 1 }, /* 0xe307c000 */ ++ { TARGET_DEV2G5 + 17, 0x3080000, 1 }, /* 0xe3080000 */ ++ { TARGET_DEV5G + 2, 0x3084000, 1 }, /* 0xe3084000 */ ++ { TARGET_PCS5G_BR + 2, 0x3088000, 1 }, /* 0xe3088000 */ ++ { TARGET_DEV2G5 + 18, 0x308c000, 1 }, /* 0xe308c000 */ ++ { TARGET_DEV2G5 + 19, 0x3090000, 1 }, /* 0xe3090000 */ ++ { TARGET_DEV2G5 + 20, 0x3094000, 1 }, /* 0xe3094000 */ ++ { TARGET_DEV10G + 5, 0x3098000, 1 }, /* 0xe3098000 */ ++ { TARGET_PCS10G_BR + 5, 0x309c000, 1 }, /* 0xe309c000 */ ++ { TARGET_DEV2G5 + 21, 0x30a0000, 1 }, /* 0xe30a0000 */ ++ { TARGET_DEV5G + 3, 0x30a4000, 1 }, /* 0xe30a4000 */ ++ { TARGET_PCS5G_BR + 3, 0x30a8000, 1 }, /* 0xe30a8000 */ ++ { TARGET_DEV2G5 + 22, 0x30ac000, 1 }, /* 0xe30ac000 */ ++ { TARGET_DEV2G5 + 23, 0x30b0000, 1 }, /* 0xe30b0000 */ ++ { TARGET_DEV2G5 + 24, 0x30b4000, 1 }, /* 0xe30b4000 */ ++ { TARGET_DEV10G + 6, 0x30b8000, 1 }, /* 0xe30b8000 */ ++ { TARGET_PCS10G_BR + 6, 0x30bc000, 1 }, /* 0xe30bc000 */ ++ { TARGET_DEV2G5 + 25, 0x30c0000, 1 }, /* 0xe30c0000 */ ++ { TARGET_DEV10G + 7, 0x30c4000, 1 }, /* 0xe30c4000 */ ++ { TARGET_PCS10G_BR + 7, 0x30c8000, 1 }, /* 0xe30c8000 */ ++ { TARGET_DEV2G5 + 26, 0x30cc000, 1 }, /* 0xe30cc000 */ ++ { TARGET_DEV10G + 8, 0x30d0000, 1 }, /* 0xe30d0000 */ ++ { TARGET_PCS10G_BR + 8, 0x30d4000, 1 }, /* 0xe30d4000 */ ++ { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ ++ { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ ++ { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ ++ { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ ++ { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ ++ { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ ++}; ++ ++static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { ++ { 1000000000, 8192 / 2, 64 }, /* 1 G */ ++ { 500000000, 8192 / 2, 64 }, /* 500 M */ ++ { 100000000, 8192 / 4, 64 }, /* 100 M */ ++ { 50000000, 8192 / 4, 64 }, /* 50 M */ ++ { 5000000, 8192 / 8, 64 }, /* 10 M */ ++}; ++ ++static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = { ++ 655355, 1048568, 6553550, 10485680 ++}; ++ ++static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx) ++{ ++ return &lan969x_sdlb_groups[idx]; ++} ++ ++static u32 lan969x_get_hsch_max_group_rate(int grp) ++{ ++ return lan969x_hsch_max_group_rate[grp]; ++} ++ ++static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) ++{ ++ if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port)) ++ return port; ++ ++ /* 10G */ ++ switch (port) { ++ case 0: ++ return 12; ++ case 4: ++ return 13; ++ case 8: ++ return 14; ++ case 12: ++ return 0; ++ default: ++ return port; ++ } ++} ++ ++static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) ++{ ++ if (lan969x_port_is_5g(port)) { ++ switch (port) { ++ case 9: ++ return 0; ++ case 13: ++ return 1; ++ case 17: ++ return 2; ++ case 21: ++ return 3; ++ } ++ } ++ ++ if (lan969x_port_is_10g(port)) { ++ switch (port) { ++ case 0: ++ return 0; ++ case 4: ++ return 1; ++ case 8: ++ return 2; ++ case 12: ++ return 3; ++ case 16: ++ return 4; ++ case 20: ++ return 5; ++ case 24: ++ return 6; ++ case 25: ++ return 7; ++ case 26: ++ return 8; ++ case 27: ++ return 9; ++ } ++ } ++ ++ /* 2g5 port */ ++ return port; ++} ++ ++static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, ++ struct sparx5_port_config *conf) ++{ ++ u32 portno = port->portno; ++ u32 inst; ++ ++ if (port->conf.portmode == conf->portmode) ++ return 0; /* Nothing to do */ ++ ++ switch (conf->portmode) { ++ case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q' */ ++ inst = (portno - portno % 4) / 4; ++ spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA); ++ break; ++ default: ++ break; ++ } ++ return 0; ++} ++ ++static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args) ++{ ++ int budget = SPARX5_MAX_PTP_ID; ++ struct sparx5 *sparx5 = args; ++ ++ while (budget--) { ++ struct sk_buff *skb, *skb_tmp, *skb_match = NULL; ++ struct skb_shared_hwtstamps shhwtstamps; ++ struct sparx5_port *port; ++ struct timespec64 ts; ++ unsigned long flags; ++ u32 val, id, txport; ++ u32 delay; ++ ++ val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); ++ ++ /* Check if a timestamp can be retrieved */ ++ if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) ++ break; ++ ++ WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL); ++ ++ if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX)) ++ continue; ++ ++ /* Retrieve the ts Tx port */ ++ txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val); ++ ++ /* Retrieve its associated skb */ ++ port = sparx5->ports[txport]; ++ ++ /* Retrieve the delay */ ++ delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); ++ delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay); ++ ++ /* Get next timestamp from fifo, which needs to be the ++ * rx timestamp which represents the id of the frame ++ */ ++ spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), ++ PTP_TWOSTEP_CTRL_PTP_NXT, ++ sparx5, PTP_TWOSTEP_CTRL); ++ ++ val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL); ++ ++ /* Check if a timestamp can be retrieved */ ++ if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD)) ++ break; ++ ++ /* Read RX timestamping to get the ID */ ++ id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC); ++ id <<= 8; ++ id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS); ++ ++ spin_lock_irqsave(&port->tx_skbs.lock, flags); ++ skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) { ++ if (SPARX5_SKB_CB(skb)->ts_id != id) ++ continue; ++ ++ __skb_unlink(skb, &port->tx_skbs); ++ skb_match = skb; ++ break; ++ } ++ spin_unlock_irqrestore(&port->tx_skbs.lock, flags); ++ ++ /* Next ts */ ++ spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1), ++ PTP_TWOSTEP_CTRL_PTP_NXT, ++ sparx5, PTP_TWOSTEP_CTRL); ++ ++ if (WARN_ON(!skb_match)) ++ continue; ++ ++ spin_lock(&sparx5->ptp_ts_id_lock); ++ sparx5->ptp_skbs--; ++ spin_unlock(&sparx5->ptp_ts_id_lock); ++ ++ /* Get the h/w timestamp */ ++ sparx5_get_hwtimestamp(sparx5, &ts, delay); ++ ++ /* Set the timestamp in the skb */ ++ shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec); ++ skb_tstamp_tx(skb_match, &shhwtstamps); ++ ++ dev_kfree_skb_any(skb_match); ++ } ++ ++ return IRQ_HANDLED; ++} ++ ++static const struct sparx5_regs lan969x_regs = { ++ .tsize = lan969x_tsize, ++ .gaddr = lan969x_gaddr, ++ .gcnt = lan969x_gcnt, ++ .gsize = lan969x_gsize, ++ .raddr = lan969x_raddr, ++ .rcnt = lan969x_rcnt, ++ .fpos = lan969x_fpos, ++ .fsize = lan969x_fsize, ++}; ++ ++static const struct sparx5_consts lan969x_consts = { ++ .n_ports = 30, ++ .n_ports_all = 35, ++ .n_hsch_l1_elems = 32, ++ .n_hsch_queues = 4, ++ .n_lb_groups = 5, ++ .n_pgids = 1054, /* (1024 + n_ports) */ ++ .n_sio_clks = 1, ++ .n_own_upsids = 1, ++ .n_auto_cals = 4, ++ .n_filters = 256, ++ .n_gates = 256, ++ .n_sdlbs = 496, ++ .n_dsm_cal_taxis = 5, ++ .buf_size = 1572864, ++ .qres_max_prio_idx = 315, ++ .qres_max_colour_idx = 323, ++ .tod_pin = 4, ++ .vcaps = lan969x_vcaps, ++ .vcap_stats = &lan969x_vcap_stats, ++ .vcaps_cfg = lan969x_vcap_inst_cfg, ++}; ++ ++static const struct sparx5_ops lan969x_ops = { ++ .is_port_2g5 = &lan969x_port_is_2g5, ++ .is_port_5g = &lan969x_port_is_5g, ++ .is_port_10g = &lan969x_port_is_10g, ++ .is_port_25g = &lan969x_port_is_25g, ++ .get_port_dev_index = &lan969x_port_dev_mapping, ++ .get_port_dev_bit = &lan969x_get_dev_mode_bit, ++ .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, ++ .get_sdlb_group = &lan969x_get_sdlb_group, ++ .set_port_mux = &lan969x_port_mux_set, ++ .ptp_irq_handler = &lan969x_ptp_irq_handler, ++ .dsm_calendar_calc = &lan969x_dsm_calendar_calc, ++}; ++ ++const struct sparx5_match_data lan969x_desc = { ++ .iomap = lan969x_main_iomap, ++ .iomap_size = ARRAY_SIZE(lan969x_main_iomap), ++ .ioranges = 2, ++ .regs = &lan969x_regs, ++ .consts = &lan969x_consts, ++ .ops = &lan969x_ops, ++}; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c +@@ -98,7 +98,6 @@ u32 sparx5_cal_speed_to_value(enum sparx + default: return 0; + } + } +-EXPORT_SYMBOL_GPL(sparx5_cal_speed_to_value); + + static u32 sparx5_bandwidth_to_calendar(u32 bw) + { +@@ -150,7 +149,6 @@ enum sparx5_cal_bw sparx5_get_port_cal_s + return SPX5_CAL_SPEED_NONE; + return sparx5_bandwidth_to_calendar(port->conf.bandwidth); + } +-EXPORT_SYMBOL_GPL(sparx5_get_port_cal_speed); + + /* Auto configure the QSYS calendar based on port configuration */ + int sparx5_config_auto_calendar(struct sparx5 *sparx5) +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -24,7 +24,7 @@ + #include + #include + +-#include "../lan969x/lan969x.h" /* for lan969x match data */ ++#include "lan969x/lan969x.h" /* for lan969x match data */ + + #include "sparx5_main_regs.h" + #include "sparx5_main.h" +@@ -1092,7 +1092,7 @@ static const struct sparx5_match_data sp + + static const struct of_device_id mchp_sparx5_match[] = { + { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc }, +-#if IS_ENABLED(CONFIG_LAN969X_SWITCH) ++#ifdef CONFIG_LAN969X_SWITCH + { .compatible = "microchip,lan9691-switch", .data = &lan969x_desc }, + #endif + { } +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c +@@ -303,7 +303,6 @@ void sparx5_get_hwtimestamp(struct sparx + + spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags); + } +-EXPORT_SYMBOL_GPL(sparx5_get_hwtimestamp); + + irqreturn_t sparx5_ptp_irq_handler(int irq, void *args) + { +--- a/drivers/net/ethernet/microchip/lan969x/lan969x.h ++++ /dev/null +@@ -1,65 +0,0 @@ +-/* SPDX-License-Identifier: GPL-2.0+ */ +-/* Microchip lan969x Switch driver +- * +- * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. +- */ +- +-#ifndef __LAN969X_H__ +-#define __LAN969X_H__ +- +-#include "../sparx5/sparx5_main.h" +-#include "../sparx5/sparx5_regs.h" +-#include "../sparx5/sparx5_vcap_impl.h" +- +-/* lan969x.c */ +-extern const struct sparx5_match_data lan969x_desc; +- +-/* lan969x_vcap_ag_api.c */ +-extern const struct vcap_statistics lan969x_vcap_stats; +-extern const struct vcap_info lan969x_vcaps[]; +- +-/* lan969x_vcap_impl.c */ +-extern const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[]; +- +-/* lan969x_regs.c */ +-extern const unsigned int lan969x_tsize[TSIZE_LAST]; +-extern const unsigned int lan969x_raddr[RADDR_LAST]; +-extern const unsigned int lan969x_rcnt[RCNT_LAST]; +-extern const unsigned int lan969x_gaddr[GADDR_LAST]; +-extern const unsigned int lan969x_gcnt[GCNT_LAST]; +-extern const unsigned int lan969x_gsize[GSIZE_LAST]; +-extern const unsigned int lan969x_fpos[FPOS_LAST]; +-extern const unsigned int lan969x_fsize[FSIZE_LAST]; +- +-static inline bool lan969x_port_is_2g5(int portno) +-{ +- return portno == 1 || portno == 2 || portno == 3 || +- portno == 5 || portno == 6 || portno == 7 || +- portno == 10 || portno == 11 || portno == 14 || +- portno == 15 || portno == 18 || portno == 19 || +- portno == 22 || portno == 23; +-} +- +-static inline bool lan969x_port_is_5g(int portno) +-{ +- return portno == 9 || portno == 13 || portno == 17 || +- portno == 21; +-} +- +-static inline bool lan969x_port_is_10g(int portno) +-{ +- return portno == 0 || portno == 4 || portno == 8 || +- portno == 12 || portno == 16 || portno == 20 || +- portno == 24 || portno == 25 || portno == 26 || +- portno == 27; +-} +- +-static inline bool lan969x_port_is_25g(int portno) +-{ +- return false; +-} +- +-/* lan969x_calendar.c */ +-int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, +- struct sparx5_calendar_data *data); +-#endif +--- a/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c ++++ /dev/null +@@ -1,191 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* Microchip lan969x Switch driver +- * +- * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. +- */ +- +-#include "lan969x.h" +- +-#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10 +-#define LAN969X_DSM_CAL_TAXIS 5 +- +-enum lan969x_dsm_cal_dev { +- DSM_CAL_DEV_2G5, +- DSM_CAL_DEV_5G, +- DSM_CAL_DEV_10G, +- DSM_CAL_DEV_OTHER, /* 1G or less */ +- DSM_CAL_DEV_MAX +-}; +- +-/* Each entry in the following struct defines properties for a given speed +- * (10G, 5G, 2.5G, or 1G or less). +- */ +-struct lan969x_dsm_cal_dev_speed { +- /* Number of devices that requires this speed. */ +- u32 n_devs; +- +- /* Array of devices that requires this speed. */ +- u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI]; +- +- /* Number of slots required for one device running this speed. */ +- u32 n_slots; +- +- /* Gap between two slots for one device running this speed. */ +- u32 gap; +-}; +- +-static u32 +-lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = { +- { 0, 4, 1, 2, 3, 5, 6, 7, 28, 29 }, +- { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 }, +- { 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 }, +- { 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 }, +- { 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 } +-}; +- +-static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx) +-{ +- if (*cal_idx >= cal_len) +- return -EINVAL; +- +- do { +- if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY) +- return 0; +- +- (*cal_idx)++; +- } while (*cal_idx < cal_len); +- +- return -ENOENT; +-} +- +-static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) +-{ +- return (speed == 10000 ? DSM_CAL_DEV_10G : +- speed == 5000 ? DSM_CAL_DEV_5G : +- speed == 2500 ? DSM_CAL_DEV_2G5 : +- DSM_CAL_DEV_OTHER); +-} +- +-static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev) +-{ +- return (dev == DSM_CAL_DEV_10G ? 10000 : +- dev == DSM_CAL_DEV_5G ? 5000 : +- dev == DSM_CAL_DEV_2G5 ? 2500 : +- 1000); +-} +- +-int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, +- struct sparx5_calendar_data *data) +-{ +- struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {}; +- u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw = 0; +- struct lan969x_dsm_cal_dev_speed *speed; +- int err; +- +- /* Maximum bandwidth for this taxi */ +- taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); +- +- memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], +- LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32)); +- +- for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { +- u32 portno = data->taxi_ports[i]; +- enum sparx5_cal_bw bw; +- +- bw = sparx5_get_port_cal_speed(sparx5, portno); +- +- if (portno < sparx5->data->consts->n_ports_all) +- data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw); +- else +- data->taxi_speeds[i] = 0; +- } +- +- /* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the +- * this taxi map. +- */ +- for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { +- u32 taxi_speed = data->taxi_speeds[i]; +- enum lan969x_dsm_cal_dev dev; +- +- if (taxi_speed == 0) +- continue; +- +- required_bw += taxi_speed; +- +- dev = lan969x_dsm_cal_get_dev(taxi_speed); +- speed = &dev_speeds[dev]; +- speed->devs[speed->n_devs++] = i; +- n_devs++; +- } +- +- if (required_bw > taxi_bw) { +- pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u", +- required_bw, taxi_bw); +- return -EINVAL; +- } +- +- if (n_devs == 0) { +- data->schedule[0] = SPX5_DSM_CAL_EMPTY; +- return 0; +- } +- +- cal_len = n_devs; +- +- /* Search for a calendar length that fits all active devices. */ +- while (cal_len < SPX5_DSM_CAL_LEN) { +- u32 bw_per_slot = taxi_bw / cal_len; +- +- n_slots = 0; +- +- for (int i = 0; i < DSM_CAL_DEV_MAX; i++) { +- speed = &dev_speeds[i]; +- +- if (speed->n_devs == 0) +- continue; +- +- required_bw = lan969x_dsm_cal_get_speed(i); +- speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot); +- +- if (speed->n_slots) +- speed->gap = DIV_ROUND_UP(cal_len, +- speed->n_slots); +- else +- speed->gap = 0; +- +- n_slots += speed->n_slots * speed->n_devs; +- } +- +- if (n_slots <= cal_len) +- break; /* Found a suitable calendar length. */ +- +- /* Not good enough yet. */ +- cal_len = n_slots; +- } +- +- if (cal_len > SPX5_DSM_CAL_LEN) { +- pr_err("Invalid length: %u for taxi: %u", cal_len, taxi); +- return -EINVAL; +- } +- +- for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++) +- data->schedule[i] = SPX5_DSM_CAL_EMPTY; +- +- /* Place the remaining devices */ +- for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) { +- speed = &dev_speeds[i]; +- for (u32 dev = 0; dev < speed->n_devs; dev++) { +- u32 idx = 0; +- +- for (n_slots = 0; n_slots < speed->n_slots; n_slots++) { +- err = lan969x_dsm_cal_idx_get(data->schedule, +- cal_len, &idx); +- if (err) +- return err; +- data->schedule[idx] = speed->devs[dev]; +- idx += speed->gap; +- } +- } +- } +- +- return 0; +-} +--- a/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c ++++ /dev/null +@@ -1,222 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +-/* Microchip lan969x Switch driver +- * +- * Copyright (c) 2024 Microchip Technology Inc. +- */ +- +-/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. +- * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b +- */ +- +-#include "lan969x.h" +- +-const unsigned int lan969x_tsize[TSIZE_LAST] = { +- [TC_DEV10G] = 10, +- [TC_DEV2G5] = 28, +- [TC_DEV5G] = 4, +- [TC_PCS10G_BR] = 10, +- [TC_PCS5G_BR] = 4, +-}; +- +-const unsigned int lan969x_raddr[RADDR_LAST] = { +- [RA_CPU_PROC_CTRL] = 160, +- [RA_GCB_SOFT_RST] = 12, +- [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20, +-}; +- +-const unsigned int lan969x_rcnt[RCNT_LAST] = { +- [RC_ANA_AC_OWN_UPSID] = 1, +- [RC_ANA_ACL_VCAP_S2_CFG] = 35, +- [RC_ANA_ACL_OWN_UPSID] = 1, +- [RC_ANA_CL_OWN_UPSID] = 1, +- [RC_ANA_L2_OWN_UPSID] = 1, +- [RC_ASM_PORT_CFG] = 32, +- [RC_DSM_BUF_CFG] = 32, +- [RC_DSM_DEV_TX_STOP_WM_CFG] = 32, +- [RC_DSM_RX_PAUSE_CFG] = 32, +- [RC_DSM_MAC_CFG] = 32, +- [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30, +- [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30, +- [RC_DSM_TAXI_CAL_CFG] = 6, +- [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30, +- [RC_HSCH_PORT_MODE] = 35, +- [RC_QFWD_SWITCH_PORT_MODE] = 35, +- [RC_QSYS_PAUSE_CFG] = 35, +- [RC_QSYS_ATOP] = 35, +- [RC_QSYS_FWD_PRESSURE] = 35, +- [RC_QSYS_CAL_AUTO] = 4, +- [RC_REW_OWN_UPSID] = 1, +- [RC_REW_RTAG_ETAG_CTRL] = 35, +-}; +- +-const unsigned int lan969x_gaddr[GADDR_LAST] = { +- [GA_ANA_AC_RAM_CTRL] = 202000, +- [GA_ANA_AC_PS_COMMON] = 202880, +- [GA_ANA_AC_MIRROR_PROBE] = 203232, +- [GA_ANA_AC_SRC] = 201728, +- [GA_ANA_AC_PGID] = 131072, +- [GA_ANA_AC_TSN_SF] = 202028, +- [GA_ANA_AC_TSN_SF_CFG] = 148480, +- [GA_ANA_AC_TSN_SF_STATUS] = 147936, +- [GA_ANA_AC_SG_ACCESS] = 202032, +- [GA_ANA_AC_SG_CONFIG] = 202752, +- [GA_ANA_AC_SG_STATUS] = 147952, +- [GA_ANA_AC_SG_STATUS_STICKY] = 202044, +- [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048, +- [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800, +- [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068, +- [GA_ANA_ACL_COMMON] = 8192, +- [GA_ANA_ACL_KEY_SEL] = 9204, +- [GA_ANA_ACL_CNT_B] = 4096, +- [GA_ANA_ACL_STICKY] = 10852, +- [GA_ANA_AC_POL_POL_ALL_CFG] = 17504, +- [GA_ANA_AC_POL_COMMON_BDLB] = 19464, +- [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472, +- [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788, +- [GA_ANA_CL_PORT] = 65536, +- [GA_ANA_CL_COMMON] = 87040, +- [GA_ANA_L2_COMMON] = 561928, +- [GA_ANA_L3_COMMON] = 370752, +- [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580, +- [GA_ASM_CFG] = 18304, +- [GA_ASM_PFC_TIMER_CFG] = 15568, +- [GA_ASM_LBK_WM_CFG] = 15596, +- [GA_ASM_LBK_MISC_CFG] = 15608, +- [GA_ASM_RAM_CTRL] = 15684, +- [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864, +- [GA_EACL_CNT_TBL] = 30720, +- [GA_EACL_POL_CFG] = 38400, +- [GA_EACL_ES2_STICKY] = 29072, +- [GA_EACL_RAM_CTRL] = 29112, +- [GA_GCB_SIO_CTRL] = 560, +- [GA_HSCH_HSCH_DWRR] = 36480, +- [GA_HSCH_HSCH_MISC] = 36608, +- [GA_HSCH_HSCH_LEAK_LISTS] = 37256, +- [GA_HSCH_SYSTEM] = 37384, +- [GA_HSCH_MMGT] = 36260, +- [GA_HSCH_TAS_CONFIG] = 37696, +- [GA_PTP_PTP_CFG] = 512, +- [GA_PTP_PTP_TOD_DOMAINS] = 528, +- [GA_PTP_PHASE_DETECTOR_CTRL] = 628, +- [GA_QSYS_CALCFG] = 2164, +- [GA_QSYS_RAM_CTRL] = 2204, +- [GA_REW_COMMON] = 98304, +- [GA_REW_PORT] = 49152, +- [GA_REW_VOE_PORT_LM_CNT] = 90112, +- [GA_REW_RAM_CTRL] = 93992, +- [GA_VOP_RAM_CTRL] = 16368, +- [GA_XQS_SYSTEM] = 5744, +- [GA_XQS_QLIMIT_SHR] = 6912, +-}; +- +-const unsigned int lan969x_gcnt[GCNT_LAST] = { +- [GC_ANA_AC_SRC] = 67, +- [GC_ANA_AC_PGID] = 1054, +- [GC_ANA_AC_TSN_SF_CFG] = 256, +- [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35, +- [GC_ANA_ACL_KEY_SEL] = 99, +- [GC_ANA_ACL_CNT_A] = 1024, +- [GC_ANA_ACL_CNT_B] = 1024, +- [GC_ANA_AC_SDLB_LBGRP_TBL] = 5, +- [GC_ANA_AC_SDLB_LBSET_TBL] = 496, +- [GC_ANA_CL_PORT] = 35, +- [GC_ANA_L2_ISDX_LIMIT] = 256, +- [GC_ANA_L2_ISDX] = 1024, +- [GC_ANA_L3_VLAN] = 4608, +- [GC_ASM_DEV_STATISTICS] = 30, +- [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68, +- [GC_EACL_CNT_TBL] = 512, +- [GC_GCB_SIO_CTRL] = 1, +- [GC_HSCH_HSCH_CFG] = 1120, +- [GC_HSCH_HSCH_DWRR] = 32, +- [GC_PTP_PTP_PINS] = 8, +- [GC_PTP_PHASE_DETECTOR_CTRL] = 8, +- [GC_REW_PORT] = 35, +- [GC_REW_VOE_PORT_LM_CNT] = 240, +-}; +- +-const unsigned int lan969x_gsize[GSIZE_LAST] = { +- [GW_ANA_AC_SRC] = 4, +- [GW_ANA_L2_COMMON] = 712, +- [GW_ASM_CFG] = 1092, +- [GW_CPU_CPU_REGS] = 180, +- [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12, +- [GW_FDMA_FDMA] = 448, +- [GW_GCB_CHIP_REGS] = 180, +- [GW_HSCH_TAS_CONFIG] = 16, +- [GW_PTP_PHASE_DETECTOR_CTRL] = 12, +- [GW_QSYS_PAUSE_CFG] = 988, +-}; +- +-const unsigned int lan969x_fpos[FPOS_LAST] = { +- [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7, +- [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6, +- [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5, +- [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4, +- [FP_CPU_PROC_CTRL_VINITHI] = 3, +- [FP_CPU_PROC_CTRL_CFGTE] = 2, +- [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1, +- [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0, +- [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8, +- [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5, +- [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3, +- [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5, +- [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4, +- [FP_FDMA_CH_CFG_CH_INJ_PORT] = 3, +- [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27, +- [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25, +- [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24, +- [FP_PTP_PHAD_CTRL_PHAD_ENA] = 5, +- [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3, +-}; +- +-const unsigned int lan969x_fsize[FSIZE_LAST] = { +- [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30, +- [FW_ANA_AC_SRC_CFG_PORT_MASK] = 30, +- [FW_ANA_AC_PGID_CFG_PORT_MASK] = 30, +- [FW_ANA_AC_TSN_SF_PORT_NUM] = 7, +- [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8, +- [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8, +- [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8, +- [FW_ANA_AC_PORT_SGE_CFG_MASK] = 17, +- [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9, +- [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3, +- [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9, +- [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9, +- [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3, +- [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9, +- [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30, +- [FW_ANA_L2_DLB_CFG_DLB_IDX] = 9, +- [FW_ANA_L2_TSN_CFG_TSN_SFID] = 8, +- [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30, +- [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2, +- [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7, +- [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5, +- [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14, +- [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6, +- [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11, +- [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14, +- [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6, +- [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14, +- [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13, +- [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8, +- [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13, +- [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8, +- [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8, +- [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8, +- [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3, +- [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6, +- [FW_QRES_RES_CFG_WM_HIGH] = 11, +- [FW_QRES_RES_STAT_MAXUSE] = 19, +- [FW_QRES_RES_STAT_CUR_INUSE] = 19, +- [FW_QSYS_PAUSE_CFG_PAUSE_START] = 11, +- [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11, +- [FW_QSYS_ATOP_ATOP] = 11, +- [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11, +- [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6, +- [FW_XQS_STAT_CFG_STAT_VIEW] = 10, +- [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14, +- [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14, +- [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14, +- [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14, +-}; +--- a/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c ++++ /dev/null +@@ -1,3843 +0,0 @@ +-// SPDX-License-Identifier: BSD-3-Clause +-/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. +- * Microchip VCAP API +- */ +- +-/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200. +- * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391 +- */ +- +-#include +-#include +- +-#include "lan969x.h" +- +-/* keyfields */ +-static const struct vcap_field is0_normal_7tuple_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_BIT, +- .offset = 0, +- .width = 1, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 1, +- .width = 1, +- }, +- [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 2, +- .width = 2, +- }, +- [VCAP_KF_LOOKUP_GEN_IDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 4, +- .width = 10, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 14, +- .width = 2, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK] = { +- .type = VCAP_FIELD_U72, +- .offset = 16, +- .width = 65, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 81, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 82, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VLAN_TAGS] = { +- .type = VCAP_FIELD_U32, +- .offset = 83, +- .width = 3, +- }, +- [VCAP_KF_8021Q_TPID0] = { +- .type = VCAP_FIELD_U32, +- .offset = 86, +- .width = 3, +- }, +- [VCAP_KF_8021Q_PCP0] = { +- .type = VCAP_FIELD_U32, +- .offset = 89, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 92, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID0] = { +- .type = VCAP_FIELD_U32, +- .offset = 93, +- .width = 12, +- }, +- [VCAP_KF_8021Q_TPID1] = { +- .type = VCAP_FIELD_U32, +- .offset = 105, +- .width = 3, +- }, +- [VCAP_KF_8021Q_PCP1] = { +- .type = VCAP_FIELD_U32, +- .offset = 108, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI1] = { +- .type = VCAP_FIELD_BIT, +- .offset = 111, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID1] = { +- .type = VCAP_FIELD_U32, +- .offset = 112, +- .width = 12, +- }, +- [VCAP_KF_8021Q_TPID2] = { +- .type = VCAP_FIELD_U32, +- .offset = 124, +- .width = 3, +- }, +- [VCAP_KF_8021Q_PCP2] = { +- .type = VCAP_FIELD_U32, +- .offset = 127, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI2] = { +- .type = VCAP_FIELD_BIT, +- .offset = 130, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID2] = { +- .type = VCAP_FIELD_U32, +- .offset = 131, +- .width = 12, +- }, +- [VCAP_KF_L2_DMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 144, +- .width = 48, +- }, +- [VCAP_KF_L2_SMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 192, +- .width = 48, +- }, +- [VCAP_KF_IP_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 240, +- .width = 1, +- }, +- [VCAP_KF_ETYPE_LEN_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 241, +- .width = 1, +- }, +- [VCAP_KF_ETYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 242, +- .width = 16, +- }, +- [VCAP_KF_IP_SNAP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 258, +- .width = 1, +- }, +- [VCAP_KF_IP4_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 259, +- .width = 1, +- }, +- [VCAP_KF_L3_FRAGMENT_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 260, +- .width = 2, +- }, +- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 262, +- .width = 1, +- }, +- [VCAP_KF_L3_OPTIONS_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 263, +- .width = 1, +- }, +- [VCAP_KF_L3_DSCP] = { +- .type = VCAP_FIELD_U32, +- .offset = 264, +- .width = 6, +- }, +- [VCAP_KF_L3_IP6_DIP] = { +- .type = VCAP_FIELD_U128, +- .offset = 270, +- .width = 128, +- }, +- [VCAP_KF_L3_IP6_SIP] = { +- .type = VCAP_FIELD_U128, +- .offset = 398, +- .width = 128, +- }, +- [VCAP_KF_TCP_UDP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 526, +- .width = 1, +- }, +- [VCAP_KF_TCP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 527, +- .width = 1, +- }, +- [VCAP_KF_L4_SPORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 528, +- .width = 16, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 544, +- .width = 8, +- }, +-}; +- +-static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 2, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 2, +- .width = 1, +- }, +- [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 3, +- .width = 2, +- }, +- [VCAP_KF_LOOKUP_GEN_IDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 5, +- .width = 10, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 15, +- .width = 2, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK] = { +- .type = VCAP_FIELD_U72, +- .offset = 17, +- .width = 65, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 82, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 83, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VLAN_TAGS] = { +- .type = VCAP_FIELD_U32, +- .offset = 84, +- .width = 3, +- }, +- [VCAP_KF_8021Q_TPID0] = { +- .type = VCAP_FIELD_U32, +- .offset = 87, +- .width = 3, +- }, +- [VCAP_KF_8021Q_PCP0] = { +- .type = VCAP_FIELD_U32, +- .offset = 90, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 93, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID0] = { +- .type = VCAP_FIELD_U32, +- .offset = 94, +- .width = 12, +- }, +- [VCAP_KF_8021Q_TPID1] = { +- .type = VCAP_FIELD_U32, +- .offset = 106, +- .width = 3, +- }, +- [VCAP_KF_8021Q_PCP1] = { +- .type = VCAP_FIELD_U32, +- .offset = 109, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI1] = { +- .type = VCAP_FIELD_BIT, +- .offset = 112, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID1] = { +- .type = VCAP_FIELD_U32, +- .offset = 113, +- .width = 12, +- }, +- [VCAP_KF_8021Q_TPID2] = { +- .type = VCAP_FIELD_U32, +- .offset = 125, +- .width = 3, +- }, +- [VCAP_KF_8021Q_PCP2] = { +- .type = VCAP_FIELD_U32, +- .offset = 128, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI2] = { +- .type = VCAP_FIELD_BIT, +- .offset = 131, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID2] = { +- .type = VCAP_FIELD_U32, +- .offset = 132, +- .width = 12, +- }, +- [VCAP_KF_IP_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 145, +- .width = 1, +- }, +- [VCAP_KF_IP4_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 146, +- .width = 1, +- }, +- [VCAP_KF_L3_FRAGMENT_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 147, +- .width = 2, +- }, +- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 149, +- .width = 1, +- }, +- [VCAP_KF_L3_OPTIONS_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 150, +- .width = 1, +- }, +- [VCAP_KF_L3_DSCP] = { +- .type = VCAP_FIELD_U32, +- .offset = 151, +- .width = 6, +- }, +- [VCAP_KF_L3_IP4_DIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 157, +- .width = 32, +- }, +- [VCAP_KF_L3_IP4_SIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 189, +- .width = 32, +- }, +- [VCAP_KF_L3_IP_PROTO] = { +- .type = VCAP_FIELD_U32, +- .offset = 221, +- .width = 8, +- }, +- [VCAP_KF_TCP_UDP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 229, +- .width = 1, +- }, +- [VCAP_KF_TCP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 230, +- .width = 1, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 231, +- .width = 8, +- }, +- [VCAP_KF_IP_PAYLOAD_5TUPLE] = { +- .type = VCAP_FIELD_U32, +- .offset = 239, +- .width = 32, +- }, +-}; +- +-static const struct vcap_field is2_mac_etype_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 4, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 4, +- .width = 1, +- }, +- [VCAP_KF_LOOKUP_PAG] = { +- .type = VCAP_FIELD_U32, +- .offset = 5, +- .width = 8, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 14, +- .width = 4, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 18, +- .width = 2, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 20, +- .width = 32, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 52, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 53, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 54, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 56, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 57, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 67, +- .width = 13, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 80, +- .width = 1, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 81, +- .width = 3, +- }, +- [VCAP_KF_L2_FWD_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 84, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_L3_DST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 88, +- .width = 1, +- }, +- [VCAP_KF_L2_DMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 89, +- .width = 48, +- }, +- [VCAP_KF_L2_SMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 137, +- .width = 48, +- }, +- [VCAP_KF_ETYPE_LEN_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 185, +- .width = 1, +- }, +- [VCAP_KF_ETYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 186, +- .width = 16, +- }, +- [VCAP_KF_L2_PAYLOAD_ETYPE] = { +- .type = VCAP_FIELD_U64, +- .offset = 202, +- .width = 64, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 266, +- .width = 16, +- }, +- [VCAP_KF_OAM_CCM_CNTS_EQ0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 282, +- .width = 1, +- }, +- [VCAP_KF_OAM_Y1731_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 283, +- .width = 1, +- }, +-}; +- +-static const struct vcap_field is2_arp_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 4, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 4, +- .width = 1, +- }, +- [VCAP_KF_LOOKUP_PAG] = { +- .type = VCAP_FIELD_U32, +- .offset = 5, +- .width = 8, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 14, +- .width = 4, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 18, +- .width = 2, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 20, +- .width = 32, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 52, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 53, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 54, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 56, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 57, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 67, +- .width = 13, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 80, +- .width = 1, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 81, +- .width = 3, +- }, +- [VCAP_KF_L2_FWD_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 84, +- .width = 1, +- }, +- [VCAP_KF_L2_SMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 85, +- .width = 48, +- }, +- [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 133, +- .width = 1, +- }, +- [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 134, +- .width = 1, +- }, +- [VCAP_KF_ARP_LEN_OK_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 135, +- .width = 1, +- }, +- [VCAP_KF_ARP_TGT_MATCH_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 136, +- .width = 1, +- }, +- [VCAP_KF_ARP_SENDER_MATCH_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 137, +- .width = 1, +- }, +- [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 138, +- .width = 1, +- }, +- [VCAP_KF_ARP_OPCODE] = { +- .type = VCAP_FIELD_U32, +- .offset = 139, +- .width = 2, +- }, +- [VCAP_KF_L3_IP4_DIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 141, +- .width = 32, +- }, +- [VCAP_KF_L3_IP4_SIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 173, +- .width = 32, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 205, +- .width = 1, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 206, +- .width = 16, +- }, +-}; +- +-static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 4, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 4, +- .width = 1, +- }, +- [VCAP_KF_LOOKUP_PAG] = { +- .type = VCAP_FIELD_U32, +- .offset = 5, +- .width = 8, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 14, +- .width = 4, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 18, +- .width = 2, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 20, +- .width = 32, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 52, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 53, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 54, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 56, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 57, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 67, +- .width = 13, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 80, +- .width = 1, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 81, +- .width = 3, +- }, +- [VCAP_KF_L2_FWD_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 84, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_L3_DST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 88, +- .width = 1, +- }, +- [VCAP_KF_IP4_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 89, +- .width = 1, +- }, +- [VCAP_KF_L3_FRAGMENT_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 90, +- .width = 2, +- }, +- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 92, +- .width = 1, +- }, +- [VCAP_KF_L3_OPTIONS_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 93, +- .width = 1, +- }, +- [VCAP_KF_L3_TTL_GT0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 94, +- .width = 1, +- }, +- [VCAP_KF_L3_TOS] = { +- .type = VCAP_FIELD_U32, +- .offset = 95, +- .width = 8, +- }, +- [VCAP_KF_L3_IP4_DIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 103, +- .width = 32, +- }, +- [VCAP_KF_L3_IP4_SIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 135, +- .width = 32, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 167, +- .width = 1, +- }, +- [VCAP_KF_TCP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 168, +- .width = 1, +- }, +- [VCAP_KF_L4_DPORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 169, +- .width = 16, +- }, +- [VCAP_KF_L4_SPORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 185, +- .width = 16, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 201, +- .width = 16, +- }, +- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 217, +- .width = 1, +- }, +- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 218, +- .width = 1, +- }, +- [VCAP_KF_L4_FIN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 219, +- .width = 1, +- }, +- [VCAP_KF_L4_SYN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 220, +- .width = 1, +- }, +- [VCAP_KF_L4_RST] = { +- .type = VCAP_FIELD_BIT, +- .offset = 221, +- .width = 1, +- }, +- [VCAP_KF_L4_PSH] = { +- .type = VCAP_FIELD_BIT, +- .offset = 222, +- .width = 1, +- }, +- [VCAP_KF_L4_ACK] = { +- .type = VCAP_FIELD_BIT, +- .offset = 223, +- .width = 1, +- }, +- [VCAP_KF_L4_URG] = { +- .type = VCAP_FIELD_BIT, +- .offset = 224, +- .width = 1, +- }, +- [VCAP_KF_L4_PAYLOAD] = { +- .type = VCAP_FIELD_U64, +- .offset = 225, +- .width = 64, +- }, +-}; +- +-static const struct vcap_field is2_ip4_other_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 4, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 4, +- .width = 1, +- }, +- [VCAP_KF_LOOKUP_PAG] = { +- .type = VCAP_FIELD_U32, +- .offset = 5, +- .width = 8, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 14, +- .width = 4, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 18, +- .width = 2, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 20, +- .width = 32, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 52, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 53, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 54, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 56, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 57, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 67, +- .width = 13, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 80, +- .width = 1, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 81, +- .width = 3, +- }, +- [VCAP_KF_L2_FWD_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 84, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_L3_DST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 88, +- .width = 1, +- }, +- [VCAP_KF_IP4_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 89, +- .width = 1, +- }, +- [VCAP_KF_L3_FRAGMENT_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 90, +- .width = 2, +- }, +- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 92, +- .width = 1, +- }, +- [VCAP_KF_L3_OPTIONS_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 93, +- .width = 1, +- }, +- [VCAP_KF_L3_TTL_GT0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 94, +- .width = 1, +- }, +- [VCAP_KF_L3_TOS] = { +- .type = VCAP_FIELD_U32, +- .offset = 95, +- .width = 8, +- }, +- [VCAP_KF_L3_IP4_DIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 103, +- .width = 32, +- }, +- [VCAP_KF_L3_IP4_SIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 135, +- .width = 32, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 167, +- .width = 1, +- }, +- [VCAP_KF_L3_IP_PROTO] = { +- .type = VCAP_FIELD_U32, +- .offset = 168, +- .width = 8, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 176, +- .width = 16, +- }, +- [VCAP_KF_L3_PAYLOAD] = { +- .type = VCAP_FIELD_U112, +- .offset = 192, +- .width = 96, +- }, +-}; +- +-static const struct vcap_field is2_ip6_std_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 4, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 4, +- .width = 1, +- }, +- [VCAP_KF_LOOKUP_PAG] = { +- .type = VCAP_FIELD_U32, +- .offset = 5, +- .width = 8, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 14, +- .width = 4, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 18, +- .width = 2, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 20, +- .width = 32, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 52, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 53, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 54, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 56, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 57, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 67, +- .width = 13, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 80, +- .width = 1, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 81, +- .width = 3, +- }, +- [VCAP_KF_L2_FWD_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 84, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_L3_TTL_GT0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 89, +- .width = 1, +- }, +- [VCAP_KF_L3_IP6_SIP] = { +- .type = VCAP_FIELD_U128, +- .offset = 90, +- .width = 128, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 218, +- .width = 1, +- }, +- [VCAP_KF_L3_IP_PROTO] = { +- .type = VCAP_FIELD_U32, +- .offset = 219, +- .width = 8, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 227, +- .width = 16, +- }, +- [VCAP_KF_L3_PAYLOAD] = { +- .type = VCAP_FIELD_U48, +- .offset = 243, +- .width = 40, +- }, +-}; +- +-static const struct vcap_field is2_ip_7tuple_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 2, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 2, +- .width = 1, +- }, +- [VCAP_KF_LOOKUP_PAG] = { +- .type = VCAP_FIELD_U32, +- .offset = 3, +- .width = 8, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_L3] = { +- .type = VCAP_FIELD_BIT, +- .offset = 11, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 12, +- .width = 4, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 16, +- .width = 2, +- }, +- [VCAP_KF_IF_IGR_PORT_MASK] = { +- .type = VCAP_FIELD_U72, +- .offset = 18, +- .width = 65, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 83, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 84, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 85, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 88, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 98, +- .width = 13, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 111, +- .width = 1, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 112, +- .width = 3, +- }, +- [VCAP_KF_L2_FWD_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 115, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 118, +- .width = 1, +- }, +- [VCAP_KF_L3_DST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 119, +- .width = 1, +- }, +- [VCAP_KF_L2_DMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 120, +- .width = 48, +- }, +- [VCAP_KF_L2_SMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 168, +- .width = 48, +- }, +- [VCAP_KF_IP4_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 218, +- .width = 1, +- }, +- [VCAP_KF_L3_TTL_GT0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 219, +- .width = 1, +- }, +- [VCAP_KF_L3_TOS] = { +- .type = VCAP_FIELD_U32, +- .offset = 220, +- .width = 8, +- }, +- [VCAP_KF_L3_IP6_DIP] = { +- .type = VCAP_FIELD_U128, +- .offset = 228, +- .width = 128, +- }, +- [VCAP_KF_L3_IP6_SIP] = { +- .type = VCAP_FIELD_U128, +- .offset = 356, +- .width = 128, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 484, +- .width = 1, +- }, +- [VCAP_KF_TCP_UDP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 485, +- .width = 1, +- }, +- [VCAP_KF_TCP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 486, +- .width = 1, +- }, +- [VCAP_KF_L4_DPORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 487, +- .width = 16, +- }, +- [VCAP_KF_L4_SPORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 503, +- .width = 16, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 519, +- .width = 16, +- }, +- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 535, +- .width = 1, +- }, +- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 536, +- .width = 1, +- }, +- [VCAP_KF_L4_FIN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 537, +- .width = 1, +- }, +- [VCAP_KF_L4_SYN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 538, +- .width = 1, +- }, +- [VCAP_KF_L4_RST] = { +- .type = VCAP_FIELD_BIT, +- .offset = 539, +- .width = 1, +- }, +- [VCAP_KF_L4_PSH] = { +- .type = VCAP_FIELD_BIT, +- .offset = 540, +- .width = 1, +- }, +- [VCAP_KF_L4_ACK] = { +- .type = VCAP_FIELD_BIT, +- .offset = 541, +- .width = 1, +- }, +- [VCAP_KF_L4_URG] = { +- .type = VCAP_FIELD_BIT, +- .offset = 542, +- .width = 1, +- }, +- [VCAP_KF_L4_PAYLOAD] = { +- .type = VCAP_FIELD_U64, +- .offset = 543, +- .width = 64, +- }, +-}; +- +-static const struct vcap_field es0_isdx_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_BIT, +- .offset = 0, +- .width = 1, +- }, +- [VCAP_KF_IF_EGR_PORT_NO] = { +- .type = VCAP_FIELD_U32, +- .offset = 1, +- .width = 6, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 7, +- .width = 13, +- }, +- [VCAP_KF_COSID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 20, +- .width = 3, +- }, +- [VCAP_KF_8021Q_TPID] = { +- .type = VCAP_FIELD_U32, +- .offset = 23, +- .width = 3, +- }, +- [VCAP_KF_L3_DPL_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 26, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 27, +- .width = 1, +- }, +- [VCAP_KF_PROT_ACTIVE] = { +- .type = VCAP_FIELD_BIT, +- .offset = 28, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 38, +- .width = 10, +- }, +-}; +- +-static const struct vcap_field es2_mac_etype_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 3, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 3, +- .width = 1, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 14, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 15, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 16, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 26, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 28, +- .width = 13, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 41, +- .width = 3, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 44, +- .width = 32, +- }, +- [VCAP_KF_IF_IGR_PORT_SEL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 76, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 77, +- .width = 7, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 84, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_COSID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 88, +- .width = 3, +- }, +- [VCAP_KF_L3_DPL_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 91, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 92, +- .width = 1, +- }, +- [VCAP_KF_L2_DMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 96, +- .width = 48, +- }, +- [VCAP_KF_L2_SMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 144, +- .width = 48, +- }, +- [VCAP_KF_ETYPE_LEN_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 192, +- .width = 1, +- }, +- [VCAP_KF_ETYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 193, +- .width = 16, +- }, +- [VCAP_KF_L2_PAYLOAD_ETYPE] = { +- .type = VCAP_FIELD_U64, +- .offset = 209, +- .width = 64, +- }, +- [VCAP_KF_OAM_CCM_CNTS_EQ0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 273, +- .width = 1, +- }, +- [VCAP_KF_OAM_Y1731_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 274, +- .width = 1, +- }, +-}; +- +-static const struct vcap_field es2_arp_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 3, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 3, +- .width = 1, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 14, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 15, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 16, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 26, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 28, +- .width = 13, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 41, +- .width = 3, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 44, +- .width = 32, +- }, +- [VCAP_KF_IF_IGR_PORT_SEL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 76, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 77, +- .width = 7, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 84, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_COSID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 88, +- .width = 3, +- }, +- [VCAP_KF_L3_DPL_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 91, +- .width = 1, +- }, +- [VCAP_KF_L2_SMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 95, +- .width = 48, +- }, +- [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 143, +- .width = 1, +- }, +- [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 144, +- .width = 1, +- }, +- [VCAP_KF_ARP_LEN_OK_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 145, +- .width = 1, +- }, +- [VCAP_KF_ARP_TGT_MATCH_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 146, +- .width = 1, +- }, +- [VCAP_KF_ARP_SENDER_MATCH_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 147, +- .width = 1, +- }, +- [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 148, +- .width = 1, +- }, +- [VCAP_KF_ARP_OPCODE] = { +- .type = VCAP_FIELD_U32, +- .offset = 149, +- .width = 2, +- }, +- [VCAP_KF_L3_IP4_DIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 151, +- .width = 32, +- }, +- [VCAP_KF_L3_IP4_SIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 183, +- .width = 32, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 215, +- .width = 1, +- }, +-}; +- +-static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 3, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 3, +- .width = 1, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 14, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 15, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 16, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 26, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 28, +- .width = 13, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 41, +- .width = 3, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 44, +- .width = 32, +- }, +- [VCAP_KF_IF_IGR_PORT_SEL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 76, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 77, +- .width = 7, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 84, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_COSID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 88, +- .width = 3, +- }, +- [VCAP_KF_L3_DPL_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 91, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 92, +- .width = 1, +- }, +- [VCAP_KF_IP4_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 96, +- .width = 1, +- }, +- [VCAP_KF_L3_FRAGMENT_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 97, +- .width = 2, +- }, +- [VCAP_KF_L3_OPTIONS_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 99, +- .width = 1, +- }, +- [VCAP_KF_L3_TTL_GT0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 100, +- .width = 1, +- }, +- [VCAP_KF_L3_TOS] = { +- .type = VCAP_FIELD_U32, +- .offset = 101, +- .width = 8, +- }, +- [VCAP_KF_L3_IP4_DIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 109, +- .width = 32, +- }, +- [VCAP_KF_L3_IP4_SIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 141, +- .width = 32, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 173, +- .width = 1, +- }, +- [VCAP_KF_TCP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 174, +- .width = 1, +- }, +- [VCAP_KF_L4_DPORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 175, +- .width = 16, +- }, +- [VCAP_KF_L4_SPORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 191, +- .width = 16, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 207, +- .width = 16, +- }, +- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 223, +- .width = 1, +- }, +- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 224, +- .width = 1, +- }, +- [VCAP_KF_L4_FIN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 225, +- .width = 1, +- }, +- [VCAP_KF_L4_SYN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 226, +- .width = 1, +- }, +- [VCAP_KF_L4_RST] = { +- .type = VCAP_FIELD_BIT, +- .offset = 227, +- .width = 1, +- }, +- [VCAP_KF_L4_PSH] = { +- .type = VCAP_FIELD_BIT, +- .offset = 228, +- .width = 1, +- }, +- [VCAP_KF_L4_ACK] = { +- .type = VCAP_FIELD_BIT, +- .offset = 229, +- .width = 1, +- }, +- [VCAP_KF_L4_URG] = { +- .type = VCAP_FIELD_BIT, +- .offset = 230, +- .width = 1, +- }, +- [VCAP_KF_L4_PAYLOAD] = { +- .type = VCAP_FIELD_U64, +- .offset = 231, +- .width = 64, +- }, +-}; +- +-static const struct vcap_field es2_ip4_other_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 3, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 3, +- .width = 1, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 14, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 15, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 16, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 26, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 28, +- .width = 13, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 41, +- .width = 3, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 44, +- .width = 32, +- }, +- [VCAP_KF_IF_IGR_PORT_SEL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 76, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 77, +- .width = 7, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 84, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_COSID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 88, +- .width = 3, +- }, +- [VCAP_KF_L3_DPL_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 91, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 92, +- .width = 1, +- }, +- [VCAP_KF_IP4_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 96, +- .width = 1, +- }, +- [VCAP_KF_L3_FRAGMENT_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 97, +- .width = 2, +- }, +- [VCAP_KF_L3_OPTIONS_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 99, +- .width = 1, +- }, +- [VCAP_KF_L3_TTL_GT0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 100, +- .width = 1, +- }, +- [VCAP_KF_L3_TOS] = { +- .type = VCAP_FIELD_U32, +- .offset = 101, +- .width = 8, +- }, +- [VCAP_KF_L3_IP4_DIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 109, +- .width = 32, +- }, +- [VCAP_KF_L3_IP4_SIP] = { +- .type = VCAP_FIELD_U32, +- .offset = 141, +- .width = 32, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 173, +- .width = 1, +- }, +- [VCAP_KF_L3_IP_PROTO] = { +- .type = VCAP_FIELD_U32, +- .offset = 174, +- .width = 8, +- }, +- [VCAP_KF_L3_PAYLOAD] = { +- .type = VCAP_FIELD_U112, +- .offset = 182, +- .width = 96, +- }, +-}; +- +-static const struct vcap_field es2_ip_7tuple_keyfield[] = { +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 0, +- .width = 1, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 10, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 11, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 12, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 13, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 23, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 25, +- .width = 13, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 38, +- .width = 3, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 41, +- .width = 32, +- }, +- [VCAP_KF_IF_IGR_PORT_SEL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 73, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 74, +- .width = 7, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 81, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 84, +- .width = 1, +- }, +- [VCAP_KF_COSID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 85, +- .width = 3, +- }, +- [VCAP_KF_L3_DPL_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 88, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 89, +- .width = 1, +- }, +- [VCAP_KF_L2_DMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 93, +- .width = 48, +- }, +- [VCAP_KF_L2_SMAC] = { +- .type = VCAP_FIELD_U48, +- .offset = 141, +- .width = 48, +- }, +- [VCAP_KF_IP4_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 191, +- .width = 1, +- }, +- [VCAP_KF_L3_TTL_GT0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 192, +- .width = 1, +- }, +- [VCAP_KF_L3_TOS] = { +- .type = VCAP_FIELD_U32, +- .offset = 193, +- .width = 8, +- }, +- [VCAP_KF_L3_IP6_DIP] = { +- .type = VCAP_FIELD_U128, +- .offset = 201, +- .width = 128, +- }, +- [VCAP_KF_L3_IP6_SIP] = { +- .type = VCAP_FIELD_U128, +- .offset = 329, +- .width = 128, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 457, +- .width = 1, +- }, +- [VCAP_KF_TCP_UDP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 458, +- .width = 1, +- }, +- [VCAP_KF_TCP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 459, +- .width = 1, +- }, +- [VCAP_KF_L4_DPORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 460, +- .width = 16, +- }, +- [VCAP_KF_L4_SPORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 476, +- .width = 16, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 492, +- .width = 16, +- }, +- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 508, +- .width = 1, +- }, +- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 509, +- .width = 1, +- }, +- [VCAP_KF_L4_FIN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 510, +- .width = 1, +- }, +- [VCAP_KF_L4_SYN] = { +- .type = VCAP_FIELD_BIT, +- .offset = 511, +- .width = 1, +- }, +- [VCAP_KF_L4_RST] = { +- .type = VCAP_FIELD_BIT, +- .offset = 512, +- .width = 1, +- }, +- [VCAP_KF_L4_PSH] = { +- .type = VCAP_FIELD_BIT, +- .offset = 513, +- .width = 1, +- }, +- [VCAP_KF_L4_ACK] = { +- .type = VCAP_FIELD_BIT, +- .offset = 514, +- .width = 1, +- }, +- [VCAP_KF_L4_URG] = { +- .type = VCAP_FIELD_BIT, +- .offset = 515, +- .width = 1, +- }, +- [VCAP_KF_L4_PAYLOAD] = { +- .type = VCAP_FIELD_U64, +- .offset = 516, +- .width = 64, +- }, +-}; +- +-static const struct vcap_field es2_ip6_std_keyfield[] = { +- [VCAP_KF_TYPE] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 3, +- }, +- [VCAP_KF_LOOKUP_FIRST_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 3, +- .width = 1, +- }, +- [VCAP_KF_L2_MC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 13, +- .width = 1, +- }, +- [VCAP_KF_L2_BC_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 14, +- .width = 1, +- }, +- [VCAP_KF_ISDX_GT0_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 15, +- .width = 1, +- }, +- [VCAP_KF_ISDX_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 16, +- .width = 10, +- }, +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 26, +- .width = 1, +- }, +- [VCAP_KF_8021Q_VID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 28, +- .width = 13, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 41, +- .width = 3, +- }, +- [VCAP_KF_IF_EGR_PORT_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 44, +- .width = 32, +- }, +- [VCAP_KF_IF_IGR_PORT_SEL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 76, +- .width = 1, +- }, +- [VCAP_KF_IF_IGR_PORT] = { +- .type = VCAP_FIELD_U32, +- .offset = 77, +- .width = 7, +- }, +- [VCAP_KF_8021Q_PCP_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 84, +- .width = 3, +- }, +- [VCAP_KF_8021Q_DEI_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 87, +- .width = 1, +- }, +- [VCAP_KF_COSID_CLS] = { +- .type = VCAP_FIELD_U32, +- .offset = 88, +- .width = 3, +- }, +- [VCAP_KF_L3_DPL_CLS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 91, +- .width = 1, +- }, +- [VCAP_KF_L3_RT_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 92, +- .width = 1, +- }, +- [VCAP_KF_L3_TTL_GT0] = { +- .type = VCAP_FIELD_BIT, +- .offset = 96, +- .width = 1, +- }, +- [VCAP_KF_L3_IP6_SIP] = { +- .type = VCAP_FIELD_U128, +- .offset = 97, +- .width = 128, +- }, +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 225, +- .width = 1, +- }, +- [VCAP_KF_L3_IP_PROTO] = { +- .type = VCAP_FIELD_U32, +- .offset = 226, +- .width = 8, +- }, +- [VCAP_KF_L4_RNG] = { +- .type = VCAP_FIELD_U32, +- .offset = 234, +- .width = 16, +- }, +- [VCAP_KF_L3_PAYLOAD] = { +- .type = VCAP_FIELD_U48, +- .offset = 250, +- .width = 40, +- }, +-}; +- +-/* keyfield_set */ +-static const struct vcap_set is0_keyfield_set[] = { +- [VCAP_KFS_NORMAL_7TUPLE] = { +- .type_id = 0, +- .sw_per_item = 12, +- .sw_cnt = 1, +- }, +- [VCAP_KFS_NORMAL_5TUPLE_IP4] = { +- .type_id = 2, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +-}; +- +-static const struct vcap_set is2_keyfield_set[] = { +- [VCAP_KFS_MAC_ETYPE] = { +- .type_id = 0, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +- [VCAP_KFS_ARP] = { +- .type_id = 3, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +- [VCAP_KFS_IP4_TCP_UDP] = { +- .type_id = 4, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +- [VCAP_KFS_IP4_OTHER] = { +- .type_id = 5, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +- [VCAP_KFS_IP6_STD] = { +- .type_id = 6, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +- [VCAP_KFS_IP_7TUPLE] = { +- .type_id = 1, +- .sw_per_item = 12, +- .sw_cnt = 1, +- }, +-}; +- +-static const struct vcap_set es0_keyfield_set[] = { +- [VCAP_KFS_ISDX] = { +- .type_id = 0, +- .sw_per_item = 1, +- .sw_cnt = 1, +- }, +-}; +- +-static const struct vcap_set es2_keyfield_set[] = { +- [VCAP_KFS_MAC_ETYPE] = { +- .type_id = 0, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +- [VCAP_KFS_ARP] = { +- .type_id = 1, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +- [VCAP_KFS_IP4_TCP_UDP] = { +- .type_id = 2, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +- [VCAP_KFS_IP4_OTHER] = { +- .type_id = 3, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +- [VCAP_KFS_IP_7TUPLE] = { +- .type_id = -1, +- .sw_per_item = 12, +- .sw_cnt = 1, +- }, +- [VCAP_KFS_IP6_STD] = { +- .type_id = 4, +- .sw_per_item = 6, +- .sw_cnt = 2, +- }, +-}; +- +-/* keyfield_set map */ +-static const struct vcap_field *is0_keyfield_set_map[] = { +- [VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield, +- [VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield, +-}; +- +-static const struct vcap_field *is2_keyfield_set_map[] = { +- [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield, +- [VCAP_KFS_ARP] = is2_arp_keyfield, +- [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield, +- [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield, +- [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield, +- [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield, +-}; +- +-static const struct vcap_field *es0_keyfield_set_map[] = { +- [VCAP_KFS_ISDX] = es0_isdx_keyfield, +-}; +- +-static const struct vcap_field *es2_keyfield_set_map[] = { +- [VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield, +- [VCAP_KFS_ARP] = es2_arp_keyfield, +- [VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield, +- [VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield, +- [VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield, +- [VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield, +-}; +- +-/* keyfield_set map sizes */ +-static int is0_keyfield_set_map_size[] = { +- [VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield), +- [VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield), +-}; +- +-static int is2_keyfield_set_map_size[] = { +- [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield), +- [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield), +- [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), +- [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield), +- [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield), +- [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield), +-}; +- +-static int es0_keyfield_set_map_size[] = { +- [VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield), +-}; +- +-static int es2_keyfield_set_map_size[] = { +- [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield), +- [VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield), +- [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), +- [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield), +- [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield), +- [VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield), +-}; +- +-/* actionfields */ +-static const struct vcap_field is0_classification_actionfield[] = { +- [VCAP_AF_TYPE] = { +- .type = VCAP_FIELD_BIT, +- .offset = 0, +- .width = 1, +- }, +- [VCAP_AF_DSCP_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 1, +- .width = 1, +- }, +- [VCAP_AF_DSCP_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 2, +- .width = 6, +- }, +- [VCAP_AF_QOS_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 12, +- .width = 1, +- }, +- [VCAP_AF_QOS_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 13, +- .width = 3, +- }, +- [VCAP_AF_DP_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 16, +- .width = 1, +- }, +- [VCAP_AF_DP_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 17, +- .width = 2, +- }, +- [VCAP_AF_DEI_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 19, +- .width = 1, +- }, +- [VCAP_AF_DEI_VAL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 20, +- .width = 1, +- }, +- [VCAP_AF_PCP_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 21, +- .width = 1, +- }, +- [VCAP_AF_PCP_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 22, +- .width = 3, +- }, +- [VCAP_AF_MAP_LOOKUP_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 25, +- .width = 2, +- }, +- [VCAP_AF_MAP_KEY] = { +- .type = VCAP_FIELD_U32, +- .offset = 27, +- .width = 3, +- }, +- [VCAP_AF_MAP_IDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 30, +- .width = 7, +- }, +- [VCAP_AF_CLS_VID_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 37, +- .width = 3, +- }, +- [VCAP_AF_VID_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 43, +- .width = 13, +- }, +- [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 66, +- .width = 1, +- }, +- [VCAP_AF_ISDX_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 67, +- .width = 10, +- }, +- [VCAP_AF_PAG_OVERRIDE_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 107, +- .width = 8, +- }, +- [VCAP_AF_PAG_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 115, +- .width = 8, +- }, +- [VCAP_AF_NXT_IDX_CTRL] = { +- .type = VCAP_FIELD_U32, +- .offset = 167, +- .width = 3, +- }, +- [VCAP_AF_NXT_IDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 170, +- .width = 10, +- }, +-}; +- +-static const struct vcap_field is0_full_actionfield[] = { +- [VCAP_AF_DSCP_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 0, +- .width = 1, +- }, +- [VCAP_AF_DSCP_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 1, +- .width = 6, +- }, +- [VCAP_AF_QOS_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 11, +- .width = 1, +- }, +- [VCAP_AF_QOS_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 12, +- .width = 3, +- }, +- [VCAP_AF_DP_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 15, +- .width = 1, +- }, +- [VCAP_AF_DP_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 16, +- .width = 2, +- }, +- [VCAP_AF_DEI_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 18, +- .width = 1, +- }, +- [VCAP_AF_DEI_VAL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 19, +- .width = 1, +- }, +- [VCAP_AF_PCP_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 20, +- .width = 1, +- }, +- [VCAP_AF_PCP_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 21, +- .width = 3, +- }, +- [VCAP_AF_MAP_LOOKUP_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 24, +- .width = 2, +- }, +- [VCAP_AF_MAP_KEY] = { +- .type = VCAP_FIELD_U32, +- .offset = 26, +- .width = 3, +- }, +- [VCAP_AF_MAP_IDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 29, +- .width = 7, +- }, +- [VCAP_AF_CLS_VID_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 36, +- .width = 3, +- }, +- [VCAP_AF_VID_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 42, +- .width = 13, +- }, +- [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 65, +- .width = 1, +- }, +- [VCAP_AF_ISDX_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 66, +- .width = 10, +- }, +- [VCAP_AF_MASK_MODE] = { +- .type = VCAP_FIELD_U32, +- .offset = 76, +- .width = 3, +- }, +- [VCAP_AF_PORT_MASK] = { +- .type = VCAP_FIELD_U48, +- .offset = 79, +- .width = 37, +- }, +- [VCAP_AF_PAG_OVERRIDE_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 174, +- .width = 8, +- }, +- [VCAP_AF_PAG_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 182, +- .width = 8, +- }, +- [VCAP_AF_NXT_IDX_CTRL] = { +- .type = VCAP_FIELD_U32, +- .offset = 266, +- .width = 3, +- }, +- [VCAP_AF_NXT_IDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 269, +- .width = 10, +- }, +-}; +- +-static const struct vcap_field is0_class_reduced_actionfield[] = { +- [VCAP_AF_TYPE] = { +- .type = VCAP_FIELD_BIT, +- .offset = 0, +- .width = 1, +- }, +- [VCAP_AF_QOS_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 5, +- .width = 1, +- }, +- [VCAP_AF_QOS_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 6, +- .width = 3, +- }, +- [VCAP_AF_DP_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 9, +- .width = 1, +- }, +- [VCAP_AF_DP_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 10, +- .width = 2, +- }, +- [VCAP_AF_MAP_LOOKUP_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 12, +- .width = 2, +- }, +- [VCAP_AF_MAP_KEY] = { +- .type = VCAP_FIELD_U32, +- .offset = 14, +- .width = 3, +- }, +- [VCAP_AF_CLS_VID_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 17, +- .width = 3, +- }, +- [VCAP_AF_VID_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 23, +- .width = 13, +- }, +- [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 46, +- .width = 1, +- }, +- [VCAP_AF_ISDX_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 47, +- .width = 10, +- }, +- [VCAP_AF_NXT_IDX_CTRL] = { +- .type = VCAP_FIELD_U32, +- .offset = 89, +- .width = 3, +- }, +- [VCAP_AF_NXT_IDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 92, +- .width = 10, +- }, +-}; +- +-static const struct vcap_field is2_base_type_actionfield[] = { +- [VCAP_AF_PIPELINE_FORCE_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 1, +- .width = 1, +- }, +- [VCAP_AF_PIPELINE_PT] = { +- .type = VCAP_FIELD_U32, +- .offset = 2, +- .width = 5, +- }, +- [VCAP_AF_HIT_ME_ONCE] = { +- .type = VCAP_FIELD_BIT, +- .offset = 7, +- .width = 1, +- }, +- [VCAP_AF_INTR_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 8, +- .width = 1, +- }, +- [VCAP_AF_CPU_COPY_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 9, +- .width = 1, +- }, +- [VCAP_AF_CPU_QUEUE_NUM] = { +- .type = VCAP_FIELD_U32, +- .offset = 10, +- .width = 3, +- }, +- [VCAP_AF_LRN_DIS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 15, +- .width = 1, +- }, +- [VCAP_AF_RT_DIS] = { +- .type = VCAP_FIELD_BIT, +- .offset = 16, +- .width = 1, +- }, +- [VCAP_AF_POLICE_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 17, +- .width = 1, +- }, +- [VCAP_AF_POLICE_IDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 18, +- .width = 5, +- }, +- [VCAP_AF_IGNORE_PIPELINE_CTRL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 23, +- .width = 1, +- }, +- [VCAP_AF_MASK_MODE] = { +- .type = VCAP_FIELD_U32, +- .offset = 27, +- .width = 3, +- }, +- [VCAP_AF_PORT_MASK] = { +- .type = VCAP_FIELD_U48, +- .offset = 30, +- .width = 37, +- }, +- [VCAP_AF_MIRROR_PROBE] = { +- .type = VCAP_FIELD_U32, +- .offset = 78, +- .width = 2, +- }, +- [VCAP_AF_MATCH_ID] = { +- .type = VCAP_FIELD_U32, +- .offset = 131, +- .width = 16, +- }, +- [VCAP_AF_MATCH_ID_MASK] = { +- .type = VCAP_FIELD_U32, +- .offset = 147, +- .width = 16, +- }, +- [VCAP_AF_CNT_ID] = { +- .type = VCAP_FIELD_U32, +- .offset = 163, +- .width = 10, +- }, +-}; +- +-static const struct vcap_field es0_es0_actionfield[] = { +- [VCAP_AF_PUSH_OUTER_TAG] = { +- .type = VCAP_FIELD_U32, +- .offset = 0, +- .width = 2, +- }, +- [VCAP_AF_PUSH_INNER_TAG] = { +- .type = VCAP_FIELD_BIT, +- .offset = 2, +- .width = 1, +- }, +- [VCAP_AF_TAG_A_TPID_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 3, +- .width = 3, +- }, +- [VCAP_AF_TAG_A_VID_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 6, +- .width = 2, +- }, +- [VCAP_AF_TAG_A_PCP_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 8, +- .width = 3, +- }, +- [VCAP_AF_TAG_A_DEI_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 11, +- .width = 3, +- }, +- [VCAP_AF_TAG_B_TPID_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 14, +- .width = 3, +- }, +- [VCAP_AF_TAG_B_VID_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 17, +- .width = 2, +- }, +- [VCAP_AF_TAG_B_PCP_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 19, +- .width = 3, +- }, +- [VCAP_AF_TAG_B_DEI_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 22, +- .width = 3, +- }, +- [VCAP_AF_TAG_C_TPID_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 25, +- .width = 3, +- }, +- [VCAP_AF_TAG_C_PCP_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 28, +- .width = 3, +- }, +- [VCAP_AF_TAG_C_DEI_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 31, +- .width = 3, +- }, +- [VCAP_AF_VID_A_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 34, +- .width = 12, +- }, +- [VCAP_AF_PCP_A_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 46, +- .width = 3, +- }, +- [VCAP_AF_DEI_A_VAL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 49, +- .width = 1, +- }, +- [VCAP_AF_VID_B_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 50, +- .width = 12, +- }, +- [VCAP_AF_PCP_B_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 62, +- .width = 3, +- }, +- [VCAP_AF_DEI_B_VAL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 65, +- .width = 1, +- }, +- [VCAP_AF_VID_C_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 66, +- .width = 12, +- }, +- [VCAP_AF_PCP_C_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 78, +- .width = 3, +- }, +- [VCAP_AF_DEI_C_VAL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 81, +- .width = 1, +- }, +- [VCAP_AF_POP_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 82, +- .width = 2, +- }, +- [VCAP_AF_UNTAG_VID_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 84, +- .width = 1, +- }, +- [VCAP_AF_PUSH_CUSTOMER_TAG] = { +- .type = VCAP_FIELD_U32, +- .offset = 85, +- .width = 2, +- }, +- [VCAP_AF_TAG_C_VID_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 87, +- .width = 2, +- }, +- [VCAP_AF_DSCP_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 127, +- .width = 3, +- }, +- [VCAP_AF_DSCP_VAL] = { +- .type = VCAP_FIELD_U32, +- .offset = 130, +- .width = 6, +- }, +- [VCAP_AF_ESDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 319, +- .width = 10, +- }, +- [VCAP_AF_FWD_SEL] = { +- .type = VCAP_FIELD_U32, +- .offset = 438, +- .width = 2, +- }, +- [VCAP_AF_CPU_QU] = { +- .type = VCAP_FIELD_U32, +- .offset = 440, +- .width = 3, +- }, +- [VCAP_AF_PIPELINE_PT] = { +- .type = VCAP_FIELD_U32, +- .offset = 443, +- .width = 2, +- }, +- [VCAP_AF_PIPELINE_ACT] = { +- .type = VCAP_FIELD_BIT, +- .offset = 445, +- .width = 1, +- }, +- [VCAP_AF_SWAP_MACS_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 454, +- .width = 1, +- }, +- [VCAP_AF_LOOP_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 455, +- .width = 1, +- }, +-}; +- +-static const struct vcap_field es2_base_type_actionfield[] = { +- [VCAP_AF_HIT_ME_ONCE] = { +- .type = VCAP_FIELD_BIT, +- .offset = 0, +- .width = 1, +- }, +- [VCAP_AF_INTR_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 1, +- .width = 1, +- }, +- [VCAP_AF_FWD_MODE] = { +- .type = VCAP_FIELD_U32, +- .offset = 2, +- .width = 2, +- }, +- [VCAP_AF_COPY_QUEUE_NUM] = { +- .type = VCAP_FIELD_U32, +- .offset = 4, +- .width = 14, +- }, +- [VCAP_AF_COPY_PORT_NUM] = { +- .type = VCAP_FIELD_U32, +- .offset = 18, +- .width = 6, +- }, +- [VCAP_AF_MIRROR_PROBE_ID] = { +- .type = VCAP_FIELD_U32, +- .offset = 24, +- .width = 2, +- }, +- [VCAP_AF_CPU_COPY_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 26, +- .width = 1, +- }, +- [VCAP_AF_CPU_QUEUE_NUM] = { +- .type = VCAP_FIELD_U32, +- .offset = 27, +- .width = 3, +- }, +- [VCAP_AF_POLICE_ENA] = { +- .type = VCAP_FIELD_BIT, +- .offset = 30, +- .width = 1, +- }, +- [VCAP_AF_POLICE_REMARK] = { +- .type = VCAP_FIELD_BIT, +- .offset = 31, +- .width = 1, +- }, +- [VCAP_AF_POLICE_IDX] = { +- .type = VCAP_FIELD_U32, +- .offset = 32, +- .width = 5, +- }, +- [VCAP_AF_ES2_REW_CMD] = { +- .type = VCAP_FIELD_U32, +- .offset = 37, +- .width = 3, +- }, +- [VCAP_AF_CNT_ID] = { +- .type = VCAP_FIELD_U32, +- .offset = 40, +- .width = 9, +- }, +- [VCAP_AF_IGNORE_PIPELINE_CTRL] = { +- .type = VCAP_FIELD_BIT, +- .offset = 49, +- .width = 1, +- }, +-}; +- +-/* actionfield_set */ +-static const struct vcap_set is0_actionfield_set[] = { +- [VCAP_AFS_CLASSIFICATION] = { +- .type_id = 1, +- .sw_per_item = 2, +- .sw_cnt = 6, +- }, +- [VCAP_AFS_FULL] = { +- .type_id = -1, +- .sw_per_item = 3, +- .sw_cnt = 4, +- }, +- [VCAP_AFS_CLASS_REDUCED] = { +- .type_id = 1, +- .sw_per_item = 1, +- .sw_cnt = 12, +- }, +-}; +- +-static const struct vcap_set is2_actionfield_set[] = { +- [VCAP_AFS_BASE_TYPE] = { +- .type_id = -1, +- .sw_per_item = 3, +- .sw_cnt = 4, +- }, +-}; +- +-static const struct vcap_set es0_actionfield_set[] = { +- [VCAP_AFS_ES0] = { +- .type_id = -1, +- .sw_per_item = 1, +- .sw_cnt = 1, +- }, +-}; +- +-static const struct vcap_set es2_actionfield_set[] = { +- [VCAP_AFS_BASE_TYPE] = { +- .type_id = -1, +- .sw_per_item = 3, +- .sw_cnt = 4, +- }, +-}; +- +-/* actionfield_set map */ +-static const struct vcap_field *is0_actionfield_set_map[] = { +- [VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield, +- [VCAP_AFS_FULL] = is0_full_actionfield, +- [VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield, +-}; +- +-static const struct vcap_field *is2_actionfield_set_map[] = { +- [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield, +-}; +- +-static const struct vcap_field *es0_actionfield_set_map[] = { +- [VCAP_AFS_ES0] = es0_es0_actionfield, +-}; +- +-static const struct vcap_field *es2_actionfield_set_map[] = { +- [VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield, +-}; +- +-/* actionfield_set map size */ +-static int is0_actionfield_set_map_size[] = { +- [VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield), +- [VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield), +- [VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield), +-}; +- +-static int is2_actionfield_set_map_size[] = { +- [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield), +-}; +- +-static int es0_actionfield_set_map_size[] = { +- [VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield), +-}; +- +-static int es2_actionfield_set_map_size[] = { +- [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield), +-}; +- +-/* Type Groups */ +-static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 5, +- .value = 16, +- }, +- { +- .offset = 52, +- .width = 1, +- .value = 0, +- }, +- { +- .offset = 104, +- .width = 2, +- .value = 0, +- }, +- { +- .offset = 156, +- .width = 3, +- .value = 0, +- }, +- { +- .offset = 208, +- .width = 2, +- .value = 0, +- }, +- { +- .offset = 260, +- .width = 1, +- .value = 0, +- }, +- { +- .offset = 312, +- .width = 4, +- .value = 0, +- }, +- { +- .offset = 364, +- .width = 1, +- .value = 0, +- }, +- { +- .offset = 416, +- .width = 2, +- .value = 0, +- }, +- { +- .offset = 468, +- .width = 3, +- .value = 0, +- }, +- { +- .offset = 520, +- .width = 2, +- .value = 0, +- }, +- { +- .offset = 572, +- .width = 1, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 4, +- .value = 8, +- }, +- { +- .offset = 52, +- .width = 1, +- .value = 0, +- }, +- { +- .offset = 104, +- .width = 2, +- .value = 0, +- }, +- { +- .offset = 156, +- .width = 3, +- .value = 0, +- }, +- { +- .offset = 208, +- .width = 2, +- .value = 0, +- }, +- { +- .offset = 260, +- .width = 1, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 3, +- .value = 4, +- }, +- { +- .offset = 156, +- .width = 1, +- .value = 0, +- }, +- { +- .offset = 312, +- .width = 2, +- .value = 0, +- }, +- { +- .offset = 468, +- .width = 1, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 2, +- .value = 2, +- }, +- { +- .offset = 156, +- .width = 1, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 3, +- .value = 4, +- }, +- { +- .offset = 156, +- .width = 1, +- .value = 0, +- }, +- { +- .offset = 312, +- .width = 2, +- .value = 0, +- }, +- { +- .offset = 468, +- .width = 1, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 2, +- .value = 2, +- }, +- { +- .offset = 156, +- .width = 1, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = { +- [12] = is0_x12_keyfield_set_typegroups, +- [6] = is0_x6_keyfield_set_typegroups, +- [3] = is0_x3_keyfield_set_typegroups, +- [2] = is0_x2_keyfield_set_typegroups, +- [1] = is0_x1_keyfield_set_typegroups, +- [13] = NULL, +-}; +- +-static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = { +- [12] = is2_x12_keyfield_set_typegroups, +- [6] = is2_x6_keyfield_set_typegroups, +- [3] = is2_x3_keyfield_set_typegroups, +- [1] = is2_x1_keyfield_set_typegroups, +- [13] = NULL, +-}; +- +-static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = { +- [1] = es0_x1_keyfield_set_typegroups, +- [2] = NULL, +-}; +- +-static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = { +- [12] = es2_x12_keyfield_set_typegroups, +- [6] = es2_x6_keyfield_set_typegroups, +- [3] = es2_x3_keyfield_set_typegroups, +- [1] = es2_x1_keyfield_set_typegroups, +- [13] = NULL, +-}; +- +-static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 3, +- .value = 4, +- }, +- { +- .offset = 103, +- .width = 2, +- .value = 0, +- }, +- { +- .offset = 206, +- .width = 2, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 2, +- .value = 2, +- }, +- { +- .offset = 103, +- .width = 1, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 1, +- .value = 1, +- }, +- {} +-}; +- +-static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 2, +- .value = 2, +- }, +- { +- .offset = 95, +- .width = 1, +- .value = 0, +- }, +- { +- .offset = 190, +- .width = 1, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = { +- { +- .offset = 0, +- .width = 2, +- .value = 2, +- }, +- { +- .offset = 19, +- .width = 1, +- .value = 0, +- }, +- { +- .offset = 38, +- .width = 1, +- .value = 0, +- }, +- {} +-}; +- +-static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = { +- {} +-}; +- +-static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = { +- [3] = is0_x3_actionfield_set_typegroups, +- [2] = is0_x2_actionfield_set_typegroups, +- [1] = is0_x1_actionfield_set_typegroups, +- [13] = NULL, +-}; +- +-static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = { +- [3] = is2_x3_actionfield_set_typegroups, +- [1] = is2_x1_actionfield_set_typegroups, +- [13] = NULL, +-}; +- +-static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = { +- [1] = es0_x1_actionfield_set_typegroups, +- [2] = NULL, +-}; +- +-static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = { +- [3] = es2_x3_actionfield_set_typegroups, +- [1] = es2_x1_actionfield_set_typegroups, +- [13] = NULL, +-}; +- +-/* Keyfieldset names */ +-static const char * const vcap_keyfield_set_names[] = { +- [VCAP_KFS_NO_VALUE] = "(None)", +- [VCAP_KFS_ARP] = "VCAP_KFS_ARP", +- [VCAP_KFS_ETAG] = "VCAP_KFS_ETAG", +- [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER", +- [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP", +- [VCAP_KFS_IP4_VID] = "VCAP_KFS_IP4_VID", +- [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER", +- [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD", +- [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP", +- [VCAP_KFS_IP6_VID] = "VCAP_KFS_IP6_VID", +- [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE", +- [VCAP_KFS_ISDX] = "VCAP_KFS_ISDX", +- [VCAP_KFS_LL_FULL] = "VCAP_KFS_LL_FULL", +- [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE", +- [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC", +- [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP", +- [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4", +- [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE", +- [VCAP_KFS_OAM] = "VCAP_KFS_OAM", +- [VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4", +- [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4", +- [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6", +-}; +- +-/* Actionfieldset names */ +-static const char * const vcap_actionfield_set_names[] = { +- [VCAP_AFS_NO_VALUE] = "(None)", +- [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE", +- [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION", +- [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED", +- [VCAP_AFS_ES0] = "VCAP_AFS_ES0", +- [VCAP_AFS_FULL] = "VCAP_AFS_FULL", +- [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP", +-}; +- +-/* Keyfield names */ +-static const char * const vcap_keyfield_names[] = { +- [VCAP_KF_NO_VALUE] = "(None)", +- [VCAP_KF_8021BR_ECID_BASE] = "8021BR_ECID_BASE", +- [VCAP_KF_8021BR_ECID_EXT] = "8021BR_ECID_EXT", +- [VCAP_KF_8021BR_E_TAGGED] = "8021BR_E_TAGGED", +- [VCAP_KF_8021BR_GRP] = "8021BR_GRP", +- [VCAP_KF_8021BR_IGR_ECID_BASE] = "8021BR_IGR_ECID_BASE", +- [VCAP_KF_8021BR_IGR_ECID_EXT] = "8021BR_IGR_ECID_EXT", +- [VCAP_KF_8021Q_DEI0] = "8021Q_DEI0", +- [VCAP_KF_8021Q_DEI1] = "8021Q_DEI1", +- [VCAP_KF_8021Q_DEI2] = "8021Q_DEI2", +- [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS", +- [VCAP_KF_8021Q_PCP0] = "8021Q_PCP0", +- [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1", +- [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2", +- [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS", +- [VCAP_KF_8021Q_TPID] = "8021Q_TPID", +- [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0", +- [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1", +- [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2", +- [VCAP_KF_8021Q_VID0] = "8021Q_VID0", +- [VCAP_KF_8021Q_VID1] = "8021Q_VID1", +- [VCAP_KF_8021Q_VID2] = "8021Q_VID2", +- [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS", +- [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS", +- [VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS", +- [VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID", +- [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS", +- [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS", +- [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE", +- [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS", +- [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS", +- [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS", +- [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS", +- [VCAP_KF_COSID_CLS] = "COSID_CLS", +- [VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA", +- [VCAP_KF_ETYPE] = "ETYPE", +- [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS", +- [VCAP_KF_HOST_MATCH] = "HOST_MATCH", +- [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK", +- [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG", +- [VCAP_KF_IF_EGR_PORT_NO] = "IF_EGR_PORT_NO", +- [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT", +- [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK", +- [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3", +- [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG", +- [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL", +- [VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL", +- [VCAP_KF_IP4_IS] = "IP4_IS", +- [VCAP_KF_IP_MC_IS] = "IP_MC_IS", +- [VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE", +- [VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS", +- [VCAP_KF_ISDX_CLS] = "ISDX_CLS", +- [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS", +- [VCAP_KF_L2_BC_IS] = "L2_BC_IS", +- [VCAP_KF_L2_DMAC] = "L2_DMAC", +- [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE", +- [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS", +- [VCAP_KF_L2_LLC] = "L2_LLC", +- [VCAP_KF_L2_MC_IS] = "L2_MC_IS", +- [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0", +- [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1", +- [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2", +- [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE", +- [VCAP_KF_L2_SMAC] = "L2_SMAC", +- [VCAP_KF_L2_SNAP] = "L2_SNAP", +- [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS", +- [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS", +- [VCAP_KF_L3_DSCP] = "L3_DSCP", +- [VCAP_KF_L3_DST_IS] = "L3_DST_IS", +- [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT", +- [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE", +- [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN", +- [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0", +- [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP", +- [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP", +- [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP", +- [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP", +- [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO", +- [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS", +- [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD", +- [VCAP_KF_L3_RT_IS] = "L3_RT_IS", +- [VCAP_KF_L3_TOS] = "L3_TOS", +- [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0", +- [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM", +- [VCAP_KF_L4_1588_VER] = "L4_1588_VER", +- [VCAP_KF_L4_ACK] = "L4_ACK", +- [VCAP_KF_L4_DPORT] = "L4_DPORT", +- [VCAP_KF_L4_FIN] = "L4_FIN", +- [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD", +- [VCAP_KF_L4_PSH] = "L4_PSH", +- [VCAP_KF_L4_RNG] = "L4_RNG", +- [VCAP_KF_L4_RST] = "L4_RST", +- [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS", +- [VCAP_KF_L4_SPORT] = "L4_SPORT", +- [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS", +- [VCAP_KF_L4_SYN] = "L4_SYN", +- [VCAP_KF_L4_URG] = "L4_URG", +- [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS", +- [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX", +- [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL", +- [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG", +- [VCAP_KF_MIRROR_PROBE] = "MIRROR_PROBE", +- [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0", +- [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED", +- [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS", +- [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS", +- [VCAP_KF_OAM_MEPID] = "OAM_MEPID", +- [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE", +- [VCAP_KF_OAM_VER] = "OAM_VER", +- [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS", +- [VCAP_KF_PROT_ACTIVE] = "PROT_ACTIVE", +- [VCAP_KF_TCP_IS] = "TCP_IS", +- [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS", +- [VCAP_KF_TYPE] = "TYPE", +-}; +- +-/* Actionfield names */ +-static const char * const vcap_actionfield_names[] = { +- [VCAP_AF_NO_VALUE] = "(None)", +- [VCAP_AF_ACL_ID] = "ACL_ID", +- [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL", +- [VCAP_AF_CNT_ID] = "CNT_ID", +- [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM", +- [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM", +- [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA", +- [VCAP_AF_CPU_QU] = "CPU_QU", +- [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM", +- [VCAP_AF_DEI_A_VAL] = "DEI_A_VAL", +- [VCAP_AF_DEI_B_VAL] = "DEI_B_VAL", +- [VCAP_AF_DEI_C_VAL] = "DEI_C_VAL", +- [VCAP_AF_DEI_ENA] = "DEI_ENA", +- [VCAP_AF_DEI_VAL] = "DEI_VAL", +- [VCAP_AF_DP_ENA] = "DP_ENA", +- [VCAP_AF_DP_VAL] = "DP_VAL", +- [VCAP_AF_DSCP_ENA] = "DSCP_ENA", +- [VCAP_AF_DSCP_SEL] = "DSCP_SEL", +- [VCAP_AF_DSCP_VAL] = "DSCP_VAL", +- [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD", +- [VCAP_AF_ESDX] = "ESDX", +- [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA", +- [VCAP_AF_FWD_MODE] = "FWD_MODE", +- [VCAP_AF_FWD_SEL] = "FWD_SEL", +- [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE", +- [VCAP_AF_HOST_MATCH] = "HOST_MATCH", +- [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL", +- [VCAP_AF_INTR_ENA] = "INTR_ENA", +- [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL", +- [VCAP_AF_ISDX_ENA] = "ISDX_ENA", +- [VCAP_AF_ISDX_VAL] = "ISDX_VAL", +- [VCAP_AF_LOOP_ENA] = "LOOP_ENA", +- [VCAP_AF_LRN_DIS] = "LRN_DIS", +- [VCAP_AF_MAP_IDX] = "MAP_IDX", +- [VCAP_AF_MAP_KEY] = "MAP_KEY", +- [VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL", +- [VCAP_AF_MASK_MODE] = "MASK_MODE", +- [VCAP_AF_MATCH_ID] = "MATCH_ID", +- [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK", +- [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA", +- [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE", +- [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID", +- [VCAP_AF_NXT_IDX] = "NXT_IDX", +- [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL", +- [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK", +- [VCAP_AF_PAG_VAL] = "PAG_VAL", +- [VCAP_AF_PCP_A_VAL] = "PCP_A_VAL", +- [VCAP_AF_PCP_B_VAL] = "PCP_B_VAL", +- [VCAP_AF_PCP_C_VAL] = "PCP_C_VAL", +- [VCAP_AF_PCP_ENA] = "PCP_ENA", +- [VCAP_AF_PCP_VAL] = "PCP_VAL", +- [VCAP_AF_PIPELINE_ACT] = "PIPELINE_ACT", +- [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA", +- [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT", +- [VCAP_AF_POLICE_ENA] = "POLICE_ENA", +- [VCAP_AF_POLICE_IDX] = "POLICE_IDX", +- [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK", +- [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY", +- [VCAP_AF_POP_VAL] = "POP_VAL", +- [VCAP_AF_PORT_MASK] = "PORT_MASK", +- [VCAP_AF_PUSH_CUSTOMER_TAG] = "PUSH_CUSTOMER_TAG", +- [VCAP_AF_PUSH_INNER_TAG] = "PUSH_INNER_TAG", +- [VCAP_AF_PUSH_OUTER_TAG] = "PUSH_OUTER_TAG", +- [VCAP_AF_QOS_ENA] = "QOS_ENA", +- [VCAP_AF_QOS_VAL] = "QOS_VAL", +- [VCAP_AF_REW_OP] = "REW_OP", +- [VCAP_AF_RT_DIS] = "RT_DIS", +- [VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA", +- [VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL", +- [VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL", +- [VCAP_AF_TAG_A_TPID_SEL] = "TAG_A_TPID_SEL", +- [VCAP_AF_TAG_A_VID_SEL] = "TAG_A_VID_SEL", +- [VCAP_AF_TAG_B_DEI_SEL] = "TAG_B_DEI_SEL", +- [VCAP_AF_TAG_B_PCP_SEL] = "TAG_B_PCP_SEL", +- [VCAP_AF_TAG_B_TPID_SEL] = "TAG_B_TPID_SEL", +- [VCAP_AF_TAG_B_VID_SEL] = "TAG_B_VID_SEL", +- [VCAP_AF_TAG_C_DEI_SEL] = "TAG_C_DEI_SEL", +- [VCAP_AF_TAG_C_PCP_SEL] = "TAG_C_PCP_SEL", +- [VCAP_AF_TAG_C_TPID_SEL] = "TAG_C_TPID_SEL", +- [VCAP_AF_TAG_C_VID_SEL] = "TAG_C_VID_SEL", +- [VCAP_AF_TYPE] = "TYPE", +- [VCAP_AF_UNTAG_VID_ENA] = "UNTAG_VID_ENA", +- [VCAP_AF_VID_A_VAL] = "VID_A_VAL", +- [VCAP_AF_VID_B_VAL] = "VID_B_VAL", +- [VCAP_AF_VID_C_VAL] = "VID_C_VAL", +- [VCAP_AF_VID_VAL] = "VID_VAL", +-}; +- +-/* VCAPs */ +-const struct vcap_info lan969x_vcaps[] = { +- [VCAP_TYPE_IS0] = { +- .name = "is0", +- .rows = 256, +- .sw_count = 12, +- .sw_width = 52, +- .sticky_width = 1, +- .act_width = 103, +- .default_cnt = 70, +- .require_cnt_dis = 0, +- .version = 1, +- .keyfield_set = is0_keyfield_set, +- .keyfield_set_size = ARRAY_SIZE(is0_keyfield_set), +- .actionfield_set = is0_actionfield_set, +- .actionfield_set_size = ARRAY_SIZE(is0_actionfield_set), +- .keyfield_set_map = is0_keyfield_set_map, +- .keyfield_set_map_size = is0_keyfield_set_map_size, +- .actionfield_set_map = is0_actionfield_set_map, +- .actionfield_set_map_size = is0_actionfield_set_map_size, +- .keyfield_set_typegroups = is0_keyfield_set_typegroups, +- .actionfield_set_typegroups = is0_actionfield_set_typegroups, +- }, +- [VCAP_TYPE_IS2] = { +- .name = "is2", +- .rows = 256, +- .sw_count = 12, +- .sw_width = 52, +- .sticky_width = 1, +- .act_width = 103, +- .default_cnt = 38, +- .require_cnt_dis = 0, +- .version = 1, +- .keyfield_set = is2_keyfield_set, +- .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set), +- .actionfield_set = is2_actionfield_set, +- .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set), +- .keyfield_set_map = is2_keyfield_set_map, +- .keyfield_set_map_size = is2_keyfield_set_map_size, +- .actionfield_set_map = is2_actionfield_set_map, +- .actionfield_set_map_size = is2_actionfield_set_map_size, +- .keyfield_set_typegroups = is2_keyfield_set_typegroups, +- .actionfield_set_typegroups = is2_actionfield_set_typegroups, +- }, +- [VCAP_TYPE_ES0] = { +- .name = "es0", +- .rows = 1536, +- .sw_count = 1, +- .sw_width = 51, +- .sticky_width = 1, +- .act_width = 469, +- .default_cnt = 35, +- .require_cnt_dis = 0, +- .version = 1, +- .keyfield_set = es0_keyfield_set, +- .keyfield_set_size = ARRAY_SIZE(es0_keyfield_set), +- .actionfield_set = es0_actionfield_set, +- .actionfield_set_size = ARRAY_SIZE(es0_actionfield_set), +- .keyfield_set_map = es0_keyfield_set_map, +- .keyfield_set_map_size = es0_keyfield_set_map_size, +- .actionfield_set_map = es0_actionfield_set_map, +- .actionfield_set_map_size = es0_actionfield_set_map_size, +- .keyfield_set_typegroups = es0_keyfield_set_typegroups, +- .actionfield_set_typegroups = es0_actionfield_set_typegroups, +- }, +- [VCAP_TYPE_ES2] = { +- .name = "es2", +- .rows = 256, +- .sw_count = 12, +- .sw_width = 52, +- .sticky_width = 1, +- .act_width = 19, +- .default_cnt = 39, +- .require_cnt_dis = 0, +- .version = 1, +- .keyfield_set = es2_keyfield_set, +- .keyfield_set_size = ARRAY_SIZE(es2_keyfield_set), +- .actionfield_set = es2_actionfield_set, +- .actionfield_set_size = ARRAY_SIZE(es2_actionfield_set), +- .keyfield_set_map = es2_keyfield_set_map, +- .keyfield_set_map_size = es2_keyfield_set_map_size, +- .actionfield_set_map = es2_actionfield_set_map, +- .actionfield_set_map_size = es2_actionfield_set_map_size, +- .keyfield_set_typegroups = es2_keyfield_set_typegroups, +- .actionfield_set_typegroups = es2_actionfield_set_typegroups, +- }, +-}; +- +-const struct vcap_statistics lan969x_vcap_stats = { +- .name = "lan969x", +- .count = 4, +- .keyfield_set_names = vcap_keyfield_set_names, +- .actionfield_set_names = vcap_actionfield_set_names, +- .keyfield_names = vcap_keyfield_names, +- .actionfield_names = vcap_actionfield_names, +-}; +--- a/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_impl.c ++++ /dev/null +@@ -1,85 +0,0 @@ +-// SPDX-License-Identifier: GPL-2.0+ +- +-#include "vcap_api.h" +-#include "lan969x.h" +- +-const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[] = { +- { +- .vtype = VCAP_TYPE_IS0, /* CLM-0 */ +- .vinst = 0, +- .map_id = 1, +- .lookups = SPARX5_IS0_LOOKUPS, +- .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, +- .first_cid = SPARX5_VCAP_CID_IS0_L0, +- .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1, +- .blockno = 2, +- .blocks = 1, +- .ingress = true, +- }, +- { +- .vtype = VCAP_TYPE_IS0, /* CLM-1 */ +- .vinst = 1, +- .map_id = 2, +- .lookups = SPARX5_IS0_LOOKUPS, +- .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, +- .first_cid = SPARX5_VCAP_CID_IS0_L2, +- .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1, +- .blockno = 3, +- .blocks = 1, +- .ingress = true, +- }, +- { +- .vtype = VCAP_TYPE_IS0, /* CLM-2 */ +- .vinst = 2, +- .map_id = 3, +- .lookups = SPARX5_IS0_LOOKUPS, +- .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, +- .first_cid = SPARX5_VCAP_CID_IS0_L4, +- .last_cid = SPARX5_VCAP_CID_IS0_MAX, +- .blockno = 4, +- .blocks = 1, +- .ingress = true, +- }, +- { +- .vtype = VCAP_TYPE_IS2, /* IS2-0 */ +- .vinst = 0, +- .map_id = 4, +- .lookups = SPARX5_IS2_LOOKUPS, +- .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, +- .first_cid = SPARX5_VCAP_CID_IS2_L0, +- .last_cid = SPARX5_VCAP_CID_IS2_L2 - 1, +- .blockno = 0, +- .blocks = 1, +- .ingress = true, +- }, +- { +- .vtype = VCAP_TYPE_IS2, /* IS2-1 */ +- .vinst = 1, +- .map_id = 5, +- .lookups = SPARX5_IS2_LOOKUPS, +- .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, +- .first_cid = SPARX5_VCAP_CID_IS2_L2, +- .last_cid = SPARX5_VCAP_CID_IS2_MAX, +- .blockno = 1, +- .blocks = 1, +- .ingress = true, +- }, +- { +- .vtype = VCAP_TYPE_ES0, +- .lookups = SPARX5_ES0_LOOKUPS, +- .lookups_per_instance = SPARX5_ES0_LOOKUPS, +- .first_cid = SPARX5_VCAP_CID_ES0_L0, +- .last_cid = SPARX5_VCAP_CID_ES0_MAX, +- .count = 1536, +- .ingress = false, +- }, +- { +- .vtype = VCAP_TYPE_ES2, +- .lookups = SPARX5_ES2_LOOKUPS, +- .lookups_per_instance = SPARX5_ES2_LOOKUPS, +- .first_cid = SPARX5_VCAP_CID_ES2_L0, +- .last_cid = SPARX5_VCAP_CID_ES2_MAX, +- .count = 1024, +- .ingress = false, +- }, +-}; +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h +@@ -0,0 +1,65 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. ++ */ ++ ++#ifndef __LAN969X_H__ ++#define __LAN969X_H__ ++ ++#include "../sparx5/sparx5_main.h" ++#include "../sparx5/sparx5_regs.h" ++#include "../sparx5/sparx5_vcap_impl.h" ++ ++/* lan969x.c */ ++extern const struct sparx5_match_data lan969x_desc; ++ ++/* lan969x_vcap_ag_api.c */ ++extern const struct vcap_statistics lan969x_vcap_stats; ++extern const struct vcap_info lan969x_vcaps[]; ++ ++/* lan969x_vcap_impl.c */ ++extern const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[]; ++ ++/* lan969x_regs.c */ ++extern const unsigned int lan969x_tsize[TSIZE_LAST]; ++extern const unsigned int lan969x_raddr[RADDR_LAST]; ++extern const unsigned int lan969x_rcnt[RCNT_LAST]; ++extern const unsigned int lan969x_gaddr[GADDR_LAST]; ++extern const unsigned int lan969x_gcnt[GCNT_LAST]; ++extern const unsigned int lan969x_gsize[GSIZE_LAST]; ++extern const unsigned int lan969x_fpos[FPOS_LAST]; ++extern const unsigned int lan969x_fsize[FSIZE_LAST]; ++ ++static inline bool lan969x_port_is_2g5(int portno) ++{ ++ return portno == 1 || portno == 2 || portno == 3 || ++ portno == 5 || portno == 6 || portno == 7 || ++ portno == 10 || portno == 11 || portno == 14 || ++ portno == 15 || portno == 18 || portno == 19 || ++ portno == 22 || portno == 23; ++} ++ ++static inline bool lan969x_port_is_5g(int portno) ++{ ++ return portno == 9 || portno == 13 || portno == 17 || ++ portno == 21; ++} ++ ++static inline bool lan969x_port_is_10g(int portno) ++{ ++ return portno == 0 || portno == 4 || portno == 8 || ++ portno == 12 || portno == 16 || portno == 20 || ++ portno == 24 || portno == 25 || portno == 26 || ++ portno == 27; ++} ++ ++static inline bool lan969x_port_is_25g(int portno) ++{ ++ return false; ++} ++ ++/* lan969x_calendar.c */ ++int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, ++ struct sparx5_calendar_data *data); ++#endif +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_calendar.c +@@ -0,0 +1,191 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. ++ */ ++ ++#include "lan969x.h" ++ ++#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10 ++#define LAN969X_DSM_CAL_TAXIS 5 ++ ++enum lan969x_dsm_cal_dev { ++ DSM_CAL_DEV_2G5, ++ DSM_CAL_DEV_5G, ++ DSM_CAL_DEV_10G, ++ DSM_CAL_DEV_OTHER, /* 1G or less */ ++ DSM_CAL_DEV_MAX ++}; ++ ++/* Each entry in the following struct defines properties for a given speed ++ * (10G, 5G, 2.5G, or 1G or less). ++ */ ++struct lan969x_dsm_cal_dev_speed { ++ /* Number of devices that requires this speed. */ ++ u32 n_devs; ++ ++ /* Array of devices that requires this speed. */ ++ u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI]; ++ ++ /* Number of slots required for one device running this speed. */ ++ u32 n_slots; ++ ++ /* Gap between two slots for one device running this speed. */ ++ u32 gap; ++}; ++ ++static u32 ++lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = { ++ { 0, 4, 1, 2, 3, 5, 6, 7, 28, 29 }, ++ { 8, 12, 9, 13, 10, 11, 14, 15, 99, 99 }, ++ { 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 }, ++ { 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 }, ++ { 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 } ++}; ++ ++static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx) ++{ ++ if (*cal_idx >= cal_len) ++ return -EINVAL; ++ ++ do { ++ if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY) ++ return 0; ++ ++ (*cal_idx)++; ++ } while (*cal_idx < cal_len); ++ ++ return -ENOENT; ++} ++ ++static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed) ++{ ++ return (speed == 10000 ? DSM_CAL_DEV_10G : ++ speed == 5000 ? DSM_CAL_DEV_5G : ++ speed == 2500 ? DSM_CAL_DEV_2G5 : ++ DSM_CAL_DEV_OTHER); ++} ++ ++static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev) ++{ ++ return (dev == DSM_CAL_DEV_10G ? 10000 : ++ dev == DSM_CAL_DEV_5G ? 5000 : ++ dev == DSM_CAL_DEV_2G5 ? 2500 : ++ 1000); ++} ++ ++int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, ++ struct sparx5_calendar_data *data) ++{ ++ struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {}; ++ u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw = 0; ++ struct lan969x_dsm_cal_dev_speed *speed; ++ int err; ++ ++ /* Maximum bandwidth for this taxi */ ++ taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); ++ ++ memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], ++ LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32)); ++ ++ for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { ++ u32 portno = data->taxi_ports[i]; ++ enum sparx5_cal_bw bw; ++ ++ bw = sparx5_get_port_cal_speed(sparx5, portno); ++ ++ if (portno < sparx5->data->consts->n_ports_all) ++ data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw); ++ else ++ data->taxi_speeds[i] = 0; ++ } ++ ++ /* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the ++ * this taxi map. ++ */ ++ for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) { ++ u32 taxi_speed = data->taxi_speeds[i]; ++ enum lan969x_dsm_cal_dev dev; ++ ++ if (taxi_speed == 0) ++ continue; ++ ++ required_bw += taxi_speed; ++ ++ dev = lan969x_dsm_cal_get_dev(taxi_speed); ++ speed = &dev_speeds[dev]; ++ speed->devs[speed->n_devs++] = i; ++ n_devs++; ++ } ++ ++ if (required_bw > taxi_bw) { ++ pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u", ++ required_bw, taxi_bw); ++ return -EINVAL; ++ } ++ ++ if (n_devs == 0) { ++ data->schedule[0] = SPX5_DSM_CAL_EMPTY; ++ return 0; ++ } ++ ++ cal_len = n_devs; ++ ++ /* Search for a calendar length that fits all active devices. */ ++ while (cal_len < SPX5_DSM_CAL_LEN) { ++ u32 bw_per_slot = taxi_bw / cal_len; ++ ++ n_slots = 0; ++ ++ for (int i = 0; i < DSM_CAL_DEV_MAX; i++) { ++ speed = &dev_speeds[i]; ++ ++ if (speed->n_devs == 0) ++ continue; ++ ++ required_bw = lan969x_dsm_cal_get_speed(i); ++ speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot); ++ ++ if (speed->n_slots) ++ speed->gap = DIV_ROUND_UP(cal_len, ++ speed->n_slots); ++ else ++ speed->gap = 0; ++ ++ n_slots += speed->n_slots * speed->n_devs; ++ } ++ ++ if (n_slots <= cal_len) ++ break; /* Found a suitable calendar length. */ ++ ++ /* Not good enough yet. */ ++ cal_len = n_slots; ++ } ++ ++ if (cal_len > SPX5_DSM_CAL_LEN) { ++ pr_err("Invalid length: %u for taxi: %u", cal_len, taxi); ++ return -EINVAL; ++ } ++ ++ for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++) ++ data->schedule[i] = SPX5_DSM_CAL_EMPTY; ++ ++ /* Place the remaining devices */ ++ for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) { ++ speed = &dev_speeds[i]; ++ for (u32 dev = 0; dev < speed->n_devs; dev++) { ++ u32 idx = 0; ++ ++ for (n_slots = 0; n_slots < speed->n_slots; n_slots++) { ++ err = lan969x_dsm_cal_idx_get(data->schedule, ++ cal_len, &idx); ++ if (err) ++ return err; ++ data->schedule[idx] = speed->devs[dev]; ++ idx += speed->gap; ++ } ++ } ++ } ++ ++ return 0; ++} +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_regs.c +@@ -0,0 +1,222 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. ++ */ ++ ++/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200. ++ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b ++ */ ++ ++#include "lan969x.h" ++ ++const unsigned int lan969x_tsize[TSIZE_LAST] = { ++ [TC_DEV10G] = 10, ++ [TC_DEV2G5] = 28, ++ [TC_DEV5G] = 4, ++ [TC_PCS10G_BR] = 10, ++ [TC_PCS5G_BR] = 4, ++}; ++ ++const unsigned int lan969x_raddr[RADDR_LAST] = { ++ [RA_CPU_PROC_CTRL] = 160, ++ [RA_GCB_SOFT_RST] = 12, ++ [RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20, ++}; ++ ++const unsigned int lan969x_rcnt[RCNT_LAST] = { ++ [RC_ANA_AC_OWN_UPSID] = 1, ++ [RC_ANA_ACL_VCAP_S2_CFG] = 35, ++ [RC_ANA_ACL_OWN_UPSID] = 1, ++ [RC_ANA_CL_OWN_UPSID] = 1, ++ [RC_ANA_L2_OWN_UPSID] = 1, ++ [RC_ASM_PORT_CFG] = 32, ++ [RC_DSM_BUF_CFG] = 32, ++ [RC_DSM_DEV_TX_STOP_WM_CFG] = 32, ++ [RC_DSM_RX_PAUSE_CFG] = 32, ++ [RC_DSM_MAC_CFG] = 32, ++ [RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30, ++ [RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30, ++ [RC_DSM_TAXI_CAL_CFG] = 6, ++ [RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30, ++ [RC_HSCH_PORT_MODE] = 35, ++ [RC_QFWD_SWITCH_PORT_MODE] = 35, ++ [RC_QSYS_PAUSE_CFG] = 35, ++ [RC_QSYS_ATOP] = 35, ++ [RC_QSYS_FWD_PRESSURE] = 35, ++ [RC_QSYS_CAL_AUTO] = 4, ++ [RC_REW_OWN_UPSID] = 1, ++ [RC_REW_RTAG_ETAG_CTRL] = 35, ++}; ++ ++const unsigned int lan969x_gaddr[GADDR_LAST] = { ++ [GA_ANA_AC_RAM_CTRL] = 202000, ++ [GA_ANA_AC_PS_COMMON] = 202880, ++ [GA_ANA_AC_MIRROR_PROBE] = 203232, ++ [GA_ANA_AC_SRC] = 201728, ++ [GA_ANA_AC_PGID] = 131072, ++ [GA_ANA_AC_TSN_SF] = 202028, ++ [GA_ANA_AC_TSN_SF_CFG] = 148480, ++ [GA_ANA_AC_TSN_SF_STATUS] = 147936, ++ [GA_ANA_AC_SG_ACCESS] = 202032, ++ [GA_ANA_AC_SG_CONFIG] = 202752, ++ [GA_ANA_AC_SG_STATUS] = 147952, ++ [GA_ANA_AC_SG_STATUS_STICKY] = 202044, ++ [GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048, ++ [GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800, ++ [GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068, ++ [GA_ANA_ACL_COMMON] = 8192, ++ [GA_ANA_ACL_KEY_SEL] = 9204, ++ [GA_ANA_ACL_CNT_B] = 4096, ++ [GA_ANA_ACL_STICKY] = 10852, ++ [GA_ANA_AC_POL_POL_ALL_CFG] = 17504, ++ [GA_ANA_AC_POL_COMMON_BDLB] = 19464, ++ [GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472, ++ [GA_ANA_AC_SDLB_LBGRP_TBL] = 31788, ++ [GA_ANA_CL_PORT] = 65536, ++ [GA_ANA_CL_COMMON] = 87040, ++ [GA_ANA_L2_COMMON] = 561928, ++ [GA_ANA_L3_COMMON] = 370752, ++ [GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580, ++ [GA_ASM_CFG] = 18304, ++ [GA_ASM_PFC_TIMER_CFG] = 15568, ++ [GA_ASM_LBK_WM_CFG] = 15596, ++ [GA_ASM_LBK_MISC_CFG] = 15608, ++ [GA_ASM_RAM_CTRL] = 15684, ++ [GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864, ++ [GA_EACL_CNT_TBL] = 30720, ++ [GA_EACL_POL_CFG] = 38400, ++ [GA_EACL_ES2_STICKY] = 29072, ++ [GA_EACL_RAM_CTRL] = 29112, ++ [GA_GCB_SIO_CTRL] = 560, ++ [GA_HSCH_HSCH_DWRR] = 36480, ++ [GA_HSCH_HSCH_MISC] = 36608, ++ [GA_HSCH_HSCH_LEAK_LISTS] = 37256, ++ [GA_HSCH_SYSTEM] = 37384, ++ [GA_HSCH_MMGT] = 36260, ++ [GA_HSCH_TAS_CONFIG] = 37696, ++ [GA_PTP_PTP_CFG] = 512, ++ [GA_PTP_PTP_TOD_DOMAINS] = 528, ++ [GA_PTP_PHASE_DETECTOR_CTRL] = 628, ++ [GA_QSYS_CALCFG] = 2164, ++ [GA_QSYS_RAM_CTRL] = 2204, ++ [GA_REW_COMMON] = 98304, ++ [GA_REW_PORT] = 49152, ++ [GA_REW_VOE_PORT_LM_CNT] = 90112, ++ [GA_REW_RAM_CTRL] = 93992, ++ [GA_VOP_RAM_CTRL] = 16368, ++ [GA_XQS_SYSTEM] = 5744, ++ [GA_XQS_QLIMIT_SHR] = 6912, ++}; ++ ++const unsigned int lan969x_gcnt[GCNT_LAST] = { ++ [GC_ANA_AC_SRC] = 67, ++ [GC_ANA_AC_PGID] = 1054, ++ [GC_ANA_AC_TSN_SF_CFG] = 256, ++ [GC_ANA_AC_STAT_CNT_CFG_PORT] = 35, ++ [GC_ANA_ACL_KEY_SEL] = 99, ++ [GC_ANA_ACL_CNT_A] = 1024, ++ [GC_ANA_ACL_CNT_B] = 1024, ++ [GC_ANA_AC_SDLB_LBGRP_TBL] = 5, ++ [GC_ANA_AC_SDLB_LBSET_TBL] = 496, ++ [GC_ANA_CL_PORT] = 35, ++ [GC_ANA_L2_ISDX_LIMIT] = 256, ++ [GC_ANA_L2_ISDX] = 1024, ++ [GC_ANA_L3_VLAN] = 4608, ++ [GC_ASM_DEV_STATISTICS] = 30, ++ [GC_EACL_ES2_KEY_SELECT_PROFILE] = 68, ++ [GC_EACL_CNT_TBL] = 512, ++ [GC_GCB_SIO_CTRL] = 1, ++ [GC_HSCH_HSCH_CFG] = 1120, ++ [GC_HSCH_HSCH_DWRR] = 32, ++ [GC_PTP_PTP_PINS] = 8, ++ [GC_PTP_PHASE_DETECTOR_CTRL] = 8, ++ [GC_REW_PORT] = 35, ++ [GC_REW_VOE_PORT_LM_CNT] = 240, ++}; ++ ++const unsigned int lan969x_gsize[GSIZE_LAST] = { ++ [GW_ANA_AC_SRC] = 4, ++ [GW_ANA_L2_COMMON] = 712, ++ [GW_ASM_CFG] = 1092, ++ [GW_CPU_CPU_REGS] = 180, ++ [GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12, ++ [GW_FDMA_FDMA] = 448, ++ [GW_GCB_CHIP_REGS] = 180, ++ [GW_HSCH_TAS_CONFIG] = 16, ++ [GW_PTP_PHASE_DETECTOR_CTRL] = 12, ++ [GW_QSYS_PAUSE_CFG] = 988, ++}; ++ ++const unsigned int lan969x_fpos[FPOS_LAST] = { ++ [FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7, ++ [FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6, ++ [FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5, ++ [FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4, ++ [FP_CPU_PROC_CTRL_VINITHI] = 3, ++ [FP_CPU_PROC_CTRL_CFGTE] = 2, ++ [FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1, ++ [FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0, ++ [FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8, ++ [FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5, ++ [FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3, ++ [FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5, ++ [FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4, ++ [FP_FDMA_CH_CFG_CH_INJ_PORT] = 3, ++ [FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27, ++ [FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25, ++ [FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24, ++ [FP_PTP_PHAD_CTRL_PHAD_ENA] = 5, ++ [FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3, ++}; ++ ++const unsigned int lan969x_fsize[FSIZE_LAST] = { ++ [FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30, ++ [FW_ANA_AC_SRC_CFG_PORT_MASK] = 30, ++ [FW_ANA_AC_PGID_CFG_PORT_MASK] = 30, ++ [FW_ANA_AC_TSN_SF_PORT_NUM] = 7, ++ [FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8, ++ [FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8, ++ [FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8, ++ [FW_ANA_AC_PORT_SGE_CFG_MASK] = 17, ++ [FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9, ++ [FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3, ++ [FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9, ++ [FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9, ++ [FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3, ++ [FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9, ++ [FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30, ++ [FW_ANA_L2_DLB_CFG_DLB_IDX] = 9, ++ [FW_ANA_L2_TSN_CFG_TSN_SFID] = 8, ++ [FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30, ++ [FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2, ++ [FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7, ++ [FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5, ++ [FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14, ++ [FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6, ++ [FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11, ++ [FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14, ++ [FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6, ++ [FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14, ++ [FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13, ++ [FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8, ++ [FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13, ++ [FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8, ++ [FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8, ++ [FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8, ++ [FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3, ++ [FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6, ++ [FW_QRES_RES_CFG_WM_HIGH] = 11, ++ [FW_QRES_RES_STAT_MAXUSE] = 19, ++ [FW_QRES_RES_STAT_CUR_INUSE] = 19, ++ [FW_QSYS_PAUSE_CFG_PAUSE_START] = 11, ++ [FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11, ++ [FW_QSYS_ATOP_ATOP] = 11, ++ [FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11, ++ [FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6, ++ [FW_XQS_STAT_CFG_STAT_VIEW] = 10, ++ [FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14, ++ [FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14, ++ [FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14, ++ [FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14, ++}; +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_ag_api.c +@@ -0,0 +1,3843 @@ ++// SPDX-License-Identifier: BSD-3-Clause ++/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries. ++ * Microchip VCAP API ++ */ ++ ++/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200. ++ * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391 ++ */ ++ ++#include ++#include ++ ++#include "lan969x.h" ++ ++/* keyfields */ ++static const struct vcap_field is0_normal_7tuple_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 1, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 2, ++ .width = 2, ++ }, ++ [VCAP_KF_LOOKUP_GEN_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 4, ++ .width = 10, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U72, ++ .offset = 16, ++ .width = 65, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 81, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 82, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 83, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_TPID0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 86, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 89, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 93, ++ .width = 12, ++ }, ++ [VCAP_KF_8021Q_TPID1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 105, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 108, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI1] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 111, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 112, ++ .width = 12, ++ }, ++ [VCAP_KF_8021Q_TPID2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 124, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 127, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI2] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 130, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 131, ++ .width = 12, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 144, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 192, ++ .width = 48, ++ }, ++ [VCAP_KF_IP_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 240, ++ .width = 1, ++ }, ++ [VCAP_KF_ETYPE_LEN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 241, ++ .width = 1, ++ }, ++ [VCAP_KF_ETYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 242, ++ .width = 16, ++ }, ++ [VCAP_KF_IP_SNAP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 258, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 259, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 260, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 262, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 263, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DSCP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 264, ++ .width = 6, ++ }, ++ [VCAP_KF_L3_IP6_DIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 270, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 398, ++ .width = 128, ++ }, ++ [VCAP_KF_TCP_UDP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 526, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 527, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 528, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 544, ++ .width = 8, ++ }, ++}; ++ ++static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 2, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 2, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 3, ++ .width = 2, ++ }, ++ [VCAP_KF_LOOKUP_GEN_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 10, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 15, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U72, ++ .offset = 17, ++ .width = 65, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 82, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 83, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_TPID0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 87, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 90, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 93, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID0] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 94, ++ .width = 12, ++ }, ++ [VCAP_KF_8021Q_TPID1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 106, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 109, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI1] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 112, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID1] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 113, ++ .width = 12, ++ }, ++ [VCAP_KF_8021Q_TPID2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 125, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_PCP2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 128, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI2] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 131, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID2] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 132, ++ .width = 12, ++ }, ++ [VCAP_KF_IP_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 145, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 146, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 147, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 149, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 150, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DSCP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 151, ++ .width = 6, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 157, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 189, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 221, ++ .width = 8, ++ }, ++ [VCAP_KF_TCP_UDP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 229, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 230, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 231, ++ .width = 8, ++ }, ++ [VCAP_KF_IP_PAYLOAD_5TUPLE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 239, ++ .width = 32, ++ }, ++}; ++ ++static const struct vcap_field is2_mac_etype_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 88, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 89, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 137, ++ .width = 48, ++ }, ++ [VCAP_KF_ETYPE_LEN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 185, ++ .width = 1, ++ }, ++ [VCAP_KF_ETYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 186, ++ .width = 16, ++ }, ++ [VCAP_KF_L2_PAYLOAD_ETYPE] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 202, ++ .width = 64, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 266, ++ .width = 16, ++ }, ++ [VCAP_KF_OAM_CCM_CNTS_EQ0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 282, ++ .width = 1, ++ }, ++ [VCAP_KF_OAM_Y1731_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 283, ++ .width = 1, ++ }, ++}; ++ ++static const struct vcap_field is2_arp_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 85, ++ .width = 48, ++ }, ++ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 133, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 134, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_LEN_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 135, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_TGT_MATCH_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 136, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_SENDER_MATCH_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 137, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 138, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_OPCODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 139, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 141, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 173, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 205, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 206, ++ .width = 16, ++ }, ++}; ++ ++static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 88, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 89, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 90, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 93, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 94, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 95, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 103, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 135, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 167, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 168, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_DPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 169, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 185, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 201, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 217, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 218, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_FIN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 219, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SYN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 220, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RST] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 221, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PSH] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 222, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_ACK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 223, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_URG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 224, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PAYLOAD] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 225, ++ .width = 64, ++ }, ++}; ++ ++static const struct vcap_field is2_ip4_other_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 88, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 89, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 90, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 93, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 94, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 95, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 103, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 135, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 167, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 168, ++ .width = 8, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 176, ++ .width = 16, ++ }, ++ [VCAP_KF_L3_PAYLOAD] = { ++ .type = VCAP_FIELD_U112, ++ .offset = 192, ++ .width = 96, ++ }, ++}; ++ ++static const struct vcap_field is2_ip6_std_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 4, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 4, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 5, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 32, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 52, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 53, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 54, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 56, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 57, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 80, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 89, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 90, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 218, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 219, ++ .width = 8, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 227, ++ .width = 16, ++ }, ++ [VCAP_KF_L3_PAYLOAD] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 243, ++ .width = 40, ++ }, ++}; ++ ++static const struct vcap_field is2_ip_7tuple_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 2, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 2, ++ .width = 1, ++ }, ++ [VCAP_KF_LOOKUP_PAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 3, ++ .width = 8, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 11, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 12, ++ .width = 4, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 2, ++ }, ++ [VCAP_KF_IF_IGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U72, ++ .offset = 18, ++ .width = 65, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 83, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 85, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 98, ++ .width = 13, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 111, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 112, ++ .width = 3, ++ }, ++ [VCAP_KF_L2_FWD_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 115, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 118, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_DST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 119, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 120, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 168, ++ .width = 48, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 218, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 219, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 220, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP6_DIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 228, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 356, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 484, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_UDP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 485, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 486, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_DPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 487, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 503, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 519, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 535, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 536, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_FIN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 537, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SYN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 538, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RST] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 539, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PSH] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 540, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_ACK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 541, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_URG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 542, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PAYLOAD] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 543, ++ .width = 64, ++ }, ++}; ++ ++static const struct vcap_field es0_isdx_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_EGR_PORT_NO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 1, ++ .width = 6, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 7, ++ .width = 13, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 20, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_TPID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 23, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 27, ++ .width = 1, ++ }, ++ [VCAP_KF_PROT_ACTIVE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 28, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 38, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field es2_mac_etype_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 96, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 144, ++ .width = 48, ++ }, ++ [VCAP_KF_ETYPE_LEN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 192, ++ .width = 1, ++ }, ++ [VCAP_KF_ETYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 193, ++ .width = 16, ++ }, ++ [VCAP_KF_L2_PAYLOAD_ETYPE] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 209, ++ .width = 64, ++ }, ++ [VCAP_KF_OAM_CCM_CNTS_EQ0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 273, ++ .width = 1, ++ }, ++ [VCAP_KF_OAM_Y1731_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 274, ++ .width = 1, ++ }, ++}; ++ ++static const struct vcap_field es2_arp_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 95, ++ .width = 48, ++ }, ++ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 143, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 144, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_LEN_OK_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 145, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_TGT_MATCH_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 146, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_SENDER_MATCH_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 147, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 148, ++ .width = 1, ++ }, ++ [VCAP_KF_ARP_OPCODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 149, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 151, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 183, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 215, ++ .width = 1, ++ }, ++}; ++ ++static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 96, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 97, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 99, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 100, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 101, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 109, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 141, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 173, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 174, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_DPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 175, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 191, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 207, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 223, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 224, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_FIN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 225, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SYN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 226, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RST] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 227, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PSH] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 228, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_ACK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 229, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_URG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 230, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PAYLOAD] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 231, ++ .width = 64, ++ }, ++}; ++ ++static const struct vcap_field es2_ip4_other_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 96, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_FRAGMENT_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 97, ++ .width = 2, ++ }, ++ [VCAP_KF_L3_OPTIONS_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 99, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 100, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 101, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP4_DIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 109, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_IP4_SIP] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 141, ++ .width = 32, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 173, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 174, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_PAYLOAD] = { ++ .type = VCAP_FIELD_U112, ++ .offset = 182, ++ .width = 96, ++ }, ++}; ++ ++static const struct vcap_field es2_ip_7tuple_keyfield[] = { ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 10, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 11, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 12, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 13, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 23, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 25, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 38, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 73, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 74, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 81, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 85, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 88, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 89, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_DMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 93, ++ .width = 48, ++ }, ++ [VCAP_KF_L2_SMAC] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 141, ++ .width = 48, ++ }, ++ [VCAP_KF_IP4_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 191, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 192, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TOS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 193, ++ .width = 8, ++ }, ++ [VCAP_KF_L3_IP6_DIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 201, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 329, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 457, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_UDP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 458, ++ .width = 1, ++ }, ++ [VCAP_KF_TCP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 459, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_DPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 460, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 476, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 492, ++ .width = 16, ++ }, ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 508, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 509, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_FIN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 510, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_SYN] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 511, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_RST] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 512, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PSH] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 513, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_ACK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 514, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_URG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 515, ++ .width = 1, ++ }, ++ [VCAP_KF_L4_PAYLOAD] = { ++ .type = VCAP_FIELD_U64, ++ .offset = 516, ++ .width = 64, ++ }, ++}; ++ ++static const struct vcap_field es2_ip6_std_keyfield[] = { ++ [VCAP_KF_TYPE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 3, ++ }, ++ [VCAP_KF_LOOKUP_FIRST_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 3, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_MC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 13, ++ .width = 1, ++ }, ++ [VCAP_KF_L2_BC_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 14, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_GT0_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_KF_ISDX_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 10, ++ }, ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_KF_8021Q_VID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 13, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 41, ++ .width = 3, ++ }, ++ [VCAP_KF_IF_EGR_PORT_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 44, ++ .width = 32, ++ }, ++ [VCAP_KF_IF_IGR_PORT_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 76, ++ .width = 1, ++ }, ++ [VCAP_KF_IF_IGR_PORT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 77, ++ .width = 7, ++ }, ++ [VCAP_KF_8021Q_PCP_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 84, ++ .width = 3, ++ }, ++ [VCAP_KF_8021Q_DEI_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 87, ++ .width = 1, ++ }, ++ [VCAP_KF_COSID_CLS] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 88, ++ .width = 3, ++ }, ++ [VCAP_KF_L3_DPL_CLS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 91, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_RT_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 92, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_TTL_GT0] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 96, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP6_SIP] = { ++ .type = VCAP_FIELD_U128, ++ .offset = 97, ++ .width = 128, ++ }, ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 225, ++ .width = 1, ++ }, ++ [VCAP_KF_L3_IP_PROTO] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 226, ++ .width = 8, ++ }, ++ [VCAP_KF_L4_RNG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 234, ++ .width = 16, ++ }, ++ [VCAP_KF_L3_PAYLOAD] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 250, ++ .width = 40, ++ }, ++}; ++ ++/* keyfield_set */ ++static const struct vcap_set is0_keyfield_set[] = { ++ [VCAP_KFS_NORMAL_7TUPLE] = { ++ .type_id = 0, ++ .sw_per_item = 12, ++ .sw_cnt = 1, ++ }, ++ [VCAP_KFS_NORMAL_5TUPLE_IP4] = { ++ .type_id = 2, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++}; ++ ++static const struct vcap_set is2_keyfield_set[] = { ++ [VCAP_KFS_MAC_ETYPE] = { ++ .type_id = 0, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_ARP] = { ++ .type_id = 3, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP4_TCP_UDP] = { ++ .type_id = 4, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP4_OTHER] = { ++ .type_id = 5, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP6_STD] = { ++ .type_id = 6, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP_7TUPLE] = { ++ .type_id = 1, ++ .sw_per_item = 12, ++ .sw_cnt = 1, ++ }, ++}; ++ ++static const struct vcap_set es0_keyfield_set[] = { ++ [VCAP_KFS_ISDX] = { ++ .type_id = 0, ++ .sw_per_item = 1, ++ .sw_cnt = 1, ++ }, ++}; ++ ++static const struct vcap_set es2_keyfield_set[] = { ++ [VCAP_KFS_MAC_ETYPE] = { ++ .type_id = 0, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_ARP] = { ++ .type_id = 1, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP4_TCP_UDP] = { ++ .type_id = 2, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP4_OTHER] = { ++ .type_id = 3, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++ [VCAP_KFS_IP_7TUPLE] = { ++ .type_id = -1, ++ .sw_per_item = 12, ++ .sw_cnt = 1, ++ }, ++ [VCAP_KFS_IP6_STD] = { ++ .type_id = 4, ++ .sw_per_item = 6, ++ .sw_cnt = 2, ++ }, ++}; ++ ++/* keyfield_set map */ ++static const struct vcap_field *is0_keyfield_set_map[] = { ++ [VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield, ++ [VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield, ++}; ++ ++static const struct vcap_field *is2_keyfield_set_map[] = { ++ [VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield, ++ [VCAP_KFS_ARP] = is2_arp_keyfield, ++ [VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield, ++ [VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield, ++ [VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield, ++ [VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield, ++}; ++ ++static const struct vcap_field *es0_keyfield_set_map[] = { ++ [VCAP_KFS_ISDX] = es0_isdx_keyfield, ++}; ++ ++static const struct vcap_field *es2_keyfield_set_map[] = { ++ [VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield, ++ [VCAP_KFS_ARP] = es2_arp_keyfield, ++ [VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield, ++ [VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield, ++ [VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield, ++ [VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield, ++}; ++ ++/* keyfield_set map sizes */ ++static int is0_keyfield_set_map_size[] = { ++ [VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield), ++ [VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield), ++}; ++ ++static int is2_keyfield_set_map_size[] = { ++ [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield), ++ [VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield), ++ [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield), ++ [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield), ++ [VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield), ++ [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield), ++}; ++ ++static int es0_keyfield_set_map_size[] = { ++ [VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield), ++}; ++ ++static int es2_keyfield_set_map_size[] = { ++ [VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield), ++ [VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield), ++ [VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield), ++ [VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield), ++ [VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield), ++ [VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield), ++}; ++ ++/* actionfields */ ++static const struct vcap_field is0_classification_actionfield[] = { ++ [VCAP_AF_TYPE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_AF_DSCP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 1, ++ .width = 1, ++ }, ++ [VCAP_AF_DSCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 2, ++ .width = 6, ++ }, ++ [VCAP_AF_QOS_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 12, ++ .width = 1, ++ }, ++ [VCAP_AF_QOS_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 13, ++ .width = 3, ++ }, ++ [VCAP_AF_DP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 16, ++ .width = 1, ++ }, ++ [VCAP_AF_DP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 17, ++ .width = 2, ++ }, ++ [VCAP_AF_DEI_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 19, ++ .width = 1, ++ }, ++ [VCAP_AF_DEI_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 20, ++ .width = 1, ++ }, ++ [VCAP_AF_PCP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 21, ++ .width = 1, ++ }, ++ [VCAP_AF_PCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 22, ++ .width = 3, ++ }, ++ [VCAP_AF_MAP_LOOKUP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 25, ++ .width = 2, ++ }, ++ [VCAP_AF_MAP_KEY] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 27, ++ .width = 3, ++ }, ++ [VCAP_AF_MAP_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 30, ++ .width = 7, ++ }, ++ [VCAP_AF_CLS_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 37, ++ .width = 3, ++ }, ++ [VCAP_AF_VID_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 43, ++ .width = 13, ++ }, ++ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 66, ++ .width = 1, ++ }, ++ [VCAP_AF_ISDX_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 67, ++ .width = 10, ++ }, ++ [VCAP_AF_PAG_OVERRIDE_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 107, ++ .width = 8, ++ }, ++ [VCAP_AF_PAG_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 115, ++ .width = 8, ++ }, ++ [VCAP_AF_NXT_IDX_CTRL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 167, ++ .width = 3, ++ }, ++ [VCAP_AF_NXT_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 170, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field is0_full_actionfield[] = { ++ [VCAP_AF_DSCP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_AF_DSCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 1, ++ .width = 6, ++ }, ++ [VCAP_AF_QOS_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 11, ++ .width = 1, ++ }, ++ [VCAP_AF_QOS_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 12, ++ .width = 3, ++ }, ++ [VCAP_AF_DP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_AF_DP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 16, ++ .width = 2, ++ }, ++ [VCAP_AF_DEI_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 18, ++ .width = 1, ++ }, ++ [VCAP_AF_DEI_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 19, ++ .width = 1, ++ }, ++ [VCAP_AF_PCP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 20, ++ .width = 1, ++ }, ++ [VCAP_AF_PCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 21, ++ .width = 3, ++ }, ++ [VCAP_AF_MAP_LOOKUP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 24, ++ .width = 2, ++ }, ++ [VCAP_AF_MAP_KEY] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 26, ++ .width = 3, ++ }, ++ [VCAP_AF_MAP_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 29, ++ .width = 7, ++ }, ++ [VCAP_AF_CLS_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 36, ++ .width = 3, ++ }, ++ [VCAP_AF_VID_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 42, ++ .width = 13, ++ }, ++ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 65, ++ .width = 1, ++ }, ++ [VCAP_AF_ISDX_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 66, ++ .width = 10, ++ }, ++ [VCAP_AF_MASK_MODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 76, ++ .width = 3, ++ }, ++ [VCAP_AF_PORT_MASK] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 79, ++ .width = 37, ++ }, ++ [VCAP_AF_PAG_OVERRIDE_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 174, ++ .width = 8, ++ }, ++ [VCAP_AF_PAG_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 182, ++ .width = 8, ++ }, ++ [VCAP_AF_NXT_IDX_CTRL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 266, ++ .width = 3, ++ }, ++ [VCAP_AF_NXT_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 269, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field is0_class_reduced_actionfield[] = { ++ [VCAP_AF_TYPE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_AF_QOS_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 5, ++ .width = 1, ++ }, ++ [VCAP_AF_QOS_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 6, ++ .width = 3, ++ }, ++ [VCAP_AF_DP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 9, ++ .width = 1, ++ }, ++ [VCAP_AF_DP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 10, ++ .width = 2, ++ }, ++ [VCAP_AF_MAP_LOOKUP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 12, ++ .width = 2, ++ }, ++ [VCAP_AF_MAP_KEY] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 3, ++ }, ++ [VCAP_AF_CLS_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 17, ++ .width = 3, ++ }, ++ [VCAP_AF_VID_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 23, ++ .width = 13, ++ }, ++ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 46, ++ .width = 1, ++ }, ++ [VCAP_AF_ISDX_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 47, ++ .width = 10, ++ }, ++ [VCAP_AF_NXT_IDX_CTRL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 89, ++ .width = 3, ++ }, ++ [VCAP_AF_NXT_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 92, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field is2_base_type_actionfield[] = { ++ [VCAP_AF_PIPELINE_FORCE_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 1, ++ .width = 1, ++ }, ++ [VCAP_AF_PIPELINE_PT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 2, ++ .width = 5, ++ }, ++ [VCAP_AF_HIT_ME_ONCE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 7, ++ .width = 1, ++ }, ++ [VCAP_AF_INTR_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 8, ++ .width = 1, ++ }, ++ [VCAP_AF_CPU_COPY_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 9, ++ .width = 1, ++ }, ++ [VCAP_AF_CPU_QUEUE_NUM] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 10, ++ .width = 3, ++ }, ++ [VCAP_AF_LRN_DIS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 15, ++ .width = 1, ++ }, ++ [VCAP_AF_RT_DIS] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 16, ++ .width = 1, ++ }, ++ [VCAP_AF_POLICE_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 17, ++ .width = 1, ++ }, ++ [VCAP_AF_POLICE_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 5, ++ }, ++ [VCAP_AF_IGNORE_PIPELINE_CTRL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 23, ++ .width = 1, ++ }, ++ [VCAP_AF_MASK_MODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 27, ++ .width = 3, ++ }, ++ [VCAP_AF_PORT_MASK] = { ++ .type = VCAP_FIELD_U48, ++ .offset = 30, ++ .width = 37, ++ }, ++ [VCAP_AF_MIRROR_PROBE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 78, ++ .width = 2, ++ }, ++ [VCAP_AF_MATCH_ID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 131, ++ .width = 16, ++ }, ++ [VCAP_AF_MATCH_ID_MASK] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 147, ++ .width = 16, ++ }, ++ [VCAP_AF_CNT_ID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 163, ++ .width = 10, ++ }, ++}; ++ ++static const struct vcap_field es0_es0_actionfield[] = { ++ [VCAP_AF_PUSH_OUTER_TAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 0, ++ .width = 2, ++ }, ++ [VCAP_AF_PUSH_INNER_TAG] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 2, ++ .width = 1, ++ }, ++ [VCAP_AF_TAG_A_TPID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 3, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_A_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 6, ++ .width = 2, ++ }, ++ [VCAP_AF_TAG_A_PCP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 8, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_A_DEI_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 11, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_B_TPID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 14, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_B_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 17, ++ .width = 2, ++ }, ++ [VCAP_AF_TAG_B_PCP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 19, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_B_DEI_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 22, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_C_TPID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 25, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_C_PCP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 28, ++ .width = 3, ++ }, ++ [VCAP_AF_TAG_C_DEI_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 31, ++ .width = 3, ++ }, ++ [VCAP_AF_VID_A_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 34, ++ .width = 12, ++ }, ++ [VCAP_AF_PCP_A_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 46, ++ .width = 3, ++ }, ++ [VCAP_AF_DEI_A_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 49, ++ .width = 1, ++ }, ++ [VCAP_AF_VID_B_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 50, ++ .width = 12, ++ }, ++ [VCAP_AF_PCP_B_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 62, ++ .width = 3, ++ }, ++ [VCAP_AF_DEI_B_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 65, ++ .width = 1, ++ }, ++ [VCAP_AF_VID_C_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 66, ++ .width = 12, ++ }, ++ [VCAP_AF_PCP_C_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 78, ++ .width = 3, ++ }, ++ [VCAP_AF_DEI_C_VAL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 81, ++ .width = 1, ++ }, ++ [VCAP_AF_POP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 82, ++ .width = 2, ++ }, ++ [VCAP_AF_UNTAG_VID_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 84, ++ .width = 1, ++ }, ++ [VCAP_AF_PUSH_CUSTOMER_TAG] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 85, ++ .width = 2, ++ }, ++ [VCAP_AF_TAG_C_VID_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 87, ++ .width = 2, ++ }, ++ [VCAP_AF_DSCP_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 127, ++ .width = 3, ++ }, ++ [VCAP_AF_DSCP_VAL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 130, ++ .width = 6, ++ }, ++ [VCAP_AF_ESDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 319, ++ .width = 10, ++ }, ++ [VCAP_AF_FWD_SEL] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 438, ++ .width = 2, ++ }, ++ [VCAP_AF_CPU_QU] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 440, ++ .width = 3, ++ }, ++ [VCAP_AF_PIPELINE_PT] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 443, ++ .width = 2, ++ }, ++ [VCAP_AF_PIPELINE_ACT] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 445, ++ .width = 1, ++ }, ++ [VCAP_AF_SWAP_MACS_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 454, ++ .width = 1, ++ }, ++ [VCAP_AF_LOOP_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 455, ++ .width = 1, ++ }, ++}; ++ ++static const struct vcap_field es2_base_type_actionfield[] = { ++ [VCAP_AF_HIT_ME_ONCE] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 0, ++ .width = 1, ++ }, ++ [VCAP_AF_INTR_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 1, ++ .width = 1, ++ }, ++ [VCAP_AF_FWD_MODE] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 2, ++ .width = 2, ++ }, ++ [VCAP_AF_COPY_QUEUE_NUM] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 4, ++ .width = 14, ++ }, ++ [VCAP_AF_COPY_PORT_NUM] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 18, ++ .width = 6, ++ }, ++ [VCAP_AF_MIRROR_PROBE_ID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 24, ++ .width = 2, ++ }, ++ [VCAP_AF_CPU_COPY_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 26, ++ .width = 1, ++ }, ++ [VCAP_AF_CPU_QUEUE_NUM] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 27, ++ .width = 3, ++ }, ++ [VCAP_AF_POLICE_ENA] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 30, ++ .width = 1, ++ }, ++ [VCAP_AF_POLICE_REMARK] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 31, ++ .width = 1, ++ }, ++ [VCAP_AF_POLICE_IDX] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 32, ++ .width = 5, ++ }, ++ [VCAP_AF_ES2_REW_CMD] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 37, ++ .width = 3, ++ }, ++ [VCAP_AF_CNT_ID] = { ++ .type = VCAP_FIELD_U32, ++ .offset = 40, ++ .width = 9, ++ }, ++ [VCAP_AF_IGNORE_PIPELINE_CTRL] = { ++ .type = VCAP_FIELD_BIT, ++ .offset = 49, ++ .width = 1, ++ }, ++}; ++ ++/* actionfield_set */ ++static const struct vcap_set is0_actionfield_set[] = { ++ [VCAP_AFS_CLASSIFICATION] = { ++ .type_id = 1, ++ .sw_per_item = 2, ++ .sw_cnt = 6, ++ }, ++ [VCAP_AFS_FULL] = { ++ .type_id = -1, ++ .sw_per_item = 3, ++ .sw_cnt = 4, ++ }, ++ [VCAP_AFS_CLASS_REDUCED] = { ++ .type_id = 1, ++ .sw_per_item = 1, ++ .sw_cnt = 12, ++ }, ++}; ++ ++static const struct vcap_set is2_actionfield_set[] = { ++ [VCAP_AFS_BASE_TYPE] = { ++ .type_id = -1, ++ .sw_per_item = 3, ++ .sw_cnt = 4, ++ }, ++}; ++ ++static const struct vcap_set es0_actionfield_set[] = { ++ [VCAP_AFS_ES0] = { ++ .type_id = -1, ++ .sw_per_item = 1, ++ .sw_cnt = 1, ++ }, ++}; ++ ++static const struct vcap_set es2_actionfield_set[] = { ++ [VCAP_AFS_BASE_TYPE] = { ++ .type_id = -1, ++ .sw_per_item = 3, ++ .sw_cnt = 4, ++ }, ++}; ++ ++/* actionfield_set map */ ++static const struct vcap_field *is0_actionfield_set_map[] = { ++ [VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield, ++ [VCAP_AFS_FULL] = is0_full_actionfield, ++ [VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield, ++}; ++ ++static const struct vcap_field *is2_actionfield_set_map[] = { ++ [VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield, ++}; ++ ++static const struct vcap_field *es0_actionfield_set_map[] = { ++ [VCAP_AFS_ES0] = es0_es0_actionfield, ++}; ++ ++static const struct vcap_field *es2_actionfield_set_map[] = { ++ [VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield, ++}; ++ ++/* actionfield_set map size */ ++static int is0_actionfield_set_map_size[] = { ++ [VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield), ++ [VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield), ++ [VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield), ++}; ++ ++static int is2_actionfield_set_map_size[] = { ++ [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield), ++}; ++ ++static int es0_actionfield_set_map_size[] = { ++ [VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield), ++}; ++ ++static int es2_actionfield_set_map_size[] = { ++ [VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield), ++}; ++ ++/* Type Groups */ ++static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 5, ++ .value = 16, ++ }, ++ { ++ .offset = 52, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 104, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 156, ++ .width = 3, ++ .value = 0, ++ }, ++ { ++ .offset = 208, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 260, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 312, ++ .width = 4, ++ .value = 0, ++ }, ++ { ++ .offset = 364, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 416, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 468, ++ .width = 3, ++ .value = 0, ++ }, ++ { ++ .offset = 520, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 572, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 4, ++ .value = 8, ++ }, ++ { ++ .offset = 52, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 104, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 156, ++ .width = 3, ++ .value = 0, ++ }, ++ { ++ .offset = 208, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 260, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 3, ++ .value = 4, ++ }, ++ { ++ .offset = 156, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 312, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 468, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 156, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 3, ++ .value = 4, ++ }, ++ { ++ .offset = 156, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 312, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 468, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 156, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = { ++ [12] = is0_x12_keyfield_set_typegroups, ++ [6] = is0_x6_keyfield_set_typegroups, ++ [3] = is0_x3_keyfield_set_typegroups, ++ [2] = is0_x2_keyfield_set_typegroups, ++ [1] = is0_x1_keyfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = { ++ [12] = is2_x12_keyfield_set_typegroups, ++ [6] = is2_x6_keyfield_set_typegroups, ++ [3] = is2_x3_keyfield_set_typegroups, ++ [1] = is2_x1_keyfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = { ++ [1] = es0_x1_keyfield_set_typegroups, ++ [2] = NULL, ++}; ++ ++static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = { ++ [12] = es2_x12_keyfield_set_typegroups, ++ [6] = es2_x6_keyfield_set_typegroups, ++ [3] = es2_x3_keyfield_set_typegroups, ++ [1] = es2_x1_keyfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 3, ++ .value = 4, ++ }, ++ { ++ .offset = 103, ++ .width = 2, ++ .value = 0, ++ }, ++ { ++ .offset = 206, ++ .width = 2, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 103, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 1, ++ .value = 1, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 95, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 190, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = { ++ { ++ .offset = 0, ++ .width = 2, ++ .value = 2, ++ }, ++ { ++ .offset = 19, ++ .width = 1, ++ .value = 0, ++ }, ++ { ++ .offset = 38, ++ .width = 1, ++ .value = 0, ++ }, ++ {} ++}; ++ ++static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = { ++ {} ++}; ++ ++static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = { ++ [3] = is0_x3_actionfield_set_typegroups, ++ [2] = is0_x2_actionfield_set_typegroups, ++ [1] = is0_x1_actionfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = { ++ [3] = is2_x3_actionfield_set_typegroups, ++ [1] = is2_x1_actionfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = { ++ [1] = es0_x1_actionfield_set_typegroups, ++ [2] = NULL, ++}; ++ ++static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = { ++ [3] = es2_x3_actionfield_set_typegroups, ++ [1] = es2_x1_actionfield_set_typegroups, ++ [13] = NULL, ++}; ++ ++/* Keyfieldset names */ ++static const char * const vcap_keyfield_set_names[] = { ++ [VCAP_KFS_NO_VALUE] = "(None)", ++ [VCAP_KFS_ARP] = "VCAP_KFS_ARP", ++ [VCAP_KFS_ETAG] = "VCAP_KFS_ETAG", ++ [VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER", ++ [VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP", ++ [VCAP_KFS_IP4_VID] = "VCAP_KFS_IP4_VID", ++ [VCAP_KFS_IP6_OTHER] = "VCAP_KFS_IP6_OTHER", ++ [VCAP_KFS_IP6_STD] = "VCAP_KFS_IP6_STD", ++ [VCAP_KFS_IP6_TCP_UDP] = "VCAP_KFS_IP6_TCP_UDP", ++ [VCAP_KFS_IP6_VID] = "VCAP_KFS_IP6_VID", ++ [VCAP_KFS_IP_7TUPLE] = "VCAP_KFS_IP_7TUPLE", ++ [VCAP_KFS_ISDX] = "VCAP_KFS_ISDX", ++ [VCAP_KFS_LL_FULL] = "VCAP_KFS_LL_FULL", ++ [VCAP_KFS_MAC_ETYPE] = "VCAP_KFS_MAC_ETYPE", ++ [VCAP_KFS_MAC_LLC] = "VCAP_KFS_MAC_LLC", ++ [VCAP_KFS_MAC_SNAP] = "VCAP_KFS_MAC_SNAP", ++ [VCAP_KFS_NORMAL_5TUPLE_IP4] = "VCAP_KFS_NORMAL_5TUPLE_IP4", ++ [VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE", ++ [VCAP_KFS_OAM] = "VCAP_KFS_OAM", ++ [VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4", ++ [VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4", ++ [VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6", ++}; ++ ++/* Actionfieldset names */ ++static const char * const vcap_actionfield_set_names[] = { ++ [VCAP_AFS_NO_VALUE] = "(None)", ++ [VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE", ++ [VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION", ++ [VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED", ++ [VCAP_AFS_ES0] = "VCAP_AFS_ES0", ++ [VCAP_AFS_FULL] = "VCAP_AFS_FULL", ++ [VCAP_AFS_SMAC_SIP] = "VCAP_AFS_SMAC_SIP", ++}; ++ ++/* Keyfield names */ ++static const char * const vcap_keyfield_names[] = { ++ [VCAP_KF_NO_VALUE] = "(None)", ++ [VCAP_KF_8021BR_ECID_BASE] = "8021BR_ECID_BASE", ++ [VCAP_KF_8021BR_ECID_EXT] = "8021BR_ECID_EXT", ++ [VCAP_KF_8021BR_E_TAGGED] = "8021BR_E_TAGGED", ++ [VCAP_KF_8021BR_GRP] = "8021BR_GRP", ++ [VCAP_KF_8021BR_IGR_ECID_BASE] = "8021BR_IGR_ECID_BASE", ++ [VCAP_KF_8021BR_IGR_ECID_EXT] = "8021BR_IGR_ECID_EXT", ++ [VCAP_KF_8021Q_DEI0] = "8021Q_DEI0", ++ [VCAP_KF_8021Q_DEI1] = "8021Q_DEI1", ++ [VCAP_KF_8021Q_DEI2] = "8021Q_DEI2", ++ [VCAP_KF_8021Q_DEI_CLS] = "8021Q_DEI_CLS", ++ [VCAP_KF_8021Q_PCP0] = "8021Q_PCP0", ++ [VCAP_KF_8021Q_PCP1] = "8021Q_PCP1", ++ [VCAP_KF_8021Q_PCP2] = "8021Q_PCP2", ++ [VCAP_KF_8021Q_PCP_CLS] = "8021Q_PCP_CLS", ++ [VCAP_KF_8021Q_TPID] = "8021Q_TPID", ++ [VCAP_KF_8021Q_TPID0] = "8021Q_TPID0", ++ [VCAP_KF_8021Q_TPID1] = "8021Q_TPID1", ++ [VCAP_KF_8021Q_TPID2] = "8021Q_TPID2", ++ [VCAP_KF_8021Q_VID0] = "8021Q_VID0", ++ [VCAP_KF_8021Q_VID1] = "8021Q_VID1", ++ [VCAP_KF_8021Q_VID2] = "8021Q_VID2", ++ [VCAP_KF_8021Q_VID_CLS] = "8021Q_VID_CLS", ++ [VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS", ++ [VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS", ++ [VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID", ++ [VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS", ++ [VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS", ++ [VCAP_KF_ARP_OPCODE] = "ARP_OPCODE", ++ [VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = "ARP_OPCODE_UNKNOWN_IS", ++ [VCAP_KF_ARP_PROTO_SPACE_OK_IS] = "ARP_PROTO_SPACE_OK_IS", ++ [VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS", ++ [VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS", ++ [VCAP_KF_COSID_CLS] = "COSID_CLS", ++ [VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA", ++ [VCAP_KF_ETYPE] = "ETYPE", ++ [VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS", ++ [VCAP_KF_HOST_MATCH] = "HOST_MATCH", ++ [VCAP_KF_IF_EGR_PORT_MASK] = "IF_EGR_PORT_MASK", ++ [VCAP_KF_IF_EGR_PORT_MASK_RNG] = "IF_EGR_PORT_MASK_RNG", ++ [VCAP_KF_IF_EGR_PORT_NO] = "IF_EGR_PORT_NO", ++ [VCAP_KF_IF_IGR_PORT] = "IF_IGR_PORT", ++ [VCAP_KF_IF_IGR_PORT_MASK] = "IF_IGR_PORT_MASK", ++ [VCAP_KF_IF_IGR_PORT_MASK_L3] = "IF_IGR_PORT_MASK_L3", ++ [VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG", ++ [VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL", ++ [VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL", ++ [VCAP_KF_IP4_IS] = "IP4_IS", ++ [VCAP_KF_IP_MC_IS] = "IP_MC_IS", ++ [VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE", ++ [VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS", ++ [VCAP_KF_ISDX_CLS] = "ISDX_CLS", ++ [VCAP_KF_ISDX_GT0_IS] = "ISDX_GT0_IS", ++ [VCAP_KF_L2_BC_IS] = "L2_BC_IS", ++ [VCAP_KF_L2_DMAC] = "L2_DMAC", ++ [VCAP_KF_L2_FRM_TYPE] = "L2_FRM_TYPE", ++ [VCAP_KF_L2_FWD_IS] = "L2_FWD_IS", ++ [VCAP_KF_L2_LLC] = "L2_LLC", ++ [VCAP_KF_L2_MC_IS] = "L2_MC_IS", ++ [VCAP_KF_L2_PAYLOAD0] = "L2_PAYLOAD0", ++ [VCAP_KF_L2_PAYLOAD1] = "L2_PAYLOAD1", ++ [VCAP_KF_L2_PAYLOAD2] = "L2_PAYLOAD2", ++ [VCAP_KF_L2_PAYLOAD_ETYPE] = "L2_PAYLOAD_ETYPE", ++ [VCAP_KF_L2_SMAC] = "L2_SMAC", ++ [VCAP_KF_L2_SNAP] = "L2_SNAP", ++ [VCAP_KF_L3_DIP_EQ_SIP_IS] = "L3_DIP_EQ_SIP_IS", ++ [VCAP_KF_L3_DPL_CLS] = "L3_DPL_CLS", ++ [VCAP_KF_L3_DSCP] = "L3_DSCP", ++ [VCAP_KF_L3_DST_IS] = "L3_DST_IS", ++ [VCAP_KF_L3_FRAGMENT] = "L3_FRAGMENT", ++ [VCAP_KF_L3_FRAGMENT_TYPE] = "L3_FRAGMENT_TYPE", ++ [VCAP_KF_L3_FRAG_INVLD_L4_LEN] = "L3_FRAG_INVLD_L4_LEN", ++ [VCAP_KF_L3_FRAG_OFS_GT0] = "L3_FRAG_OFS_GT0", ++ [VCAP_KF_L3_IP4_DIP] = "L3_IP4_DIP", ++ [VCAP_KF_L3_IP4_SIP] = "L3_IP4_SIP", ++ [VCAP_KF_L3_IP6_DIP] = "L3_IP6_DIP", ++ [VCAP_KF_L3_IP6_SIP] = "L3_IP6_SIP", ++ [VCAP_KF_L3_IP_PROTO] = "L3_IP_PROTO", ++ [VCAP_KF_L3_OPTIONS_IS] = "L3_OPTIONS_IS", ++ [VCAP_KF_L3_PAYLOAD] = "L3_PAYLOAD", ++ [VCAP_KF_L3_RT_IS] = "L3_RT_IS", ++ [VCAP_KF_L3_TOS] = "L3_TOS", ++ [VCAP_KF_L3_TTL_GT0] = "L3_TTL_GT0", ++ [VCAP_KF_L4_1588_DOM] = "L4_1588_DOM", ++ [VCAP_KF_L4_1588_VER] = "L4_1588_VER", ++ [VCAP_KF_L4_ACK] = "L4_ACK", ++ [VCAP_KF_L4_DPORT] = "L4_DPORT", ++ [VCAP_KF_L4_FIN] = "L4_FIN", ++ [VCAP_KF_L4_PAYLOAD] = "L4_PAYLOAD", ++ [VCAP_KF_L4_PSH] = "L4_PSH", ++ [VCAP_KF_L4_RNG] = "L4_RNG", ++ [VCAP_KF_L4_RST] = "L4_RST", ++ [VCAP_KF_L4_SEQUENCE_EQ0_IS] = "L4_SEQUENCE_EQ0_IS", ++ [VCAP_KF_L4_SPORT] = "L4_SPORT", ++ [VCAP_KF_L4_SPORT_EQ_DPORT_IS] = "L4_SPORT_EQ_DPORT_IS", ++ [VCAP_KF_L4_SYN] = "L4_SYN", ++ [VCAP_KF_L4_URG] = "L4_URG", ++ [VCAP_KF_LOOKUP_FIRST_IS] = "LOOKUP_FIRST_IS", ++ [VCAP_KF_LOOKUP_GEN_IDX] = "LOOKUP_GEN_IDX", ++ [VCAP_KF_LOOKUP_GEN_IDX_SEL] = "LOOKUP_GEN_IDX_SEL", ++ [VCAP_KF_LOOKUP_PAG] = "LOOKUP_PAG", ++ [VCAP_KF_MIRROR_PROBE] = "MIRROR_PROBE", ++ [VCAP_KF_OAM_CCM_CNTS_EQ0] = "OAM_CCM_CNTS_EQ0", ++ [VCAP_KF_OAM_DETECTED] = "OAM_DETECTED", ++ [VCAP_KF_OAM_FLAGS] = "OAM_FLAGS", ++ [VCAP_KF_OAM_MEL_FLAGS] = "OAM_MEL_FLAGS", ++ [VCAP_KF_OAM_MEPID] = "OAM_MEPID", ++ [VCAP_KF_OAM_OPCODE] = "OAM_OPCODE", ++ [VCAP_KF_OAM_VER] = "OAM_VER", ++ [VCAP_KF_OAM_Y1731_IS] = "OAM_Y1731_IS", ++ [VCAP_KF_PROT_ACTIVE] = "PROT_ACTIVE", ++ [VCAP_KF_TCP_IS] = "TCP_IS", ++ [VCAP_KF_TCP_UDP_IS] = "TCP_UDP_IS", ++ [VCAP_KF_TYPE] = "TYPE", ++}; ++ ++/* Actionfield names */ ++static const char * const vcap_actionfield_names[] = { ++ [VCAP_AF_NO_VALUE] = "(None)", ++ [VCAP_AF_ACL_ID] = "ACL_ID", ++ [VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL", ++ [VCAP_AF_CNT_ID] = "CNT_ID", ++ [VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM", ++ [VCAP_AF_COPY_QUEUE_NUM] = "COPY_QUEUE_NUM", ++ [VCAP_AF_CPU_COPY_ENA] = "CPU_COPY_ENA", ++ [VCAP_AF_CPU_QU] = "CPU_QU", ++ [VCAP_AF_CPU_QUEUE_NUM] = "CPU_QUEUE_NUM", ++ [VCAP_AF_DEI_A_VAL] = "DEI_A_VAL", ++ [VCAP_AF_DEI_B_VAL] = "DEI_B_VAL", ++ [VCAP_AF_DEI_C_VAL] = "DEI_C_VAL", ++ [VCAP_AF_DEI_ENA] = "DEI_ENA", ++ [VCAP_AF_DEI_VAL] = "DEI_VAL", ++ [VCAP_AF_DP_ENA] = "DP_ENA", ++ [VCAP_AF_DP_VAL] = "DP_VAL", ++ [VCAP_AF_DSCP_ENA] = "DSCP_ENA", ++ [VCAP_AF_DSCP_SEL] = "DSCP_SEL", ++ [VCAP_AF_DSCP_VAL] = "DSCP_VAL", ++ [VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD", ++ [VCAP_AF_ESDX] = "ESDX", ++ [VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA", ++ [VCAP_AF_FWD_MODE] = "FWD_MODE", ++ [VCAP_AF_FWD_SEL] = "FWD_SEL", ++ [VCAP_AF_HIT_ME_ONCE] = "HIT_ME_ONCE", ++ [VCAP_AF_HOST_MATCH] = "HOST_MATCH", ++ [VCAP_AF_IGNORE_PIPELINE_CTRL] = "IGNORE_PIPELINE_CTRL", ++ [VCAP_AF_INTR_ENA] = "INTR_ENA", ++ [VCAP_AF_ISDX_ADD_REPLACE_SEL] = "ISDX_ADD_REPLACE_SEL", ++ [VCAP_AF_ISDX_ENA] = "ISDX_ENA", ++ [VCAP_AF_ISDX_VAL] = "ISDX_VAL", ++ [VCAP_AF_LOOP_ENA] = "LOOP_ENA", ++ [VCAP_AF_LRN_DIS] = "LRN_DIS", ++ [VCAP_AF_MAP_IDX] = "MAP_IDX", ++ [VCAP_AF_MAP_KEY] = "MAP_KEY", ++ [VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL", ++ [VCAP_AF_MASK_MODE] = "MASK_MODE", ++ [VCAP_AF_MATCH_ID] = "MATCH_ID", ++ [VCAP_AF_MATCH_ID_MASK] = "MATCH_ID_MASK", ++ [VCAP_AF_MIRROR_ENA] = "MIRROR_ENA", ++ [VCAP_AF_MIRROR_PROBE] = "MIRROR_PROBE", ++ [VCAP_AF_MIRROR_PROBE_ID] = "MIRROR_PROBE_ID", ++ [VCAP_AF_NXT_IDX] = "NXT_IDX", ++ [VCAP_AF_NXT_IDX_CTRL] = "NXT_IDX_CTRL", ++ [VCAP_AF_PAG_OVERRIDE_MASK] = "PAG_OVERRIDE_MASK", ++ [VCAP_AF_PAG_VAL] = "PAG_VAL", ++ [VCAP_AF_PCP_A_VAL] = "PCP_A_VAL", ++ [VCAP_AF_PCP_B_VAL] = "PCP_B_VAL", ++ [VCAP_AF_PCP_C_VAL] = "PCP_C_VAL", ++ [VCAP_AF_PCP_ENA] = "PCP_ENA", ++ [VCAP_AF_PCP_VAL] = "PCP_VAL", ++ [VCAP_AF_PIPELINE_ACT] = "PIPELINE_ACT", ++ [VCAP_AF_PIPELINE_FORCE_ENA] = "PIPELINE_FORCE_ENA", ++ [VCAP_AF_PIPELINE_PT] = "PIPELINE_PT", ++ [VCAP_AF_POLICE_ENA] = "POLICE_ENA", ++ [VCAP_AF_POLICE_IDX] = "POLICE_IDX", ++ [VCAP_AF_POLICE_REMARK] = "POLICE_REMARK", ++ [VCAP_AF_POLICE_VCAP_ONLY] = "POLICE_VCAP_ONLY", ++ [VCAP_AF_POP_VAL] = "POP_VAL", ++ [VCAP_AF_PORT_MASK] = "PORT_MASK", ++ [VCAP_AF_PUSH_CUSTOMER_TAG] = "PUSH_CUSTOMER_TAG", ++ [VCAP_AF_PUSH_INNER_TAG] = "PUSH_INNER_TAG", ++ [VCAP_AF_PUSH_OUTER_TAG] = "PUSH_OUTER_TAG", ++ [VCAP_AF_QOS_ENA] = "QOS_ENA", ++ [VCAP_AF_QOS_VAL] = "QOS_VAL", ++ [VCAP_AF_REW_OP] = "REW_OP", ++ [VCAP_AF_RT_DIS] = "RT_DIS", ++ [VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA", ++ [VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL", ++ [VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL", ++ [VCAP_AF_TAG_A_TPID_SEL] = "TAG_A_TPID_SEL", ++ [VCAP_AF_TAG_A_VID_SEL] = "TAG_A_VID_SEL", ++ [VCAP_AF_TAG_B_DEI_SEL] = "TAG_B_DEI_SEL", ++ [VCAP_AF_TAG_B_PCP_SEL] = "TAG_B_PCP_SEL", ++ [VCAP_AF_TAG_B_TPID_SEL] = "TAG_B_TPID_SEL", ++ [VCAP_AF_TAG_B_VID_SEL] = "TAG_B_VID_SEL", ++ [VCAP_AF_TAG_C_DEI_SEL] = "TAG_C_DEI_SEL", ++ [VCAP_AF_TAG_C_PCP_SEL] = "TAG_C_PCP_SEL", ++ [VCAP_AF_TAG_C_TPID_SEL] = "TAG_C_TPID_SEL", ++ [VCAP_AF_TAG_C_VID_SEL] = "TAG_C_VID_SEL", ++ [VCAP_AF_TYPE] = "TYPE", ++ [VCAP_AF_UNTAG_VID_ENA] = "UNTAG_VID_ENA", ++ [VCAP_AF_VID_A_VAL] = "VID_A_VAL", ++ [VCAP_AF_VID_B_VAL] = "VID_B_VAL", ++ [VCAP_AF_VID_C_VAL] = "VID_C_VAL", ++ [VCAP_AF_VID_VAL] = "VID_VAL", ++}; ++ ++/* VCAPs */ ++const struct vcap_info lan969x_vcaps[] = { ++ [VCAP_TYPE_IS0] = { ++ .name = "is0", ++ .rows = 256, ++ .sw_count = 12, ++ .sw_width = 52, ++ .sticky_width = 1, ++ .act_width = 103, ++ .default_cnt = 70, ++ .require_cnt_dis = 0, ++ .version = 1, ++ .keyfield_set = is0_keyfield_set, ++ .keyfield_set_size = ARRAY_SIZE(is0_keyfield_set), ++ .actionfield_set = is0_actionfield_set, ++ .actionfield_set_size = ARRAY_SIZE(is0_actionfield_set), ++ .keyfield_set_map = is0_keyfield_set_map, ++ .keyfield_set_map_size = is0_keyfield_set_map_size, ++ .actionfield_set_map = is0_actionfield_set_map, ++ .actionfield_set_map_size = is0_actionfield_set_map_size, ++ .keyfield_set_typegroups = is0_keyfield_set_typegroups, ++ .actionfield_set_typegroups = is0_actionfield_set_typegroups, ++ }, ++ [VCAP_TYPE_IS2] = { ++ .name = "is2", ++ .rows = 256, ++ .sw_count = 12, ++ .sw_width = 52, ++ .sticky_width = 1, ++ .act_width = 103, ++ .default_cnt = 38, ++ .require_cnt_dis = 0, ++ .version = 1, ++ .keyfield_set = is2_keyfield_set, ++ .keyfield_set_size = ARRAY_SIZE(is2_keyfield_set), ++ .actionfield_set = is2_actionfield_set, ++ .actionfield_set_size = ARRAY_SIZE(is2_actionfield_set), ++ .keyfield_set_map = is2_keyfield_set_map, ++ .keyfield_set_map_size = is2_keyfield_set_map_size, ++ .actionfield_set_map = is2_actionfield_set_map, ++ .actionfield_set_map_size = is2_actionfield_set_map_size, ++ .keyfield_set_typegroups = is2_keyfield_set_typegroups, ++ .actionfield_set_typegroups = is2_actionfield_set_typegroups, ++ }, ++ [VCAP_TYPE_ES0] = { ++ .name = "es0", ++ .rows = 1536, ++ .sw_count = 1, ++ .sw_width = 51, ++ .sticky_width = 1, ++ .act_width = 469, ++ .default_cnt = 35, ++ .require_cnt_dis = 0, ++ .version = 1, ++ .keyfield_set = es0_keyfield_set, ++ .keyfield_set_size = ARRAY_SIZE(es0_keyfield_set), ++ .actionfield_set = es0_actionfield_set, ++ .actionfield_set_size = ARRAY_SIZE(es0_actionfield_set), ++ .keyfield_set_map = es0_keyfield_set_map, ++ .keyfield_set_map_size = es0_keyfield_set_map_size, ++ .actionfield_set_map = es0_actionfield_set_map, ++ .actionfield_set_map_size = es0_actionfield_set_map_size, ++ .keyfield_set_typegroups = es0_keyfield_set_typegroups, ++ .actionfield_set_typegroups = es0_actionfield_set_typegroups, ++ }, ++ [VCAP_TYPE_ES2] = { ++ .name = "es2", ++ .rows = 256, ++ .sw_count = 12, ++ .sw_width = 52, ++ .sticky_width = 1, ++ .act_width = 19, ++ .default_cnt = 39, ++ .require_cnt_dis = 0, ++ .version = 1, ++ .keyfield_set = es2_keyfield_set, ++ .keyfield_set_size = ARRAY_SIZE(es2_keyfield_set), ++ .actionfield_set = es2_actionfield_set, ++ .actionfield_set_size = ARRAY_SIZE(es2_actionfield_set), ++ .keyfield_set_map = es2_keyfield_set_map, ++ .keyfield_set_map_size = es2_keyfield_set_map_size, ++ .actionfield_set_map = es2_actionfield_set_map, ++ .actionfield_set_map_size = es2_actionfield_set_map_size, ++ .keyfield_set_typegroups = es2_keyfield_set_typegroups, ++ .actionfield_set_typegroups = es2_actionfield_set_typegroups, ++ }, ++}; ++ ++const struct vcap_statistics lan969x_vcap_stats = { ++ .name = "lan969x", ++ .count = 4, ++ .keyfield_set_names = vcap_keyfield_set_names, ++ .actionfield_set_names = vcap_actionfield_set_names, ++ .keyfield_names = vcap_keyfield_names, ++ .actionfield_names = vcap_actionfield_names, ++}; +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_impl.c +@@ -0,0 +1,85 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include "vcap_api.h" ++#include "lan969x.h" ++ ++const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[] = { ++ { ++ .vtype = VCAP_TYPE_IS0, /* CLM-0 */ ++ .vinst = 0, ++ .map_id = 1, ++ .lookups = SPARX5_IS0_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, ++ .first_cid = SPARX5_VCAP_CID_IS0_L0, ++ .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1, ++ .blockno = 2, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_IS0, /* CLM-1 */ ++ .vinst = 1, ++ .map_id = 2, ++ .lookups = SPARX5_IS0_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, ++ .first_cid = SPARX5_VCAP_CID_IS0_L2, ++ .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1, ++ .blockno = 3, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_IS0, /* CLM-2 */ ++ .vinst = 2, ++ .map_id = 3, ++ .lookups = SPARX5_IS0_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS0_LOOKUPS / 3, ++ .first_cid = SPARX5_VCAP_CID_IS0_L4, ++ .last_cid = SPARX5_VCAP_CID_IS0_MAX, ++ .blockno = 4, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_IS2, /* IS2-0 */ ++ .vinst = 0, ++ .map_id = 4, ++ .lookups = SPARX5_IS2_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, ++ .first_cid = SPARX5_VCAP_CID_IS2_L0, ++ .last_cid = SPARX5_VCAP_CID_IS2_L2 - 1, ++ .blockno = 0, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_IS2, /* IS2-1 */ ++ .vinst = 1, ++ .map_id = 5, ++ .lookups = SPARX5_IS2_LOOKUPS, ++ .lookups_per_instance = SPARX5_IS2_LOOKUPS / 2, ++ .first_cid = SPARX5_VCAP_CID_IS2_L2, ++ .last_cid = SPARX5_VCAP_CID_IS2_MAX, ++ .blockno = 1, ++ .blocks = 1, ++ .ingress = true, ++ }, ++ { ++ .vtype = VCAP_TYPE_ES0, ++ .lookups = SPARX5_ES0_LOOKUPS, ++ .lookups_per_instance = SPARX5_ES0_LOOKUPS, ++ .first_cid = SPARX5_VCAP_CID_ES0_L0, ++ .last_cid = SPARX5_VCAP_CID_ES0_MAX, ++ .count = 1536, ++ .ingress = false, ++ }, ++ { ++ .vtype = VCAP_TYPE_ES2, ++ .lookups = SPARX5_ES2_LOOKUPS, ++ .lookups_per_instance = SPARX5_ES2_LOOKUPS, ++ .first_cid = SPARX5_VCAP_CID_ES2_L0, ++ .last_cid = SPARX5_VCAP_CID_ES2_MAX, ++ .count = 1024, ++ .ingress = false, ++ }, ++}; diff --git a/target/linux/microchipsw/patches-6.12/0061-v6.13-net-lan969x-fix-the-use-of-spin_lock-in-PTP-handler.patch b/target/linux/microchipsw/patches-6.12/0061-v6.13-net-lan969x-fix-the-use-of-spin_lock-in-PTP-handler.patch new file mode 100644 index 0000000000..691092ba16 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0061-v6.13-net-lan969x-fix-the-use-of-spin_lock-in-PTP-handler.patch @@ -0,0 +1,33 @@ +From f7a21fee946712acc54102479f0ebaaff48164e4 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 5 Dec 2024 14:54:25 +0100 +Subject: [PATCH 66/82] net: lan969x: fix the use of spin_lock in PTP handler + +We are mixing the use of spin_lock() and spin_lock_irqsave() functions +in the PTP handler of lan969x. Fix this by correctly using the _irqsave +variants. + +Fixes: 24fe83541755 ("net: lan969x: add PTP handler function") +Signed-off-by: Daniel Machon + +[1]: https://lore.kernel.org/netdev/20241024-sparx5-lan969x-switch-driver-2-v2-10-a0b5fae88a0f@microchip.com/ + +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c +@@ -273,9 +273,9 @@ static irqreturn_t lan969x_ptp_irq_handl + if (WARN_ON(!skb_match)) + continue; + +- spin_lock(&sparx5->ptp_ts_id_lock); ++ spin_lock_irqsave(&sparx5->ptp_ts_id_lock, flags); + sparx5->ptp_skbs--; +- spin_unlock(&sparx5->ptp_ts_id_lock); ++ spin_unlock_irqrestore(&sparx5->ptp_ts_id_lock, flags); + + /* Get the h/w timestamp */ + sparx5_get_hwtimestamp(sparx5, &ts, delay); diff --git a/target/linux/microchipsw/patches-6.12/0062-v6.13-net-sparx5-fix-default-value-of-monitor-ports.patch b/target/linux/microchipsw/patches-6.12/0062-v6.13-net-sparx5-fix-default-value-of-monitor-ports.patch new file mode 100644 index 0000000000..9ad9fe82ae --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0062-v6.13-net-sparx5-fix-default-value-of-monitor-ports.patch @@ -0,0 +1,42 @@ +From e647f95a65d299fbb58ef8d44795abab3bc63d41 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Thu, 5 Dec 2024 14:54:27 +0100 +Subject: [PATCH 67/82] net: sparx5: fix default value of monitor ports + +When doing port mirroring, the physical port to send the frame to, is +written to the FRMC_PORT_VAL field of the QFWD_FRAME_COPY_CFG register. +This field is 7 bits wide on sparx5 and 6 bits wide on lan969x, and has +a default value of 65 and 30, respectively (the number of front ports). + +On mirror deletion, we set the default value of the monitor port to +65 for this field, in case no more ports exists for the mirror. Needless +to say, this will not fit the 6 bits on lan969x. + +Fix this by correctly using the n_ports constant instead. + +Fixes: 3f9e46347a46 ("net: sparx5: use SPX5_CONST for constants which already have a symbol") +Signed-off-by: Daniel Machon +Signed-off-by: David S. Miller +--- + drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c | 3 +-- + 1 file changed, 1 insertion(+), 2 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_mirror.c +@@ -12,7 +12,6 @@ + #define SPX5_MIRROR_DISABLED 0 + #define SPX5_MIRROR_EGRESS 1 + #define SPX5_MIRROR_INGRESS 2 +-#define SPX5_MIRROR_MONITOR_PORT_DEFAULT 65 + #define SPX5_QFWD_MP_OFFSET 9 /* Mirror port offset in the QFWD register */ + + /* Convert from bool ingress/egress to mirror direction */ +@@ -200,7 +199,7 @@ void sparx5_mirror_del(struct sparx5_mal + + sparx5_mirror_monitor_set(sparx5, + mirror_idx, +- SPX5_MIRROR_MONITOR_PORT_DEFAULT); ++ sparx5->data->consts->n_ports); + } + + void sparx5_mirror_stats(struct sparx5_mall_entry *entry, diff --git a/target/linux/microchipsw/patches-6.12/0063-v6.14-net-sparx5-do-some-preparation-work.patch b/target/linux/microchipsw/patches-6.12/0063-v6.14-net-sparx5-do-some-preparation-work.patch new file mode 100644 index 0000000000..75cf4d1f41 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0063-v6.14-net-sparx5-do-some-preparation-work.patch @@ -0,0 +1,78 @@ +From 4bb216d318259f940eb2248dc91ade01edea1cc4 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 20 Dec 2024 14:48:40 +0100 +Subject: [PATCH 68/82] net: sparx5: do some preparation work + +The sparx5_port_init() does initial configuration of a variety of +different features and options for each port. Some are shared for all +types of devices, some are not. As it is now, common configuration is +done after configuration of low-speed devices. This will not work when +adding RGMII support in a subsequent patch. + +In preparation for lan969x RGMII support, move a block of code, that +configures 2g5 devices, down. This ensures that the configuration common +to all devices is done before configuration of 2g5, 5g, 10g and 25g +devices. + +Reviewed-by: Steen Hegelund +Reviewed-by: Horatiu Vultur +Tested-by: Robert Marko +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-1-fa8ba5dff732@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../ethernet/microchip/sparx5/sparx5_port.c | 36 +++++++++---------- + 1 file changed, 18 insertions(+), 18 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -1067,24 +1067,6 @@ int sparx5_port_init(struct sparx5 *spar + if (err) + return err; + +- /* Configure MAC vlan awareness */ +- err = sparx5_port_max_tags_set(sparx5, port); +- if (err) +- return err; +- +- /* Set Max Length */ +- spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), +- DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, +- sparx5, +- DEV2G5_MAC_MAXLEN_CFG(port->portno)); +- +- /* 1G/2G5: Signal Detect configuration */ +- spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | +- DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | +- DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), +- sparx5, +- DEV2G5_PCS1G_SD_CFG(port->portno)); +- + /* Set Pause WM hysteresis */ + spx5_rmw(QSYS_PAUSE_CFG_PAUSE_START_SET(pause_start) | + QSYS_PAUSE_CFG_PAUSE_STOP_SET(pause_stop) | +@@ -1108,6 +1090,24 @@ int sparx5_port_init(struct sparx5 *spar + ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, + sparx5, ANA_CL_FILTER_CTRL(port->portno)); + ++ /* Configure MAC vlan awareness */ ++ err = sparx5_port_max_tags_set(sparx5, port); ++ if (err) ++ return err; ++ ++ /* Set Max Length */ ++ spx5_rmw(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(ETH_MAXLEN), ++ DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, ++ sparx5, ++ DEV2G5_MAC_MAXLEN_CFG(port->portno)); ++ ++ /* 1G/2G5: Signal Detect configuration */ ++ spx5_wr(DEV2G5_PCS1G_SD_CFG_SD_POL_SET(sd_pol) | ++ DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(sd_sel) | ++ DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(sd_ena), ++ sparx5, ++ DEV2G5_PCS1G_SD_CFG(port->portno)); ++ + if (conf->portmode == PHY_INTERFACE_MODE_QSGMII || + conf->portmode == PHY_INTERFACE_MODE_SGMII) { + err = sparx5_serdes_set(sparx5, port, conf); diff --git a/target/linux/microchipsw/patches-6.12/0064-v6.14-net-sparx5-add-function-for-RGMII-port-check.patch b/target/linux/microchipsw/patches-6.12/0064-v6.14-net-sparx5-add-function-for-RGMII-port-check.patch new file mode 100644 index 0000000000..e332d6e045 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0064-v6.14-net-sparx5-add-function-for-RGMII-port-check.patch @@ -0,0 +1,82 @@ +From b479572cf00c11a1b57c2fc61e2d2e0f4fb84c4e Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 20 Dec 2024 14:48:41 +0100 +Subject: [PATCH 69/82] net: sparx5: add function for RGMII port check + +The lan969x device contains two RGMII port interfaces, sitting at port +28 and 29. Add function: is_port_rgmii() to the match data ops, that +checks if a given port is an RGMII port or not. For Sparx5, this +function always returns false. + +Reviewed-by: Steen Hegelund +Reviewed-by: Horatiu Vultur +Tested-by: Robert Marko +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-2-fa8ba5dff732@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c | 1 + + drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h | 5 +++++ + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 1 + + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 1 + + drivers/net/ethernet/microchip/sparx5/sparx5_port.h | 5 +++++ + 5 files changed, 13 insertions(+) + +--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c +@@ -329,6 +329,7 @@ static const struct sparx5_ops lan969x_o + .is_port_5g = &lan969x_port_is_5g, + .is_port_10g = &lan969x_port_is_10g, + .is_port_25g = &lan969x_port_is_25g, ++ .is_port_rgmii = &lan969x_port_is_rgmii, + .get_port_dev_index = &lan969x_port_dev_mapping, + .get_port_dev_bit = &lan969x_get_dev_mode_bit, + .get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate, +--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h +@@ -59,6 +59,11 @@ static inline bool lan969x_port_is_25g(i + return false; + } + ++static inline bool lan969x_port_is_rgmii(int portno) ++{ ++ return portno == 28 || portno == 29; ++} ++ + /* lan969x_calendar.c */ + int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, + struct sparx5_calendar_data *data); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -1072,6 +1072,7 @@ static const struct sparx5_ops sparx5_op + .is_port_5g = &sparx5_port_is_5g, + .is_port_10g = &sparx5_port_is_10g, + .is_port_25g = &sparx5_port_is_25g, ++ .is_port_rgmii = &sparx5_port_is_rgmii, + .get_port_dev_index = &sparx5_port_dev_mapping, + .get_port_dev_bit = &sparx5_port_dev_mapping, + .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -313,6 +313,7 @@ struct sparx5_ops { + bool (*is_port_5g)(int portno); + bool (*is_port_10g)(int portno); + bool (*is_port_25g)(int portno); ++ bool (*is_port_rgmii)(int portno); + u32 (*get_port_dev_index)(struct sparx5 *sparx5, int port); + u32 (*get_port_dev_bit)(struct sparx5 *sparx5, int port); + u32 (*get_hsch_max_group_rate)(int grp); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.h +@@ -40,6 +40,11 @@ static inline bool sparx5_port_is_25g(in + return portno >= 56 && portno <= 63; + } + ++static inline bool sparx5_port_is_rgmii(int portno) ++{ ++ return false; ++} ++ + static inline u32 sparx5_to_high_dev(struct sparx5 *sparx5, int port) + { + const struct sparx5_ops *ops = sparx5->data->ops; diff --git a/target/linux/microchipsw/patches-6.12/0065-v6.14-net-sparx5-use-is_port_rgmii-throughout.patch b/target/linux/microchipsw/patches-6.12/0065-v6.14-net-sparx5-use-is_port_rgmii-throughout.patch new file mode 100644 index 0000000000..9928c62303 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0065-v6.14-net-sparx5-use-is_port_rgmii-throughout.patch @@ -0,0 +1,115 @@ +From 1593303768bbf218cb4a7a8f9a9b1968e5e63aa7 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 20 Dec 2024 14:48:42 +0100 +Subject: [PATCH 70/82] net: sparx5: use is_port_rgmii() throughout + +Now that we can check if a given port is an RGMII port, use it in the +following cases: + + - To set RGMII PHY modes for RGMII port devices. + + - To avoid checking for a SerDes node in the devicetree, when the port + is an RGMII port. + + - To bail out of sparx5_port_init() when the common configuration is + done. + +Reviewed-by: Steen Hegelund +Reviewed-by: Horatiu Vultur +Tested-by: Robert Marko +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-3-fa8ba5dff732@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../ethernet/microchip/sparx5/sparx5_main.c | 28 +++++++++++++------ + .../ethernet/microchip/sparx5/sparx5_port.c | 3 ++ + 2 files changed, 23 insertions(+), 8 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -313,10 +313,13 @@ static int sparx5_create_port(struct spa + struct initial_port_config *config) + { + struct sparx5_port *spx5_port; ++ const struct sparx5_ops *ops; + struct net_device *ndev; + struct phylink *phylink; + int err; + ++ ops = sparx5->data->ops; ++ + ndev = sparx5_create_netdev(sparx5, config->portno); + if (IS_ERR(ndev)) { + dev_err(sparx5->dev, "Could not create net device: %02u\n", +@@ -357,6 +360,9 @@ static int sparx5_create_port(struct spa + MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD | + MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD; + ++ if (ops->is_port_rgmii(spx5_port->portno)) ++ phy_interface_set_rgmii(spx5_port->phylink_config.supported_interfaces); ++ + __set_bit(PHY_INTERFACE_MODE_SGMII, + spx5_port->phylink_config.supported_interfaces); + __set_bit(PHY_INTERFACE_MODE_QSGMII, +@@ -830,6 +836,7 @@ static int mchp_sparx5_probe(struct plat + struct initial_port_config *configs, *config; + struct device_node *np = pdev->dev.of_node; + struct device_node *ports, *portnp; ++ const struct sparx5_ops *ops; + struct reset_control *reset; + struct sparx5 *sparx5; + int idx = 0, err = 0; +@@ -851,6 +858,7 @@ static int mchp_sparx5_probe(struct plat + return -EINVAL; + + regs = sparx5->data->regs; ++ ops = sparx5->data->ops; + + /* Do switch core reset if available */ + reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); +@@ -880,7 +888,7 @@ static int mchp_sparx5_probe(struct plat + + for_each_available_child_of_node(ports, portnp) { + struct sparx5_port_config *conf; +- struct phy *serdes; ++ struct phy *serdes = NULL; + u32 portno; + + err = of_property_read_u32(portnp, "reg", &portno); +@@ -910,13 +918,17 @@ static int mchp_sparx5_probe(struct plat + conf->sd_sgpio = ~0; + else + sparx5->sd_sgpio_remapping = true; +- serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); +- if (IS_ERR(serdes)) { +- err = dev_err_probe(sparx5->dev, PTR_ERR(serdes), +- "port %u: missing serdes\n", +- portno); +- of_node_put(portnp); +- goto cleanup_config; ++ /* There is no SerDes node for RGMII ports. */ ++ if (!ops->is_port_rgmii(portno)) { ++ serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); ++ if (IS_ERR(serdes)) { ++ err = dev_err_probe(sparx5->dev, ++ PTR_ERR(serdes), ++ "port %u: missing serdes\n", ++ portno); ++ of_node_put(portnp); ++ goto cleanup_config; ++ } + } + config->portno = portno; + config->node = portnp; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -1090,6 +1090,9 @@ int sparx5_port_init(struct sparx5 *spar + ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, + sparx5, ANA_CL_FILTER_CTRL(port->portno)); + ++ if (ops->is_port_rgmii(port->portno)) ++ return 0; /* RGMII device - nothing more to configure */ ++ + /* Configure MAC vlan awareness */ + err = sparx5_port_max_tags_set(sparx5, port); + if (err) diff --git a/target/linux/microchipsw/patches-6.12/0066-v6.14-net-sparx5-skip-low-speed-configuration-when-port-is.patch b/target/linux/microchipsw/patches-6.12/0066-v6.14-net-sparx5-skip-low-speed-configuration-when-port-is.patch new file mode 100644 index 0000000000..44a6f08a07 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0066-v6.14-net-sparx5-skip-low-speed-configuration-when-port-is.patch @@ -0,0 +1,40 @@ +From 013f57f35a14c04449ff58684d9986bb663375d7 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 20 Dec 2024 14:48:43 +0100 +Subject: [PATCH 71/82] net: sparx5: skip low-speed configuration when port is + RGMII + +When doing a port config, we configure low-speed port devices, among +other things. We have a check to ensure, that the device is indeed a +low-speed device, an not a high-speed device. Add an additional check, +to ensure that the device is not an RGMII device. + +Reviewed-by: Steen Hegelund +Reviewed-by: Horatiu Vultur +Tested-by: Robert Marko +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-4-fa8ba5dff732@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -994,6 +994,7 @@ int sparx5_port_config(struct sparx5 *sp + struct sparx5_port *port, + struct sparx5_port_config *conf) + { ++ bool rgmii = phy_interface_mode_is_rgmii(conf->phy_mode); + bool high_speed_dev = sparx5_is_baser(conf->portmode); + const struct sparx5_ops *ops = sparx5->data->ops; + int err, urgency, stop_wm; +@@ -1003,7 +1004,7 @@ int sparx5_port_config(struct sparx5 *sp + return err; + + /* high speed device is already configured */ +- if (!high_speed_dev) ++ if (!rgmii && !high_speed_dev) + sparx5_port_config_low_set(sparx5, port, conf); + + /* Configure flow control */ diff --git a/target/linux/microchipsw/patches-6.12/0067-v6.14-net-sparx5-only-return-PCS-for-modes-that-require-it.patch b/target/linux/microchipsw/patches-6.12/0067-v6.14-net-sparx5-only-return-PCS-for-modes-that-require-it.patch new file mode 100644 index 0000000000..381a31c186 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0067-v6.14-net-sparx5-only-return-PCS-for-modes-that-require-it.patch @@ -0,0 +1,40 @@ +From be45d246122e57af37216fa846439205ed2cf671 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 20 Dec 2024 14:48:44 +0100 +Subject: [PATCH 72/82] net: sparx5: only return PCS for modes that require it + +The RGMII ports have no PCS to configure. Make sure we only return the +PCS for port modes that require it. + +Reviewed-by: Russell King (Oracle) +Tested-by: Robert Marko +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-5-fa8ba5dff732@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/microchip/sparx5/sparx5_phylink.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c +@@ -32,7 +32,19 @@ sparx5_phylink_mac_select_pcs(struct phy + { + struct sparx5_port *port = netdev_priv(to_net_dev(config->dev)); + +- return &port->phylink_pcs; ++ /* Return the PCS for all the modes that require it. */ ++ switch (interface) { ++ case PHY_INTERFACE_MODE_SGMII: ++ case PHY_INTERFACE_MODE_QSGMII: ++ case PHY_INTERFACE_MODE_1000BASEX: ++ case PHY_INTERFACE_MODE_2500BASEX: ++ case PHY_INTERFACE_MODE_5GBASER: ++ case PHY_INTERFACE_MODE_10GBASER: ++ case PHY_INTERFACE_MODE_25GBASER: ++ return &port->phylink_pcs; ++ default: ++ return NULL; ++ } + } + + static void sparx5_phylink_mac_config(struct phylink_config *config, diff --git a/target/linux/microchipsw/patches-6.12/0068-v6.14-net-sparx5-verify-RGMII-speeds.patch b/target/linux/microchipsw/patches-6.12/0068-v6.14-net-sparx5-verify-RGMII-speeds.patch new file mode 100644 index 0000000000..bb814fc6ae --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0068-v6.14-net-sparx5-verify-RGMII-speeds.patch @@ -0,0 +1,37 @@ +From 3695a85ef07bf3ac9a2ecc458a4c199b5ab755b1 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 20 Dec 2024 14:48:45 +0100 +Subject: [PATCH 73/82] net: sparx5: verify RGMII speeds + +When doing a port config, we verify the port speed against the PHY mode +and supported speeds of that PHY mode. Add checks for the four RGMII phy +modes: RGMII, RGMII_ID, RGMII_TXID and RGMII_RXID. + +Reviewed-by: Steen Hegelund +Reviewed-by: Horatiu Vultur +Tested-by: Robert Marko +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-6-fa8ba5dff732@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_port.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -257,6 +257,15 @@ static int sparx5_port_verify_speed(stru + conf->speed != SPEED_25000)) + return sparx5_port_error(port, conf, SPX5_PERR_SPEED); + break; ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ case PHY_INTERFACE_MODE_RGMII_TXID: ++ case PHY_INTERFACE_MODE_RGMII_RXID: ++ if (conf->speed != SPEED_1000 && ++ conf->speed != SPEED_100 && ++ conf->speed != SPEED_10) ++ return sparx5_port_error(port, conf, SPX5_PERR_SPEED); ++ break; + default: + return sparx5_port_error(port, conf, SPX5_PERR_IFTYPE); + } diff --git a/target/linux/microchipsw/patches-6.12/0069-v6.14-net-lan969x-add-RGMII-registers.patch b/target/linux/microchipsw/patches-6.12/0069-v6.14-net-lan969x-add-RGMII-registers.patch new file mode 100644 index 0000000000..0283b04b30 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0069-v6.14-net-lan969x-add-RGMII-registers.patch @@ -0,0 +1,211 @@ +From 49fbe4bb20903f595b1c22b51aa6a9d3bf0ed5de Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 20 Dec 2024 14:48:46 +0100 +Subject: [PATCH 74/82] net: lan969x: add RGMII registers + +Configuration of RGMII is done by configuring the GPIO and clock +settings in the HSIOWRAP target, and configuring the RGMII port devices +in the DEVRGMII target. Both targets contain registers replicated for +the number of RGMII port devices, which is two. + +Add said targets and register macros required to configure RGMII. + +Reviewed-by: Steen Hegelund +Reviewed-by: Horatiu Vultur +Tested-by: Robert Marko +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-7-fa8ba5dff732@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../microchip/sparx5/lan969x/lan969x.c | 3 + + .../microchip/sparx5/sparx5_main_regs.h | 145 ++++++++++++++++++ + 2 files changed, 148 insertions(+) + +--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c +@@ -90,9 +90,12 @@ static const struct sparx5_main_io_resou + { TARGET_DEV2G5 + 27, 0x30d8000, 1 }, /* 0xe30d8000 */ + { TARGET_DEV10G + 9, 0x30dc000, 1 }, /* 0xe30dc000 */ + { TARGET_PCS10G_BR + 9, 0x30e0000, 1 }, /* 0xe30e0000 */ ++ { TARGET_DEVRGMII, 0x30e4000, 1 }, /* 0xe30e4000 */ ++ { TARGET_DEVRGMII + 1, 0x30e8000, 1 }, /* 0xe30e8000 */ + { TARGET_DSM, 0x30ec000, 1 }, /* 0xe30ec000 */ + { TARGET_PORT_CONF, 0x30f0000, 1 }, /* 0xe30f0000 */ + { TARGET_ASM, 0x3200000, 1 }, /* 0xe3200000 */ ++ { TARGET_HSIO_WRAP, 0x3408000, 1 }, /* 0xe3408000 */ + }; + + static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h +@@ -37,6 +37,7 @@ enum sparx5_target { + TARGET_FDMA = 117, + TARGET_GCB = 118, + TARGET_HSCH = 119, ++ TARGET_HSIO_WRAP = 120, + TARGET_LRN = 122, + TARGET_PCEP = 129, + TARGET_PCS10G_BR = 132, +@@ -54,6 +55,7 @@ enum sparx5_target { + TARGET_VCAP_SUPER = 326, + TARGET_VOP = 327, + TARGET_XQS = 331, ++ TARGET_DEVRGMII = 392, + NUM_TARGETS = 517 + }; + +@@ -5367,6 +5369,69 @@ extern const struct sparx5_regs *regs; + #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\ + FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x) + ++/* LAN969X ONLY */ ++/* HSIOWRAP:XMII_CFG:XMII_CFG */ ++#define HSIO_WRAP_XMII_CFG(g) \ ++ __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 0, 0, 1, 4) ++ ++#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG GENMASK(2, 1) ++#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(x)\ ++ FIELD_PREP(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x) ++#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_GET(x)\ ++ FIELD_GET(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x) ++ ++/* LAN969X ONLY */ ++/* HSIOWRAP:XMII_CFG:RGMII_CFG */ ++#define HSIO_WRAP_RGMII_CFG(g) \ ++ __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 4, 0, 1, 4) ++ ++#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG GENMASK(4, 2) ++#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(x)\ ++ FIELD_PREP(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x) ++#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_GET(x)\ ++ FIELD_GET(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x) ++ ++#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST BIT(1) ++#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(x)\ ++ FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x) ++#define HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_GET(x)\ ++ FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_TX_RST, x) ++ ++#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST BIT(0) ++#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(x)\ ++ FIELD_PREP(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x) ++#define HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_GET(x)\ ++ FIELD_GET(HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, x) ++ ++/* LAN969X ONLY */ ++/* HSIOWRAP:XMII_CFG:DLL_CFG */ ++#define HSIO_WRAP_DLL_CFG(g, r) \ ++ __REG(TARGET_HSIO_WRAP, 0, 1, 116, g, 2, 20, 12, r, 2, 4) ++ ++#define HSIO_WRAP_DLL_CFG_DLL_ENA BIT(19) ++#define HSIO_WRAP_DLL_CFG_DLL_ENA_SET(x)\ ++ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_ENA, x) ++#define HSIO_WRAP_DLL_CFG_DLL_ENA_GET(x)\ ++ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_ENA, x) ++ ++#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA BIT(18) ++#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(x)\ ++ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x) ++#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_GET(x)\ ++ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x) ++ ++#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL GENMASK(17, 15) ++#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(x)\ ++ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x) ++#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_GET(x)\ ++ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x) ++ ++#define HSIO_WRAP_DLL_CFG_DLL_RST BIT(0) ++#define HSIO_WRAP_DLL_CFG_DLL_RST_SET(x)\ ++ FIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_RST, x) ++#define HSIO_WRAP_DLL_CFG_DLL_RST_GET(x)\ ++ FIELD_GET(HSIO_WRAP_DLL_CFG_DLL_RST, x) ++ + /* LRN:COMMON:COMMON_ACCESS_CTRL */ + #define LRN_COMMON_ACCESS_CTRL \ + __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4) +@@ -8110,4 +8175,84 @@ extern const struct sparx5_regs *regs; + #define XQS_CNT(g) \ + __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4) + ++/* LAN969X ONLY */ ++/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */ ++#define DEVRGMII_DEV_RST_CTRL(t) \ ++ __REG(TARGET_DEVRGMII, t, 2, 0, 0, 1, 36, 0, 0, 1, 4) ++ ++#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20) ++#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(x)\ ++ FIELD_PREP(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x) ++#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_GET(x)\ ++ FIELD_GET(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x) ++ ++/* LAN969X ONLY */ ++/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */ ++#define DEVRGMII_MAC_ENA_CFG(t) \ ++ __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 0, 0, 1, 4) ++ ++#define DEVRGMII_MAC_ENA_CFG_RX_ENA BIT(4) ++#define DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(x)\ ++ FIELD_PREP(DEVRGMII_MAC_ENA_CFG_RX_ENA, x) ++#define DEVRGMII_MAC_ENA_CFG_RX_ENA_GET(x)\ ++ FIELD_GET(DEVRGMII_MAC_ENA_CFG_RX_ENA, x) ++ ++#define DEVRGMII_MAC_ENA_CFG_TX_ENA BIT(0) ++#define DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(x)\ ++ FIELD_PREP(DEVRGMII_MAC_ENA_CFG_TX_ENA, x) ++#define DEVRGMII_MAC_ENA_CFG_TX_ENA_GET(x)\ ++ FIELD_GET(DEVRGMII_MAC_ENA_CFG_TX_ENA, x) ++ ++/* LAN969X ONLY */ ++/* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */ ++#define DEVRGMII_MAC_TAGS_CFG(t) \ ++ __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 12, 0, 1, 4) ++ ++#define DEVRGMII_MAC_TAGS_CFG_TAG_ID GENMASK(31, 16) ++#define DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(x)\ ++ FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x) ++#define DEVRGMII_MAC_TAGS_CFG_TAG_ID_GET(x)\ ++ FIELD_GET(DEVRGMII_MAC_TAGS_CFG_TAG_ID, x) ++ ++#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA BIT(3) ++#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\ ++ FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) ++#define DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\ ++ FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x) ++ ++#define DEVRGMII_MAC_TAGS_CFG_PB_ENA GENMASK(2, 1) ++#define DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(x)\ ++ FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x) ++#define DEVRGMII_MAC_TAGS_CFG_PB_ENA_GET(x)\ ++ FIELD_GET(DEVRGMII_MAC_TAGS_CFG_PB_ENA, x) ++ ++#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA BIT(0) ++#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\ ++ FIELD_PREP(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x) ++#define DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\ ++ FIELD_GET(DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA, x) ++ ++/* LAN969X ONLY */ ++/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */ ++#define DEVRGMII_MAC_IFG_CFG(t) \ ++ __REG(TARGET_DEVRGMII, t, 2, 36, 0, 1, 36, 24, 0, 1, 4) ++ ++#define DEVRGMII_MAC_IFG_CFG_TX_IFG GENMASK(12, 8) ++#define DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(x)\ ++ FIELD_PREP(DEVRGMII_MAC_IFG_CFG_TX_IFG, x) ++#define DEVRGMII_MAC_IFG_CFG_TX_IFG_GET(x)\ ++ FIELD_GET(DEVRGMII_MAC_IFG_CFG_TX_IFG, x) ++ ++#define DEVRGMII_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4) ++#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(x)\ ++ FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x) ++#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_GET(x)\ ++ FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x) ++ ++#define DEVRGMII_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0) ++#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(x)\ ++ FIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x) ++#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_GET(x)\ ++ FIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x) ++ + #endif /* _SPARX5_MAIN_REGS_H_ */ diff --git a/target/linux/microchipsw/patches-6.12/0070-v6.14-net-lan969x-add-RGMII-implementation.patch b/target/linux/microchipsw/patches-6.12/0070-v6.14-net-lan969x-add-RGMII-implementation.patch new file mode 100644 index 0000000000..af196f44cc --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0070-v6.14-net-lan969x-add-RGMII-implementation.patch @@ -0,0 +1,320 @@ +From d5444792be67ed47aed76685e62b0f0c29c5e22c Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 20 Dec 2024 14:48:47 +0100 +Subject: [PATCH 75/82] net: lan969x: add RGMII implementation + +The lan969x switch device includes two RGMII port interfaces (port 28 +and 29) supporting data speeds of 1 Gbps, 100 Mbps and 10 Mbps. MAC +level delays are configurable through the HSIO_WRAP target, by choosing +a phase shift selector, corresponding to a certain time delay in nano +seconds. + +Add new file: lan969x_rgmii.c that contains the implementation for +configuring the RGMII port devices. MAC level delays are configured +using the "{rx,tx}-internal-delay-ps" properties. These properties must +be specified independently of the phy-mode. If missing, or set to zero, +the MAC will not apply any delay. + +Reviewed-by: Steen Hegelund +Reviewed-by: Horatiu Vultur +Tested-by: Robert Marko +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-8-fa8ba5dff732@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../net/ethernet/microchip/sparx5/Makefile | 3 +- + .../microchip/sparx5/lan969x/lan969x.c | 1 + + .../microchip/sparx5/lan969x/lan969x.h | 5 + + .../microchip/sparx5/lan969x/lan969x_rgmii.c | 224 ++++++++++++++++++ + .../ethernet/microchip/sparx5/sparx5_main.h | 2 + + .../ethernet/microchip/sparx5/sparx5_port.c | 6 + + 6 files changed, 240 insertions(+), 1 deletion(-) + create mode 100644 drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c + +--- a/drivers/net/ethernet/microchip/sparx5/Makefile ++++ b/drivers/net/ethernet/microchip/sparx5/Makefile +@@ -20,7 +20,8 @@ sparx5-switch-$(CONFIG_LAN969X_SWITCH) + + lan969x/lan969x.o \ + lan969x/lan969x_calendar.o \ + lan969x/lan969x_vcap_ag_api.o \ +- lan969x/lan969x_vcap_impl.o ++ lan969x/lan969x_vcap_impl.o \ ++ lan969x/lan969x_rgmii.o + + # Provide include files + ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap +--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c +@@ -340,6 +340,7 @@ static const struct sparx5_ops lan969x_o + .set_port_mux = &lan969x_port_mux_set, + .ptp_irq_handler = &lan969x_ptp_irq_handler, + .dsm_calendar_calc = &lan969x_dsm_calendar_calc, ++ .port_config_rgmii = &lan969x_port_config_rgmii, + }; + + const struct sparx5_match_data lan969x_desc = { +--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h +@@ -67,4 +67,9 @@ static inline bool lan969x_port_is_rgmii + /* lan969x_calendar.c */ + int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, + struct sparx5_calendar_data *data); ++ ++/* lan969x_rgmii.c */ ++int lan969x_port_config_rgmii(struct sparx5_port *port, ++ struct sparx5_port_config *conf); ++ + #endif +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c +@@ -0,0 +1,224 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. ++ */ ++ ++#include "lan969x.h" ++ ++/* Tx clock selectors */ ++#define LAN969X_RGMII_TX_CLK_SEL_125MHZ 1 /* 1000Mbps */ ++#define LAN969X_RGMII_TX_CLK_SEL_25MHZ 2 /* 100Mbps */ ++#define LAN969X_RGMII_TX_CLK_SEL_2M5MHZ 3 /* 10Mbps */ ++ ++/* Port speed selectors */ ++#define LAN969X_RGMII_SPEED_SEL_10 0 /* Select 10Mbps speed */ ++#define LAN969X_RGMII_SPEED_SEL_100 1 /* Select 100Mbps speed */ ++#define LAN969X_RGMII_SPEED_SEL_1000 2 /* Select 1000Mbps speed */ ++ ++/* Clock delay selectors */ ++#define LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS 2 /* Phase shift 45deg */ ++#define LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS 3 /* Phase shift 77deg */ ++#define LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS 4 /* Phase shift 90deg */ ++#define LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS 5 /* Phase shift 112deg */ ++#define LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS 6 /* Phase shift 135deg */ ++#define LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS 7 /* Phase shift 147deg */ ++ ++#define LAN969X_RGMII_PORT_START_IDX 28 /* Index of the first RGMII port */ ++#define LAN969X_RGMII_IFG_TX 4 /* TX Inter Frame Gap value */ ++#define LAN969X_RGMII_IFG_RX1 5 /* RX1 Inter Frame Gap value */ ++#define LAN969X_RGMII_IFG_RX2 1 /* RX2 Inter Frame Gap value */ ++ ++#define RGMII_PORT_IDX(port) ((port)->portno - LAN969X_RGMII_PORT_START_IDX) ++ ++/* Get the tx clock selector based on the port speed. */ ++static int lan969x_rgmii_get_clk_sel(int speed) ++{ ++ return (speed == SPEED_10 ? LAN969X_RGMII_TX_CLK_SEL_2M5MHZ : ++ speed == SPEED_100 ? LAN969X_RGMII_TX_CLK_SEL_25MHZ : ++ LAN969X_RGMII_TX_CLK_SEL_125MHZ); ++} ++ ++/* Get the port speed selector based on the port speed. */ ++static int lan969x_rgmii_get_speed_sel(int speed) ++{ ++ return (speed == SPEED_10 ? LAN969X_RGMII_SPEED_SEL_10 : ++ speed == SPEED_100 ? LAN969X_RGMII_SPEED_SEL_100 : ++ LAN969X_RGMII_SPEED_SEL_1000); ++} ++ ++/* Get the clock delay selector based on the clock delay in picoseconds. */ ++static int lan969x_rgmii_get_clk_delay_sel(struct sparx5_port *port, ++ u32 delay_ps, u32 *clk_delay_sel) ++{ ++ switch (delay_ps) { ++ case 0: ++ /* Hardware default selector. */ ++ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS; ++ break; ++ case 1000: ++ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS; ++ break; ++ case 1700: ++ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS; ++ break; ++ case 2000: ++ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS; ++ break; ++ case 2500: ++ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS; ++ break; ++ case 3000: ++ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS; ++ break; ++ case 3300: ++ *clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS; ++ break; ++ default: ++ dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++/* Configure the RGMII tx clock frequency. */ ++static void lan969x_rgmii_tx_clk_config(struct sparx5_port *port, ++ struct sparx5_port_config *conf) ++{ ++ u32 clk_sel = lan969x_rgmii_get_clk_sel(conf->speed); ++ u32 idx = RGMII_PORT_IDX(port); ++ ++ /* Take the RGMII clock domain out of reset and set tx clock ++ * frequency. ++ */ ++ spx5_rmw(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(clk_sel) | ++ HSIO_WRAP_RGMII_CFG_RGMII_TX_RST_SET(0) | ++ HSIO_WRAP_RGMII_CFG_RGMII_RX_RST_SET(0), ++ HSIO_WRAP_RGMII_CFG_TX_CLK_CFG | ++ HSIO_WRAP_RGMII_CFG_RGMII_TX_RST | ++ HSIO_WRAP_RGMII_CFG_RGMII_RX_RST, ++ port->sparx5, HSIO_WRAP_RGMII_CFG(idx)); ++} ++ ++/* Configure the RGMII port device. */ ++static void lan969x_rgmii_port_device_config(struct sparx5_port *port, ++ struct sparx5_port_config *conf) ++{ ++ u32 dtag, dotag, etype, speed_sel, idx = RGMII_PORT_IDX(port); ++ ++ speed_sel = lan969x_rgmii_get_speed_sel(conf->speed); ++ ++ etype = (port->vlan_type == SPX5_VLAN_PORT_TYPE_S_CUSTOM ? ++ port->custom_etype : ++ port->vlan_type == SPX5_VLAN_PORT_TYPE_C ? ++ ETH_P_8021Q : ETH_P_8021AD); ++ ++ dtag = port->max_vlan_tags == SPX5_PORT_MAX_TAGS_TWO; ++ dotag = port->max_vlan_tags != SPX5_PORT_MAX_TAGS_NONE; ++ ++ /* Enable the MAC. */ ++ spx5_wr(DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(1) | ++ DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(1), ++ port->sparx5, DEVRGMII_MAC_ENA_CFG(idx)); ++ ++ /* Configure the Inter Frame Gap. */ ++ spx5_wr(DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(LAN969X_RGMII_IFG_TX) | ++ DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(LAN969X_RGMII_IFG_RX1) | ++ DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(LAN969X_RGMII_IFG_RX2), ++ port->sparx5, DEVRGMII_MAC_IFG_CFG(idx)); ++ ++ /* Configure port data rate. */ ++ spx5_wr(DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(speed_sel), ++ port->sparx5, DEVRGMII_DEV_RST_CTRL(idx)); ++ ++ /* Configure VLAN awareness. */ ++ spx5_wr(DEVRGMII_MAC_TAGS_CFG_TAG_ID_SET(etype) | ++ DEVRGMII_MAC_TAGS_CFG_PB_ENA_SET(dtag) | ++ DEVRGMII_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(dotag) | ++ DEVRGMII_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(dotag), ++ port->sparx5, ++ DEVRGMII_MAC_TAGS_CFG(idx)); ++} ++ ++/* Configure the RGMII delay lines in the MAC. ++ * ++ * We use the rx-internal-delay-ps" and "tx-internal-delay-ps" properties to ++ * configure the rx and tx delays for the MAC. If these properties are missing ++ * or set to zero, the MAC will not apply any delay. ++ * ++ * The PHY side delays are determined by the PHY mode ++ * (e.g. PHY_INTERFACE_MODE_RGMII_{ID, RXID, TXID}), and ignored by the MAC side ++ * entirely. ++ */ ++static int lan969x_rgmii_delay_config(struct sparx5_port *port, ++ struct sparx5_port_config *conf) ++{ ++ u32 tx_clk_sel, rx_clk_sel, tx_delay_ps = 0, rx_delay_ps = 0; ++ u32 idx = RGMII_PORT_IDX(port); ++ int err; ++ ++ of_property_read_u32(port->of_node, "rx-internal-delay-ps", ++ &rx_delay_ps); ++ ++ of_property_read_u32(port->of_node, "tx-internal-delay-ps", ++ &tx_delay_ps); ++ ++ err = lan969x_rgmii_get_clk_delay_sel(port, rx_delay_ps, &rx_clk_sel); ++ if (err) ++ return err; ++ ++ err = lan969x_rgmii_get_clk_delay_sel(port, tx_delay_ps, &tx_clk_sel); ++ if (err) ++ return err; ++ ++ /* Configure rx delay. */ ++ spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) | ++ HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) | ++ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(!!rx_delay_ps) | ++ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(rx_clk_sel), ++ HSIO_WRAP_DLL_CFG_DLL_RST | ++ HSIO_WRAP_DLL_CFG_DLL_ENA | ++ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA | ++ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, ++ port->sparx5, HSIO_WRAP_DLL_CFG(idx, 0)); ++ ++ /* Configure tx delay. */ ++ spx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) | ++ HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) | ++ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(!!tx_delay_ps) | ++ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(tx_clk_sel), ++ HSIO_WRAP_DLL_CFG_DLL_RST | ++ HSIO_WRAP_DLL_CFG_DLL_ENA | ++ HSIO_WRAP_DLL_CFG_DLL_CLK_ENA | ++ HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, ++ port->sparx5, HSIO_WRAP_DLL_CFG(idx, 1)); ++ ++ return 0; ++} ++ ++/* Configure GPIO's to be used as RGMII interface. */ ++static void lan969x_rgmii_gpio_config(struct sparx5_port *port) ++{ ++ u32 idx = RGMII_PORT_IDX(port); ++ ++ /* Enable the RGMII on the GPIOs. */ ++ spx5_wr(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(1), port->sparx5, ++ HSIO_WRAP_XMII_CFG(!idx)); ++} ++ ++int lan969x_port_config_rgmii(struct sparx5_port *port, ++ struct sparx5_port_config *conf) ++{ ++ int err; ++ ++ err = lan969x_rgmii_delay_config(port, conf); ++ if (err) ++ return err; ++ ++ lan969x_rgmii_tx_clk_config(port, conf); ++ lan969x_rgmii_gpio_config(port); ++ lan969x_rgmii_port_device_config(port, conf); ++ ++ return 0; ++} +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -324,6 +324,8 @@ struct sparx5_ops { + irqreturn_t (*ptp_irq_handler)(int irq, void *args); + int (*dsm_calendar_calc)(struct sparx5 *sparx5, u32 taxi, + struct sparx5_calendar_data *data); ++ int (*port_config_rgmii)(struct sparx5_port *port, ++ struct sparx5_port_config *conf); + }; + + struct sparx5_main_io_resource { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_port.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_port.c +@@ -1012,6 +1012,12 @@ int sparx5_port_config(struct sparx5 *sp + if (err) + return err; + ++ if (rgmii) { ++ err = ops->port_config_rgmii(port, conf); ++ if (err) ++ return err; ++ } ++ + /* high speed device is already configured */ + if (!rgmii && !high_speed_dev) + sparx5_port_config_low_set(sparx5, port, conf); diff --git a/target/linux/microchipsw/patches-6.12/0071-v6.14-net-sparx5-enable-FDMA-on-lan969x.patch b/target/linux/microchipsw/patches-6.12/0071-v6.14-net-sparx5-enable-FDMA-on-lan969x.patch new file mode 100644 index 0000000000..bb016ffb6b --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0071-v6.14-net-sparx5-enable-FDMA-on-lan969x.patch @@ -0,0 +1,32 @@ +From f7c39a31269c23cba94476b0fa99f547cde1a4ed Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 13 Jan 2025 20:36:05 +0100 +Subject: [PATCH 76/82] net: sparx5: enable FDMA on lan969x + +In a previous series, we made sure that FDMA was not initialized and +started on lan969x. Now that we are going to support it, undo that +change. In addition, make sure the chip ID check is only applicable on +Sparx5, as this is a check that is only relevant on this platform. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-1-c468f02fd623@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++-- + 1 file changed, 3 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -784,8 +784,9 @@ static int sparx5_start(struct sparx5 *s + + /* Start Frame DMA with fallback to register based INJ/XTR */ + err = -ENXIO; +- if (sparx5->fdma_irq >= 0 && is_sparx5(sparx5)) { +- if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0) ++ if (sparx5->fdma_irq >= 0) { ++ if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0 || ++ !is_sparx5(sparx5)) + err = devm_request_irq(sparx5->dev, + sparx5->fdma_irq, + sparx5_fdma_handler, diff --git a/target/linux/microchipsw/patches-6.12/0072-v6.14-net-sparx5-split-sparx5_fdma_-start-stop.patch b/target/linux/microchipsw/patches-6.12/0072-v6.14-net-sparx5-split-sparx5_fdma_-start-stop.patch new file mode 100644 index 0000000000..a9195e3e68 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0072-v6.14-net-sparx5-split-sparx5_fdma_-start-stop.patch @@ -0,0 +1,135 @@ +From c4448d20c23c45be9d59b40f3892e134d2e3f155 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 13 Jan 2025 20:36:06 +0100 +Subject: [PATCH 77/82] net: sparx5: split sparx5_fdma_{start(),stop()} + +The two functions: sparx5_fdma_{start(),stop()} are responsible for a +number of things, namely: allocation and initialization of FDMA buffers, +activation FDMA channels in hardware and activation of the NAPI +instance. + +This patch splits the buffer allocation and initialization into init and +deinit functions, and the channel and NAPI activation into start and +stop functions. This serves two purposes: 1) the start() and stop() +functions can be reused for lan969x and 2) prepares for future MTU +change support, where we must be able to stop and start the FDMA +channels and NAPI instance, without free'ing and reallocating the FDMA +buffers. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-2-c468f02fd623@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../ethernet/microchip/sparx5/sparx5_fdma.c | 44 ++++++++++++++----- + .../ethernet/microchip/sparx5/sparx5_main.c | 7 ++- + .../ethernet/microchip/sparx5/sparx5_main.h | 2 + + 3 files changed, 41 insertions(+), 12 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c +@@ -260,10 +260,6 @@ static int sparx5_fdma_rx_alloc(struct s + fdma_dcbs_init(fdma, FDMA_DCB_INFO_DATAL(fdma->db_size), + FDMA_DCB_STATUS_INTR); + +- netif_napi_add_weight(rx->ndev, &rx->napi, sparx5_fdma_napi_callback, +- FDMA_WEIGHT); +- napi_enable(&rx->napi); +- sparx5_fdma_rx_activate(sparx5, rx); + return 0; + } + +@@ -410,7 +406,7 @@ static void sparx5_fdma_injection_mode(s + } + } + +-int sparx5_fdma_start(struct sparx5 *sparx5) ++int sparx5_fdma_init(struct sparx5 *sparx5) + { + int err; + +@@ -443,24 +439,52 @@ int sparx5_fdma_start(struct sparx5 *spa + return err; + } + ++int sparx5_fdma_deinit(struct sparx5 *sparx5) ++{ ++ sparx5_fdma_stop(sparx5); ++ fdma_free_phys(&sparx5->rx.fdma); ++ fdma_free_phys(&sparx5->tx.fdma); ++ ++ return 0; ++} ++ + static u32 sparx5_fdma_port_ctrl(struct sparx5 *sparx5) + { + return spx5_rd(sparx5, FDMA_PORT_CTRL(0)); + } + ++int sparx5_fdma_start(struct sparx5 *sparx5) ++{ ++ struct sparx5_rx *rx = &sparx5->rx; ++ ++ netif_napi_add_weight(rx->ndev, ++ &rx->napi, ++ sparx5_fdma_napi_callback, ++ FDMA_WEIGHT); ++ ++ napi_enable(&rx->napi); ++ ++ sparx5_fdma_rx_activate(sparx5, rx); ++ ++ return 0; ++} ++ + int sparx5_fdma_stop(struct sparx5 *sparx5) + { ++ struct sparx5_rx *rx = &sparx5->rx; ++ struct sparx5_tx *tx = &sparx5->tx; + u32 val; + +- napi_disable(&sparx5->rx.napi); ++ napi_disable(&rx->napi); ++ + /* Stop the fdma and channel interrupts */ +- sparx5_fdma_rx_deactivate(sparx5, &sparx5->rx); +- sparx5_fdma_tx_deactivate(sparx5, &sparx5->tx); ++ sparx5_fdma_rx_deactivate(sparx5, rx); ++ sparx5_fdma_tx_deactivate(sparx5, tx); ++ + /* Wait for the RX channel to stop */ + read_poll_timeout(sparx5_fdma_port_ctrl, val, + FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(val) == 0, + 500, 10000, 0, sparx5); +- fdma_free_phys(&sparx5->rx.fdma); +- fdma_free_phys(&sparx5->tx.fdma); ++ + return 0; + } +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -792,8 +792,11 @@ static int sparx5_start(struct sparx5 *s + sparx5_fdma_handler, + 0, + "sparx5-fdma", sparx5); +- if (!err) +- err = sparx5_fdma_start(sparx5); ++ if (!err) { ++ err = sparx5_fdma_init(sparx5); ++ if (!err) ++ sparx5_fdma_start(sparx5); ++ } + if (err) + sparx5->fdma_irq = -ENXIO; + } else { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -436,6 +436,8 @@ int sparx5_manual_injection_mode(struct + void sparx5_port_inj_timer_setup(struct sparx5_port *port); + + /* sparx5_fdma.c */ ++int sparx5_fdma_init(struct sparx5 *sparx5); ++int sparx5_fdma_deinit(struct sparx5 *sparx5); + int sparx5_fdma_start(struct sparx5 *sparx5); + int sparx5_fdma_stop(struct sparx5 *sparx5); + int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); diff --git a/target/linux/microchipsw/patches-6.12/0073-v6.14-net-sparx5-activate-FDMA-tx-in-start.patch b/target/linux/microchipsw/patches-6.12/0073-v6.14-net-sparx5-activate-FDMA-tx-in-start.patch new file mode 100644 index 0000000000..86ff7b7d88 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0073-v6.14-net-sparx5-activate-FDMA-tx-in-start.patch @@ -0,0 +1,61 @@ +From 9415d95bb109ed59b4487ff2a90ef8309a8e7e06 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 13 Jan 2025 20:36:07 +0100 +Subject: [PATCH 78/82] net: sparx5: activate FDMA tx in start() + +The function sparx5_fdma_tx_activate() is responsible for configuring +the TX FDMA instance and activating the channel. TX activation has +previously been done in the xmit() function, when the first frame is +transmitted. Now that we have separate functions for starting and +stopping the FDMA, it seems reasonable to move the TX activation to the +start function. This change has no implications on the functionality. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-3-c468f02fd623@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c | 11 ++++------- + 1 file changed, 4 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c +@@ -217,7 +217,6 @@ int sparx5_fdma_xmit(struct sparx5 *spar + { + struct sparx5_tx *tx = &sparx5->tx; + struct fdma *fdma = &tx->fdma; +- static bool first_time = true; + void *virt_addr; + + fdma_dcb_advance(fdma); +@@ -238,12 +237,8 @@ int sparx5_fdma_xmit(struct sparx5 *spar + FDMA_DCB_STATUS_BLOCKO(0) | + FDMA_DCB_STATUS_BLOCKL(skb->len + IFH_LEN * 4 + 4)); + +- if (first_time) { +- sparx5_fdma_tx_activate(sparx5, tx); +- first_time = false; +- } else { +- sparx5_fdma_reload(sparx5, fdma); +- } ++ sparx5_fdma_reload(sparx5, fdma); ++ + return NETDEV_TX_OK; + } + +@@ -456,6 +451,7 @@ static u32 sparx5_fdma_port_ctrl(struct + int sparx5_fdma_start(struct sparx5 *sparx5) + { + struct sparx5_rx *rx = &sparx5->rx; ++ struct sparx5_tx *tx = &sparx5->tx; + + netif_napi_add_weight(rx->ndev, + &rx->napi, +@@ -465,6 +461,7 @@ int sparx5_fdma_start(struct sparx5 *spa + napi_enable(&rx->napi); + + sparx5_fdma_rx_activate(sparx5, rx); ++ sparx5_fdma_tx_activate(sparx5, tx); + + return 0; + } diff --git a/target/linux/microchipsw/patches-6.12/0074-v6.14-net-sparx5-ops-out-certain-FDMA-functions.patch b/target/linux/microchipsw/patches-6.12/0074-v6.14-net-sparx5-ops-out-certain-FDMA-functions.patch new file mode 100644 index 0000000000..ea55d8564b --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0074-v6.14-net-sparx5-ops-out-certain-FDMA-functions.patch @@ -0,0 +1,146 @@ +From 72d96799c80510f1bec9d72e6b4f9b5273069201 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 13 Jan 2025 20:36:08 +0100 +Subject: [PATCH 79/82] net: sparx5: ops out certain FDMA functions + +We are going to implement the RX and TX paths a bit differently on +lan969x and therefore need to introduce new ops for FDMA functions: +init, deinit, xmit and poll. Assign the Sparx5 equivalents for these and +update the code throughout. Also add a 'struct net_device' argument to +the xmit() function, as we will be needing that for lan969x. + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-4-c468f02fd623@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c | 8 +++++--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 9 +++++++-- + drivers/net/ethernet/microchip/sparx5/sparx5_main.h | 9 ++++++++- + drivers/net/ethernet/microchip/sparx5/sparx5_packet.c | 5 ++++- + 4 files changed, 24 insertions(+), 7 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c +@@ -183,7 +183,7 @@ static bool sparx5_fdma_rx_get_frame(str + return true; + } + +-static int sparx5_fdma_napi_callback(struct napi_struct *napi, int weight) ++int sparx5_fdma_napi_callback(struct napi_struct *napi, int weight) + { + struct sparx5_rx *rx = container_of(napi, struct sparx5_rx, napi); + struct sparx5 *sparx5 = container_of(rx, struct sparx5, rx); +@@ -213,7 +213,8 @@ static int sparx5_fdma_napi_callback(str + return counter; + } + +-int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb) ++int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, ++ struct net_device *dev) + { + struct sparx5_tx *tx = &sparx5->tx; + struct fdma *fdma = &tx->fdma; +@@ -450,12 +451,13 @@ static u32 sparx5_fdma_port_ctrl(struct + + int sparx5_fdma_start(struct sparx5 *sparx5) + { ++ const struct sparx5_ops *ops = sparx5->data->ops; + struct sparx5_rx *rx = &sparx5->rx; + struct sparx5_tx *tx = &sparx5->tx; + + netif_napi_add_weight(rx->ndev, + &rx->napi, +- sparx5_fdma_napi_callback, ++ ops->fdma_poll, + FDMA_WEIGHT); + + napi_enable(&rx->napi); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -793,7 +793,7 @@ static int sparx5_start(struct sparx5 *s + 0, + "sparx5-fdma", sparx5); + if (!err) { +- err = sparx5_fdma_init(sparx5); ++ err = ops->fdma_init(sparx5); + if (!err) + sparx5_fdma_start(sparx5); + } +@@ -1030,6 +1030,7 @@ cleanup_pnode: + static void mchp_sparx5_remove(struct platform_device *pdev) + { + struct sparx5 *sparx5 = platform_get_drvdata(pdev); ++ const struct sparx5_ops *ops = sparx5->data->ops; + + debugfs_remove_recursive(sparx5->debugfs_root); + if (sparx5->xtr_irq) { +@@ -1041,7 +1042,7 @@ static void mchp_sparx5_remove(struct pl + sparx5->fdma_irq = -ENXIO; + } + sparx5_ptp_deinit(sparx5); +- sparx5_fdma_stop(sparx5); ++ ops->fdma_deinit(sparx5); + sparx5_cleanup_ports(sparx5); + sparx5_vcap_destroy(sparx5); + /* Unregister netdevs */ +@@ -1096,6 +1097,10 @@ static const struct sparx5_ops sparx5_op + .set_port_mux = &sparx5_port_mux_set, + .ptp_irq_handler = &sparx5_ptp_irq_handler, + .dsm_calendar_calc = &sparx5_dsm_calendar_calc, ++ .fdma_init = &sparx5_fdma_init, ++ .fdma_deinit = &sparx5_fdma_deinit, ++ .fdma_poll = &sparx5_fdma_napi_callback, ++ .fdma_xmit = &sparx5_fdma_xmit, + }; + + static const struct sparx5_match_data sparx5_desc = { +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -326,6 +326,11 @@ struct sparx5_ops { + struct sparx5_calendar_data *data); + int (*port_config_rgmii)(struct sparx5_port *port, + struct sparx5_port_config *conf); ++ int (*fdma_init)(struct sparx5 *sparx5); ++ int (*fdma_deinit)(struct sparx5 *sparx5); ++ int (*fdma_poll)(struct napi_struct *napi, int weight); ++ int (*fdma_xmit)(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, ++ struct net_device *dev); + }; + + struct sparx5_main_io_resource { +@@ -440,7 +445,9 @@ int sparx5_fdma_init(struct sparx5 *spar + int sparx5_fdma_deinit(struct sparx5 *sparx5); + int sparx5_fdma_start(struct sparx5 *sparx5); + int sparx5_fdma_stop(struct sparx5 *sparx5); +-int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb); ++int sparx5_fdma_napi_callback(struct napi_struct *napi, int weight); ++int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, ++ struct net_device *dev); + irqreturn_t sparx5_fdma_handler(int irq, void *args); + + /* sparx5_mactable.c */ +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +@@ -232,9 +232,12 @@ netdev_tx_t sparx5_port_xmit_impl(struct + struct net_device_stats *stats = &dev->stats; + struct sparx5_port *port = netdev_priv(dev); + struct sparx5 *sparx5 = port->sparx5; ++ const struct sparx5_ops *ops; + u32 ifh[IFH_LEN]; + netdev_tx_t ret; + ++ ops = sparx5->data->ops; ++ + memset(ifh, 0, IFH_LEN * 4); + sparx5_set_port_ifh(sparx5, ifh, port->portno); + +@@ -254,7 +257,7 @@ netdev_tx_t sparx5_port_xmit_impl(struct + skb_tx_timestamp(skb); + spin_lock(&sparx5->tx_lock); + if (sparx5->fdma_irq > 0) +- ret = sparx5_fdma_xmit(sparx5, ifh, skb); ++ ret = ops->fdma_xmit(sparx5, ifh, skb, dev); + else + ret = sparx5_inject(sparx5, ifh, skb, dev); + spin_unlock(&sparx5->tx_lock); diff --git a/target/linux/microchipsw/patches-6.12/0075-v6.14-net-lan969x-add-FDMA-implementation.patch b/target/linux/microchipsw/patches-6.12/0075-v6.14-net-lan969x-add-FDMA-implementation.patch new file mode 100644 index 0000000000..b3ebf47a2d --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0075-v6.14-net-lan969x-add-FDMA-implementation.patch @@ -0,0 +1,609 @@ +From 181ee0484e3a966b02ddb238c2abfdbecebafe97 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Mon, 13 Jan 2025 20:36:09 +0100 +Subject: [PATCH 80/82] net: lan969x: add FDMA implementation + +The lan969x switch device supports manual frame injection and extraction +to and from the switch core, using a number of injection and extraction +queues. This technique is currently supported, but delivers poor +performance compared to Frame DMA (FDMA). + +This lan969x implementation of FDMA, hooks into the existing FDMA for +Sparx5, but requires its own RX and TX handling, as lan969x does not +support the same native cache coherency that Sparx5 does. Effectively, +this means that we are going to use the DMA mapping API for mapping and +unmapping TX buffers. The RX loop will utilize the page pool API for +efficient RX handling. Other than that, the implementation is largely +the same, and utilizes the FDMA library for DCB and DB handling. + +Some numbers: + +Manual injection/extraction (before this series): + +// iperf3 -c 1.0.1.1 + +[ ID] Interval Transfer Bitrate +[ 5] 0.00-10.02 sec 345 MBytes 289 Mbits/sec sender +[ 5] 0.00-10.06 sec 345 MBytes 288 Mbits/sec receiver + +FDMA (after this series): + +// iperf3 -c 1.0.1.1 + +[ ID] Interval Transfer Bitrate +[ 5] 0.00-10.03 sec 1.10 GBytes 940 Mbits/sec sender +[ 5] 0.00-10.07 sec 1.10 GBytes 936 Mbits/sec receiver + +Reviewed-by: Steen Hegelund +Signed-off-by: Daniel Machon +Link: https://patch.msgid.link/20250113-sparx5-lan969x-switch-driver-5-v2-5-c468f02fd623@microchip.com +Signed-off-by: Jakub Kicinski +--- + drivers/net/ethernet/microchip/sparx5/Kconfig | 1 + + .../net/ethernet/microchip/sparx5/Makefile | 3 +- + .../microchip/sparx5/lan969x/lan969x.c | 4 + + .../microchip/sparx5/lan969x/lan969x.h | 7 + + .../microchip/sparx5/lan969x/lan969x_fdma.c | 406 ++++++++++++++++++ + .../ethernet/microchip/sparx5/sparx5_fdma.c | 7 +- + .../ethernet/microchip/sparx5/sparx5_main.h | 21 +- + .../ethernet/microchip/sparx5/sparx5_packet.c | 6 + + 8 files changed, 448 insertions(+), 7 deletions(-) + create mode 100644 drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_fdma.c + +--- a/drivers/net/ethernet/microchip/sparx5/Kconfig ++++ b/drivers/net/ethernet/microchip/sparx5/Kconfig +@@ -28,5 +28,6 @@ config SPARX5_DCB + config LAN969X_SWITCH + bool "Lan969x switch driver" + depends on SPARX5_SWITCH ++ select PAGE_POOL + help + This driver supports the lan969x family of network switch devices. +--- a/drivers/net/ethernet/microchip/sparx5/Makefile ++++ b/drivers/net/ethernet/microchip/sparx5/Makefile +@@ -21,7 +21,8 @@ sparx5-switch-$(CONFIG_LAN969X_SWITCH) + + lan969x/lan969x_calendar.o \ + lan969x/lan969x_vcap_ag_api.o \ + lan969x/lan969x_vcap_impl.o \ +- lan969x/lan969x_rgmii.o ++ lan969x/lan969x_rgmii.o \ ++ lan969x/lan969x_fdma.o + + # Provide include files + ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap +--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c +@@ -341,6 +341,10 @@ static const struct sparx5_ops lan969x_o + .ptp_irq_handler = &lan969x_ptp_irq_handler, + .dsm_calendar_calc = &lan969x_dsm_calendar_calc, + .port_config_rgmii = &lan969x_port_config_rgmii, ++ .fdma_init = &lan969x_fdma_init, ++ .fdma_deinit = &lan969x_fdma_deinit, ++ .fdma_poll = &lan969x_fdma_napi_poll, ++ .fdma_xmit = &lan969x_fdma_xmit, + }; + + const struct sparx5_match_data lan969x_desc = { +--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h +@@ -72,4 +72,11 @@ int lan969x_dsm_calendar_calc(struct spa + int lan969x_port_config_rgmii(struct sparx5_port *port, + struct sparx5_port_config *conf); + ++/* lan969x_fdma.c */ ++int lan969x_fdma_init(struct sparx5 *sparx5); ++int lan969x_fdma_deinit(struct sparx5 *sparx5); ++int lan969x_fdma_napi_poll(struct napi_struct *napi, int weight); ++int lan969x_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, ++ struct net_device *dev); ++ + #endif +--- /dev/null ++++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_fdma.c +@@ -0,0 +1,406 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* Microchip lan969x Switch driver ++ * ++ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries. ++ */ ++#include ++ ++#include "../sparx5_main.h" ++#include "../sparx5_main_regs.h" ++#include "../sparx5_port.h" ++ ++#include "fdma_api.h" ++#include "lan969x.h" ++ ++#define FDMA_PRIV(fdma) ((struct sparx5 *)((fdma)->priv)) ++ ++static int lan969x_fdma_tx_dataptr_cb(struct fdma *fdma, int dcb, int db, ++ u64 *dataptr) ++{ ++ *dataptr = FDMA_PRIV(fdma)->tx.dbs[dcb].dma_addr; ++ ++ return 0; ++} ++ ++static int lan969x_fdma_rx_dataptr_cb(struct fdma *fdma, int dcb, int db, ++ u64 *dataptr) ++{ ++ struct sparx5_rx *rx = &FDMA_PRIV(fdma)->rx; ++ struct page *page; ++ ++ page = page_pool_dev_alloc_pages(rx->page_pool); ++ if (unlikely(!page)) ++ return -ENOMEM; ++ ++ rx->page[dcb][db] = page; ++ ++ *dataptr = page_pool_get_dma_addr(page); ++ ++ return 0; ++} ++ ++static int lan969x_fdma_get_next_dcb(struct sparx5_tx *tx) ++{ ++ struct fdma *fdma = &tx->fdma; ++ ++ for (int i = 0; i < fdma->n_dcbs; ++i) ++ if (!tx->dbs[i].used && !fdma_is_last(fdma, &fdma->dcbs[i])) ++ return i; ++ ++ return -ENOSPC; ++} ++ ++static void lan969x_fdma_tx_clear_buf(struct sparx5 *sparx5, int weight) ++{ ++ struct fdma *fdma = &sparx5->tx.fdma; ++ struct sparx5_tx_buf *db; ++ unsigned long flags; ++ int i; ++ ++ spin_lock_irqsave(&sparx5->tx_lock, flags); ++ ++ for (i = 0; i < fdma->n_dcbs; ++i) { ++ db = &sparx5->tx.dbs[i]; ++ ++ if (!db->used) ++ continue; ++ ++ if (!fdma_db_is_done(fdma_db_get(fdma, i, 0))) ++ continue; ++ ++ db->dev->stats.tx_bytes += db->skb->len; ++ db->dev->stats.tx_packets++; ++ sparx5->tx.packets++; ++ ++ dma_unmap_single(sparx5->dev, ++ db->dma_addr, ++ db->skb->len, ++ DMA_TO_DEVICE); ++ ++ if (!db->ptp) ++ napi_consume_skb(db->skb, weight); ++ ++ db->used = false; ++ } ++ ++ spin_unlock_irqrestore(&sparx5->tx_lock, flags); ++} ++ ++static void lan969x_fdma_free_pages(struct sparx5_rx *rx) ++{ ++ struct fdma *fdma = &rx->fdma; ++ ++ for (int i = 0; i < fdma->n_dcbs; ++i) { ++ for (int j = 0; j < fdma->n_dbs; ++j) ++ page_pool_put_full_page(rx->page_pool, ++ rx->page[i][j], false); ++ } ++} ++ ++static struct sk_buff *lan969x_fdma_rx_get_frame(struct sparx5 *sparx5, ++ struct sparx5_rx *rx) ++{ ++ const struct sparx5_consts *consts = sparx5->data->consts; ++ struct fdma *fdma = &rx->fdma; ++ struct sparx5_port *port; ++ struct frame_info fi; ++ struct sk_buff *skb; ++ struct fdma_db *db; ++ struct page *page; ++ ++ db = &fdma->dcbs[fdma->dcb_index].db[fdma->db_index]; ++ page = rx->page[fdma->dcb_index][fdma->db_index]; ++ ++ sparx5_ifh_parse(sparx5, page_address(page), &fi); ++ port = fi.src_port < consts->n_ports ? sparx5->ports[fi.src_port] : ++ NULL; ++ if (WARN_ON(!port)) ++ goto free_page; ++ ++ skb = build_skb(page_address(page), fdma->db_size); ++ if (unlikely(!skb)) ++ goto free_page; ++ ++ skb_mark_for_recycle(skb); ++ skb_put(skb, fdma_db_len_get(db)); ++ skb_pull(skb, IFH_LEN * sizeof(u32)); ++ ++ skb->dev = port->ndev; ++ ++ if (likely(!(skb->dev->features & NETIF_F_RXFCS))) ++ skb_trim(skb, skb->len - ETH_FCS_LEN); ++ ++ sparx5_ptp_rxtstamp(sparx5, skb, fi.timestamp); ++ skb->protocol = eth_type_trans(skb, skb->dev); ++ ++ if (test_bit(port->portno, sparx5->bridge_mask)) ++ skb->offload_fwd_mark = 1; ++ ++ skb->dev->stats.rx_bytes += skb->len; ++ skb->dev->stats.rx_packets++; ++ ++ return skb; ++ ++free_page: ++ page_pool_recycle_direct(rx->page_pool, page); ++ ++ return NULL; ++} ++ ++static int lan969x_fdma_rx_alloc(struct sparx5 *sparx5) ++{ ++ struct sparx5_rx *rx = &sparx5->rx; ++ struct fdma *fdma = &rx->fdma; ++ int err; ++ ++ struct page_pool_params pp_params = { ++ .order = 0, ++ .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, ++ .pool_size = fdma->n_dcbs * fdma->n_dbs, ++ .nid = NUMA_NO_NODE, ++ .dev = sparx5->dev, ++ .dma_dir = DMA_FROM_DEVICE, ++ .offset = 0, ++ .max_len = fdma->db_size - ++ SKB_DATA_ALIGN(sizeof(struct skb_shared_info)), ++ }; ++ ++ rx->page_pool = page_pool_create(&pp_params); ++ if (IS_ERR(rx->page_pool)) ++ return PTR_ERR(rx->page_pool); ++ ++ err = fdma_alloc_coherent(sparx5->dev, fdma); ++ if (err) ++ return err; ++ ++ fdma_dcbs_init(fdma, ++ FDMA_DCB_INFO_DATAL(fdma->db_size), ++ FDMA_DCB_STATUS_INTR); ++ ++ return 0; ++} ++ ++static int lan969x_fdma_tx_alloc(struct sparx5 *sparx5) ++{ ++ struct sparx5_tx *tx = &sparx5->tx; ++ struct fdma *fdma = &tx->fdma; ++ int err; ++ ++ tx->dbs = kcalloc(fdma->n_dcbs, ++ sizeof(struct sparx5_tx_buf), ++ GFP_KERNEL); ++ if (!tx->dbs) ++ return -ENOMEM; ++ ++ err = fdma_alloc_coherent(sparx5->dev, fdma); ++ if (err) { ++ kfree(tx->dbs); ++ return err; ++ } ++ ++ fdma_dcbs_init(fdma, ++ FDMA_DCB_INFO_DATAL(fdma->db_size), ++ FDMA_DCB_STATUS_DONE); ++ ++ return 0; ++} ++ ++static void lan969x_fdma_rx_init(struct sparx5 *sparx5) ++{ ++ struct fdma *fdma = &sparx5->rx.fdma; ++ ++ fdma->channel_id = FDMA_XTR_CHANNEL; ++ fdma->n_dcbs = FDMA_DCB_MAX; ++ fdma->n_dbs = 1; ++ fdma->priv = sparx5; ++ fdma->size = fdma_get_size(fdma); ++ fdma->db_size = PAGE_SIZE; ++ fdma->ops.dataptr_cb = &lan969x_fdma_rx_dataptr_cb; ++ fdma->ops.nextptr_cb = &fdma_nextptr_cb; ++ ++ /* Fetch a netdev for SKB and NAPI use, any will do */ ++ for (int idx = 0; idx < sparx5->data->consts->n_ports; ++idx) { ++ struct sparx5_port *port = sparx5->ports[idx]; ++ ++ if (port && port->ndev) { ++ sparx5->rx.ndev = port->ndev; ++ break; ++ } ++ } ++} ++ ++static void lan969x_fdma_tx_init(struct sparx5 *sparx5) ++{ ++ struct fdma *fdma = &sparx5->tx.fdma; ++ ++ fdma->channel_id = FDMA_INJ_CHANNEL; ++ fdma->n_dcbs = FDMA_DCB_MAX; ++ fdma->n_dbs = 1; ++ fdma->priv = sparx5; ++ fdma->size = fdma_get_size(fdma); ++ fdma->db_size = PAGE_SIZE; ++ fdma->ops.dataptr_cb = &lan969x_fdma_tx_dataptr_cb; ++ fdma->ops.nextptr_cb = &fdma_nextptr_cb; ++} ++ ++int lan969x_fdma_napi_poll(struct napi_struct *napi, int weight) ++{ ++ struct sparx5_rx *rx = container_of(napi, struct sparx5_rx, napi); ++ struct sparx5 *sparx5 = container_of(rx, struct sparx5, rx); ++ int old_dcb, dcb_reload, counter = 0; ++ struct fdma *fdma = &rx->fdma; ++ struct sk_buff *skb; ++ ++ dcb_reload = fdma->dcb_index; ++ ++ lan969x_fdma_tx_clear_buf(sparx5, weight); ++ ++ /* Process RX data */ ++ while (counter < weight) { ++ if (!fdma_has_frames(fdma)) ++ break; ++ ++ skb = lan969x_fdma_rx_get_frame(sparx5, rx); ++ if (!skb) ++ break; ++ ++ napi_gro_receive(&rx->napi, skb); ++ ++ fdma_db_advance(fdma); ++ counter++; ++ /* Check if the DCB can be reused */ ++ if (fdma_dcb_is_reusable(fdma)) ++ continue; ++ ++ fdma_db_reset(fdma); ++ fdma_dcb_advance(fdma); ++ } ++ ++ /* Allocate new pages and map them */ ++ while (dcb_reload != fdma->dcb_index) { ++ old_dcb = dcb_reload; ++ dcb_reload++; ++ /* n_dcbs must be a power of 2 */ ++ dcb_reload &= fdma->n_dcbs - 1; ++ ++ fdma_dcb_add(fdma, ++ old_dcb, ++ FDMA_DCB_INFO_DATAL(fdma->db_size), ++ FDMA_DCB_STATUS_INTR); ++ ++ sparx5_fdma_reload(sparx5, fdma); ++ } ++ ++ if (counter < weight && napi_complete_done(napi, counter)) ++ spx5_wr(0xff, sparx5, FDMA_INTR_DB_ENA); ++ ++ return counter; ++} ++ ++int lan969x_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, ++ struct net_device *dev) ++{ ++ int next_dcb, needed_headroom, needed_tailroom, err; ++ struct sparx5_tx *tx = &sparx5->tx; ++ struct fdma *fdma = &tx->fdma; ++ struct sparx5_tx_buf *db_buf; ++ u64 status; ++ ++ next_dcb = lan969x_fdma_get_next_dcb(tx); ++ if (next_dcb < 0) ++ return -EBUSY; ++ ++ needed_headroom = max_t(int, IFH_LEN * 4 - skb_headroom(skb), 0); ++ needed_tailroom = max_t(int, ETH_FCS_LEN - skb_tailroom(skb), 0); ++ if (needed_headroom || needed_tailroom || skb_header_cloned(skb)) { ++ err = pskb_expand_head(skb, needed_headroom, needed_tailroom, ++ GFP_ATOMIC); ++ if (unlikely(err)) ++ return err; ++ } ++ ++ skb_push(skb, IFH_LEN * 4); ++ memcpy(skb->data, ifh, IFH_LEN * 4); ++ skb_put(skb, ETH_FCS_LEN); ++ ++ db_buf = &tx->dbs[next_dcb]; ++ db_buf->dma_addr = dma_map_single(sparx5->dev, ++ skb->data, ++ skb->len, ++ DMA_TO_DEVICE); ++ if (dma_mapping_error(sparx5->dev, db_buf->dma_addr)) ++ return -ENOMEM; ++ ++ db_buf->dev = dev; ++ db_buf->skb = skb; ++ db_buf->ptp = false; ++ db_buf->used = true; ++ ++ if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && ++ SPARX5_SKB_CB(skb)->rew_op == IFH_REW_OP_TWO_STEP_PTP) ++ db_buf->ptp = true; ++ ++ status = FDMA_DCB_STATUS_SOF | ++ FDMA_DCB_STATUS_EOF | ++ FDMA_DCB_STATUS_BLOCKO(0) | ++ FDMA_DCB_STATUS_BLOCKL(skb->len) | ++ FDMA_DCB_STATUS_INTR; ++ ++ fdma_dcb_advance(fdma); ++ fdma_dcb_add(fdma, next_dcb, 0, status); ++ ++ sparx5_fdma_reload(sparx5, fdma); ++ ++ return NETDEV_TX_OK; ++} ++ ++int lan969x_fdma_init(struct sparx5 *sparx5) ++{ ++ struct sparx5_rx *rx = &sparx5->rx; ++ int err; ++ ++ lan969x_fdma_rx_init(sparx5); ++ lan969x_fdma_tx_init(sparx5); ++ sparx5_fdma_injection_mode(sparx5); ++ ++ err = dma_set_mask_and_coherent(sparx5->dev, DMA_BIT_MASK(64)); ++ if (err) { ++ dev_err(sparx5->dev, "Failed to set 64-bit FDMA mask"); ++ return err; ++ } ++ ++ err = lan969x_fdma_rx_alloc(sparx5); ++ if (err) { ++ dev_err(sparx5->dev, "Failed to allocate RX buffers: %d\n", ++ err); ++ return err; ++ } ++ ++ err = lan969x_fdma_tx_alloc(sparx5); ++ if (err) { ++ fdma_free_coherent(sparx5->dev, &rx->fdma); ++ dev_err(sparx5->dev, "Failed to allocate TX buffers: %d\n", ++ err); ++ return err; ++ } ++ ++ /* Reset FDMA state */ ++ spx5_wr(FDMA_CTRL_NRESET_SET(0), sparx5, FDMA_CTRL); ++ spx5_wr(FDMA_CTRL_NRESET_SET(1), sparx5, FDMA_CTRL); ++ ++ return err; ++} ++ ++int lan969x_fdma_deinit(struct sparx5 *sparx5) ++{ ++ struct sparx5_rx *rx = &sparx5->rx; ++ struct sparx5_tx *tx = &sparx5->tx; ++ ++ sparx5_fdma_stop(sparx5); ++ fdma_free_coherent(sparx5->dev, &tx->fdma); ++ fdma_free_coherent(sparx5->dev, &rx->fdma); ++ lan969x_fdma_free_pages(rx); ++ page_pool_destroy(rx->page_pool); ++ ++ return 0; ++} +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_fdma.c +@@ -18,9 +18,6 @@ + #include "sparx5_main.h" + #include "sparx5_port.h" + +-#define FDMA_XTR_CHANNEL 6 +-#define FDMA_INJ_CHANNEL 0 +- + #define FDMA_XTR_BUFFER_SIZE 2048 + #define FDMA_WEIGHT 4 + +@@ -133,7 +130,7 @@ static void sparx5_fdma_tx_deactivate(st + sparx5, FDMA_CH_ACTIVATE); + } + +-static void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma) ++void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma) + { + /* Reload the RX channel */ + spx5_wr(BIT(fdma->channel_id), sparx5, FDMA_CH_RELOAD); +@@ -340,7 +337,7 @@ irqreturn_t sparx5_fdma_handler(int irq, + return IRQ_HANDLED; + } + +-static void sparx5_fdma_injection_mode(struct sparx5 *sparx5) ++void sparx5_fdma_injection_mode(struct sparx5 *sparx5) + { + const int byte_swap = 1; + int portno; +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.h ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.h +@@ -112,6 +112,8 @@ enum sparx5_feature { + #define XTR_QUEUE 0 + #define INJ_QUEUE 0 + ++#define FDMA_XTR_CHANNEL 6 ++#define FDMA_INJ_CHANNEL 0 + #define FDMA_DCB_MAX 64 + #define FDMA_RX_DCB_MAX_DBS 15 + #define FDMA_TX_DCB_MAX_DBS 1 +@@ -157,11 +159,25 @@ struct sparx5_calendar_data { + */ + struct sparx5_rx { + struct fdma fdma; +- struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; ++ struct page_pool *page_pool; ++ union { ++ struct sk_buff *skb[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; ++ struct page *page[FDMA_DCB_MAX][FDMA_RX_DCB_MAX_DBS]; ++ }; + dma_addr_t dma; + struct napi_struct napi; + struct net_device *ndev; + u64 packets; ++ u8 page_order; ++}; ++ ++/* Used to store information about TX buffers. */ ++struct sparx5_tx_buf { ++ struct net_device *dev; ++ struct sk_buff *skb; ++ dma_addr_t dma_addr; ++ bool used; ++ bool ptp; + }; + + /* Frame DMA transmit state: +@@ -169,6 +185,7 @@ struct sparx5_rx { + */ + struct sparx5_tx { + struct fdma fdma; ++ struct sparx5_tx_buf *dbs; + u64 packets; + u64 dropped; + }; +@@ -449,6 +466,8 @@ int sparx5_fdma_napi_callback(struct nap + int sparx5_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb, + struct net_device *dev); + irqreturn_t sparx5_fdma_handler(int irq, void *args); ++void sparx5_fdma_reload(struct sparx5 *sparx5, struct fdma *fdma); ++void sparx5_fdma_injection_mode(struct sparx5 *sparx5); + + /* sparx5_mactable.c */ + void sparx5_mact_pull_work(struct work_struct *work); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_packet.c +@@ -267,6 +267,12 @@ netdev_tx_t sparx5_port_xmit_impl(struct + if (ret < 0) + goto drop; + ++ if (!is_sparx5(sparx5)) ++ /* When lan969x and TX_OK, stats and SKB consumption is handled ++ * in the TX completion loop, so dont go any further. ++ */ ++ return NETDEV_TX_OK; ++ + stats->tx_bytes += skb->len; + stats->tx_packets++; + sparx5->tx.packets++; diff --git a/target/linux/microchipsw/patches-6.12/0077-v6.18-net-sparx5-lan969x-Add-support-for-ethtool-pause-par.patch b/target/linux/microchipsw/patches-6.12/0077-v6.18-net-sparx5-lan969x-Add-support-for-ethtool-pause-par.patch new file mode 100644 index 0000000000..6e5ddff63a --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0077-v6.18-net-sparx5-lan969x-Add-support-for-ethtool-pause-par.patch @@ -0,0 +1,62 @@ +From b3461fb971b0db9158653bdbcb99d1327f7eeff0 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Wed, 17 Sep 2025 13:49:43 +0200 +Subject: [PATCH 82/82] net: sparx5/lan969x: Add support for ethtool pause + parameters + +Implement get_pauseparam() and set_pauseparam() ethtool operations for +Sparx5 ports. This allows users to query and configure IEEE 802.3x +pause frame settings via: + +ethtool -a ethX +ethtool -A ethX rx on|off tx on|off autoneg on|off + +The driver delegates pause parameter handling to phylink through +phylink_ethtool_get_pauseparam() and phylink_ethtool_set_pauseparam(). + +The underlying configuration of pause frame generation and reception is +already implemented in the driver; this patch only wires it up to the +standard ethtool interface, making the feature accessible to userspace. + +Signed-off-by: Daniel Machon +Reviewed-by: Russell King (Oracle) +Link: https://patch.msgid.link/20250917-802-3x-pause-v1-1-3d1565a68a96@microchip.com +Signed-off-by: Jakub Kicinski +--- + .../ethernet/microchip/sparx5/sparx5_ethtool.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ethtool.c +@@ -1212,6 +1212,22 @@ static int sparx5_get_ts_info(struct net + return 0; + } + ++static void sparx5_get_pauseparam(struct net_device *dev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct sparx5_port *port = netdev_priv(dev); ++ ++ phylink_ethtool_get_pauseparam(port->phylink, pause); ++} ++ ++static int sparx5_set_pauseparam(struct net_device *dev, ++ struct ethtool_pauseparam *pause) ++{ ++ struct sparx5_port *port = netdev_priv(dev); ++ ++ return phylink_ethtool_set_pauseparam(port->phylink, pause); ++} ++ + const struct ethtool_ops sparx5_ethtool_ops = { + .get_sset_count = sparx5_get_sset_count, + .get_strings = sparx5_get_sset_strings, +@@ -1224,6 +1240,8 @@ const struct ethtool_ops sparx5_ethtool_ + .get_eth_ctrl_stats = sparx5_get_eth_mac_ctrl_stats, + .get_rmon_stats = sparx5_get_eth_rmon_stats, + .get_ts_info = sparx5_get_ts_info, ++ .get_pauseparam = sparx5_get_pauseparam, ++ .set_pauseparam = sparx5_set_pauseparam, + }; + + int sparx_stats_init(struct sparx5 *sparx5) diff --git a/target/linux/microchipsw/patches-6.12/0078-v6.14-spi-atmel-quadspi-Add-support-for-sama7g5-QSPI.patch b/target/linux/microchipsw/patches-6.12/0078-v6.14-spi-atmel-quadspi-Add-support-for-sama7g5-QSPI.patch new file mode 100644 index 0000000000..e005bb8f98 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0078-v6.14-spi-atmel-quadspi-Add-support-for-sama7g5-QSPI.patch @@ -0,0 +1,1175 @@ +From 388e3b42aa5a15009457e250d623b2ee74bf4f92 Mon Sep 17 00:00:00 2001 +From: Tudor Ambarus +Date: Thu, 28 Nov 2024 18:43:15 +0100 +Subject: [PATCH 098/112] spi: atmel-quadspi: Add support for sama7g5 QSPI +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The sama7g5 QSPI controller uses dedicated clocks for the +QSPI Controller Interface and the QSPI Controller Core, and +requires synchronization before accessing registers or bit +fields. + +QSPI_SR.SYNCBSY must be zero before accessing any of the bits: +QSPI_CR.QSPIEN, QSPI_CR.QSPIDIS, QSPI_CR.SRFRSH, QSPI_CR.SWRST, +QSPI_CR.UPDCFG, QSPI_CR.STTFR, QSPI_CR.RTOUT, QSPI_CR.LASTXFER. + +Also, the QSPI controller core configuration can be updated by +writing the QSPI_CR.UPDCFG bit to ‘1’. This is needed by the +following registers: QSPI_MR, QSPI_SCR, QSPI_IAR, QSPI_WICR, +QSPI_IFR, QSPI_RICR, QSPI_SMR, QSPI_SKR,QSPI_REFRESH, QSPI_WRACNT +QSPI_PCALCFG. + +The Octal SPI supports frequencies up to 200 MHZ DDR. The need +for output impedance calibration arises. To avoid the degradation +of the signal quality, a PAD calibration cell is used to adjust +the output impedance to the driven I/Os. + +The transmission flow requires different sequences for setting +the configuration and for the actual transfer, than what is in +the sama5d2 and sam9x60 versions of the IP. Different interrupts +are handled. aq->ops->set_cfg() and aq->ops->transfer() are +introduced to help differentiating the flows. + +Tested single and octal SPI mode with mx66lm1g45g. + +Signed-off-by: Tudor Ambarus +Link: https://lore.kernel.org/r/20211214133404.121739-1-tudor.ambarus@microchip.com +[varshini.rajendran@microchip.com: Fixed conflicts and ported to 6.1.4] +Signed-off-by: Varshini Rajendran +[ csokas.bence: Forward-port to master and address feedback ] +Signed-off-by: Csókás, Bence +Link: https://patch.msgid.link/20241128174316.3209354-3-csokas.bence@prolan.hu +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 816 +++++++++++++++++++++++++++++++++++- + 1 file changed, 798 insertions(+), 18 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -11,11 +11,15 @@ + * This driver is based on drivers/mtd/spi-nor/fsl-quadspi.c from Freescale. + */ + ++#include + #include + #include ++#include ++#include + #include + #include + #include ++#include + #include + #include + #include +@@ -34,6 +38,7 @@ + #define QSPI_IDR 0x0018 /* Interrupt Disable Register */ + #define QSPI_IMR 0x001c /* Interrupt Mask Register */ + #define QSPI_SCR 0x0020 /* Serial Clock Register */ ++#define QSPI_SR2 0x0024 /* SAMA7G5 Status Register */ + + #define QSPI_IAR 0x0030 /* Instruction Address Register */ + #define QSPI_ICR 0x0034 /* Instruction Code Register */ +@@ -44,16 +49,32 @@ + #define QSPI_SMR 0x0040 /* Scrambling Mode Register */ + #define QSPI_SKR 0x0044 /* Scrambling Key Register */ + ++#define QSPI_REFRESH 0x0050 /* Refresh Register */ ++#define QSPI_WRACNT 0x0054 /* Write Access Counter Register */ ++#define QSPI_DLLCFG 0x0058 /* DLL Configuration Register */ ++#define QSPI_PCALCFG 0x005C /* Pad Calibration Configuration Register */ ++#define QSPI_PCALBP 0x0060 /* Pad Calibration Bypass Register */ ++#define QSPI_TOUT 0x0064 /* Timeout Register */ ++ + #define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */ + #define QSPI_WPSR 0x00E8 /* Write Protection Status Register */ + + #define QSPI_VERSION 0x00FC /* Version Register */ + ++#define SAMA7G5_QSPI0_MAX_SPEED_HZ 200000000 ++#define SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ 133000000 + + /* Bitfields in QSPI_CR (Control Register) */ + #define QSPI_CR_QSPIEN BIT(0) + #define QSPI_CR_QSPIDIS BIT(1) ++#define QSPI_CR_DLLON BIT(2) ++#define QSPI_CR_DLLOFF BIT(3) ++#define QSPI_CR_STPCAL BIT(4) ++#define QSPI_CR_SRFRSH BIT(5) + #define QSPI_CR_SWRST BIT(7) ++#define QSPI_CR_UPDCFG BIT(8) ++#define QSPI_CR_STTFR BIT(9) ++#define QSPI_CR_RTOUT BIT(10) + #define QSPI_CR_LASTXFER BIT(24) + + /* Bitfields in QSPI_MR (Mode Register) */ +@@ -61,12 +82,14 @@ + #define QSPI_MR_LLB BIT(1) + #define QSPI_MR_WDRBT BIT(2) + #define QSPI_MR_SMRM BIT(3) ++#define QSPI_MR_DQSDLYEN BIT(3) + #define QSPI_MR_CSMODE_MASK GENMASK(5, 4) + #define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4) + #define QSPI_MR_CSMODE_LASTXFER (1 << 4) + #define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4) + #define QSPI_MR_NBBITS_MASK GENMASK(11, 8) + #define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK) ++#define QSPI_MR_OENSD BIT(15) + #define QSPI_MR_DLYBCT_MASK GENMASK(23, 16) + #define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK) + #define QSPI_MR_DLYCS_MASK GENMASK(31, 24) +@@ -80,6 +103,13 @@ + #define QSPI_SR_CSR BIT(8) + #define QSPI_SR_CSS BIT(9) + #define QSPI_SR_INSTRE BIT(10) ++#define QSPI_SR_LWRA BIT(11) ++#define QSPI_SR_QITF BIT(12) ++#define QSPI_SR_QITR BIT(13) ++#define QSPI_SR_CSFA BIT(14) ++#define QSPI_SR_CSRA BIT(15) ++#define QSPI_SR_RFRSHD BIT(16) ++#define QSPI_SR_TOUT BIT(17) + #define QSPI_SR_QSPIENS BIT(24) + + #define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR) +@@ -92,9 +122,22 @@ + #define QSPI_SCR_DLYBS_MASK GENMASK(23, 16) + #define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK) + ++/* Bitfields in QSPI_SR2 (SAMA7G5 Status Register) */ ++#define QSPI_SR2_SYNCBSY BIT(0) ++#define QSPI_SR2_QSPIENS BIT(1) ++#define QSPI_SR2_CSS BIT(2) ++#define QSPI_SR2_RBUSY BIT(3) ++#define QSPI_SR2_HIDLE BIT(4) ++#define QSPI_SR2_DLOCK BIT(5) ++#define QSPI_SR2_CALBSY BIT(6) ++ ++/* Bitfields in QSPI_IAR (Instruction Address Register) */ ++#define QSPI_IAR_ADDR GENMASK(31, 0) ++ + /* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */ + #define QSPI_ICR_INST_MASK GENMASK(7, 0) + #define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK) ++#define QSPI_ICR_INST_MASK_SAMA7G5 GENMASK(15, 0) + #define QSPI_ICR_OPT_MASK GENMASK(23, 16) + #define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK) + +@@ -107,6 +150,9 @@ + #define QSPI_IFR_WIDTH_QUAD_IO (4 << 0) + #define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0) + #define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0) ++#define QSPI_IFR_WIDTH_OCT_OUTPUT (7 << 0) ++#define QSPI_IFR_WIDTH_OCT_IO (8 << 0) ++#define QSPI_IFR_WIDTH_OCT_CMD (9 << 0) + #define QSPI_IFR_INSTEN BIT(4) + #define QSPI_IFR_ADDREN BIT(5) + #define QSPI_IFR_OPTEN BIT(6) +@@ -117,19 +163,60 @@ + #define QSPI_IFR_OPTL_4BIT (2 << 8) + #define QSPI_IFR_OPTL_8BIT (3 << 8) + #define QSPI_IFR_ADDRL BIT(10) ++#define QSPI_IFR_ADDRL_SAMA7G5 GENMASK(11, 10) + #define QSPI_IFR_TFRTYP_MEM BIT(12) + #define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13) + #define QSPI_IFR_CRM BIT(14) ++#define QSPI_IFR_DDREN BIT(15) + #define QSPI_IFR_NBDUM_MASK GENMASK(20, 16) + #define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK) ++#define QSPI_IFR_END BIT(22) ++#define QSPI_IFR_SMRM BIT(23) + #define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */ ++#define QSPI_IFR_DQSEN BIT(25) ++#define QSPI_IFR_DDRCMDEN BIT(26) ++#define QSPI_IFR_HFWBEN BIT(27) ++#define QSPI_IFR_PROTTYP GENMASK(29, 28) ++#define QSPI_IFR_PROTTYP_STD_SPI 0 ++#define QSPI_IFR_PROTTYP_TWIN_QUAD 1 ++#define QSPI_IFR_PROTTYP_OCTAFLASH 2 ++#define QSPI_IFR_PROTTYP_HYPERFLASH 3 + + /* Bitfields in QSPI_SMR (Scrambling Mode Register) */ + #define QSPI_SMR_SCREN BIT(0) + #define QSPI_SMR_RVDIS BIT(1) ++#define QSPI_SMR_SCRKL BIT(2) ++ ++/* Bitfields in QSPI_REFRESH (Refresh Register) */ ++#define QSPI_REFRESH_DELAY_COUNTER GENMASK(31, 0) ++ ++/* Bitfields in QSPI_WRACNT (Write Access Counter Register) */ ++#define QSPI_WRACNT_NBWRA GENMASK(31, 0) ++ ++/* Bitfields in QSPI_DLLCFG (DLL Configuration Register) */ ++#define QSPI_DLLCFG_RANGE BIT(0) ++ ++/* Bitfields in QSPI_PCALCFG (DLL Pad Calibration Configuration Register) */ ++#define QSPI_PCALCFG_AAON BIT(0) ++#define QSPI_PCALCFG_DAPCAL BIT(1) ++#define QSPI_PCALCFG_DIFFPM BIT(2) ++#define QSPI_PCALCFG_CLKDIV GENMASK(6, 4) ++#define QSPI_PCALCFG_CALCNT GENMASK(16, 8) ++#define QSPI_PCALCFG_CALP GENMASK(27, 24) ++#define QSPI_PCALCFG_CALN GENMASK(31, 28) ++ ++/* Bitfields in QSPI_PCALBP (DLL Pad Calibration Bypass Register) */ ++#define QSPI_PCALBP_BPEN BIT(0) ++#define QSPI_PCALBP_CALPBP GENMASK(11, 8) ++#define QSPI_PCALBP_CALNBP GENMASK(19, 16) ++ ++/* Bitfields in QSPI_TOUT (Timeout Register) */ ++#define QSPI_TOUT_TCNTM GENMASK(15, 0) + + /* Bitfields in QSPI_WPMR (Write Protection Mode Register) */ + #define QSPI_WPMR_WPEN BIT(0) ++#define QSPI_WPMR_WPITEN BIT(1) ++#define QSPI_WPMR_WPCREN BIT(2) + #define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8) + #define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK) + +@@ -139,10 +226,42 @@ + #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC) + + #define ATMEL_QSPI_TIMEOUT 1000 /* ms */ ++#define ATMEL_QSPI_SYNC_TIMEOUT 300 /* ms */ ++#define QSPI_DLLCFG_THRESHOLD_FREQ 90000000U ++#define QSPI_CALIB_TIME 2000 /* 2 us */ ++ ++/* Use PIO for small transfers. */ ++#define ATMEL_QSPI_DMA_MIN_BYTES 16 ++/** ++ * struct atmel_qspi_pcal - Pad Calibration Clock Division ++ * @pclk_rate: peripheral clock rate. ++ * @pclkdiv: calibration clock division. The clock applied to the calibration ++ * cell is divided by pclkdiv + 1. ++ */ ++struct atmel_qspi_pcal { ++ u32 pclk_rate; ++ u8 pclk_div; ++}; ++ ++#define ATMEL_QSPI_PCAL_ARRAY_SIZE 8 ++static const struct atmel_qspi_pcal pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE] = { ++ {25000000, 0}, ++ {50000000, 1}, ++ {75000000, 2}, ++ {100000000, 3}, ++ {125000000, 4}, ++ {150000000, 5}, ++ {175000000, 6}, ++ {200000000, 7}, ++}; + + struct atmel_qspi_caps { ++ u32 max_speed_hz; + bool has_qspick; ++ bool has_gclk; + bool has_ricr; ++ bool octal; ++ bool has_dma; + }; + + struct atmel_qspi_ops; +@@ -152,6 +271,7 @@ struct atmel_qspi { + void __iomem *mem; + struct clk *pclk; + struct clk *qspick; ++ struct clk *gclk; + struct platform_device *pdev; + const struct atmel_qspi_caps *caps; + const struct atmel_qspi_ops *ops; +@@ -160,7 +280,12 @@ struct atmel_qspi { + u32 irq_mask; + u32 mr; + u32 scr; ++ u32 slave_max_speed_hz; + struct completion cmd_completion; ++ struct completion dma_completion; ++ dma_addr_t mmap_phys_base; ++ struct dma_chan *rx_chan; ++ struct dma_chan *tx_chan; + }; + + struct atmel_qspi_ops { +@@ -187,6 +312,19 @@ static const struct atmel_qspi_mode atme + { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, + }; + ++static const struct atmel_qspi_mode atmel_qspi_sama7g5_modes[] = { ++ { 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI }, ++ { 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT }, ++ { 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT }, ++ { 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO }, ++ { 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO }, ++ { 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD }, ++ { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD }, ++ { 1, 1, 8, QSPI_IFR_WIDTH_OCT_OUTPUT }, ++ { 1, 8, 8, QSPI_IFR_WIDTH_OCT_IO }, ++ { 8, 8, 8, QSPI_IFR_WIDTH_OCT_CMD }, ++}; ++ + #ifdef VERBOSE_DEBUG + static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz) + { +@@ -209,6 +347,8 @@ static const char *atmel_qspi_reg_name(u + return "IMR"; + case QSPI_SCR: + return "SCR"; ++ case QSPI_SR2: ++ return "SR2"; + case QSPI_IAR: + return "IAR"; + case QSPI_ICR: +@@ -221,6 +361,18 @@ static const char *atmel_qspi_reg_name(u + return "SMR"; + case QSPI_SKR: + return "SKR"; ++ case QSPI_REFRESH: ++ return "REFRESH"; ++ case QSPI_WRACNT: ++ return "WRACNT"; ++ case QSPI_DLLCFG: ++ return "DLLCFG"; ++ case QSPI_PCALCFG: ++ return "PCALCFG"; ++ case QSPI_PCALBP: ++ return "PCALBP"; ++ case QSPI_TOUT: ++ return "TOUT"; + case QSPI_WPMR: + return "WPMR"; + case QSPI_WPSR: +@@ -288,12 +440,31 @@ static int atmel_qspi_find_mode(const st + return -EOPNOTSUPP; + } + ++static int atmel_qspi_sama7g5_find_mode(const struct spi_mem_op *op) ++{ ++ u32 i; ++ ++ for (i = 0; i < ARRAY_SIZE(atmel_qspi_sama7g5_modes); i++) ++ if (atmel_qspi_is_compatible(op, &atmel_qspi_sama7g5_modes[i])) ++ return i; ++ ++ return -EOPNOTSUPP; ++} ++ + static bool atmel_qspi_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) + { ++ struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller); + if (!spi_mem_default_supports_op(mem, op)) + return false; + ++ if (aq->caps->octal) { ++ if (atmel_qspi_sama7g5_find_mode(op) < 0) ++ return false; ++ else ++ return true; ++ } ++ + if (atmel_qspi_find_mode(op) < 0) + return false; + +@@ -474,6 +645,296 @@ static int atmel_qspi_transfer(struct sp + return atmel_qspi_wait_for_completion(aq, QSPI_SR_CMD_COMPLETED); + } + ++static int atmel_qspi_reg_sync(struct atmel_qspi *aq) ++{ ++ u32 val; ++ int ret; ++ ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_SYNCBSY), 40, ++ ATMEL_QSPI_SYNC_TIMEOUT); ++ return ret; ++} ++ ++static int atmel_qspi_update_config(struct atmel_qspi *aq) ++{ ++ int ret; ++ ++ ret = atmel_qspi_reg_sync(aq); ++ if (ret) ++ return ret; ++ atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); ++ return atmel_qspi_reg_sync(aq); ++} ++ ++static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, ++ const struct spi_mem_op *op, u32 *offset) ++{ ++ u32 iar, icr, ifr; ++ int mode, ret; ++ ++ iar = 0; ++ icr = FIELD_PREP(QSPI_ICR_INST_MASK_SAMA7G5, op->cmd.opcode); ++ ifr = QSPI_IFR_INSTEN; ++ ++ mode = atmel_qspi_sama7g5_find_mode(op); ++ if (mode < 0) ++ return mode; ++ ifr |= atmel_qspi_sama7g5_modes[mode].config; ++ ++ if (op->dummy.buswidth && op->dummy.nbytes) { ++ if (op->addr.dtr && op->dummy.dtr && op->data.dtr) ++ ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 / ++ (2 * op->dummy.buswidth)); ++ else ++ ifr |= QSPI_IFR_NBDUM(op->dummy.nbytes * 8 / ++ op->dummy.buswidth); ++ } ++ ++ if (op->addr.buswidth && op->addr.nbytes) { ++ ifr |= FIELD_PREP(QSPI_IFR_ADDRL_SAMA7G5, op->addr.nbytes - 1) | ++ QSPI_IFR_ADDREN; ++ iar = FIELD_PREP(QSPI_IAR_ADDR, op->addr.val); ++ } ++ ++ if (op->addr.dtr && op->dummy.dtr && op->data.dtr) { ++ ifr |= QSPI_IFR_DDREN; ++ if (op->cmd.dtr) ++ ifr |= QSPI_IFR_DDRCMDEN; ++ ++ ifr |= QSPI_IFR_DQSEN; ++ } ++ ++ if (op->cmd.buswidth == 8 || op->addr.buswidth == 8 || ++ op->data.buswidth == 8) ++ ifr |= FIELD_PREP(QSPI_IFR_PROTTYP, QSPI_IFR_PROTTYP_OCTAFLASH); ++ ++ /* offset of the data access in the QSPI memory space */ ++ *offset = iar; ++ ++ /* Set data enable */ ++ if (op->data.nbytes) { ++ ifr |= QSPI_IFR_DATAEN; ++ ++ if (op->addr.nbytes) ++ ifr |= QSPI_IFR_TFRTYP_MEM; ++ } ++ ++ /* ++ * If the QSPI controller is set in regular SPI mode, set it in ++ * Serial Memory Mode (SMM). ++ */ ++ if (aq->mr != QSPI_MR_SMM) { ++ atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); ++ aq->mr = QSPI_MR_SMM; ++ ++ ret = atmel_qspi_update_config(aq); ++ if (ret) ++ return ret; ++ } ++ ++ /* Clear pending interrupts */ ++ (void)atmel_qspi_read(aq, QSPI_SR); ++ ++ /* Set QSPI Instruction Frame registers */ ++ if (op->addr.nbytes && !op->data.nbytes) ++ atmel_qspi_write(iar, aq, QSPI_IAR); ++ ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ atmel_qspi_write(icr, aq, QSPI_RICR); ++ } else { ++ atmel_qspi_write(icr, aq, QSPI_WICR); ++ if (op->data.nbytes) ++ atmel_qspi_write(FIELD_PREP(QSPI_WRACNT_NBWRA, ++ op->data.nbytes), ++ aq, QSPI_WRACNT); ++ } ++ ++ atmel_qspi_write(ifr, aq, QSPI_IFR); ++ ++ return atmel_qspi_update_config(aq); ++} ++ ++static void atmel_qspi_dma_callback(void *param) ++{ ++ struct atmel_qspi *aq = param; ++ ++ complete(&aq->dma_completion); ++} ++ ++static int atmel_qspi_dma_xfer(struct atmel_qspi *aq, struct dma_chan *chan, ++ dma_addr_t dma_dst, dma_addr_t dma_src, ++ unsigned int len) ++{ ++ struct dma_async_tx_descriptor *tx; ++ dma_cookie_t cookie; ++ int ret; ++ ++ tx = dmaengine_prep_dma_memcpy(chan, dma_dst, dma_src, len, ++ DMA_PREP_INTERRUPT | DMA_CTRL_ACK); ++ if (!tx) { ++ dev_err(&aq->pdev->dev, "device_prep_dma_memcpy error\n"); ++ return -EIO; ++ } ++ ++ reinit_completion(&aq->dma_completion); ++ tx->callback = atmel_qspi_dma_callback; ++ tx->callback_param = aq; ++ cookie = tx->tx_submit(tx); ++ ret = dma_submit_error(cookie); ++ if (ret) { ++ dev_err(&aq->pdev->dev, "dma_submit_error %d\n", cookie); ++ return ret; ++ } ++ ++ dma_async_issue_pending(chan); ++ ret = wait_for_completion_timeout(&aq->dma_completion, ++ msecs_to_jiffies(20 * ATMEL_QSPI_TIMEOUT)); ++ if (ret == 0) { ++ dmaengine_terminate_sync(chan); ++ dev_err(&aq->pdev->dev, "DMA wait_for_completion_timeout\n"); ++ return -ETIMEDOUT; ++ } ++ ++ return 0; ++} ++ ++static int atmel_qspi_dma_rx_xfer(struct spi_mem *mem, ++ const struct spi_mem_op *op, ++ struct sg_table *sgt, loff_t loff) ++{ ++ struct atmel_qspi *aq = ++ spi_controller_get_devdata(mem->spi->controller); ++ struct scatterlist *sg; ++ dma_addr_t dma_src; ++ unsigned int i, len; ++ int ret; ++ ++ dma_src = aq->mmap_phys_base + loff; ++ ++ for_each_sg(sgt->sgl, sg, sgt->nents, i) { ++ len = sg_dma_len(sg); ++ ret = atmel_qspi_dma_xfer(aq, aq->rx_chan, sg_dma_address(sg), ++ dma_src, len); ++ if (ret) ++ return ret; ++ dma_src += len; ++ } ++ ++ return 0; ++} ++ ++static int atmel_qspi_dma_tx_xfer(struct spi_mem *mem, ++ const struct spi_mem_op *op, ++ struct sg_table *sgt, loff_t loff) ++{ ++ struct atmel_qspi *aq = ++ spi_controller_get_devdata(mem->spi->controller); ++ struct scatterlist *sg; ++ dma_addr_t dma_dst; ++ unsigned int i, len; ++ int ret; ++ ++ dma_dst = aq->mmap_phys_base + loff; ++ ++ for_each_sg(sgt->sgl, sg, sgt->nents, i) { ++ len = sg_dma_len(sg); ++ ret = atmel_qspi_dma_xfer(aq, aq->tx_chan, dma_dst, ++ sg_dma_address(sg), len); ++ if (ret) ++ return ret; ++ dma_dst += len; ++ } ++ ++ return 0; ++} ++ ++static int atmel_qspi_dma_transfer(struct spi_mem *mem, ++ const struct spi_mem_op *op, loff_t loff) ++{ ++ struct sg_table sgt; ++ int ret; ++ ++ ret = spi_controller_dma_map_mem_op_data(mem->spi->controller, op, ++ &sgt); ++ if (ret) ++ return ret; ++ ++ if (op->data.dir == SPI_MEM_DATA_IN) ++ ret = atmel_qspi_dma_rx_xfer(mem, op, &sgt, loff); ++ else ++ ret = atmel_qspi_dma_tx_xfer(mem, op, &sgt, loff); ++ ++ spi_controller_dma_unmap_mem_op_data(mem->spi->controller, op, &sgt); ++ ++ return ret; ++} ++ ++static int atmel_qspi_sama7g5_transfer(struct spi_mem *mem, ++ const struct spi_mem_op *op, u32 offset) ++{ ++ struct atmel_qspi *aq = ++ spi_controller_get_devdata(mem->spi->controller); ++ u32 val; ++ int ret; ++ ++ if (!op->data.nbytes) { ++ /* Start the transfer. */ ++ ret = atmel_qspi_reg_sync(aq); ++ if (ret) ++ return ret; ++ atmel_qspi_write(QSPI_CR_STTFR, aq, QSPI_CR); ++ ++ return atmel_qspi_wait_for_completion(aq, QSPI_SR_CSRA); ++ } ++ ++ /* Send/Receive data. */ ++ if (op->data.dir == SPI_MEM_DATA_IN) { ++ if (aq->rx_chan && op->addr.nbytes && ++ op->data.nbytes > ATMEL_QSPI_DMA_MIN_BYTES) { ++ ret = atmel_qspi_dma_transfer(mem, op, offset); ++ if (ret) ++ return ret; ++ } else { ++ memcpy_fromio(op->data.buf.in, aq->mem + offset, ++ op->data.nbytes); ++ } ++ ++ if (op->addr.nbytes) { ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_RBUSY), 40, ++ ATMEL_QSPI_SYNC_TIMEOUT); ++ if (ret) ++ return ret; ++ } ++ } else { ++ if (aq->tx_chan && op->addr.nbytes && ++ op->data.nbytes > ATMEL_QSPI_DMA_MIN_BYTES) { ++ ret = atmel_qspi_dma_transfer(mem, op, offset); ++ if (ret) ++ return ret; ++ } else { ++ memcpy_toio(aq->mem + offset, op->data.buf.out, ++ op->data.nbytes); ++ } ++ ++ ret = atmel_qspi_wait_for_completion(aq, QSPI_SR_LWRA); ++ if (ret) ++ return ret; ++ } ++ ++ /* Release the chip-select. */ ++ ret = atmel_qspi_reg_sync(aq); ++ if (ret) { ++ pm_runtime_mark_last_busy(&aq->pdev->dev); ++ pm_runtime_put_autosuspend(&aq->pdev->dev); ++ return ret; ++ } ++ atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); ++ ++ return atmel_qspi_wait_for_completion(aq, QSPI_SR_CSRA); ++} ++ + static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) + { + struct atmel_qspi *aq = spi_controller_get_devdata(mem->spi->controller); +@@ -518,6 +979,160 @@ static const struct spi_controller_mem_o + .get_name = atmel_qspi_get_name + }; + ++static int atmel_qspi_set_pad_calibration(struct atmel_qspi *aq) ++{ ++ unsigned long pclk_rate; ++ u32 status, val; ++ int i, ret; ++ u8 pclk_div = 0; ++ ++ pclk_rate = clk_get_rate(aq->pclk); ++ if (!pclk_rate) ++ return -EINVAL; ++ ++ for (i = 0; i < ATMEL_QSPI_PCAL_ARRAY_SIZE; i++) { ++ if (pclk_rate <= pcal[i].pclk_rate) { ++ pclk_div = pcal[i].pclk_div; ++ break; ++ } ++ } ++ ++ /* ++ * Use the biggest divider in case the peripheral clock exceeds ++ * 200MHZ. ++ */ ++ if (pclk_rate > pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_rate) ++ pclk_div = pcal[ATMEL_QSPI_PCAL_ARRAY_SIZE - 1].pclk_div; ++ ++ /* Disable QSPI while configuring the pad calibration. */ ++ status = atmel_qspi_read(aq, QSPI_SR2); ++ if (status & QSPI_SR2_QSPIENS) { ++ ret = atmel_qspi_reg_sync(aq); ++ if (ret) ++ return ret; ++ atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); ++ } ++ ++ /* ++ * The analog circuitry is not shut down at the end of the calibration ++ * and the start-up time is only required for the first calibration ++ * sequence, thus increasing performance. Set the delay between the Pad ++ * calibration analog circuitry and the calibration request to 2us. ++ */ ++ atmel_qspi_write(QSPI_PCALCFG_AAON | ++ FIELD_PREP(QSPI_PCALCFG_CLKDIV, pclk_div) | ++ FIELD_PREP(QSPI_PCALCFG_CALCNT, ++ 2 * (pclk_rate / 1000000)), ++ aq, QSPI_PCALCFG); ++ ++ /* DLL On + start calibration. */ ++ atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); ++ ++ /* Check synchronization status before updating configuration. */ ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ (val & QSPI_SR2_DLOCK) && ++ !(val & QSPI_SR2_CALBSY), 40, ++ ATMEL_QSPI_TIMEOUT); ++ ++ /* Refresh analogic blocks every 1 ms.*/ ++ atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, ++ aq->slave_max_speed_hz / 1000), ++ aq, QSPI_REFRESH); ++ ++ return ret; ++} ++ ++static int atmel_qspi_set_gclk(struct atmel_qspi *aq) ++{ ++ u32 status, val; ++ int ret; ++ ++ /* Disable DLL before setting GCLK */ ++ status = atmel_qspi_read(aq, QSPI_SR2); ++ if (status & QSPI_SR2_DLOCK) { ++ atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); ++ ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_DLOCK), 40, ++ ATMEL_QSPI_TIMEOUT); ++ if (ret) ++ return ret; ++ } ++ ++ if (aq->slave_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) ++ atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); ++ else ++ atmel_qspi_write(0, aq, QSPI_DLLCFG); ++ ++ ret = clk_set_rate(aq->gclk, aq->slave_max_speed_hz); ++ if (ret) { ++ dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n"); ++ return ret; ++ } ++ ++ /* Enable the QSPI generic clock */ ++ ret = clk_prepare_enable(aq->gclk); ++ if (ret) ++ dev_err(&aq->pdev->dev, "Failed to enable generic clock.\n"); ++ ++ return ret; ++} ++ ++static int atmel_qspi_sama7g5_init(struct atmel_qspi *aq) ++{ ++ u32 val; ++ int ret; ++ ++ ret = atmel_qspi_set_gclk(aq); ++ if (ret) ++ return ret; ++ ++ if (aq->caps->octal) { ++ ret = atmel_qspi_set_pad_calibration(aq); ++ if (ret) ++ return ret; ++ } else { ++ atmel_qspi_write(QSPI_CR_DLLON, aq, QSPI_CR); ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ (val & QSPI_SR2_DLOCK), 40, ++ ATMEL_QSPI_TIMEOUT); ++ } ++ ++ /* Set the QSPI controller by default in Serial Memory Mode */ ++ atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); ++ aq->mr = QSPI_MR_SMM; ++ ret = atmel_qspi_update_config(aq); ++ if (ret) ++ return ret; ++ ++ /* Enable the QSPI controller. */ ++ atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ val & QSPI_SR2_QSPIENS, 40, ++ ATMEL_QSPI_SYNC_TIMEOUT); ++ if (ret) ++ return ret; ++ ++ if (aq->caps->octal) { ++ ret = readl_poll_timeout(aq->regs + QSPI_SR, val, ++ val & QSPI_SR_RFRSHD, 40, ++ ATMEL_QSPI_TIMEOUT); ++ } ++ ++ atmel_qspi_write(QSPI_TOUT_TCNTM, aq, QSPI_TOUT); ++ return ret; ++} ++ ++static int atmel_qspi_sama7g5_setup(struct spi_device *spi) ++{ ++ struct atmel_qspi *aq = spi_controller_get_devdata(spi->controller); ++ ++ /* The controller can communicate with a single slave. */ ++ aq->slave_max_speed_hz = spi->max_speed_hz; ++ ++ return atmel_qspi_sama7g5_init(aq); ++} ++ + static int atmel_qspi_setup(struct spi_device *spi) + { + struct spi_controller *ctrl = spi->controller; +@@ -532,6 +1147,9 @@ static int atmel_qspi_setup(struct spi_d + if (!spi->max_speed_hz) + return -EINVAL; + ++ if (aq->caps->has_gclk) ++ return atmel_qspi_sama7g5_setup(spi); ++ + src_rate = clk_get_rate(aq->pclk); + if (!src_rate) + return -EINVAL; +@@ -589,8 +1207,18 @@ static int atmel_qspi_set_cs_timing(stru + return 0; + } + +-static void atmel_qspi_init(struct atmel_qspi *aq) ++static int atmel_qspi_init(struct atmel_qspi *aq) + { ++ int ret; ++ ++ if (aq->caps->has_gclk) { ++ ret = atmel_qspi_reg_sync(aq); ++ if (ret) ++ return ret; ++ atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); ++ return 0; ++ } ++ + /* Reset the QSPI controller */ + atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); + +@@ -600,6 +1228,7 @@ static void atmel_qspi_init(struct atmel + + /* Enable the QSPI controller */ + atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); ++ return 0; + } + + static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id) +@@ -621,11 +1250,59 @@ static irqreturn_t atmel_qspi_interrupt( + return IRQ_HANDLED; + } + ++static int atmel_qspi_dma_init(struct spi_controller *ctrl) ++{ ++ struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); ++ int ret; ++ ++ aq->rx_chan = dma_request_chan(&aq->pdev->dev, "rx"); ++ if (IS_ERR(aq->rx_chan)) { ++ aq->rx_chan = NULL; ++ return dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan), ++ "RX DMA channel is not available\n"); ++ } ++ ++ aq->tx_chan = dma_request_chan(&aq->pdev->dev, "tx"); ++ if (IS_ERR(aq->tx_chan)) { ++ ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->tx_chan), ++ "TX DMA channel is not available\n"); ++ goto release_rx_chan; ++ } ++ ++ ctrl->dma_rx = aq->rx_chan; ++ ctrl->dma_tx = aq->tx_chan; ++ init_completion(&aq->dma_completion); ++ ++ dev_info(&aq->pdev->dev, "Using %s (tx) and %s (rx) for DMA transfers\n", ++ dma_chan_name(aq->tx_chan), dma_chan_name(aq->rx_chan)); ++ ++ return 0; ++ ++release_rx_chan: ++ dma_release_channel(aq->rx_chan); ++ aq->rx_chan = NULL; ++ aq->tx_chan = NULL; ++ return ret; ++} ++ ++static void atmel_qspi_dma_release(struct atmel_qspi *aq) ++{ ++ if (aq->rx_chan) ++ dma_release_channel(aq->rx_chan); ++ if (aq->tx_chan) ++ dma_release_channel(aq->tx_chan); ++} ++ + static const struct atmel_qspi_ops atmel_qspi_ops = { + .set_cfg = atmel_qspi_set_cfg, + .transfer = atmel_qspi_transfer, + }; + ++static const struct atmel_qspi_ops atmel_qspi_sama7g5_ops = { ++ .set_cfg = atmel_qspi_sama7g5_set_cfg, ++ .transfer = atmel_qspi_sama7g5_transfer, ++}; ++ + static int atmel_qspi_probe(struct platform_device *pdev) + { + struct spi_controller *ctrl; +@@ -637,7 +1314,27 @@ static int atmel_qspi_probe(struct platf + if (!ctrl) + return -ENOMEM; + ++ aq = spi_controller_get_devdata(ctrl); ++ ++ aq->caps = of_device_get_match_data(&pdev->dev); ++ if (!aq->caps) { ++ dev_err(&pdev->dev, "Could not retrieve QSPI caps\n"); ++ return -EINVAL; ++ } ++ ++ init_completion(&aq->cmd_completion); ++ aq->pdev = pdev; ++ + ctrl->mode_bits = SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ++ if (aq->caps->octal) ++ ctrl->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; ++ ++ if (aq->caps->has_gclk) ++ aq->ops = &atmel_qspi_sama7g5_ops; ++ else ++ aq->ops = &atmel_qspi_ops; ++ ++ ctrl->max_speed_hz = aq->caps->max_speed_hz; + ctrl->setup = atmel_qspi_setup; + ctrl->set_cs_timing = atmel_qspi_set_cs_timing; + ctrl->bus_num = -1; +@@ -646,12 +1343,6 @@ static int atmel_qspi_probe(struct platf + ctrl->dev.of_node = pdev->dev.of_node; + platform_set_drvdata(pdev, ctrl); + +- aq = spi_controller_get_devdata(ctrl); +- +- init_completion(&aq->cmd_completion); +- aq->pdev = pdev; +- aq->ops = &atmel_qspi_ops; +- + /* Map the registers */ + aq->regs = devm_platform_ioremap_resource_byname(pdev, "qspi_base"); + if (IS_ERR(aq->regs)) +@@ -666,6 +1357,7 @@ static int atmel_qspi_probe(struct platf + "missing AHB memory\n"); + + aq->mmap_size = resource_size(res); ++ aq->mmap_phys_base = (dma_addr_t)res->start; + + /* Get the peripheral clock */ + aq->pclk = devm_clk_get(&pdev->dev, "pclk"); +@@ -682,13 +1374,6 @@ static int atmel_qspi_probe(struct platf + return dev_err_probe(&pdev->dev, err, + "failed to enable the peripheral clock\n"); + +- aq->caps = of_device_get_match_data(&pdev->dev); +- if (!aq->caps) { +- dev_err(&pdev->dev, "Could not retrieve QSPI caps\n"); +- err = -EINVAL; +- goto disable_pclk; +- } +- + if (aq->caps->has_qspick) { + /* Get the QSPI system clock */ + aq->qspick = devm_clk_get(&pdev->dev, "qspick"); +@@ -705,18 +1390,32 @@ static int atmel_qspi_probe(struct platf + "failed to enable the QSPI system clock\n"); + goto disable_pclk; + } ++ } else if (aq->caps->has_gclk) { ++ /* Get the QSPI generic clock */ ++ aq->gclk = devm_clk_get(&pdev->dev, "gclk"); ++ if (IS_ERR(aq->gclk)) { ++ dev_err(&pdev->dev, "missing Generic clock\n"); ++ err = PTR_ERR(aq->gclk); ++ goto disable_pclk; ++ } ++ } ++ ++ if (aq->caps->has_dma) { ++ err = atmel_qspi_dma_init(ctrl); ++ if (err == -EPROBE_DEFER) ++ goto disable_qspick; + } + + /* Request the IRQ */ + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + err = irq; +- goto disable_qspick; ++ goto dma_release; + } + err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt, + 0, dev_name(&pdev->dev), aq); + if (err) +- goto disable_qspick; ++ goto dma_release; + + pm_runtime_set_autosuspend_delay(&pdev->dev, 500); + pm_runtime_use_autosuspend(&pdev->dev); +@@ -724,7 +1423,9 @@ static int atmel_qspi_probe(struct platf + pm_runtime_enable(&pdev->dev); + pm_runtime_get_noresume(&pdev->dev); + +- atmel_qspi_init(aq); ++ err = atmel_qspi_init(aq); ++ if (err) ++ goto dma_release; + + err = spi_register_controller(ctrl); + if (err) { +@@ -732,13 +1433,16 @@ static int atmel_qspi_probe(struct platf + pm_runtime_disable(&pdev->dev); + pm_runtime_set_suspended(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); +- goto disable_qspick; ++ goto dma_release; + } + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; + ++dma_release: ++ if (aq->caps->has_dma) ++ atmel_qspi_dma_release(aq); + disable_qspick: + clk_disable_unprepare(aq->qspick); + disable_pclk: +@@ -747,6 +1451,44 @@ disable_pclk: + return err; + } + ++static int atmel_qspi_sama7g5_suspend(struct atmel_qspi *aq) ++{ ++ int ret; ++ u32 val; ++ ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_RBUSY) && ++ (val & QSPI_SR2_HIDLE), 40, ++ ATMEL_QSPI_SYNC_TIMEOUT); ++ if (ret) ++ return ret; ++ ++ atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_QSPIENS), 40, ++ ATMEL_QSPI_SYNC_TIMEOUT); ++ if (ret) ++ return ret; ++ ++ clk_disable_unprepare(aq->gclk); ++ ++ atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_DLOCK), 40, ++ ATMEL_QSPI_TIMEOUT); ++ if (ret) ++ return ret; ++ ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_CALBSY), 40, ++ ATMEL_QSPI_TIMEOUT); ++ if (ret) ++ return ret; ++ ++ clk_disable_unprepare(aq->pclk); ++ return 0; ++} ++ + static void atmel_qspi_remove(struct platform_device *pdev) + { + struct spi_controller *ctrl = platform_get_drvdata(pdev); +@@ -757,6 +1499,16 @@ static void atmel_qspi_remove(struct pla + + ret = pm_runtime_get_sync(&pdev->dev); + if (ret >= 0) { ++ if (aq->caps->has_dma) ++ atmel_qspi_dma_release(aq); ++ ++ if (aq->caps->has_gclk) { ++ ret = atmel_qspi_sama7g5_suspend(aq); ++ if (ret) ++ dev_warn(&pdev->dev, "Failed to de-init device on remove: %d\n", ret); ++ return; ++ } ++ + atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); + clk_disable(aq->qspick); + clk_disable(aq->pclk); +@@ -787,6 +1539,9 @@ static int __maybe_unused atmel_qspi_sus + if (ret < 0) + return ret; + ++ if (aq->caps->has_gclk) ++ return atmel_qspi_sama7g5_suspend(aq); ++ + atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); + + pm_runtime_mark_last_busy(dev); +@@ -814,6 +1569,9 @@ static int __maybe_unused atmel_qspi_res + return ret; + } + ++ if (aq->caps->has_gclk) ++ return atmel_qspi_sama7g5_init(aq); ++ + ret = pm_runtime_force_resume(dev); + if (ret < 0) + return ret; +@@ -869,6 +1627,19 @@ static const struct atmel_qspi_caps atme + .has_ricr = true, + }; + ++static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = { ++ .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, ++ .has_gclk = true, ++ .octal = true, ++ .has_dma = true, ++}; ++ ++static const struct atmel_qspi_caps atmel_sama7g5_qspi_caps = { ++ .max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, ++ .has_gclk = true, ++ .has_dma = true, ++}; ++ + static const struct of_device_id atmel_qspi_dt_ids[] = { + { + .compatible = "atmel,sama5d2-qspi", +@@ -878,6 +1649,15 @@ static const struct of_device_id atmel_q + .compatible = "microchip,sam9x60-qspi", + .data = &atmel_sam9x60_qspi_caps, + }, ++ { ++ .compatible = "microchip,sama7g5-ospi", ++ .data = &atmel_sama7g5_ospi_caps, ++ }, ++ { ++ .compatible = "microchip,sama7g5-qspi", ++ .data = &atmel_sama7g5_qspi_caps, ++ }, ++ + { /* sentinel */ } + }; + diff --git a/target/linux/microchipsw/patches-6.12/0079-v6.14-spi-atmel-quadspi-Factor-out-switching-to-Serial-Mem.patch b/target/linux/microchipsw/patches-6.12/0079-v6.14-spi-atmel-quadspi-Factor-out-switching-to-Serial-Mem.patch new file mode 100644 index 0000000000..f13641e1ce --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0079-v6.14-spi-atmel-quadspi-Factor-out-switching-to-Serial-Mem.patch @@ -0,0 +1,181 @@ +From 36087601ba5fed2fe42134bf59f6ba75029fd7f7 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= +Date: Wed, 18 Dec 2024 16:17:54 +0100 +Subject: [PATCH 099/112] spi: atmel-quadspi: Factor out switching to Serial + Memory Mode to function +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +SAMA7G5 support (that was forward-ported from v6.1) re-introduced +a bug that was fixed in v6.12, thankfully only in the codepath of +the new SoC. But to prevent similar mistakes in the future, we +split out the offending code to a function, and use this, fixed +version everywhere. + +To facilitate this, support function `atmel_qspi_update_config()` +also had to be moved upwards. For best viewing experience, use +`--color-moved-ws="allow-indentation-change" --color-moved`. + +Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") +Reported-by: Alexander Dahl +Closes: https://lore.kernel.org/linux-spi/20241218-appliance-jaws-90773405977a@thorsis.com/ +Signed-off-by: Bence Csókás +Link: https://patch.msgid.link/20241218151754.365519-1-csokas.bence@prolan.hu +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 101 +++++++++++++++++++----------------- + 1 file changed, 53 insertions(+), 48 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -414,6 +414,28 @@ static void atmel_qspi_write(u32 value, + writel_relaxed(value, aq->regs + offset); + } + ++static int atmel_qspi_reg_sync(struct atmel_qspi *aq) ++{ ++ u32 val; ++ int ret; ++ ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_SYNCBSY), 40, ++ ATMEL_QSPI_SYNC_TIMEOUT); ++ return ret; ++} ++ ++static int atmel_qspi_update_config(struct atmel_qspi *aq) ++{ ++ int ret; ++ ++ ret = atmel_qspi_reg_sync(aq); ++ if (ret) ++ return ret; ++ atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); ++ return atmel_qspi_reg_sync(aq); ++} ++ + static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op, + const struct atmel_qspi_mode *mode) + { +@@ -476,6 +498,25 @@ static bool atmel_qspi_supports_op(struc + return true; + } + ++/* ++ * If the QSPI controller is set in regular SPI mode, set it in ++ * Serial Memory Mode (SMM). ++ */ ++static int atmel_qspi_set_serial_memory_mode(struct atmel_qspi *aq) ++{ ++ int ret = 0; ++ ++ if (!(aq->mr & QSPI_MR_SMM)) { ++ aq->mr |= QSPI_MR_SMM; ++ atmel_qspi_write(aq->mr, aq, QSPI_MR); ++ ++ if (aq->caps->has_gclk) ++ ret = atmel_qspi_update_config(aq); ++ } ++ ++ return ret; ++} ++ + static int atmel_qspi_set_cfg(struct atmel_qspi *aq, + const struct spi_mem_op *op, u32 *offset) + { +@@ -555,14 +596,9 @@ static int atmel_qspi_set_cfg(struct atm + ifr |= QSPI_IFR_TFRTYP_MEM; + } + +- /* +- * If the QSPI controller is set in regular SPI mode, set it in +- * Serial Memory Mode (SMM). +- */ +- if (!(aq->mr & QSPI_MR_SMM)) { +- aq->mr |= QSPI_MR_SMM; +- atmel_qspi_write(aq->mr, aq, QSPI_MR); +- } ++ mode = atmel_qspi_set_serial_memory_mode(aq); ++ if (mode < 0) ++ return mode; + + /* Clear pending interrupts */ + (void)atmel_qspi_read(aq, QSPI_SR); +@@ -645,28 +681,6 @@ static int atmel_qspi_transfer(struct sp + return atmel_qspi_wait_for_completion(aq, QSPI_SR_CMD_COMPLETED); + } + +-static int atmel_qspi_reg_sync(struct atmel_qspi *aq) +-{ +- u32 val; +- int ret; +- +- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, +- !(val & QSPI_SR2_SYNCBSY), 40, +- ATMEL_QSPI_SYNC_TIMEOUT); +- return ret; +-} +- +-static int atmel_qspi_update_config(struct atmel_qspi *aq) +-{ +- int ret; +- +- ret = atmel_qspi_reg_sync(aq); +- if (ret) +- return ret; +- atmel_qspi_write(QSPI_CR_UPDCFG, aq, QSPI_CR); +- return atmel_qspi_reg_sync(aq); +-} +- + static int atmel_qspi_sama7g5_set_cfg(struct atmel_qspi *aq, + const struct spi_mem_op *op, u32 *offset) + { +@@ -720,18 +734,9 @@ static int atmel_qspi_sama7g5_set_cfg(st + ifr |= QSPI_IFR_TFRTYP_MEM; + } + +- /* +- * If the QSPI controller is set in regular SPI mode, set it in +- * Serial Memory Mode (SMM). +- */ +- if (aq->mr != QSPI_MR_SMM) { +- atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); +- aq->mr = QSPI_MR_SMM; +- +- ret = atmel_qspi_update_config(aq); +- if (ret) +- return ret; +- } ++ ret = atmel_qspi_set_serial_memory_mode(aq); ++ if (ret < 0) ++ return ret; + + /* Clear pending interrupts */ + (void)atmel_qspi_read(aq, QSPI_SR); +@@ -1099,10 +1104,9 @@ static int atmel_qspi_sama7g5_init(struc + } + + /* Set the QSPI controller by default in Serial Memory Mode */ +- atmel_qspi_write(QSPI_MR_SMM | QSPI_MR_DQSDLYEN, aq, QSPI_MR); +- aq->mr = QSPI_MR_SMM; +- ret = atmel_qspi_update_config(aq); +- if (ret) ++ aq->mr |= QSPI_MR_DQSDLYEN; ++ ret = atmel_qspi_set_serial_memory_mode(aq); ++ if (ret < 0) + return ret; + + /* Enable the QSPI controller. */ +@@ -1223,8 +1227,9 @@ static int atmel_qspi_init(struct atmel_ + atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR); + + /* Set the QSPI controller by default in Serial Memory Mode */ +- aq->mr |= QSPI_MR_SMM; +- atmel_qspi_write(aq->mr, aq, QSPI_MR); ++ ret = atmel_qspi_set_serial_memory_mode(aq); ++ if (ret < 0) ++ return ret; + + /* Enable the QSPI controller */ + atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR); diff --git a/target/linux/microchipsw/patches-6.12/0080-v6.14-spi-atmel-quadspi-Use-devm_-clock-management.patch b/target/linux/microchipsw/patches-6.12/0080-v6.14-spi-atmel-quadspi-Use-devm_-clock-management.patch new file mode 100644 index 0000000000..d84361567f --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0080-v6.14-spi-atmel-quadspi-Use-devm_-clock-management.patch @@ -0,0 +1,131 @@ +From 7c8bec1bb999e6f44e326fdf7157d5e37b748aca Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= +Date: Thu, 19 Dec 2024 15:28:51 +0100 +Subject: [PATCH 100/112] spi: atmel-quadspi: Use devm_ clock management +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Clean up error handling by using the new devm_ +clock handling functions. This should make it +easier to add new code, as we can eliminate the +"goto ladder" in probe(). + +Signed-off-by: Bence Csókás +Link: https://patch.msgid.link/20241219142851.430959-1-csokas.bence@prolan.hu +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 42 ++++++++++--------------------------- + 1 file changed, 11 insertions(+), 31 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -1365,50 +1365,37 @@ static int atmel_qspi_probe(struct platf + aq->mmap_phys_base = (dma_addr_t)res->start; + + /* Get the peripheral clock */ +- aq->pclk = devm_clk_get(&pdev->dev, "pclk"); ++ aq->pclk = devm_clk_get_enabled(&pdev->dev, "pclk"); + if (IS_ERR(aq->pclk)) +- aq->pclk = devm_clk_get(&pdev->dev, NULL); ++ aq->pclk = devm_clk_get_enabled(&pdev->dev, NULL); + + if (IS_ERR(aq->pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(aq->pclk), + "missing peripheral clock\n"); + +- /* Enable the peripheral clock */ +- err = clk_prepare_enable(aq->pclk); +- if (err) +- return dev_err_probe(&pdev->dev, err, +- "failed to enable the peripheral clock\n"); +- + if (aq->caps->has_qspick) { + /* Get the QSPI system clock */ +- aq->qspick = devm_clk_get(&pdev->dev, "qspick"); ++ aq->qspick = devm_clk_get_enabled(&pdev->dev, "qspick"); + if (IS_ERR(aq->qspick)) { + dev_err(&pdev->dev, "missing system clock\n"); + err = PTR_ERR(aq->qspick); +- goto disable_pclk; ++ return err; + } + +- /* Enable the QSPI system clock */ +- err = clk_prepare_enable(aq->qspick); +- if (err) { +- dev_err(&pdev->dev, +- "failed to enable the QSPI system clock\n"); +- goto disable_pclk; +- } + } else if (aq->caps->has_gclk) { + /* Get the QSPI generic clock */ + aq->gclk = devm_clk_get(&pdev->dev, "gclk"); + if (IS_ERR(aq->gclk)) { + dev_err(&pdev->dev, "missing Generic clock\n"); + err = PTR_ERR(aq->gclk); +- goto disable_pclk; ++ return err; + } + } + + if (aq->caps->has_dma) { + err = atmel_qspi_dma_init(ctrl); + if (err == -EPROBE_DEFER) +- goto disable_qspick; ++ return err; + } + + /* Request the IRQ */ +@@ -1448,10 +1435,6 @@ static int atmel_qspi_probe(struct platf + dma_release: + if (aq->caps->has_dma) + atmel_qspi_dma_release(aq); +-disable_qspick: +- clk_disable_unprepare(aq->qspick); +-disable_pclk: +- clk_disable_unprepare(aq->pclk); + + return err; + } +@@ -1490,7 +1473,6 @@ static int atmel_qspi_sama7g5_suspend(st + if (ret) + return ret; + +- clk_disable_unprepare(aq->pclk); + return 0; + } + +@@ -1515,8 +1497,6 @@ static void atmel_qspi_remove(struct pla + } + + atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); +- clk_disable(aq->qspick); +- clk_disable(aq->pclk); + } else { + /* + * atmel_qspi_runtime_{suspend,resume} just disable and enable +@@ -1526,9 +1506,6 @@ static void atmel_qspi_remove(struct pla + dev_warn(&pdev->dev, "Failed to resume device on remove\n"); + } + +- clk_unprepare(aq->qspick); +- clk_unprepare(aq->pclk); +- + pm_runtime_disable(&pdev->dev); + pm_runtime_dont_use_autosuspend(&pdev->dev); + pm_runtime_put_noidle(&pdev->dev); +@@ -1544,8 +1521,11 @@ static int __maybe_unused atmel_qspi_sus + if (ret < 0) + return ret; + +- if (aq->caps->has_gclk) +- return atmel_qspi_sama7g5_suspend(aq); ++ if (aq->caps->has_gclk) { ++ ret = atmel_qspi_sama7g5_suspend(aq); ++ clk_disable_unprepare(aq->pclk); ++ return ret; ++ } + + atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR); + diff --git a/target/linux/microchipsw/patches-6.12/0081-v6.14-spi-atmel-quadspi-Update-to-current-device-naming-te.patch b/target/linux/microchipsw/patches-6.12/0081-v6.14-spi-atmel-quadspi-Update-to-current-device-naming-te.patch new file mode 100644 index 0000000000..f5787551c5 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0081-v6.14-spi-atmel-quadspi-Update-to-current-device-naming-te.patch @@ -0,0 +1,66 @@ +From 2eaa23a57b91442f98ae2c77ab1258a2bf0065b9 Mon Sep 17 00:00:00 2001 +From: Alexander Dahl +Date: Thu, 9 Jan 2025 10:48:43 +0100 +Subject: [PATCH 101/112] spi: atmel-quadspi: Update to current device naming + terminology + +For v6.9 the spi subsystem changed the terminology to host and target +devices, see commit 99769a52464d ("spi: Update the "master/slave" +terminology in documentation") for reference. Support for SAMA7G5 was +forward ported recently from an old vendor branch before that +terminology change, so naming for the new struct member is adapted to +follow the current scheme. + +Signed-off-by: Alexander Dahl +Link: https://patch.msgid.link/20250109094843.36014-1-ada@thorsis.com +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 12 ++++++------ + 1 file changed, 6 insertions(+), 6 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -280,7 +280,7 @@ struct atmel_qspi { + u32 irq_mask; + u32 mr; + u32 scr; +- u32 slave_max_speed_hz; ++ u32 target_max_speed_hz; + struct completion cmd_completion; + struct completion dma_completion; + dma_addr_t mmap_phys_base; +@@ -1041,7 +1041,7 @@ static int atmel_qspi_set_pad_calibratio + + /* Refresh analogic blocks every 1 ms.*/ + atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, +- aq->slave_max_speed_hz / 1000), ++ aq->target_max_speed_hz / 1000), + aq, QSPI_REFRESH); + + return ret; +@@ -1064,12 +1064,12 @@ static int atmel_qspi_set_gclk(struct at + return ret; + } + +- if (aq->slave_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) ++ if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) + atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); + else + atmel_qspi_write(0, aq, QSPI_DLLCFG); + +- ret = clk_set_rate(aq->gclk, aq->slave_max_speed_hz); ++ ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); + if (ret) { + dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n"); + return ret; +@@ -1131,8 +1131,8 @@ static int atmel_qspi_sama7g5_setup(stru + { + struct atmel_qspi *aq = spi_controller_get_devdata(spi->controller); + +- /* The controller can communicate with a single slave. */ +- aq->slave_max_speed_hz = spi->max_speed_hz; ++ /* The controller can communicate with a single peripheral device (target). */ ++ aq->target_max_speed_hz = spi->max_speed_hz; + + return atmel_qspi_sama7g5_init(aq); + } diff --git a/target/linux/microchipsw/patches-6.12/0082-v6.14-spi-atmel-quadspi-Fix-warning-in-doc-comment.patch b/target/linux/microchipsw/patches-6.12/0082-v6.14-spi-atmel-quadspi-Fix-warning-in-doc-comment.patch new file mode 100644 index 0000000000..6a919c1707 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0082-v6.14-spi-atmel-quadspi-Fix-warning-in-doc-comment.patch @@ -0,0 +1,34 @@ +From 9a39bca30a65f571fae33ac9c76e67ebca44b2a4 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= +Date: Mon, 3 Feb 2025 16:12:49 +0100 +Subject: [PATCH 102/112] spi: atmel-quadspi: Fix warning in doc-comment +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The doc-comment for `struct atmel_qspi_pcal` had a typo in one of the +struct members' name, causing a warning with the `W=1` option. + +Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") +Reported-by: kernel test robot +Closes: https://lore.kernel.org/oe-kbuild-all/202501311707.Ltj0qXse-lkp@intel.com/ +Signed-off-by: Bence Csókás +Link: https://patch.msgid.link/20250203151249.79876-2-csokas.bence@prolan.hu +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -235,8 +235,8 @@ + /** + * struct atmel_qspi_pcal - Pad Calibration Clock Division + * @pclk_rate: peripheral clock rate. +- * @pclkdiv: calibration clock division. The clock applied to the calibration +- * cell is divided by pclkdiv + 1. ++ * @pclk_div: calibration clock division. The clock applied to the calibration ++ * cell is divided by pclk_div + 1. + */ + struct atmel_qspi_pcal { + u32 pclk_rate; diff --git a/target/linux/microchipsw/patches-6.12/0083-v6.14-spi-atmel-quadspi-remove-references-to-runtime-PM-on.patch b/target/linux/microchipsw/patches-6.12/0083-v6.14-spi-atmel-quadspi-remove-references-to-runtime-PM-on.patch new file mode 100644 index 0000000000..6ed49863a0 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0083-v6.14-spi-atmel-quadspi-remove-references-to-runtime-PM-on.patch @@ -0,0 +1,41 @@ +From 74a3cec06e0d0604d9e075e4976a9f434f112488 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Fri, 7 Feb 2025 13:21:45 +0100 +Subject: [PATCH 103/112] spi: atmel-quadspi: remove references to runtime PM + on error path +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +There is no need to call runtime PM put APIs on error path of +`atmel_qspi_sama7g5_transfer()` as the caller (`atmel_qspi_exec_op()`) +of it will take care of this if needed. + +Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") +Signed-off-by: Claudiu Beznea +Signed-off-by: Durai Manickam KR +Reported-by: Alexander Dahl +Closes: https://lore.kernel.org/linux-spi/20250109-carat-festivity-5f088e1add3c@thorsis.com/ +[ csokas.bence: Rebase and clarify msg, fix/add tags ] +Signed-off-by: Bence Csókás +Link: https://patch.msgid.link/20250207122145.162183-2-csokas.bence@prolan.hu +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 5 +---- + 1 file changed, 1 insertion(+), 4 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -930,11 +930,8 @@ static int atmel_qspi_sama7g5_transfer(s + + /* Release the chip-select. */ + ret = atmel_qspi_reg_sync(aq); +- if (ret) { +- pm_runtime_mark_last_busy(&aq->pdev->dev); +- pm_runtime_put_autosuspend(&aq->pdev->dev); ++ if (ret) + return ret; +- } + atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR); + + return atmel_qspi_wait_for_completion(aq, QSPI_SR_CSRA); diff --git a/target/linux/microchipsw/patches-6.12/0084-v6.15-spi-atmel-quadspi-Fix-printed-error-code-during-DMA-.patch b/target/linux/microchipsw/patches-6.12/0084-v6.15-spi-atmel-quadspi-Fix-printed-error-code-during-DMA-.patch new file mode 100644 index 0000000000..1e56e50034 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0084-v6.15-spi-atmel-quadspi-Fix-printed-error-code-during-DMA-.patch @@ -0,0 +1,49 @@ +From c015516392a271e179e4f898908c402ec93ce13a Mon Sep 17 00:00:00 2001 +From: Krzysztof Kozlowski +Date: Thu, 1 May 2025 17:01:59 +0200 +Subject: [PATCH 104/112] spi: atmel-quadspi: Fix printed error code during DMA + setup + +On dma_request_chan() failure driver NULL-ifies the 'rx_chan' and +immediately uses it as PTR_ERR() so dev_err_probe() prints incorrect +error code. Rework the code so proper error code will be printed and +NULL-ifying of 'rx_chan' will happen in common error handling block +(failure of DMA setup is not fatal for the driver and further code +depends on 'rx_chan' being non-NULL for DMA operations). + +Reported by Smatch: + drivers/spi/atmel-quadspi.c:1287 atmel_qspi_dma_init() warn: passing zero to 'PTR_ERR' + +Signed-off-by: Krzysztof Kozlowski +Link: https://patch.msgid.link/20250501-n-smatch-fixes-v2-1-d2ad9c1f2e67@linaro.org +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -1259,9 +1259,9 @@ static int atmel_qspi_dma_init(struct sp + + aq->rx_chan = dma_request_chan(&aq->pdev->dev, "rx"); + if (IS_ERR(aq->rx_chan)) { +- aq->rx_chan = NULL; +- return dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan), +- "RX DMA channel is not available\n"); ++ ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan), ++ "RX DMA channel is not available\n"); ++ goto null_rx_chan; + } + + aq->tx_chan = dma_request_chan(&aq->pdev->dev, "tx"); +@@ -1282,8 +1282,9 @@ static int atmel_qspi_dma_init(struct sp + + release_rx_chan: + dma_release_channel(aq->rx_chan); +- aq->rx_chan = NULL; + aq->tx_chan = NULL; ++null_rx_chan: ++ aq->rx_chan = NULL; + return ret; + } + diff --git a/target/linux/microchipsw/patches-6.12/0086-v6.15-spi-atmel-quadspi-Fix-unbalanced-pm_runtime-by-using.patch b/target/linux/microchipsw/patches-6.12/0086-v6.15-spi-atmel-quadspi-Fix-unbalanced-pm_runtime-by-using.patch new file mode 100644 index 0000000000..3853d7d23e --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0086-v6.15-spi-atmel-quadspi-Fix-unbalanced-pm_runtime-by-using.patch @@ -0,0 +1,62 @@ +From e56d9480ea806b1d92d16b882c40e7216f2cf2f2 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= +Date: Thu, 27 Mar 2025 20:59:27 +0100 +Subject: [PATCH 106/112] spi: atmel-quadspi: Fix unbalanced pm_runtime by + using devm_ API +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Fix unbalanced PM in error path of `atmel_qspi_probe()` +by using `devm_pm_runtime_*()` functions. + +Reported-by: Alexander Dahl +Closes: https://lore.kernel.org/linux-spi/20250110-paycheck-irregular-bcddab1276c7@thorsis.com/ +Fixes: 5af42209a4d2 ("spi: atmel-quadspi: Add support for sama7g5 QSPI") +Signed-off-by: Bence Csókás +Link: https://patch.msgid.link/20250327195928.680771-4-csokas.bence@prolan.hu +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 17 ++++------------- + 1 file changed, 4 insertions(+), 13 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -1409,22 +1409,17 @@ static int atmel_qspi_probe(struct platf + + pm_runtime_set_autosuspend_delay(&pdev->dev, 500); + pm_runtime_use_autosuspend(&pdev->dev); +- pm_runtime_set_active(&pdev->dev); +- pm_runtime_enable(&pdev->dev); +- pm_runtime_get_noresume(&pdev->dev); ++ devm_pm_runtime_set_active_enabled(&pdev->dev); ++ devm_pm_runtime_get_noresume(&pdev->dev); + + err = atmel_qspi_init(aq); + if (err) + goto dma_release; + + err = spi_register_controller(ctrl); +- if (err) { +- pm_runtime_put_noidle(&pdev->dev); +- pm_runtime_disable(&pdev->dev); +- pm_runtime_set_suspended(&pdev->dev); +- pm_runtime_dont_use_autosuspend(&pdev->dev); ++ if (err) + goto dma_release; +- } ++ + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + +@@ -1503,10 +1498,6 @@ static void atmel_qspi_remove(struct pla + */ + dev_warn(&pdev->dev, "Failed to resume device on remove\n"); + } +- +- pm_runtime_disable(&pdev->dev); +- pm_runtime_dont_use_autosuspend(&pdev->dev); +- pm_runtime_put_noidle(&pdev->dev); + } + + static int __maybe_unused atmel_qspi_suspend(struct device *dev) diff --git a/target/linux/microchipsw/patches-6.12/0087-v6.17-dmaengine-Add-devm_dma_request_chan.patch b/target/linux/microchipsw/patches-6.12/0087-v6.17-dmaengine-Add-devm_dma_request_chan.patch new file mode 100644 index 0000000000..1349734383 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0087-v6.17-dmaengine-Add-devm_dma_request_chan.patch @@ -0,0 +1,81 @@ +From 92da9095958114aca94d7ab0c8fa76ee556d412d Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= +Date: Tue, 10 Jun 2025 10:22:53 +0200 +Subject: [PATCH 107/112] dmaengine: Add devm_dma_request_chan() +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Expand the arsenal of devm functions for DMA devices, this time for +requesting channels. + +Signed-off-by: Bence Csókás +Link: https://lore.kernel.org/r/20250610082256.400492-2-csokas.bence@prolan.hu +Signed-off-by: Vinod Koul +--- + drivers/dma/dmaengine.c | 30 ++++++++++++++++++++++++++++++ + include/linux/dmaengine.h | 7 +++++++ + 2 files changed, 37 insertions(+) + +--- a/drivers/dma/dmaengine.c ++++ b/drivers/dma/dmaengine.c +@@ -926,6 +926,36 @@ void dma_release_channel(struct dma_chan + } + EXPORT_SYMBOL_GPL(dma_release_channel); + ++static void dmaenginem_release_channel(void *chan) ++{ ++ dma_release_channel(chan); ++} ++ ++/** ++ * devm_dma_request_chan - try to allocate an exclusive slave channel ++ * @dev: pointer to client device structure ++ * @name: slave channel name ++ * ++ * Returns pointer to appropriate DMA channel on success or an error pointer. ++ * ++ * The operation is managed and will be undone on driver detach. ++ */ ++ ++struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name) ++{ ++ struct dma_chan *chan = dma_request_chan(dev, name); ++ int ret = 0; ++ ++ if (!IS_ERR(chan)) ++ ret = devm_add_action_or_reset(dev, dmaenginem_release_channel, chan); ++ ++ if (ret) ++ return ERR_PTR(ret); ++ ++ return chan; ++} ++EXPORT_SYMBOL_GPL(devm_dma_request_chan); ++ + /** + * dmaengine_get - register interest in dma_channels + */ +--- a/include/linux/dmaengine.h ++++ b/include/linux/dmaengine.h +@@ -1521,6 +1521,7 @@ struct dma_chan *__dma_request_channel(c + + struct dma_chan *dma_request_chan(struct device *dev, const char *name); + struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask); ++struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name); + + void dma_release_channel(struct dma_chan *chan); + int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps); +@@ -1557,6 +1558,12 @@ static inline struct dma_chan *dma_reque + { + return ERR_PTR(-ENODEV); + } ++ ++static inline struct dma_chan *devm_dma_request_chan(struct device *dev, const char *name) ++{ ++ return ERR_PTR(-ENODEV); ++} ++ + static inline void dma_release_channel(struct dma_chan *chan) + { + } diff --git a/target/linux/microchipsw/patches-6.12/0088-v6.17-spi-atmel-quadspi-Use-devm_dma_request_chan.patch b/target/linux/microchipsw/patches-6.12/0088-v6.17-spi-atmel-quadspi-Use-devm_dma_request_chan.patch new file mode 100644 index 0000000000..388ba0128a --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0088-v6.17-spi-atmel-quadspi-Use-devm_dma_request_chan.patch @@ -0,0 +1,122 @@ +From 4b031c48133b762ef9bb6cb40b9ec040acaef970 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Bence=20Cs=C3=B3k=C3=A1s?= +Date: Tue, 10 Jun 2025 10:22:54 +0200 +Subject: [PATCH 108/112] spi: atmel-quadspi: Use `devm_dma_request_chan()` +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Leave releasing of DMA channels up to the devm facilities. This way we can +eliminate the rest of the "goto ladder". + +Signed-off-by: Bence Csókás +Link: https://patch.msgid.link/20250610082256.400492-3-csokas.bence@prolan.hu +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 48 ++++++++++--------------------------- + 1 file changed, 13 insertions(+), 35 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -1257,18 +1257,21 @@ static int atmel_qspi_dma_init(struct sp + struct atmel_qspi *aq = spi_controller_get_devdata(ctrl); + int ret; + +- aq->rx_chan = dma_request_chan(&aq->pdev->dev, "rx"); ++ aq->rx_chan = devm_dma_request_chan(&aq->pdev->dev, "rx"); + if (IS_ERR(aq->rx_chan)) { + ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->rx_chan), + "RX DMA channel is not available\n"); +- goto null_rx_chan; ++ aq->rx_chan = NULL; ++ return ret; + } + +- aq->tx_chan = dma_request_chan(&aq->pdev->dev, "tx"); ++ aq->tx_chan = devm_dma_request_chan(&aq->pdev->dev, "tx"); + if (IS_ERR(aq->tx_chan)) { + ret = dev_err_probe(&aq->pdev->dev, PTR_ERR(aq->tx_chan), + "TX DMA channel is not available\n"); +- goto release_rx_chan; ++ aq->rx_chan = NULL; ++ aq->tx_chan = NULL; ++ return ret; + } + + ctrl->dma_rx = aq->rx_chan; +@@ -1279,21 +1282,6 @@ static int atmel_qspi_dma_init(struct sp + dma_chan_name(aq->tx_chan), dma_chan_name(aq->rx_chan)); + + return 0; +- +-release_rx_chan: +- dma_release_channel(aq->rx_chan); +- aq->tx_chan = NULL; +-null_rx_chan: +- aq->rx_chan = NULL; +- return ret; +-} +- +-static void atmel_qspi_dma_release(struct atmel_qspi *aq) +-{ +- if (aq->rx_chan) +- dma_release_channel(aq->rx_chan); +- if (aq->tx_chan) +- dma_release_channel(aq->tx_chan); + } + + static const struct atmel_qspi_ops atmel_qspi_ops = { +@@ -1398,14 +1386,13 @@ static int atmel_qspi_probe(struct platf + + /* Request the IRQ */ + irq = platform_get_irq(pdev, 0); +- if (irq < 0) { +- err = irq; +- goto dma_release; +- } ++ if (irq < 0) ++ return irq; ++ + err = devm_request_irq(&pdev->dev, irq, atmel_qspi_interrupt, + 0, dev_name(&pdev->dev), aq); + if (err) +- goto dma_release; ++ return err; + + pm_runtime_set_autosuspend_delay(&pdev->dev, 500); + pm_runtime_use_autosuspend(&pdev->dev); +@@ -1414,22 +1401,16 @@ static int atmel_qspi_probe(struct platf + + err = atmel_qspi_init(aq); + if (err) +- goto dma_release; ++ return err; + + err = spi_register_controller(ctrl); + if (err) +- goto dma_release; ++ return err; + + pm_runtime_mark_last_busy(&pdev->dev); + pm_runtime_put_autosuspend(&pdev->dev); + + return 0; +- +-dma_release: +- if (aq->caps->has_dma) +- atmel_qspi_dma_release(aq); +- +- return err; + } + + static int atmel_qspi_sama7g5_suspend(struct atmel_qspi *aq) +@@ -1479,9 +1460,6 @@ static void atmel_qspi_remove(struct pla + + ret = pm_runtime_get_sync(&pdev->dev); + if (ret >= 0) { +- if (aq->caps->has_dma) +- atmel_qspi_dma_release(aq); +- + if (aq->caps->has_gclk) { + ret = atmel_qspi_sama7g5_suspend(aq); + if (ret) diff --git a/target/linux/microchipsw/patches-6.12/0089-v6.18-spi-atmel-quadspi-add-padcalib-2xgclk-and-dllon-capa.patch b/target/linux/microchipsw/patches-6.12/0089-v6.18-spi-atmel-quadspi-add-padcalib-2xgclk-and-dllon-capa.patch new file mode 100644 index 0000000000..07450619e2 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0089-v6.18-spi-atmel-quadspi-add-padcalib-2xgclk-and-dllon-capa.patch @@ -0,0 +1,178 @@ +From 0f52d98240cdce03944c967d4fe4faab032f8f57 Mon Sep 17 00:00:00 2001 +From: Varshini Rajendran +Date: Mon, 8 Sep 2025 09:44:18 +0530 +Subject: [PATCH 109/112] spi: atmel-quadspi: add padcalib, 2xgclk, and dllon + capabilities + +Introduce capability flags for SoC-specific variations of the QuadSPI +controller: + + - has_padcalib: controller supports pad calibration + - has_2xgclk: requires GCLK at half the data rate (2x clocking) + - has_dllon: controller supports DLL clock + +Set `has_padcalib` for Octal controllers that provide pad calibration +support. Use `has_2xgclk` for controllers that require the GCLK to run +at twice the data rate. Differentiate SoC integration variants with the +`has_dllon` flag and set it as needed. + +Signed-off-by: Varshini Rajendran +Signed-off-by: Dharma Balasubiramani +Link: https://patch.msgid.link/20250908-microchip-qspi-v2-3-8f3d69fdd5c9@microchip.com +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 92 ++++++++++++++++++++++++------------- + 1 file changed, 60 insertions(+), 32 deletions(-) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -262,6 +262,9 @@ struct atmel_qspi_caps { + bool has_ricr; + bool octal; + bool has_dma; ++ bool has_2xgclk; ++ bool has_padcalib; ++ bool has_dllon; + }; + + struct atmel_qspi_ops; +@@ -1028,13 +1031,25 @@ static int atmel_qspi_set_pad_calibratio + aq, QSPI_PCALCFG); + + /* DLL On + start calibration. */ +- atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); ++ if (aq->caps->has_dllon) ++ atmel_qspi_write(QSPI_CR_DLLON | QSPI_CR_STPCAL, aq, QSPI_CR); ++ /* If there is no DLL support only start calibration. */ ++ else ++ atmel_qspi_write(QSPI_CR_STPCAL, aq, QSPI_CR); + +- /* Check synchronization status before updating configuration. */ +- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, +- (val & QSPI_SR2_DLOCK) && +- !(val & QSPI_SR2_CALBSY), 40, +- ATMEL_QSPI_TIMEOUT); ++ /* ++ * Check DLL clock lock and synchronization status before updating ++ * configuration. ++ */ ++ if (aq->caps->has_dllon) ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ (val & QSPI_SR2_DLOCK) && ++ !(val & QSPI_SR2_CALBSY), 40, ++ ATMEL_QSPI_TIMEOUT); ++ else ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_CALBSY), 40, ++ ATMEL_QSPI_TIMEOUT); + + /* Refresh analogic blocks every 1 ms.*/ + atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, +@@ -1050,23 +1065,28 @@ static int atmel_qspi_set_gclk(struct at + int ret; + + /* Disable DLL before setting GCLK */ +- status = atmel_qspi_read(aq, QSPI_SR2); +- if (status & QSPI_SR2_DLOCK) { +- atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); ++ if (aq->caps->has_dllon) { ++ status = atmel_qspi_read(aq, QSPI_SR2); ++ if (status & QSPI_SR2_DLOCK) { ++ atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_DLOCK), 40, ++ ATMEL_QSPI_TIMEOUT); ++ if (ret) ++ return ret; ++ } + +- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, +- !(val & QSPI_SR2_DLOCK), 40, +- ATMEL_QSPI_TIMEOUT); +- if (ret) +- return ret; ++ if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) ++ atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); ++ else ++ atmel_qspi_write(0, aq, QSPI_DLLCFG); + } + +- if (aq->target_max_speed_hz > QSPI_DLLCFG_THRESHOLD_FREQ) +- atmel_qspi_write(QSPI_DLLCFG_RANGE, aq, QSPI_DLLCFG); ++ if (aq->caps->has_2xgclk) ++ ret = clk_set_rate(aq->gclk, 2 * aq->target_max_speed_hz); + else +- atmel_qspi_write(0, aq, QSPI_DLLCFG); ++ ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); + +- ret = clk_set_rate(aq->gclk, aq->target_max_speed_hz); + if (ret) { + dev_err(&aq->pdev->dev, "Failed to set generic clock rate.\n"); + return ret; +@@ -1089,11 +1109,16 @@ static int atmel_qspi_sama7g5_init(struc + if (ret) + return ret; + +- if (aq->caps->octal) { ++ /* ++ * Check if the SoC supports pad calibration in Octal SPI mode. ++ * Proceed only if both the capabilities are true. ++ */ ++ if (aq->caps->octal && aq->caps->has_padcalib) { + ret = atmel_qspi_set_pad_calibration(aq); + if (ret) + return ret; +- } else { ++ /* Start DLL on only if the SoC supports the same */ ++ } else if (aq->caps->has_dllon) { + atmel_qspi_write(QSPI_CR_DLLON, aq, QSPI_CR); + ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, + (val & QSPI_SR2_DLOCK), 40, +@@ -1434,19 +1459,19 @@ static int atmel_qspi_sama7g5_suspend(st + + clk_disable_unprepare(aq->gclk); + +- atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); +- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, +- !(val & QSPI_SR2_DLOCK), 40, +- ATMEL_QSPI_TIMEOUT); +- if (ret) +- return ret; +- +- ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, +- !(val & QSPI_SR2_CALBSY), 40, +- ATMEL_QSPI_TIMEOUT); +- if (ret) +- return ret; ++ if (aq->caps->has_dllon) { ++ atmel_qspi_write(QSPI_CR_DLLOFF, aq, QSPI_CR); ++ ret = readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_DLOCK), 40, ++ ATMEL_QSPI_TIMEOUT); ++ if (ret) ++ return ret; ++ } + ++ if (aq->caps->has_padcalib) ++ return readl_poll_timeout(aq->regs + QSPI_SR2, val, ++ !(val & QSPI_SR2_CALBSY), 40, ++ ATMEL_QSPI_TIMEOUT); + return 0; + } + +@@ -1584,12 +1609,15 @@ static const struct atmel_qspi_caps atme + .has_gclk = true, + .octal = true, + .has_dma = true, ++ .has_padcalib = true, ++ .has_dllon = true, + }; + + static const struct atmel_qspi_caps atmel_sama7g5_qspi_caps = { + .max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, + .has_gclk = true, + .has_dma = true, ++ .has_dllon = true, + }; + + static const struct of_device_id atmel_qspi_dt_ids[] = { diff --git a/target/linux/microchipsw/patches-6.12/0090-v6.18-spi-atmel-quadspi-add-support-for-SAM9X7-QSPI-contro.patch b/target/linux/microchipsw/patches-6.12/0090-v6.18-spi-atmel-quadspi-add-support-for-SAM9X7-QSPI-contro.patch new file mode 100644 index 0000000000..a4d9587de9 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0090-v6.18-spi-atmel-quadspi-add-support-for-SAM9X7-QSPI-contro.patch @@ -0,0 +1,58 @@ +From ea6e579557cf85f3b0ed3c94c3e4d69afbcba46c Mon Sep 17 00:00:00 2001 +From: Varshini Rajendran +Date: Mon, 8 Sep 2025 09:44:19 +0530 +Subject: [PATCH 110/112] spi: atmel-quadspi: add support for SAM9X7 QSPI + controller + +Add support for the QuadSPI controller found on the SAM9X7 SoC. + +This controller does not implement pad calibration. It supports +operation up to 100 MHz, and requires the GCK to run at twice +the data rate. + +Signed-off-by: Varshini Rajendran +Signed-off-by: Dharma Balasubiramani +Link: https://patch.msgid.link/20250908-microchip-qspi-v2-4-8f3d69fdd5c9@microchip.com +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 15 +++++++++++++++ + 1 file changed, 15 insertions(+) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -63,6 +63,7 @@ + + #define SAMA7G5_QSPI0_MAX_SPEED_HZ 200000000 + #define SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ 133000000 ++#define SAM9X7_QSPI_MAX_SPEED_HZ 100000000 + + /* Bitfields in QSPI_CR (Control Register) */ + #define QSPI_CR_QSPIEN BIT(0) +@@ -1604,6 +1605,16 @@ static const struct atmel_qspi_caps atme + .has_ricr = true, + }; + ++static const struct atmel_qspi_caps atmel_sam9x7_ospi_caps = { ++ .max_speed_hz = SAM9X7_QSPI_MAX_SPEED_HZ, ++ .has_gclk = true, ++ .octal = true, ++ .has_dma = true, ++ .has_2xgclk = true, ++ .has_padcalib = false, ++ .has_dllon = false, ++}; ++ + static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = { + .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, + .has_gclk = true, +@@ -1637,6 +1648,10 @@ static const struct of_device_id atmel_q + .compatible = "microchip,sama7g5-qspi", + .data = &atmel_sama7g5_qspi_caps, + }, ++ { ++ .compatible = "microchip,sam9x7-ospi", ++ .data = &atmel_sam9x7_ospi_caps, ++ }, + + { /* sentinel */ } + }; diff --git a/target/linux/microchipsw/patches-6.12/0091-v6.18-spi-atmel-quadspi-Add-support-for-sama7d65-QSPI.patch b/target/linux/microchipsw/patches-6.12/0091-v6.18-spi-atmel-quadspi-Add-support-for-sama7d65-QSPI.patch new file mode 100644 index 0000000000..305b75bb8e --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0091-v6.18-spi-atmel-quadspi-Add-support-for-sama7d65-QSPI.patch @@ -0,0 +1,57 @@ +From f157bc4635178eccb282031d7c2ba2867bd3274c Mon Sep 17 00:00:00 2001 +From: Varshini Rajendran +Date: Mon, 8 Sep 2025 09:44:20 +0530 +Subject: [PATCH 111/112] spi: atmel-quadspi: Add support for sama7d65 QSPI + +Add support for sama7d65 QSPI controller and define its caps. + +Signed-off-by: Varshini Rajendran +Link: https://patch.msgid.link/20250908-microchip-qspi-v2-5-8f3d69fdd5c9@microchip.com +Signed-off-by: Mark Brown +--- + drivers/spi/atmel-quadspi.c | 27 +++++++++++++++++++++++++++ + 1 file changed, 27 insertions(+) + +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -1615,6 +1615,24 @@ static const struct atmel_qspi_caps atme + .has_dllon = false, + }; + ++static const struct atmel_qspi_caps atmel_sama7d65_ospi_caps = { ++ .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, ++ .has_gclk = true, ++ .octal = true, ++ .has_dma = true, ++ .has_2xgclk = true, ++ .has_padcalib = true, ++ .has_dllon = false, ++}; ++ ++static const struct atmel_qspi_caps atmel_sama7d65_qspi_caps = { ++ .max_speed_hz = SAMA7G5_QSPI1_SDR_MAX_SPEED_HZ, ++ .has_gclk = true, ++ .has_dma = true, ++ .has_2xgclk = true, ++ .has_dllon = false, ++}; ++ + static const struct atmel_qspi_caps atmel_sama7g5_ospi_caps = { + .max_speed_hz = SAMA7G5_QSPI0_MAX_SPEED_HZ, + .has_gclk = true, +@@ -1652,6 +1670,15 @@ static const struct of_device_id atmel_q + .compatible = "microchip,sam9x7-ospi", + .data = &atmel_sam9x7_ospi_caps, + }, ++ { ++ .compatible = "microchip,sama7d65-ospi", ++ .data = &atmel_sama7d65_ospi_caps, ++ }, ++ { ++ .compatible = "microchip,sama7d65-qspi", ++ .data = &atmel_sama7d65_qspi_caps, ++ }, ++ + + { /* sentinel */ } + }; diff --git a/target/linux/microchipsw/patches-6.12/0092-v6.18-net-sparx5-lan969x-fix-flooding-configuration-on-bri.patch b/target/linux/microchipsw/patches-6.12/0092-v6.18-net-sparx5-lan969x-fix-flooding-configuration-on-bri.patch new file mode 100644 index 0000000000..16093394d7 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/0092-v6.18-net-sparx5-lan969x-fix-flooding-configuration-on-bri.patch @@ -0,0 +1,137 @@ +From c9d1b0b54258ba13b567dd116ead3c7c30cba7d8 Mon Sep 17 00:00:00 2001 +From: Daniel Machon +Date: Fri, 3 Oct 2025 14:35:59 +0200 +Subject: [PATCH] net: sparx5/lan969x: fix flooding configuration on bridge + join/leave +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +The sparx5 driver programs UC/MC/BC flooding in sparx5_update_fwd() by +unconditionally applying bridge_fwd_mask to all flood PGIDs. Any bridge +topology change that triggers sparx5_update_fwd() (for example enslaving +another port) therefore reinstalls flooding in hardware for already +bridged ports, regardless of their per-port flood flags. + +This results in clobbering of the flood masks, and desynchronization +between software and hardware: the bridge still reports “flood off” for +the port, but hardware has flooding enabled due to unconditional PGID +reprogramming. + +Steps to reproduce: + + $ ip link add br0 type bridge + $ ip link set br0 up + $ ip link set eth0 master br0 + $ ip link set eth0 up + $ bridge link set dev eth0 flood off + $ ip link set eth1 master br0 + $ ip link set eth1 up + +At this point, flooding is silently re-enabled for eth0. Software still +shows “flood off” for eth0, but hardware has flooding enabled. + +To fix this, flooding is now set explicitly during bridge join/leave, +through sparx5_port_attr_bridge_flags(): + + On bridge join, UC/MC/BC flooding is enabled by default. + + On bridge leave, UC/MC/BC flooding is disabled. + + sparx5_update_fwd() no longer touches the flood PGIDs, clobbering + the flood masks, and desynchronizing software and hardware. + + Initialization of the flooding PGIDs have been moved to + sparx5_start(). This is required as flooding PGIDs defaults to + 0x3fffffff in hardware and the initialization was previously handled + in sparx5_update_fwd(), which was removed. + +With this change, user-configured flooding flags persist across bridge +updates and are no longer overridden by sparx5_update_fwd(). + +Fixes: d6fce5141929 ("net: sparx5: add switching support") +Signed-off-by: Daniel Machon +Reviewed-by: Simon Horman +Link: https://patch.msgid.link/20251003-fix-flood-fwd-v1-1-48eb478b2904@microchip.com +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/microchip/sparx5/sparx5_main.c | 5 +++++ + .../net/ethernet/microchip/sparx5/sparx5_switchdev.c | 12 ++++++++++++ + drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c | 10 ---------- + 3 files changed, 17 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c +@@ -709,6 +709,11 @@ static int sparx5_start(struct sparx5 *s + /* Init masks */ + sparx5_update_fwd(sparx5); + ++ /* Init flood masks */ ++ for (int pgid = sparx5_get_pgid(sparx5, PGID_UC_FLOOD); ++ pgid <= sparx5_get_pgid(sparx5, PGID_BCAST); pgid++) ++ sparx5_pgid_clear(sparx5, pgid); ++ + /* CPU copy CPU pgids */ + spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, + ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU))); +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_switchdev.c +@@ -176,6 +176,7 @@ static int sparx5_port_bridge_join(struc + struct net_device *bridge, + struct netlink_ext_ack *extack) + { ++ struct switchdev_brport_flags flags = {0}; + struct sparx5 *sparx5 = port->sparx5; + struct net_device *ndev = port->ndev; + int err; +@@ -205,6 +206,11 @@ static int sparx5_port_bridge_join(struc + */ + __dev_mc_unsync(ndev, sparx5_mc_unsync); + ++ /* Enable uc/mc/bc flooding */ ++ flags.mask = BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD; ++ flags.val = flags.mask; ++ sparx5_port_attr_bridge_flags(port, flags); ++ + return 0; + + err_switchdev_offload: +@@ -215,6 +221,7 @@ err_switchdev_offload: + static void sparx5_port_bridge_leave(struct sparx5_port *port, + struct net_device *bridge) + { ++ struct switchdev_brport_flags flags = {0}; + struct sparx5 *sparx5 = port->sparx5; + + switchdev_bridge_port_unoffload(port->ndev, NULL, NULL, NULL); +@@ -234,6 +241,11 @@ static void sparx5_port_bridge_leave(str + + /* Port enters in host more therefore restore mc list */ + __dev_mc_sync(port->ndev, sparx5_mc_sync, sparx5_mc_unsync); ++ ++ /* Disable uc/mc/bc flooding */ ++ flags.mask = BR_FLOOD | BR_MCAST_FLOOD | BR_BCAST_FLOOD; ++ flags.val = 0; ++ sparx5_port_attr_bridge_flags(port, flags); + } + + static int sparx5_port_changeupper(struct net_device *dev, +--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c ++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vlan.c +@@ -167,16 +167,6 @@ void sparx5_update_fwd(struct sparx5 *sp + /* Divide up fwd mask in 32 bit words */ + bitmap_to_arr32(mask, sparx5->bridge_fwd_mask, SPX5_PORTS); + +- /* Update flood masks */ +- for (port = sparx5_get_pgid(sparx5, PGID_UC_FLOOD); +- port <= sparx5_get_pgid(sparx5, PGID_BCAST); port++) { +- spx5_wr(mask[0], sparx5, ANA_AC_PGID_CFG(port)); +- if (is_sparx5(sparx5)) { +- spx5_wr(mask[1], sparx5, ANA_AC_PGID_CFG1(port)); +- spx5_wr(mask[2], sparx5, ANA_AC_PGID_CFG2(port)); +- } +- } +- + /* Update SRC masks */ + for (port = 0; port < sparx5->data->consts->n_ports; port++) { + if (test_bit(port, sparx5->bridge_fwd_mask)) { diff --git a/target/linux/microchipsw/patches-6.12/100-clk-lan966x-make-it-selectable-for-ARCH_LAN969X.patch b/target/linux/microchipsw/patches-6.12/100-clk-lan966x-make-it-selectable-for-ARCH_LAN969X.patch new file mode 100644 index 0000000000..1dfc08848e --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/100-clk-lan966x-make-it-selectable-for-ARCH_LAN969X.patch @@ -0,0 +1,26 @@ +From 78d996ea8dbc6fa21ecb28d1b6167d6f2e0043cb Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Fri, 8 Nov 2024 12:22:34 +0100 +Subject: [PATCH 07/25] clk: lan966x: make it selectable for ARCH_LAN969X + +LAN969x uses the same LAN966x clock driver so make it selectable for +ARCH_LAN969X. + +Signed-off-by: Robert Marko +Link: https://lore.kernel.org/r/20241108112355.20251-1-robert.marko@sartura.hr +Signed-off-by: Stephen Boyd +--- + drivers/clk/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/clk/Kconfig ++++ b/drivers/clk/Kconfig +@@ -259,7 +259,7 @@ config COMMON_CLK_LAN966X + tristate "Generic Clock Controller driver for LAN966X SoC" + depends on HAS_IOMEM + depends on OF +- depends on SOC_LAN966 || COMPILE_TEST ++ depends on SOC_LAN966 || ARCH_LAN969X || COMPILE_TEST + help + This driver provides support for Generic Clock Controller(GCK) on + LAN966X SoC. GCK generates and supplies clock to various peripherals diff --git a/target/linux/microchipsw/patches-6.12/102-phy-sparx5-serdes-make-it-selectable-for-ARCH_LAN969.patch b/target/linux/microchipsw/patches-6.12/102-phy-sparx5-serdes-make-it-selectable-for-ARCH_LAN969.patch new file mode 100644 index 0000000000..c00f90913a --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/102-phy-sparx5-serdes-make-it-selectable-for-ARCH_LAN969.patch @@ -0,0 +1,25 @@ +From f11759a7a2c10d32324adf3cc5d4fe95ef74df77 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Wed, 17 Sep 2025 12:55:14 +0200 +Subject: [PATCH 16/25] phy: sparx5-serdes: make it selectable for ARCH_LAN969X + +LAN969x uses the SparX-5 SERDES driver, so make it selectable for +ARCH_LAN969X. + +Signed-off-by: Robert Marko +Reviewed-by: Daniel Machon +--- + drivers/phy/microchip/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/phy/microchip/Kconfig ++++ b/drivers/phy/microchip/Kconfig +@@ -6,7 +6,7 @@ + config PHY_SPARX5_SERDES + tristate "Microchip Sparx5 SerDes PHY driver" + select GENERIC_PHY +- depends on ARCH_SPARX5 || COMPILE_TEST ++ depends on ARCH_SPARX5 || ARCH_LAN969X || COMPILE_TEST + depends on OF + depends on HAS_IOMEM + help diff --git a/target/linux/microchipsw/patches-6.12/103-include-dt-bindings-add-LAN969x-clock-bindings.patch b/target/linux/microchipsw/patches-6.12/103-include-dt-bindings-add-LAN969x-clock-bindings.patch new file mode 100644 index 0000000000..591e0b01cb --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/103-include-dt-bindings-add-LAN969x-clock-bindings.patch @@ -0,0 +1,40 @@ +From 7dffd83ae4ae02a43d61b15af6edb199fcc7ebb3 Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 5 Nov 2024 12:08:06 +0100 +Subject: [PATCH] include: dt-bindings: add LAN969x clock bindings + +Add the required LAN969x clock bindings. + +Signed-off-by: Robert Marko +--- + include/dt-bindings/clock/microchip,lan969x.h | 24 +++++++++++++++++++ + 1 file changed, 24 insertions(+) + create mode 100644 include/dt-bindings/clock/microchip,lan969x.h + +--- /dev/null ++++ b/include/dt-bindings/clock/microchip,lan969x.h +@@ -0,0 +1,24 @@ ++/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ ++ ++#ifndef _DT_BINDINGS_CLK_LAN969X_H ++#define _DT_BINDINGS_CLK_LAN969X_H ++ ++#define GCK_ID_QSPI0 0 ++#define GCK_ID_QSPI2 1 ++#define GCK_ID_SDMMC0 2 ++#define GCK_ID_SDMMC1 3 ++#define GCK_ID_MCAN0 4 ++#define GCK_ID_MCAN1 5 ++#define GCK_ID_FLEXCOM0 6 ++#define GCK_ID_FLEXCOM1 7 ++#define GCK_ID_FLEXCOM2 8 ++#define GCK_ID_FLEXCOM3 9 ++#define GCK_ID_TIMER 10 ++#define GCK_ID_USB_REFCLK 11 ++ ++/* Gate clocks */ ++#define GCK_GATE_USB_DRD 12 ++#define GCK_GATE_MCRAMC 13 ++#define GCK_GATE_HMATRIX 14 ++ ++#endif diff --git a/target/linux/microchipsw/patches-6.12/104-reset-sparx5-add-LAN969x-support.patch b/target/linux/microchipsw/patches-6.12/104-reset-sparx5-add-LAN969x-support.patch new file mode 100644 index 0000000000..92e02755ec --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/104-reset-sparx5-add-LAN969x-support.patch @@ -0,0 +1,26 @@ +From f7a517f6f1c0ac240e2a2b2bae9c7efb4a92430a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 5 Nov 2024 13:36:21 +0100 +Subject: [PATCH] reset: sparx5: add LAN969x support + +LAN969x uses the same reset configuration as LAN966x, but we need to +allow compiling it when ARCH_LAN969X is selected. + +A fallback compatible to LAN966x will be used. + +Signed-off-by: Robert Marko +--- + drivers/reset/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/reset/Kconfig ++++ b/drivers/reset/Kconfig +@@ -147,7 +147,7 @@ config RESET_LPC18XX + + config RESET_MCHP_SPARX5 + bool "Microchip Sparx5 reset driver" +- depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST ++ depends on ARCH_SPARX5 || ARCH_LAN969X || SOC_LAN966 || COMPILE_TEST + default y if SPARX5_SWITCH + select MFD_SYSCON + help diff --git a/target/linux/microchipsw/patches-6.12/105-hwmon-sparx5-make-it-selectable-for-ARCH_MICROCHIP.patch b/target/linux/microchipsw/patches-6.12/105-hwmon-sparx5-make-it-selectable-for-ARCH_MICROCHIP.patch new file mode 100644 index 0000000000..6648f5fa3b --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/105-hwmon-sparx5-make-it-selectable-for-ARCH_MICROCHIP.patch @@ -0,0 +1,24 @@ +From 2d275ce15f57f3b61fdb06d65b7d159e9581203b Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 5 Nov 2024 17:57:37 +0100 +Subject: [PATCH] hwmon: sparx5: make it selectable for ARCH_MICROCHIP + +LAN969x uses the same sensor and driver, so make it selectable for +ARCH_MICROCHIP. + +Signed-off-by: Robert Marko +--- + drivers/hwmon/Kconfig | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/hwmon/Kconfig ++++ b/drivers/hwmon/Kconfig +@@ -602,7 +602,7 @@ config SENSORS_I5K_AMB + + config SENSORS_SPARX5 + tristate "Sparx5 SoC temperature sensor" +- depends on ARCH_SPARX5 || COMPILE_TEST ++ depends on ARCH_MICROCHIP || COMPILE_TEST + help + If you say yes here you get support for temperature monitoring + with the Microchip Sparx5 SoC. diff --git a/target/linux/microchipsw/patches-6.12/106-mmc-sdhci-of-at91-implement-quirk-SDCLK-stop-while-r.patch b/target/linux/microchipsw/patches-6.12/106-mmc-sdhci-of-at91-implement-quirk-SDCLK-stop-while-r.patch new file mode 100644 index 0000000000..adf01f2876 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/106-mmc-sdhci-of-at91-implement-quirk-SDCLK-stop-while-r.patch @@ -0,0 +1,66 @@ +From de3bcf0068734c5076695dd8a6f7dd400c2abc2d Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Mon, 30 Mar 2020 13:32:37 +0300 +Subject: [PATCH 084/110] mmc: sdhci-of-at91: implement quirk: SDCLK stop while + reset and switch + +SAMA7G5 SDMMC HW block needs to have SDCLK stopped while resetting the +IP and changing UHS mode. +Implement this quirk. + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -101,6 +101,11 @@ static void sdhci_at91_set_uhs_signaling + unsigned int timing) + { + u8 mc1r; ++ u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ /* SDCLK must be disabled while changing the mode */ ++ if (clk & SDHCI_CLOCK_CARD_EN) ++ sdhci_writew(host, clk & ~SDHCI_CLOCK_CARD_EN, ++ SDHCI_CLOCK_CONTROL); + + if (timing == MMC_TIMING_MMC_DDR52) { + mc1r = sdhci_readb(host, SDMMC_MC1R); +@@ -108,6 +113,12 @@ static void sdhci_at91_set_uhs_signaling + sdhci_writeb(host, mc1r, SDMMC_MC1R); + } + sdhci_set_uhs_signaling(host, timing); ++ ++ /* reenable SDCLK */ ++ if (clk & SDHCI_CLOCK_CARD_EN) { ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ sdhci_writew(host, clk | SDHCI_CLOCK_CARD_EN, SDHCI_CLOCK_CONTROL); ++ } + } + + static void sdhci_at91_reset(struct sdhci_host *host, u8 mask) +@@ -115,9 +126,21 @@ static void sdhci_at91_reset(struct sdhc + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_at91_priv *priv = sdhci_pltfm_priv(pltfm_host); + unsigned int tmp; ++ u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ ++ /* SDCLK must be disabled while resetting the HW block */ ++ if (clk & SDHCI_CLOCK_CARD_EN) ++ sdhci_writew(host, clk & ~SDHCI_CLOCK_CARD_EN, ++ SDHCI_CLOCK_CONTROL); + + sdhci_reset(host, mask); + ++ /* reenable SDCLK */ ++ if (clk & SDHCI_CLOCK_CARD_EN) { ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ sdhci_writew(host, clk | SDHCI_CLOCK_CARD_EN, SDHCI_CLOCK_CONTROL); ++ } ++ + if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) + || mmc_gpio_get_cd(host->mmc) >= 0) + sdhci_at91_set_force_card_detect(host); diff --git a/target/linux/microchipsw/patches-6.12/107-mmc-sdhci-of-at91-add-hw_reset-callback.patch b/target/linux/microchipsw/patches-6.12/107-mmc-sdhci-of-at91-add-hw_reset-callback.patch new file mode 100644 index 0000000000..5f0f0f888c --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/107-mmc-sdhci-of-at91-add-hw_reset-callback.patch @@ -0,0 +1,58 @@ +From d471f0bf01a95c04d0bc1d907aba73db54877cbb Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Wed, 1 Jul 2020 16:17:36 +0300 +Subject: [PATCH 085/110] mmc: sdhci-of-at91: add hw_reset callback + +Add hardware reset callback that can reset an eMMC. +This is only used in combination with specific DT property cap-mmc-hw-reset. +It uses the MC1R register to enable and disable the reset pin. + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -25,6 +25,7 @@ + + #define SDMMC_MC1R 0x204 + #define SDMMC_MC1R_DDR BIT(3) ++#define SDMMC_MC1R_RSTN BIT(6) + #define SDMMC_MC1R_FCD BIT(7) + #define SDMMC_CACR 0x230 + #define SDMMC_CACR_CAPWREN BIT(0) +@@ -157,12 +158,31 @@ static void sdhci_at91_reset(struct sdhc + } + } + ++static void sdhci_at91_hw_reset(struct sdhci_host *host) ++{ ++ u8 mc1r; ++ ++ mc1r = readb(host->ioaddr + SDMMC_MC1R); ++ ++ mc1r |= SDMMC_MC1R_RSTN; ++ writeb(mc1r, host->ioaddr + SDMMC_MC1R); ++ ++ udelay(10); ++ ++ mc1r &= ~SDMMC_MC1R_RSTN; ++ writeb(mc1r, host->ioaddr + SDMMC_MC1R); ++ ++ /* JEDEC specifies a minimum of 200us for tRSCA (reset to command) */ ++ usleep_range(200, 500); ++} ++ + static const struct sdhci_ops sdhci_at91_sama5d2_ops = { + .set_clock = sdhci_at91_set_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_at91_reset, + .set_uhs_signaling = sdhci_at91_set_uhs_signaling, + .set_power = sdhci_set_power_and_bus_voltage, ++ .hw_reset = sdhci_at91_hw_reset, + }; + + static const struct sdhci_pltfm_data sdhci_sama5d2_pdata = { diff --git a/target/linux/microchipsw/patches-6.12/108-mmc-sdhci-of-at91-add-compatible-to-sama7g5-SoC.patch b/target/linux/microchipsw/patches-6.12/108-mmc-sdhci-of-at91-add-compatible-to-sama7g5-SoC.patch new file mode 100644 index 0000000000..2e72783fb7 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/108-mmc-sdhci-of-at91-add-compatible-to-sama7g5-SoC.patch @@ -0,0 +1,73 @@ +From 31cf8b12619925d2229f1f7dfbed7025372acf24 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Wed, 1 Jul 2020 16:30:33 +0300 +Subject: [PATCH 086/110] mmc: sdhci-of-at91: add compatible to sama7g5 SoC + +Add compatible and support for sama7g5 SDMMC block. + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 19 ++++++++++++++++--- + 1 file changed, 16 insertions(+), 3 deletions(-) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -40,6 +40,8 @@ struct sdhci_at91_soc_data { + const struct sdhci_pltfm_data *pdata; + bool baseclk_is_generated_internally; + unsigned int divider_for_baseclk; ++ unsigned int max_sdr104_clk; ++ bool hs200_broken; + }; + + struct sdhci_at91_priv { +@@ -192,6 +194,8 @@ static const struct sdhci_pltfm_data sdh + static const struct sdhci_at91_soc_data soc_data_sama5d2 = { + .pdata = &sdhci_sama5d2_pdata, + .baseclk_is_generated_internally = false, ++ .max_sdr104_clk = 120000000, ++ .hs200_broken = true, + }; + + static const struct sdhci_at91_soc_data soc_data_sam9x60 = { +@@ -200,9 +204,17 @@ static const struct sdhci_at91_soc_data + .divider_for_baseclk = 2, + }; + ++static const struct sdhci_at91_soc_data soc_data_sama7g5 = { ++ .pdata = &sdhci_sama5d2_pdata, ++ .baseclk_is_generated_internally = true, ++ .divider_for_baseclk = 2, ++ .max_sdr104_clk = 200000000, ++}; ++ + static const struct of_device_id sdhci_at91_dt_match[] = { + { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, + { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, ++ { .compatible = "microchip,sama7g5-sdhci", .data = &soc_data_sama7g5 }, + {} + }; + MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); +@@ -259,7 +271,7 @@ static int sdhci_at91_set_clks_presets(s + preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; + writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, + host->ioaddr + SDHCI_PRESET_FOR_SDR50); +- preset_div = DIV_ROUND_UP(gck_rate, 120000000) - 1; ++ preset_div = DIV_ROUND_UP(gck_rate, priv->soc_data->max_sdr104_clk) - 1; + writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, + host->ioaddr + SDHCI_PRESET_FOR_SDR104); + preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; +@@ -425,8 +437,9 @@ static int sdhci_at91_probe(struct platf + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + +- /* HS200 is broken at this moment */ +- host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; ++ /* check if HS200 is broken on this platform */ ++ if (priv->soc_data->hs200_broken) ++ host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; + + ret = sdhci_add_host(host); + if (ret) diff --git a/target/linux/microchipsw/patches-6.12/109-mmc-sdhci-of-at91-add-support-for-HS400-and-HS400ES.patch b/target/linux/microchipsw/patches-6.12/109-mmc-sdhci-of-at91-add-support-for-HS400-and-HS400ES.patch new file mode 100644 index 0000000000..57837a87f5 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/109-mmc-sdhci-of-at91-add-support-for-HS400-and-HS400ES.patch @@ -0,0 +1,95 @@ +From 760de36744213a6bdfb84c7b7a51e3eea2e83d6c Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Wed, 1 Jul 2020 16:43:01 +0300 +Subject: [PATCH 087/110] mmc: sdhci-of-at91: add support for HS400 and HS400ES + +Add support for HS400 and HS400ES timings. + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 45 +++++++++++++++++++++++++++----- + 1 file changed, 39 insertions(+), 6 deletions(-) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -27,6 +27,9 @@ + #define SDMMC_MC1R_DDR BIT(3) + #define SDMMC_MC1R_RSTN BIT(6) + #define SDMMC_MC1R_FCD BIT(7) ++#define SDMMC_MC3R 0x206 ++#define SDMMC_MC3R_HS400EN BIT(0) ++#define SDMMC_MC3R_ESMEN BIT(1) + #define SDMMC_CACR 0x230 + #define SDMMC_CACR_CAPWREN BIT(0) + #define SDMMC_CACR_KEY (0x46 << 8) +@@ -103,18 +106,32 @@ static void sdhci_at91_set_clock(struct + static void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) + { +- u8 mc1r; +- u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ u16 clk; ++ u8 mc3r, mc1r; ++ ++ mc1r = readb(host->ioaddr + SDMMC_MC1R); ++ mc3r = readb(host->ioaddr + SDMMC_MC3R); ++ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); ++ + /* SDCLK must be disabled while changing the mode */ + if (clk & SDHCI_CLOCK_CARD_EN) + sdhci_writew(host, clk & ~SDHCI_CLOCK_CARD_EN, + SDHCI_CLOCK_CONTROL); + +- if (timing == MMC_TIMING_MMC_DDR52) { +- mc1r = sdhci_readb(host, SDMMC_MC1R); ++ if (timing == MMC_TIMING_MMC_DDR52 || timing == MMC_TIMING_MMC_HS400) + mc1r |= SDMMC_MC1R_DDR; +- sdhci_writeb(host, mc1r, SDMMC_MC1R); +- } ++ else ++ mc1r &= ~SDMMC_MC1R_DDR; ++ ++ sdhci_writeb(host, mc1r, SDMMC_MC1R); ++ ++ if (timing == MMC_TIMING_MMC_HS400) ++ mc3r |= SDMMC_MC3R_HS400EN; ++ else ++ mc3r &= ~SDMMC_MC3R_HS400EN; ++ ++ writeb(mc3r, host->ioaddr + SDMMC_MC3R); ++ + sdhci_set_uhs_signaling(host, timing); + + /* reenable SDCLK */ +@@ -366,6 +383,20 @@ static const struct dev_pm_ops sdhci_at9 + NULL) + }; + ++static void at91_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) ++{ ++ struct sdhci_host *host = mmc_priv(mmc); ++ u8 mc3r; ++ ++ mc3r = readb(host->ioaddr + SDMMC_MC3R); ++ if (ios->enhanced_strobe) ++ mc3r |= SDMMC_MC3R_ESMEN; ++ else ++ mc3r &= ~SDMMC_MC3R_ESMEN; ++ ++ writeb(mc3r, host->ioaddr + SDMMC_MC3R); ++} ++ + static int sdhci_at91_probe(struct platform_device *pdev) + { + const struct sdhci_at91_soc_data *soc_data; +@@ -445,6 +476,8 @@ static int sdhci_at91_probe(struct platf + if (ret) + goto pm_runtime_disable; + ++ host->mmc_host_ops.hs400_enhanced_strobe = at91_sdhci_hs400_enhanced_strobe; ++ + /* + * When calling sdhci_runtime_suspend_host(), the sdhci layer makes + * the assumption that all the clocks of the controller are disabled. diff --git a/target/linux/microchipsw/patches-6.12/110-sdhci-sdhci-of-at91-issue-IP-reset-at-probe.patch b/target/linux/microchipsw/patches-6.12/110-sdhci-sdhci-of-at91-issue-IP-reset-at-probe.patch new file mode 100644 index 0000000000..8dab7e7935 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/110-sdhci-sdhci-of-at91-issue-IP-reset-at-probe.patch @@ -0,0 +1,28 @@ +From bf303f307373baf222cb130253651b64c5533cf3 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Tue, 2 Jun 2020 12:36:13 +0300 +Subject: [PATCH 088/110] sdhci: sdhci-of-at91: issue IP reset at probe + +Issue IP reset at probe time. +This will avoid clock glitches if input clocks are being requested +again. + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -417,6 +417,9 @@ static int sdhci_at91_probe(struct platf + priv = sdhci_pltfm_priv(pltfm_host); + priv->soc_data = soc_data; + ++ /* Perform a software reset before using the IP */ ++ sdhci_at91_reset(host, SDHCI_RESET_ALL); ++ + priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); + if (IS_ERR(priv->mainck)) { + if (soc_data->baseclk_is_generated_internally) { diff --git a/target/linux/microchipsw/patches-6.12/111-mmc-sdhci-of-at91-perform-a-hardware-reset-at-probe-.patch b/target/linux/microchipsw/patches-6.12/111-mmc-sdhci-of-at91-perform-a-hardware-reset-at-probe-.patch new file mode 100644 index 0000000000..85e3398ad9 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/111-mmc-sdhci-of-at91-perform-a-hardware-reset-at-probe-.patch @@ -0,0 +1,28 @@ +From 32fa920f5dd8ba4b4ea79f2e9729bd57bed3db1b Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Fri, 3 Jul 2020 10:42:37 +0300 +Subject: [PATCH 089/110] mmc: sdhci-of-at91: perform a hardware reset at probe + time + +For eMMC, it may happen that the memory is left by the bootloader in a bad state. +We need to perform a hardware reset by asserting/deasserting the RSTN line. +This will ensure the memory comes out in a clean state. + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -419,6 +419,8 @@ static int sdhci_at91_probe(struct platf + + /* Perform a software reset before using the IP */ + sdhci_at91_reset(host, SDHCI_RESET_ALL); ++ /* Perform a hardware reset before using the IP */ ++ sdhci_at91_hw_reset(host); + + priv->mainck = devm_clk_get(&pdev->dev, "baseclk"); + if (IS_ERR(priv->mainck)) { diff --git a/target/linux/microchipsw/patches-6.12/112-mmc-sdhci-of-at91-add-preset-for-HS400-mode.patch b/target/linux/microchipsw/patches-6.12/112-mmc-sdhci-of-at91-add-preset-for-HS400-mode.patch new file mode 100644 index 0000000000..a36bf7b6b6 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/112-mmc-sdhci-of-at91-add-preset-for-HS400-mode.patch @@ -0,0 +1,36 @@ +From 01a24658497ed31d5b2de4c686772d27dcd19bbe Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Mon, 3 Aug 2020 15:29:37 +0300 +Subject: [PATCH 090/110] mmc: sdhci-of-at91: add preset for HS400 mode + +Add clock and driver strength preset for HS400 mode. + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -39,6 +39,9 @@ + + #define SDHCI_AT91_PRESET_COMMON_CONF 0x400 /* drv type B, programmable clock mode */ + ++/* drv type A, programmable clock mode */ ++#define SDHCI_AT91_PRESET_DRVA_CONF (SDHCI_AT91_PRESET_COMMON_CONF \ ++ | 0x4000) + struct sdhci_at91_soc_data { + const struct sdhci_pltfm_data *pdata; + bool baseclk_is_generated_internally; +@@ -294,6 +297,9 @@ static int sdhci_at91_set_clks_presets(s + preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; + writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, + host->ioaddr + SDHCI_PRESET_FOR_DDR50); ++ preset_div = DIV_ROUND_UP(gck_rate, priv->soc_data->max_sdr104_clk) - 1; ++ writew(SDHCI_AT91_PRESET_DRVA_CONF | preset_div, ++ host->ioaddr + SDHCI_PRESET_FOR_HS400); + + clk_prepare_enable(priv->mainck); + clk_prepare_enable(priv->gck); diff --git a/target/linux/microchipsw/patches-6.12/113-mmc-sdhci-of-at91-disable-selectively-clocks-on-pm-r.patch b/target/linux/microchipsw/patches-6.12/113-mmc-sdhci-of-at91-disable-selectively-clocks-on-pm-r.patch new file mode 100644 index 0000000000..5dffdb5a00 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/113-mmc-sdhci-of-at91-disable-selectively-clocks-on-pm-r.patch @@ -0,0 +1,66 @@ +From 23699095b2547a6714efb627783dc18478115328 Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 26 Nov 2020 20:15:09 +0200 +Subject: [PATCH 091/110] mmc: sdhci-of-at91: disable selectively clocks on pm + runtime + +SAMA7G5's SDMMC run-time clock disabling is not supported. +Add support to avoid this scenario for SAMA7G5. + +Signed-off-by: Claudiu Beznea +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 14 +++++++++++--- + 1 file changed, 11 insertions(+), 3 deletions(-) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -48,6 +48,7 @@ struct sdhci_at91_soc_data { + unsigned int divider_for_baseclk; + unsigned int max_sdr104_clk; + bool hs200_broken; ++ bool pm_runtime_disable_clks; + }; + + struct sdhci_at91_priv { +@@ -216,12 +217,14 @@ static const struct sdhci_at91_soc_data + .baseclk_is_generated_internally = false, + .max_sdr104_clk = 120000000, + .hs200_broken = true, ++ .pm_runtime_disable_clks = true, + }; + + static const struct sdhci_at91_soc_data soc_data_sam9x60 = { + .pdata = &sdhci_sama5d2_pdata, + .baseclk_is_generated_internally = true, + .divider_for_baseclk = 2, ++ .pm_runtime_disable_clks = true, + }; + + static const struct sdhci_at91_soc_data soc_data_sama7g5 = { +@@ -336,9 +339,11 @@ static int sdhci_at91_runtime_suspend(st + if (host->tuning_mode != SDHCI_TUNING_MODE_3) + mmc_retune_needed(host->mmc); + +- clk_disable_unprepare(priv->gck); +- clk_disable_unprepare(priv->hclock); +- clk_disable_unprepare(priv->mainck); ++ if (priv->soc_data->pm_runtime_disable_clks) { ++ clk_disable_unprepare(priv->gck); ++ clk_disable_unprepare(priv->hclock); ++ clk_disable_unprepare(priv->mainck); ++ } + + return ret; + } +@@ -359,6 +364,9 @@ static int sdhci_at91_runtime_resume(str + goto out; + } + ++ if (!priv->soc_data->pm_runtime_disable_clks) ++ goto out; ++ + ret = clk_prepare_enable(priv->mainck); + if (ret) { + dev_err(dev, "can't enable mainck\n"); diff --git a/target/linux/microchipsw/patches-6.12/114-mmc-sdhci-of-at91-do-not-advertise-SDR104-mode-suppo.patch b/target/linux/microchipsw/patches-6.12/114-mmc-sdhci-of-at91-do-not-advertise-SDR104-mode-suppo.patch new file mode 100644 index 0000000000..d28f55a7d1 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/114-mmc-sdhci-of-at91-do-not-advertise-SDR104-mode-suppo.patch @@ -0,0 +1,40 @@ +From 0538f47fa414e52843c75c3cc72790ad0ec196b8 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Fri, 20 Sep 2019 12:09:29 +0300 +Subject: [PATCH 092/110] mmc: sdhci-of-at91: do not advertise SDR104 mode + support + +There are several issues with SDR104 mode and tuning so remove it from +the capabilities of the host controller. + +Signed-off-by: Ludovic Desroches +[eugen.hristev@microchip.com: re-pick this commit was removed with upstream patch] +Signed-off-by: Eugen Hristev +Signed-off-by: Tudor Ambarus +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -256,6 +256,18 @@ static int sdhci_at91_set_clks_presets(s + caps0 = readl(host->ioaddr + SDHCI_CAPABILITIES); + caps1 = readl(host->ioaddr + SDHCI_CAPABILITIES_1); + ++ /* ++ * We experience some issues with SDR104. If the SD clock is higher ++ * than 100 MHz, we can get data corruption. With a 100 MHz clock, ++ * the tuning procedure may fail. For those reasons, it is useless to ++ * advertise that we can use SDR104 mode, so remove it from ++ * the capabilities. ++ */ ++ writel(SDMMC_CACR_KEY | SDMMC_CACR_CAPWREN, host->ioaddr + SDMMC_CACR); ++ caps1 &= (~SDHCI_SUPPORT_SDR104); ++ writel(caps1, host->ioaddr + SDHCI_CAPABILITIES_1); ++ writel(0, host->ioaddr + SDMMC_CACR); ++ + gck_rate = clk_get_rate(priv->gck); + if (priv->soc_data->baseclk_is_generated_internally) + clk_base_rate = gck_rate / priv->soc_data->divider_for_baseclk; diff --git a/target/linux/microchipsw/patches-6.12/115-mmc-sdhci-of-at91-avoid-division-by-zero.patch b/target/linux/microchipsw/patches-6.12/115-mmc-sdhci-of-at91-avoid-division-by-zero.patch new file mode 100644 index 0000000000..14742f38e2 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/115-mmc-sdhci-of-at91-avoid-division-by-zero.patch @@ -0,0 +1,48 @@ +From fa79ded408b14cbf687c7139eadce368c0f7003b Mon Sep 17 00:00:00 2001 +From: Claudiu Beznea +Date: Thu, 13 Jan 2022 13:18:24 +0200 +Subject: [PATCH 093/110] mmc: sdhci-of-at91: avoid division by zero + +Avoid division by zero and setting invalid values to address pointed +by SDHCI_PRESET_FOR_SDR104. + +Fixes: bac9f2f1caa5 ("mmc: sdhci-of-at91: add preset for HS400 mode") +Fixes: d85a06913358 ("mmc: sdhci-of-at91: add compatible to sama7g5 SoC") +Signed-off-by: Claudiu Beznea +Reviewed-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 18 ++++++++++++------ + 1 file changed, 12 insertions(+), 6 deletions(-) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -306,15 +306,21 @@ static int sdhci_at91_set_clks_presets(s + preset_div = DIV_ROUND_UP(gck_rate, 100000000) - 1; + writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, + host->ioaddr + SDHCI_PRESET_FOR_SDR50); +- preset_div = DIV_ROUND_UP(gck_rate, priv->soc_data->max_sdr104_clk) - 1; +- writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, +- host->ioaddr + SDHCI_PRESET_FOR_SDR104); ++ if (priv->soc_data->max_sdr104_clk) { ++ preset_div = DIV_ROUND_UP(gck_rate, ++ priv->soc_data->max_sdr104_clk) - 1; ++ writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, ++ host->ioaddr + SDHCI_PRESET_FOR_SDR104); ++ } + preset_div = DIV_ROUND_UP(gck_rate, 50000000) - 1; + writew(SDHCI_AT91_PRESET_COMMON_CONF | preset_div, + host->ioaddr + SDHCI_PRESET_FOR_DDR50); +- preset_div = DIV_ROUND_UP(gck_rate, priv->soc_data->max_sdr104_clk) - 1; +- writew(SDHCI_AT91_PRESET_DRVA_CONF | preset_div, +- host->ioaddr + SDHCI_PRESET_FOR_HS400); ++ if (priv->soc_data->max_sdr104_clk) { ++ preset_div = DIV_ROUND_UP(gck_rate, ++ priv->soc_data->max_sdr104_clk) - 1; ++ writew(SDHCI_AT91_PRESET_DRVA_CONF | preset_div, ++ host->ioaddr + SDHCI_PRESET_FOR_HS400); ++ } + + clk_prepare_enable(priv->mainck); + clk_prepare_enable(priv->gck); diff --git a/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-sama7g5-required-quirks.patch b/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-sama7g5-required-quirks.patch new file mode 100644 index 0000000000..5f74ac87e4 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-sama7g5-required-quirks.patch @@ -0,0 +1,24 @@ +From f1f3703830bfc8d35e1535f78f38a4b5799f0e99 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Mon, 19 Dec 2022 12:52:00 +0200 +Subject: [PATCH 095/110] mmc: sdhci-of-at91: add sama7g5 required quirks + +Add quirks for sama7g5 product + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -232,6 +232,7 @@ static const struct sdhci_at91_soc_data + .baseclk_is_generated_internally = true, + .divider_for_baseclk = 2, + .max_sdr104_clk = 200000000, ++ .quirks2 = SDHCI_QUIRK2_AT91_HS400_PRESET, + }; + + static const struct of_device_id sdhci_at91_dt_match[] = { diff --git a/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-soc-data-field-quirks2.patch b/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-soc-data-field-quirks2.patch new file mode 100644 index 0000000000..69d2562413 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/116-mmc-sdhci-of-at91-add-soc-data-field-quirks2.patch @@ -0,0 +1,50 @@ +From 63c7037be0a9c8e1155b78ce6448cc012401e441 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Mon, 19 Dec 2022 12:17:42 +0200 +Subject: [PATCH 094/110] mmc: sdhci-of-at91: add soc data field quirks2 + +Add a quirks2 field in the soc_data struct, this replaces +the hs200_broken bool. The purpose is to be able to add multiple +quirks in the soc_data without having bools for each of them. +Storing them in a single variable makes the code cleaner. + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/at91/mmc) +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci-of-at91.c | 8 +++----- + 1 file changed, 3 insertions(+), 5 deletions(-) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -47,8 +47,8 @@ struct sdhci_at91_soc_data { + bool baseclk_is_generated_internally; + unsigned int divider_for_baseclk; + unsigned int max_sdr104_clk; +- bool hs200_broken; + bool pm_runtime_disable_clks; ++ u32 quirks2; + }; + + struct sdhci_at91_priv { +@@ -216,8 +216,8 @@ static const struct sdhci_at91_soc_data + .pdata = &sdhci_sama5d2_pdata, + .baseclk_is_generated_internally = false, + .max_sdr104_clk = 120000000, +- .hs200_broken = true, + .pm_runtime_disable_clks = true, ++ .quirks2 = SDHCI_QUIRK2_BROKEN_HS200, + }; + + static const struct sdhci_at91_soc_data soc_data_sam9x60 = { +@@ -506,9 +506,7 @@ static int sdhci_at91_probe(struct platf + pm_runtime_set_autosuspend_delay(&pdev->dev, 50); + pm_runtime_use_autosuspend(&pdev->dev); + +- /* check if HS200 is broken on this platform */ +- if (priv->soc_data->hs200_broken) +- host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; ++ host->quirks2 |= priv->soc_data->quirks2; + + ret = sdhci_add_host(host); + if (ret) diff --git a/target/linux/microchipsw/patches-6.12/117-mmc-introduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch b/target/linux/microchipsw/patches-6.12/117-mmc-introduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch new file mode 100644 index 0000000000..8c72d543e6 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/117-mmc-introduce-SDHCI_QUIRK2_AT91_HS400_PRESET.patch @@ -0,0 +1,37 @@ +From 87ec8e4cb7d7e13d51c351c7e2fcb069081d54c4 Mon Sep 17 00:00:00 2001 +From: Eugen Hristev +Date: Mon, 3 Aug 2020 15:30:49 +0300 +Subject: [PATCH 096/110] mmc: introduce SDHCI_QUIRK2_AT91_HS400_PRESET + +AT91 architecture uses a different HS400 preset register offset. + +Signed-off-by: Eugen Hristev +(cherry picked from linux-6.1-trunk/mmc) +[andrei.simion: increment the value for left shift for + AT91 specific HS400 preset register] +Signed-off-by: Andrei Simion +--- + drivers/mmc/host/sdhci.h | 5 +++++ + 1 file changed, 5 insertions(+) + +--- a/drivers/mmc/host/sdhci.h ++++ b/drivers/mmc/host/sdhci.h +@@ -270,6 +270,7 @@ + #define SDHCI_PRESET_FOR_SDR104 0x6C + #define SDHCI_PRESET_FOR_DDR50 0x6E + #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */ ++#define SDHCI_PRESET_FOR_HS400_AT91 0x244 /* AT91 specific */ + #define SDHCI_PRESET_DRV_MASK GENMASK(15, 14) + #define SDHCI_PRESET_CLKGEN_SEL BIT(10) + #define SDHCI_PRESET_SDCLK_FREQ_MASK GENMASK(9, 0) +@@ -484,6 +485,10 @@ struct sdhci_host { + #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) + /* Issue CMD and DATA reset together */ + #define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) ++/* ++ * AT91 specific HS400 preset register ++ */ ++#define SDHCI_QUIRK2_AT91_HS400_PRESET (1<<20) + + int irq; /* Device IRQ */ + void __iomem *ioaddr; /* Mapped address */ diff --git a/target/linux/microchipsw/patches-6.12/118-mmc-mmc-sdhci-of-at91-add-LAN969x.patch b/target/linux/microchipsw/patches-6.12/118-mmc-mmc-sdhci-of-at91-add-LAN969x.patch new file mode 100644 index 0000000000..0f5c21ed1d --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/118-mmc-mmc-sdhci-of-at91-add-LAN969x.patch @@ -0,0 +1,33 @@ +From d3f47257f94abccd0e0dc61221cd3f36d3c8adfd Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Tue, 5 Nov 2024 15:48:27 +0100 +Subject: [PATCH 097/110] mmc: mmc: sdhci-of-at91: add LAN969x + +Add support for LAN969x SoC. + +Signed-off-by: Robert Marko +--- + drivers/mmc/host/sdhci-of-at91.c | 8 ++++++++ + 1 file changed, 8 insertions(+) + +--- a/drivers/mmc/host/sdhci-of-at91.c ++++ b/drivers/mmc/host/sdhci-of-at91.c +@@ -235,10 +235,18 @@ static const struct sdhci_at91_soc_data + .quirks2 = SDHCI_QUIRK2_AT91_HS400_PRESET, + }; + ++static const struct sdhci_at91_soc_data soc_data_lan969x = { ++ .pdata = &sdhci_sama5d2_pdata, ++ .max_sdr104_clk = 100000000, ++ .baseclk_is_generated_internally = true, ++ .divider_for_baseclk = 2, ++}; ++ + static const struct of_device_id sdhci_at91_dt_match[] = { + { .compatible = "atmel,sama5d2-sdhci", .data = &soc_data_sama5d2 }, + { .compatible = "microchip,sam9x60-sdhci", .data = &soc_data_sam9x60 }, + { .compatible = "microchip,sama7g5-sdhci", .data = &soc_data_sama7g5 }, ++ { .compatible = "microchip,lan9691-sdhci", .data = &soc_data_lan969x }, + {} + }; + MODULE_DEVICE_TABLE(of, sdhci_at91_dt_match); diff --git a/target/linux/microchipsw/patches-6.12/119-spi-atmel-quadspi-Add-support-for-LAN969x-QSPI0.patch b/target/linux/microchipsw/patches-6.12/119-spi-atmel-quadspi-Add-support-for-LAN969x-QSPI0.patch new file mode 100644 index 0000000000..cd32fcd8b2 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/119-spi-atmel-quadspi-Add-support-for-LAN969x-QSPI0.patch @@ -0,0 +1,80 @@ +From 9df17cd4cbde177d11fe5b42209cb07a8cc5fd2a Mon Sep 17 00:00:00 2001 +From: Robert Marko +Date: Mon, 22 Sep 2025 16:30:16 +0200 +Subject: [PATCH 112/112] spi: atmel-quadspi: Add support for LAN969x QSPI0 + +LAN969x has a similar QSPI0 controller to sama7g5 but with no octal mode +support. + +Sadly, DMA does not currently work and auto refresh must be disabled as +otherwise board will simply freeze. + +Signed-off-by: Robert Marko +--- + drivers/spi/Kconfig | 2 +- + drivers/spi/atmel-quadspi.c | 21 ++++++++++++++++++--- + 2 files changed, 19 insertions(+), 4 deletions(-) + +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -147,7 +147,7 @@ config SPI_AT91_USART + + config SPI_ATMEL_QUADSPI + tristate "Atmel Quad SPI Controller" +- depends on ARCH_AT91 || COMPILE_TEST ++ depends on ARCH_MICROCHIP || COMPILE_TEST + depends on OF && HAS_IOMEM + help + This enables support for the Quad SPI controller in master mode. +--- a/drivers/spi/atmel-quadspi.c ++++ b/drivers/spi/atmel-quadspi.c +@@ -1053,9 +1053,9 @@ static int atmel_qspi_set_pad_calibratio + ATMEL_QSPI_TIMEOUT); + + /* Refresh analogic blocks every 1 ms.*/ +- atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, ++ /*atmel_qspi_write(FIELD_PREP(QSPI_REFRESH_DELAY_COUNTER, + aq->target_max_speed_hz / 1000), +- aq, QSPI_REFRESH); ++ aq, QSPI_REFRESH);*/ + + return ret; + } +@@ -1114,7 +1114,7 @@ static int atmel_qspi_sama7g5_init(struc + * Check if the SoC supports pad calibration in Octal SPI mode. + * Proceed only if both the capabilities are true. + */ +- if (aq->caps->octal && aq->caps->has_padcalib) { ++ if (aq->caps->has_padcalib) { + ret = atmel_qspi_set_pad_calibration(aq); + if (ret) + return ret; +@@ -1649,6 +1649,17 @@ static const struct atmel_qspi_caps atme + .has_dllon = true, + }; + ++static const struct atmel_qspi_caps microchip_lan969x_qspi_caps = { ++ .max_speed_hz = SAM9X7_QSPI_MAX_SPEED_HZ, ++ .has_gclk = true, ++ .octal = false, ++ /* It supports using DMA but its currently broken */ ++ .has_dma = false, ++ .has_2xgclk = false, ++ .has_padcalib = true, ++ .has_dllon = true, ++}; ++ + static const struct of_device_id atmel_qspi_dt_ids[] = { + { + .compatible = "atmel,sama5d2-qspi", +@@ -1678,6 +1689,10 @@ static const struct of_device_id atmel_q + .compatible = "microchip,sama7d65-qspi", + .data = &atmel_sama7d65_qspi_caps, + }, ++ { ++ .compatible = "microchip,lan9691-qspi", ++ .data = µchip_lan969x_qspi_caps, ++ }, + + + { /* sentinel */ } diff --git a/target/linux/microchipsw/patches-6.12/121-nvmem-lan9662-otp-add-support-for-LAN969x.patch b/target/linux/microchipsw/patches-6.12/121-nvmem-lan9662-otp-add-support-for-LAN969x.patch new file mode 100644 index 0000000000..c317ebdab8 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/121-nvmem-lan9662-otp-add-support-for-LAN969x.patch @@ -0,0 +1,68 @@ +From 7ec8c81eae48ceb1e07a00be65716769827b747e Mon Sep 17 00:00:00 2001 +From: Horatiu Vultur +Date: Wed, 3 Jan 2024 11:10:44 +0100 +Subject: [PATCH] nvmem: lan9662-otp: add support for LAN969x + +Microchip LAN969x provides OTP with the same control logic, only the size +differs as LAN969x has 16KB of OTP instead of 8KB like on LAN966x. + +Signed-off-by: Horatiu Vultur +Signed-off-by: Robert Marko +--- + drivers/nvmem/Kconfig | 2 +- + drivers/nvmem/lan9662-otpc.c | 12 +++++++++--- + 2 files changed, 10 insertions(+), 4 deletions(-) + +--- a/drivers/nvmem/Kconfig ++++ b/drivers/nvmem/Kconfig +@@ -127,7 +127,7 @@ config NVMEM_JZ4780_EFUSE + + config NVMEM_LAN9662_OTPC + tristate "Microchip LAN9662 OTP controller support" +- depends on SOC_LAN966 || COMPILE_TEST ++ depends on SOC_LAN966 || ARCH_LAN969X || COMPILE_TEST + depends on HAS_IOMEM + help + This driver enables the OTP controller available on Microchip LAN9662 +--- a/drivers/nvmem/lan9662-otpc.c ++++ b/drivers/nvmem/lan9662-otpc.c +@@ -27,7 +27,6 @@ + #define OTP_OTP_STATUS_OTP_CPUMPEN BIT(1) + #define OTP_OTP_STATUS_OTP_BUSY BIT(0) + +-#define OTP_MEM_SIZE 8192 + #define OTP_SLEEP_US 10 + #define OTP_TIMEOUT_US 500000 + +@@ -176,7 +175,6 @@ static struct nvmem_config otp_config = + .word_size = 1, + .reg_read = lan9662_otp_read, + .reg_write = lan9662_otp_write, +- .size = OTP_MEM_SIZE, + }; + + static int lan9662_otp_probe(struct platform_device *pdev) +@@ -196,6 +194,7 @@ static int lan9662_otp_probe(struct plat + + otp_config.priv = otp; + otp_config.dev = dev; ++ otp_config.size = (uintptr_t) device_get_match_data(dev); + + nvmem = devm_nvmem_register(dev, &otp_config); + +@@ -203,7 +202,14 @@ static int lan9662_otp_probe(struct plat + } + + static const struct of_device_id lan9662_otp_match[] = { +- { .compatible = "microchip,lan9662-otpc", }, ++ { ++ .compatible = "microchip,lan9662-otpc", ++ .data = (const void *) SZ_8K, ++ }, ++ { ++ .compatible = "microchip,lan9691-otpc", ++ .data = (const void *) SZ_16K, ++ }, + { }, + }; + MODULE_DEVICE_TABLE(of, lan9662_otp_match); diff --git a/target/linux/microchipsw/patches-6.12/900-dmaengine-at_xdmac-get-the-number-of-DMA-channels-fr.patch b/target/linux/microchipsw/patches-6.12/900-dmaengine-at_xdmac-get-the-number-of-DMA-channels-fr.patch new file mode 100644 index 0000000000..9069451315 --- /dev/null +++ b/target/linux/microchipsw/patches-6.12/900-dmaengine-at_xdmac-get-the-number-of-DMA-channels-fr.patch @@ -0,0 +1,64 @@ +From cb65fd2bb68fdbf719d1ce08b11b92d431be8a84 Mon Sep 17 00:00:00 2001 +From: Tony Han +Date: Tue, 12 Dec 2023 13:32:42 +0800 +Subject: [PATCH] dmaengine: at_xdmac: get the number of DMA channels from + device tree + +In case of kernel runs in non-secure mode, the number of DMA channels can +be got from device tree since the value read from GTYPE register is "0" as +it's always secured. +As the number of channels can never be negative, update them to the type +"unsigned". + +Signed-off-by: Tony Han +Reviewed-by: Cristian Birsan +--- + drivers/dma/at_xdmac.c | 26 +++++++++++++++++++++++--- + 1 file changed, 23 insertions(+), 3 deletions(-) + +--- a/drivers/dma/at_xdmac.c ++++ b/drivers/dma/at_xdmac.c +@@ -2259,12 +2259,29 @@ static int __maybe_unused atmel_xdmac_ru + return clk_enable(atxdmac->clk); + } + ++static inline int at_xdmac_get_channel_number(struct platform_device *pdev, ++ u32 reg, u32 *pchannels) ++{ ++ int ret; ++ ++ if (reg) { ++ *pchannels = AT_XDMAC_NB_CH(reg); ++ return 0; ++ } ++ ++ ret = of_property_read_u32(pdev->dev.of_node, "dma-channels", pchannels); ++ if (ret) ++ dev_err(&pdev->dev, "can't get number of channels\n"); ++ ++ return ret; ++} ++ + static int at_xdmac_probe(struct platform_device *pdev) + { + struct at_xdmac *atxdmac; +- int irq, nr_channels, i, ret; ++ int irq, ret; + void __iomem *base; +- u32 reg; ++ u32 nr_channels, i, reg; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) +@@ -2280,7 +2297,10 @@ static int at_xdmac_probe(struct platfor + * of channels to do the allocation. + */ + reg = readl_relaxed(base + AT_XDMAC_GTYPE); +- nr_channels = AT_XDMAC_NB_CH(reg); ++ ret = at_xdmac_get_channel_number(pdev, reg, &nr_channels); ++ if (ret) ++ return ret; ++ + if (nr_channels > AT_XDMAC_MAX_CHAN) { + dev_err(&pdev->dev, "invalid number of channels (%u)\n", + nr_channels); From 5205c0c426073aed5912d2bf35f3a3b56670911e Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Thu, 25 Sep 2025 22:44:10 +0200 Subject: [PATCH 2/6] microchipsw: lan969x: add Microchip EV23X71A Microchip EV23X71A is a LAN9696 based EVB. Specifications: * CPU: Microchip LAN9696 switch SoC * DRAM: 1GB DDR4 * Storage: * 2MB QSPI NOR * 4GB eMMC * Networking: * 24 x 10/100/1000 RJ45 via LAN8814 Quad PHY-s over QSGMII * 4 x 100/1000/2500/5000/10000 SFP+ ports * 1 x 10/100/1000 management RJ45 via LAN8840 PHY over RGMII (U-Boot too) * USB: 1 x USB2.0 Type-A * Management via USB-C (MCP2200): * UART @ 115200 baud * GPIO-s for bootstrap, reset and clock selection * DIP switch for boostrap configuration * LED-s: * 2 per networking port (Green and Yellow) * Green status LED * Yellow reset LED * Hard reset button * Power: * 12V DC barrel jack * 48/56V DC screw terminal * Selectable via toggle switch * PTP support: * Sync-E DPLL ZL30732B to generate the board required clocks * Two SMAs for PTP and two for Station clock inputs and outputs * Two ITU-T G.8275-compliant RS-422 interfaces for PTP applications * External PoE: * Option for PoE add-on, like EV14Y36A (IEEE 802.3af/at/bt Type 4 standard com-pliant) * Option for external CPU control via SPI and PCIe Installation instructions: 1. Connect to UART via the USB-C port 2. Connect the management port 3. Boot and interrupt U-Boot 4. TFTP the OpenWrt initramfs image and boot it 5. SCP the OpenWrt eMMC GPT image to a running OpenWrt initramfs to /tmp openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img.gz And decompress it via: gzip -d /tmp/openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img.gz 6. Wipe eMMC with: dd if=/dev/zero of=/dev/mmcblk0 bs=1M 7. Flash OpenWrt eMMC image with: dd if=/tmp/openwrt-microchipsw-lan969x-microchip_ev23x71a-squashfs-emmc-gpt.img of=/dev/mmcblk0 After a restart OpenWrt will boot, and then regular sysupgrade can be used for upgrades. Signed-off-by: Robert Marko --- config/Config-images.in | 2 +- .../arm-trusted-firmware-microchipsw/Makefile | 78 ++ package/boot/uboot-microchipsw/Makefile | 37 + .../patches/200-cmd-add-imsz-and-imszb.patch | 139 ++++ .../src/board/microchip/lan969x/lan969x.env | 10 + .../microchipsw/dts/lan9696-ev23x71a.dts | 787 ++++++++++++++++++ target/linux/microchipsw/image/Makefile | 2 + target/linux/microchipsw/image/lan969x.mk | 41 + .../lan969x/base-files/etc/board.d/01_leds | 23 + .../lan969x/base-files/etc/board.d/02_network | 25 + .../base-files/lib/upgrade/platform.sh | 31 + .../linux/microchipsw/lan969x/config-default | 1 + target/linux/microchipsw/lan969x/target.mk | 5 +- 13 files changed, 1179 insertions(+), 2 deletions(-) create mode 100644 package/boot/arm-trusted-firmware-microchipsw/Makefile create mode 100644 package/boot/uboot-microchipsw/Makefile create mode 100644 package/boot/uboot-microchipsw/patches/200-cmd-add-imsz-and-imszb.patch create mode 100644 package/boot/uboot-microchipsw/src/board/microchip/lan969x/lan969x.env create mode 100644 target/linux/microchipsw/dts/lan9696-ev23x71a.dts create mode 100644 target/linux/microchipsw/image/lan969x.mk create mode 100644 target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds create mode 100644 target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network create mode 100644 target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh diff --git a/config/Config-images.in b/config/Config-images.in index 9b04ddbeec..fcc5fa52cb 100644 --- a/config/Config-images.in +++ b/config/Config-images.in @@ -336,7 +336,7 @@ menu "Target Images" int "Root filesystem partition size (in MiB)" depends on USES_ROOTFS_PART || TARGET_ROOTFS_EXT4FS default 232 if TARGET_loongarch64 - default 448 if TARGET_mediatek + default 448 if TARGET_mediatek || TARGET_microchipsw default 104 help Select the root filesystem partition size. diff --git a/package/boot/arm-trusted-firmware-microchipsw/Makefile b/package/boot/arm-trusted-firmware-microchipsw/Makefile new file mode 100644 index 0000000000..fae462aa0b --- /dev/null +++ b/package/boot/arm-trusted-firmware-microchipsw/Makefile @@ -0,0 +1,78 @@ +include $(TOPDIR)/rules.mk + +PKG_NAME:=arm-trusted-firmware-microchipsw +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL=https://github.com/microchip-ung/arm-trusted-firmware.git +PKG_SOURCE_DATE:=2024-08-13 +PKG_SOURCE_VERSION:=67fcfcab71f78ac7d4af834c37b29f8c98dd5ff1 +PKG_MIRROR_HASH:=777c68273e84028de77750f3fe8a1219b02f01d43ce35948893ac642d8eb10d7 + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/kernel.mk +include $(INCLUDE_DIR)/trusted-firmware-a.mk +include $(INCLUDE_DIR)/package.mk + +define Trusted-Firmware-A/Default + BUILD_TARGET:=microchipsw + TFA_IMAGE:=fip.bin fwu_fip.bin fwu.html +endef + +define Trusted-Firmware-A/ev23x71a + NAME:=Microchip EV23X71A + BUILD_SUBTARGET:=lan969x + BUILD_DEVICES:=microchip_ev23x71a + PLAT:=lan969x_a0 + DEPENDS:=+u-boot-ev23x71a +endef + +TFA_TARGETS:= ev23x71a + +MBEDTLS_NAME:=mbedtls +MBEDTLS_RELEASE:=2.28.10 +MBEDTLS_SOURCE:=$(MBEDTLS_NAME)-$(MBEDTLS_RELEASE).tar.zst + +define Download/mbedtls + FILE:=$(MBEDTLS_SOURCE) + PROTO:=git + URL:=https://github.com/Mbed-TLS/mbedtls.git + SOURCE_VERSION:=2fc8413bfcb51354c8e679141b17b3f1a5942561 + MIRROR_HASH:=40b94a76572ad1ca89738929ab81d6024f678f22691eb3bd633c076ac18a334a + SUBDIR:=$(MBEDTLS_NAME) +endef + +define Build/Prepare + # Download mbedtls + $(eval $(call Download,mbedtls)) + + $(call Build/Prepare/Default,) + + $(TAR) -C $(PKG_BUILD_DIR) -xf $(DL_DIR)/$(MBEDTLS_SOURCE) +endef + +# We must not pass OPENSSL_DIR as locally built mbedtls is used +define Build/Compile + +unset CC; \ + $(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \ + CROSS_COMPILE=$(TARGET_CROSS) \ + $(if $(DTC),DTC="$(DTC)") \ + PLAT=$(PLAT) \ + BUILD_STRING="OpenWrt $(PKG_VERSION_PREFIX)$(PKG_VERSION)-$(PKG_RELEASE) ($(VARIANT))" \ + $(TFA_MAKE_FLAGS) +endef + +TFA_MAKE_FLAGS += \ + MBEDTLS_DIR=$(PKG_BUILD_DIR)/$(MBEDTLS_NAME) \ + BL33=$(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.bin \ + KEY_ALG=ecdsa GENERATE_COT=1 TRUSTED_BOARD_BOOT=1 \ + all fip fwu_fip + +define Package/trusted-firmware-a/install + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(INSTALL_DATA) $(PKG_BUILD_DIR)/build/$(PLAT)/release/fip.bin $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-fip.bin + $(CP) $(patsubst %,$(PKG_BUILD_DIR)/build/$(PLAT)/release/%,$(TFA_IMAGE)) $(1)/ +endef + +$(eval $(call BuildPackage/Trusted-Firmware-A)) diff --git a/package/boot/uboot-microchipsw/Makefile b/package/boot/uboot-microchipsw/Makefile new file mode 100644 index 0000000000..f727739276 --- /dev/null +++ b/package/boot/uboot-microchipsw/Makefile @@ -0,0 +1,37 @@ +include $(TOPDIR)/rules.mk + +PKG_RELEASE:=1 + +PKG_SOURCE_PROTO:=git +PKG_SOURCE_URL:=https://github.com/microchip-ung/u-boot.git +PKG_SOURCE_DATE:=2025-09-22 +PKG_SOURCE_VERSION:=c1abab62a00a6b8f43f663a0a30dd0a7fd6a4e95 +PKG_MIRROR_HASH:=6405c426afd8bacbb4cc985da4ca1bd04b54a0d2aa3bb3ba8f7571dbe5913055 + +PKG_MAINTAINER:=Robert Marko + +include $(INCLUDE_DIR)/u-boot.mk +include $(INCLUDE_DIR)/package.mk +include $(INCLUDE_DIR)/kernel.mk + +define U-Boot/Default + BUILD_TARGET:=microchipsw + HIDDEN:=1 + UBOOT_IMAGE:=u-boot.bin +endef + +define U-Boot/ev23x71a + NAME:=Microchip EV23X71A + BUILD_DEVICES:=microchip_ev23x71a + BUILD_SUBTARGET:=lan969x + UBOOT_CONFIG:=mchp_lan969x +endef + +UBOOT_TARGETS:= ev23x71a + +define Build/InstallDev + $(INSTALL_DIR) $(STAGING_DIR_IMAGE) + $(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-$(UBOOT_IMAGE) +endef + +$(eval $(call BuildPackage/U-Boot)) diff --git a/package/boot/uboot-microchipsw/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-microchipsw/patches/200-cmd-add-imsz-and-imszb.patch new file mode 100644 index 0000000000..9872ccbf26 --- /dev/null +++ b/package/boot/uboot-microchipsw/patches/200-cmd-add-imsz-and-imszb.patch @@ -0,0 +1,139 @@ +--- a/cmd/bootm.c ++++ b/cmd/bootm.c +@@ -260,6 +260,76 @@ U_BOOT_CMD( + /* iminfo - print header info for a requested image */ + /*******************************************************************/ + #if defined(CONFIG_CMD_IMI) ++#define SECTOR_SHIFT 9 ++static int image_totalsize(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[], short int in_blocks) ++{ ++ ulong addr; ++ void *hdr; ++ uint32_t bsize, tsize = 0; ++ char buf[16]; ++ ++ if (argc >= 2) ++ addr = simple_strtoul(argv[1], NULL, 16); ++ else ++ addr = image_load_addr; ++ ++ hdr = (void *)map_sysmem(addr, 0); ++ ++ switch (genimg_get_format(hdr)) { ++ case IMAGE_FORMAT_LEGACY: ++ if(CONFIG_IS_ENABLED(LEGACY_IMAGE_FORMAT)) ++ tsize = image_get_image_size(hdr); ++ break; ++ case IMAGE_FORMAT_FIT: ++ if(CONFIG_IS_ENABLED(FIT)) ++ tsize = fit_get_totalsize(hdr); ++ break; ++ } ++ ++ unmap_sysmem(hdr); ++ if (tsize == 0) ++ return 1; ++ ++ bsize = (tsize >> SECTOR_SHIFT) + ((tsize & ((1 << SECTOR_SHIFT) - 1))?1:0); ++ ++ if (!in_blocks) ++ snprintf(buf, sizeof(buf), "%x", tsize); ++ else ++ snprintf(buf, sizeof(buf), "%x", bsize); ++ ++ if (argc >= 3) ++ return env_set(argv[2], buf); ++ else ++ printf("%s\n", buf); ++ ++ return 0; ++} ++ ++static int do_imsz(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ return image_totalsize(cmdtp, flag, argc, argv, 0); ++} ++ ++static int do_imszb(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ return image_totalsize(cmdtp, flag, argc, argv, 1); ++} ++ ++U_BOOT_CMD( ++ imsz, CONFIG_SYS_MAXARGS, 1, do_imsz, ++ "get image total size (in bytes)", ++ "addr [maxhdrlen] [varname]\n" ++); ++ ++U_BOOT_CMD( ++ imszb, CONFIG_SYS_MAXARGS, 1, do_imszb, ++ "get image total size (in blocks)", ++ "addr [maxhdrlen] [varname]\n" ++); ++ + static int do_iminfo(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) + { +--- a/boot/image-fit.c ++++ b/boot/image-fit.c +@@ -2054,6 +2054,47 @@ static const char *fit_get_image_type_pr + return "unknown"; + } + ++size_t fit_get_totalsize(const void *fit) ++{ ++ int ret, ndepth, noffset, images_noffset; ++ size_t data_size, hdrsize, img_total, max_size = 0; ++ const void *data; ++ ++ ret = fdt_check_header(fit); ++ if (ret) { ++ debug("Wrong FIT format: not a flattened device tree (err=%d)\n", ++ ret); ++ return 0; ++ } ++ ++ hdrsize = fdt_totalsize(fit); ++ ++ /* take care of simple FIT with internal images */ ++ max_size = hdrsize; ++ ++ images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); ++ if (images_noffset < 0) ++ goto out; ++ ++ for (ndepth = 0, ++ noffset = fdt_next_node(fit, images_noffset, &ndepth); ++ (noffset >= 0) && (ndepth > 0); ++ noffset = fdt_next_node(fit, noffset, &ndepth)) { ++ if (ndepth == 1) { ++ ret = fit_image_get_data(fit, noffset, &data, &data_size); ++ if (ret) ++ goto out; ++ ++ img_total = data_size + (data - fit); ++ ++ max_size = (max_size > img_total) ? max_size : img_total; ++ } ++ } ++ ++out: ++ return max_size; ++} ++ + int fit_image_load(struct bootm_headers *images, ulong addr, + const char **fit_unamep, const char **fit_uname_configp, + int arch, int ph_type, int bootstage_id, +--- a/include/image.h ++++ b/include/image.h +@@ -1113,6 +1113,7 @@ int fit_parse_subimage(const char *spec, + ulong *addr, const char **image_name); + + int fit_get_subimage_count(const void *fit, int images_noffset); ++size_t fit_get_totalsize(const void *fit); + void fit_print_contents(const void *fit); + void fit_image_print(const void *fit, int noffset, const char *p); + diff --git a/package/boot/uboot-microchipsw/src/board/microchip/lan969x/lan969x.env b/package/boot/uboot-microchipsw/src/board/microchip/lan969x/lan969x.env new file mode 100644 index 0000000000..4ea48bca0c --- /dev/null +++ b/package/boot/uboot-microchipsw/src/board/microchip/lan969x/lan969x.env @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +fdt_high=0xffffffff +baudrate=115200 +bootdelay=3 +loadaddr=0x64000000 +bootargs=console=ttyAT0,115200 root=PARTLABEL=rootfs rootwait +mmc_read_kernel=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr $part_addr $image_size +boot_system=part start mmc 0 kernel part_addr && part size mmc 0 kernel part_size && run mmc_read_kernel && bootm +bootcmd=run boot_system diff --git a/target/linux/microchipsw/dts/lan9696-ev23x71a.dts b/target/linux/microchipsw/dts/lan9696-ev23x71a.dts new file mode 100644 index 0000000000..2ccc0345ac --- /dev/null +++ b/target/linux/microchipsw/dts/lan9696-ev23x71a.dts @@ -0,0 +1,787 @@ +/dts-v1/; + +#include +#include +#include "lan969x.dtsi" + +/ { + model = "Microchip EV23X71A"; + compatible = "microchip,ev23x71a", "microchip,lan969x"; + + aliases { + serial0 = &usart0; + led-boot = &led_status; + led-failsafe = &led_status; + led-running = &led_status; + led-upgrade = &led_status; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio 60 GPIO_ACTIVE_LOW>; + open-source; + priority = <200>; + }; + + i2c-mux { + compatible = "i2c-mux-gpio"; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c3>; + + mux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH + &sgpio_out 0 2 GPIO_ACTIVE_HIGH + &sgpio_out 0 3 GPIO_ACTIVE_HIGH>; + idle-state = <0x8>; + + i2c_sfp0: i2c@0 { + reg = <0x0>; + }; + + i2c_sfp1: i2c@1 { + reg = <0x1>; + }; + + i2c_sfp2: i2c@2 { + reg = <0x2>; + }; + + i2c_sfp3: i2c@3 { + reg = <0x3>; + }; + + i2c_poe: i2c@7 { + reg = <0x7>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status: led-status { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&gpio 61 GPIO_ACTIVE_LOW>; + }; + + led-sfp1-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp1-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <0>; + gpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp2-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp2-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + gpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp3-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp3-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + gpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp4-green { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led-sfp4-yellow { + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <3>; + gpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + mux-controller { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>, + <&sgpio_out 1 3 GPIO_ACTIVE_LOW>; + }; + + sfp0: sfp0 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp0>; + tx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + tx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>; + }; + + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + tx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>; + }; + + sfp3: sfp3 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp3>; + tx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>; + los-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>; + tx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&usart0 { + pinctrl-0 = <&fc0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&flx2 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&spi2 { + pinctrl-0 = <&fc2_pins>; + pinctrl-names = "default"; + cs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&flx3 { + atmel,flexcom-mode = ; + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&fc3_pins>; + pinctrl-names = "default"; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + i2c-sda-hold-time-ns = <1500>; + status = "okay"; +}; + +&gpio { + emmc_sd_pins: emmc-sd-pins { + /* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */ + pins = "GPIO_14", "GPIO_15", "GPIO_16", "GPIO_17", + "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_21", + "GPIO_22", "GPIO_23", "GPIO_24"; + function = "emmc_sd"; + }; + + fan_pins: fan-pins { + pins = "GPIO_25", "GPIO_26"; + function = "fan"; + }; + + fc0_pins: fc0-pins { + pins = "GPIO_3", "GPIO_4"; + function = "fc"; + }; + + fc2_pins: fc2-pins { + pins = "GPIO_64", "GPIO_65", "GPIO_66"; + function = "fc"; + }; + + fc3_pins: fc3-pins { + pins = "GPIO_55", "GPIO_56"; + function = "fc"; + }; + + mdio_pins: mdio-pins { + pins = "GPIO_9", "GPIO_10"; + function = "miim"; + }; + + mdio_irq_pins: mdio-irq-pins { + pins = "GPIO_11"; + function = "miim_irq"; + }; + + sgpio_pins: sgpio-pins { + /* SCK, D0, D1, LD */ + pins = "GPIO_5", "GPIO_6", "GPIO_7", "GPIO_8"; + function = "sgpio_a"; + }; + + usb_ulpi_pins: usb-ulpi-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", "GPIO_33", + "GPIO_34", "GPIO_35", "GPIO_36", "GPIO_37", + "GPIO_38", "GPIO_39", "GPIO_40", "GPIO_41"; + function = "usb_ulpi"; + }; + + usb_rst_pins: usb-rst-pins { + pins = "GPIO_12"; + function = "usb2phy_rst"; + }; + + usb_over_pins: usb-over-pins { + pins = "GPIO_13"; + function = "usb_over_detect"; + }; + + usb_power_pins: usb-power-pins { + pins = "GPIO_1"; + function = "usb_power"; + }; + + ptp_out_pins: ptp-out-pins { + pins = "GPIO_58"; + function = "ptpsync_4"; + }; + + ptp_ext_pins: ptp-ext-pins { + pins = "GPIO_59"; + function = "ptpsync_5"; + }; +}; + +&qspi0 { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <100000000>; + #address-cells = <1>; + #size-cells = <1>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; + +&sdmmc0 { + pinctrl-0 = <&emmc_sd_pins>; + pinctrl-names = "default"; + max-frequency = <100000000>; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + disable-wp; + status = "okay"; +}; + +&tmon { + pinctrl-0 = <&fan_pins>; + pinctrl-names = "default"; +}; + +&mdio0 { + pinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>; + pinctrl-names = "default"; + reset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>; + status = "okay"; + + phy3: phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy4: phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy5: phy@5 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <5>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy6: phy@6 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <6>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy7: phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy8: phy@8 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <8>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy9: phy@9 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <9>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy10: phy@10 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <10>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy11: phy@11 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <11>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy12: phy@12 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <12>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy13: phy@13 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <13>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy14: phy@14 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <14>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy15: phy@15 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <15>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy16: phy@16 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <16>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy17: phy@17 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <17>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy18: phy@18 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <18>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy19: phy@19 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <19>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy20: phy@20 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <20>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy21: phy@21 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <21>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy22: phy@22 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <22>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy23: phy@23 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <23>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy24: phy@24 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <24>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy25: phy@25 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <25>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy26: phy@26 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <26>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; + + phy27: phy@27 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <27>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio>; + }; +}; + +&serdes { + status = "okay"; +}; + +&sgpio { + pinctrl-0 = <&sgpio_pins>; + pinctrl-names = "default"; + + microchip,sgpio-port-ranges = <0 1>, <6 9>; + status = "okay"; + + gpio@0 { + ngpios = <128>; + }; + gpio@1 { + ngpios = <128>; + }; +}; + +&switch { + pinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>; + pinctrl-names = "default"; + + status = "okay"; + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + port0: port@0 { + reg = <0>; + microchip,bandwidth = <1000>; + phy-handle = <&phy4>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + }; + + port1: port@1 { + reg = <1>; + microchip,bandwidth = <1000>; + phy-handle = <&phy5>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + }; + + port2: port@2 { + reg = <2>; + microchip,bandwidth = <1000>; + phy-handle = <&phy6>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + }; + + port3: port@3 { + reg = <3>; + microchip,bandwidth = <1000>; + phy-handle = <&phy7>; + phy-mode = "qsgmii"; + phys = <&serdes 0>; + }; + + port4: port@4 { + reg = <4>; + microchip,bandwidth = <1000>; + phy-handle = <&phy8>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + }; + + port5: port@5 { + reg = <5>; + microchip,bandwidth = <1000>; + phy-handle = <&phy9>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + }; + + port6: port@6 { + reg = <6>; + microchip,bandwidth = <1000>; + phy-handle = <&phy10>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + }; + + port7: port@7 { + reg = <7>; + microchip,bandwidth = <1000>; + phy-handle = <&phy11>; + phy-mode = "qsgmii"; + phys = <&serdes 1>; + }; + + port8: port@8 { + reg = <8>; + microchip,bandwidth = <1000>; + phy-handle = <&phy12>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + }; + + port9: port@9 { + reg = <9>; + microchip,bandwidth = <1000>; + phy-handle = <&phy13>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + }; + + port10: port@10 { + reg = <10>; + microchip,bandwidth = <1000>; + phy-handle = <&phy14>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + }; + + port11: port@11 { + reg = <11>; + microchip,bandwidth = <1000>; + phy-handle = <&phy15>; + phy-mode = "qsgmii"; + phys = <&serdes 2>; + }; + + port12: port@12 { + reg = <12>; + microchip,bandwidth = <1000>; + phy-handle = <&phy16>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + }; + + port13: port@13 { + reg = <13>; + microchip,bandwidth = <1000>; + phy-handle = <&phy17>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + }; + + port14: port@14 { + reg = <14>; + microchip,bandwidth = <1000>; + phy-handle = <&phy18>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + }; + + port15: port@15 { + reg = <15>; + microchip,bandwidth = <1000>; + phy-handle = <&phy19>; + phy-mode = "qsgmii"; + phys = <&serdes 3>; + }; + + port16: port@16 { + reg = <16>; + microchip,bandwidth = <1000>; + phy-handle = <&phy20>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + }; + + port17: port@17 { + reg = <17>; + microchip,bandwidth = <1000>; + phy-handle = <&phy21>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + }; + + port18: port@18 { + reg = <18>; + microchip,bandwidth = <1000>; + phy-handle = <&phy22>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + }; + + port19: port@19 { + reg = <19>; + microchip,bandwidth = <1000>; + phy-handle = <&phy23>; + phy-mode = "qsgmii"; + phys = <&serdes 4>; + }; + + port20: port@20 { + reg = <20>; + microchip,bandwidth = <1000>; + phy-handle = <&phy24>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + }; + + port21: port@21 { + reg = <21>; + microchip,bandwidth = <1000>; + phy-handle = <&phy25>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + }; + + port22: port@22 { + reg = <22>; + microchip,bandwidth = <1000>; + phy-handle = <&phy26>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + }; + + port23: port@23 { + reg = <23>; + microchip,bandwidth = <1000>; + phy-handle = <&phy27>; + phy-mode = "qsgmii"; + phys = <&serdes 5>; + }; + + port24: port@24 { + reg = <24>; + microchip,bandwidth = <10000>; + phys = <&serdes 6>; + phy-mode = "10gbase-r"; + sfp = <&sfp0>; + microchip,sd-sgpio = <24>; + managed = "in-band-status"; + }; + + port25: port@25 { + reg = <25>; + microchip,bandwidth = <10000>; + phys = <&serdes 7>; + phy-mode = "10gbase-r"; + sfp = <&sfp1>; + microchip,sd-sgpio = <28>; + managed = "in-band-status"; + }; + + port26: port@26 { + reg = <26>; + microchip,bandwidth = <10000>; + phys = <&serdes 8>; + phy-mode = "10gbase-r"; + sfp = <&sfp2>; + microchip,sd-sgpio = <32>; + managed = "in-band-status"; + }; + + port27: port@27 { + reg = <27>; + microchip,bandwidth = <10000>; + phys = <&serdes 9>; + phy-mode = "10gbase-r"; + sfp = <&sfp3>; + microchip,sd-sgpio = <36>; + managed = "in-band-status"; + }; + + port29: port@29 { + reg = <29>; + microchip,bandwidth = <1000>; + phys = <&serdes 11>; + phy-handle = <&phy3>; + phy-mode = "rgmii"; + rx-internal-delay-ps = <1000>; + tx-internal-delay-ps = <1000>; + }; + }; +}; + +&usb { + status = "okay"; + pinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>; + pinctrl-names = "default"; +}; diff --git a/target/linux/microchipsw/image/Makefile b/target/linux/microchipsw/image/Makefile index 4bee818578..2922c366c0 100644 --- a/target/linux/microchipsw/image/Makefile +++ b/target/linux/microchipsw/image/Makefile @@ -18,4 +18,6 @@ define Device/FitImage KERNEL_NAME := Image endef +include $(SUBTARGET).mk + $(eval $(call BuildImage)) diff --git a/target/linux/microchipsw/image/lan969x.mk b/target/linux/microchipsw/image/lan969x.mk new file mode 100644 index 0000000000..04b681b017 --- /dev/null +++ b/target/linux/microchipsw/image/lan969x.mk @@ -0,0 +1,41 @@ +define Build/lan969x-fip + cat $(STAGING_DIR_IMAGE)/$1-fip.bin >> $@ +endef + +define Build/lan969x-gpt-emmc + cp $@ $@.tmp 2>/dev/null || true + ptgen -g -o $@.tmp -a 1 -l 1024 \ + -t 0x83 -N fip -r -p 8M@1M \ + -t 0x83 -N fip.bak -r -p 8M@9M \ + -t 0x83 -N Env -r -p 2M@17M \ + $(if $(findstring flash,$1), \ + -t 0x2e -N kernel -p $(CONFIG_TARGET_KERNEL_PARTSIZE)M@19M \ + -t 0x2e -N rootfs -p $(CONFIG_TARGET_ROOTFS_PARTSIZE)M + ) + cat $@.tmp >> $@ + rm $@.tmp +endef + +define Build/append-kernel-part + dd if=$(IMAGE_KERNEL) bs=$(CONFIG_TARGET_KERNEL_PARTSIZE)M conv=sync >> $@ +endef + +define Device/microchip_ev23x71a + $(call Device/FitImage) + DEVICE_VENDOR := Microchip + DEVICE_MODEL := EV23X71A + SOC := lan9696 + DEVICE_PACKAGES := kmod-i2c-mux-gpio + IMAGES += emmc-atf-gpt.gz emmc-gpt.img.gz + IMAGE/emmc-atf-gpt.gz := lan969x-gpt-emmc |\ + pad-to 1M | lan969x-fip ev23x71a |\ + pad-to 9M | lan969x-fip ev23x71a |\ + gzip + IMAGE/emmc-gpt.img.gz := lan969x-gpt-emmc flash |\ + pad-to 1M | lan969x-fip ev23x71a |\ + pad-to 9M | lan969x-fip ev23x71a |\ + pad-to 19M | append-kernel-part |\ + append-rootfs |\ + gzip +endef +TARGET_DEVICES += microchip_ev23x71a diff --git a/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds b/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds new file mode 100644 index 0000000000..6e3da9e0ec --- /dev/null +++ b/target/linux/microchipsw/lan969x/base-files/etc/board.d/01_leds @@ -0,0 +1,23 @@ + +. /lib/functions/uci-defaults.sh + +board_config_update + +board=$(board_name) + +case "$board" in +microchip,ev23x71a) + ucidef_set_led_netdev "sfp1-link" "SFP1-LINK" "green:lan-0" "eth24" "link" + ucidef_set_led_netdev "sfp1-traffic" "SFP1-TRAFFIC" "yellow:lan-0" "eth24" "tx rx" + ucidef_set_led_netdev "sfp2-link" "SFP2-LINK" "green:lan-1" "eth25" "link" + ucidef_set_led_netdev "sfp2-traffic" "SFP2-TRAFFIC" "yellow:lan-1" "eth25" "tx rx" + ucidef_set_led_netdev "sfp3-link" "SFP3-LINK" "green:lan-2" "eth26" "link" + ucidef_set_led_netdev "sfp3-traffic" "SFP3-TRAFFIC" "yellow:lan-2" "eth26" "tx rx" + ucidef_set_led_netdev "sfp4-link" "SFP4-LINK" "green:lan-3" "eth27" "link" + ucidef_set_led_netdev "sfp4-traffic" "SFP4-TRAFFIC" "yellow:lan-3" "eth27" "tx rx" + ;; +esac + +board_config_flush + +exit 0 diff --git a/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network b/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network new file mode 100644 index 0000000000..be28e56192 --- /dev/null +++ b/target/linux/microchipsw/lan969x/base-files/etc/board.d/02_network @@ -0,0 +1,25 @@ + +. /lib/functions/uci-defaults.sh +. /lib/functions/system.sh + +lan969x_setup_interfaces() +{ + local board="$1" + + case "$board" in + microchip,ev23x71a) + lan_list=$(ls -1 -v -d /sys/class/net/eth* | xargs -n1 basename | xargs) + ucidef_set_interface_lan "$lan_list" + ;; + *) + echo "Unsupported hardware. Network interfaces not initialized" + ;; + esac +} + +board_config_update +board=$(board_name) +lan969x_setup_interfaces $board +board_config_flush + +exit 0 diff --git a/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh b/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000000..a3d4b488f0 --- /dev/null +++ b/target/linux/microchipsw/lan969x/base-files/lib/upgrade/platform.sh @@ -0,0 +1,31 @@ +PART_NAME=firmware +REQUIRE_IMAGE_METADATA=1 + +RAMFS_COPY_BIN='fw_printenv fw_setenv' +RAMFS_COPY_DATA='/etc/fw_env.config /var/lock/fw_printenv.lock' + +platform_check_image() { + return 0; +} + +platform_do_upgrade() { + case "$(board_name)" in + microchip,ev23x71a) + CI_KERNPART="kernel" + CI_ROOTPART="rootfs" + emmc_do_upgrade "$1" + ;; + *) + default_do_upgrade "$1" + ;; + esac +} + +platform_copy_config() { + case "$(board_name)" in + microchip,ev23x71a) + emmc_copy_config + ;; + esac + return 0; +} diff --git a/target/linux/microchipsw/lan969x/config-default b/target/linux/microchipsw/lan969x/config-default index fd4b7424e8..620c2e61ce 100644 --- a/target/linux/microchipsw/lan969x/config-default +++ b/target/linux/microchipsw/lan969x/config-default @@ -44,6 +44,7 @@ CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_PSCI_FW=y CONFIG_AT_XDMAC=y CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y +CONFIG_BLK_DEV_LOOP=y CONFIG_BUILTIN_RETURN_ADDRESS_STRIPS_PAC=y CONFIG_CC_HAVE_SHADOW_CALL_STACK=y CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y diff --git a/target/linux/microchipsw/lan969x/target.mk b/target/linux/microchipsw/lan969x/target.mk index dce697a82d..bc77e62a5b 100644 --- a/target/linux/microchipsw/lan969x/target.mk +++ b/target/linux/microchipsw/lan969x/target.mk @@ -1,7 +1,10 @@ SUBTARGET:=lan969x BOARDNAME:=Microchip LAN969x switches +FEATURES+= boot-part rootfs-part -DEFAULT_PACKAGES += kmod-usb3 kmod-usb-dwc3 +DEFAULT_PACKAGES += kmod-usb3 kmod-usb-dwc3 \ + e2fsprogs kmod-fs-ext4 losetup \ + kmod-fs-f2fs f2fs-tools define Target/Description Build firmware images for Microchip LAN969x switch based boards. From c820f097e0bede3ec09c62ca9608d915da21e62d Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Wed, 3 Dec 2025 18:39:52 +0100 Subject: [PATCH 3/6] tools: gnulib: install .m4 file with gl_ prefix It was found that there is currently a conflict for the cond.m4 that is also shipped by automake, making the gnulib one having priority causing problem with finding AM_CONDITIONAL macro. To handle this, install gnulib .m4 file with a gl_ prefix to the filename. This make sure gnulib .m4 file won't have name conflict with automake .m4 default files permitting correct autoreconf run of any affected package by this. Signed-off-by: Christian Marangi --- tools/gnulib/Makefile | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/tools/gnulib/Makefile b/tools/gnulib/Makefile index 1237fad46e..018ff5db14 100644 --- a/tools/gnulib/Makefile +++ b/tools/gnulib/Makefile @@ -13,10 +13,15 @@ include $(INCLUDE_DIR)/host-build.mk define Host/Configure endef +# On installing the .m4 files, we add a gl_ prefix to prevent any conflict with +# automake. It was found that there is currently a conflict for the cond.m4 that +# is also shipped by automake, making the gnulib one having priority causing +# problem with finding AM_CONDITIONAL macro. define Host/Install $(call Host/Uninstall) $(INSTALL_DIR) $(1)/share/aclocal - $(INSTALL_DATA) $(HOST_BUILD_DIR)/m4/*.m4 $(1)/share/aclocal/ + $(foreach m4,$(notdir $(wildcard $(HOST_BUILD_DIR)/m4/*.m4)), + $(INSTALL_DATA) $(HOST_BUILD_DIR)/m4/$(m4) $(1)/share/aclocal/gl_$(m4)) $(CP) $(HOST_BUILD_DIR)/ $(1)/share/gnulib/ ln -sf ../share/gnulib/gnulib-tool $(STAGING_DIR_HOST)/bin/gnulib-tool endef From 8ad5f35a9013ca7c65e86e7aef92617903afeab0 Mon Sep 17 00:00:00 2001 From: Christian Marangi Date: Wed, 3 Dec 2025 19:58:00 +0100 Subject: [PATCH 4/6] autoconf-archive: backport patch for C++23 support Backport upstream patch for C++23 support on ax_cxx_compile_stdcxx.m4. This is needed by Asterisk package to correctly configure. It's currently not possible to bump to a more recent autoconf-archive release 2024.10.16 as it's currently affected by multiple BUGs ([1]) [1] https://github.com/openwrt/openwrt/commit/e1acc7a67b92fa964710afe0a3ae2dad5c1f00c7 Signed-off-by: Christian Marangi --- ..._CXX_COMPILE_STDCXX-Add-C-23-support.patch | 90 +++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 tools/autoconf-archive/patches/001-AX_CXX_COMPILE_STDCXX-Add-C-23-support.patch diff --git a/tools/autoconf-archive/patches/001-AX_CXX_COMPILE_STDCXX-Add-C-23-support.patch b/tools/autoconf-archive/patches/001-AX_CXX_COMPILE_STDCXX-Add-C-23-support.patch new file mode 100644 index 0000000000..c44409cc15 --- /dev/null +++ b/tools/autoconf-archive/patches/001-AX_CXX_COMPILE_STDCXX-Add-C-23-support.patch @@ -0,0 +1,90 @@ +From 833c9c2e5b65383c8c1353b6beb88f52dede640f Mon Sep 17 00:00:00 2001 +From: Olly Betts +Date: Wed, 29 May 2024 07:54:24 +1200 +Subject: [PATCH] AX_CXX_COMPILE_STDCXX: Add C++23 support + +--- + m4/ax_cxx_compile_stdcxx.m4 | 47 ++++++++++++++++++++++++++++++++++--- + 1 file changed, 44 insertions(+), 3 deletions(-) + +--- a/m4/ax_cxx_compile_stdcxx.m4 ++++ b/m4/ax_cxx_compile_stdcxx.m4 +@@ -10,8 +10,8 @@ + # + # Check for baseline language coverage in the compiler for the specified + # version of the C++ standard. If necessary, add switches to CXX and +-# CXXCPP to enable support. VERSION may be '11', '14', '17', or '20' for +-# the respective C++ standard version. ++# CXXCPP to enable support. VERSION may be '11', '14', '17', '20', or ++# '23' for the respective C++ standard version. + # + # The second argument, if specified, indicates whether you insist on an + # extended mode (e.g. -std=gnu++11) or a strict conformance mode (e.g. +@@ -43,7 +43,7 @@ + # and this notice are preserved. This file is offered as-is, without any + # warranty. + +-#serial 18 ++#serial 19 + + dnl This macro is based on the code from the AX_CXX_COMPILE_STDCXX_11 macro + dnl (serial version number 13). +@@ -53,6 +53,7 @@ AC_DEFUN([AX_CXX_COMPILE_STDCXX], [dnl + [$1], [14], [ax_cxx_compile_alternatives="14 1y"], + [$1], [17], [ax_cxx_compile_alternatives="17 1z"], + [$1], [20], [ax_cxx_compile_alternatives="20"], ++ [$1], [23], [ax_cxx_compile_alternatives="23"], + [m4_fatal([invalid first argument `$1' to AX_CXX_COMPILE_STDCXX])])dnl + m4_if([$2], [], [], + [$2], [ext], [], +@@ -186,6 +187,16 @@ m4_define([_AX_CXX_COMPILE_STDCXX_testbo + _AX_CXX_COMPILE_STDCXX_testbody_new_in_20 + ) + ++dnl Test body for checking C++23 support ++ ++m4_define([_AX_CXX_COMPILE_STDCXX_testbody_23], ++ _AX_CXX_COMPILE_STDCXX_testbody_new_in_11 ++ _AX_CXX_COMPILE_STDCXX_testbody_new_in_14 ++ _AX_CXX_COMPILE_STDCXX_testbody_new_in_17 ++ _AX_CXX_COMPILE_STDCXX_testbody_new_in_20 ++ _AX_CXX_COMPILE_STDCXX_testbody_new_in_23 ++) ++ + + dnl Tests for new features in C++11 + +@@ -1016,3 +1027,33 @@ namespace cxx20 + #endif // __cplusplus < 202002L && !defined _MSC_VER + + ]]) ++ ++ ++dnl Tests for new features in C++23 ++ ++m4_define([_AX_CXX_COMPILE_STDCXX_testbody_new_in_23], [[ ++ ++#ifndef __cplusplus ++ ++#error "This is not a C++ compiler" ++ ++#elif (defined _MSVC_LANG ? _MSVC_LANG : __cplusplus) < 202302L ++ ++#error "This is not a C++23 compiler" ++ ++#else ++ ++#include ++ ++namespace cxx23 ++{ ++ ++// As C++23 supports feature test macros in the standard, there is no ++// immediate need to actually test for feature availability on the ++// Autoconf side. ++ ++} // namespace cxx23 ++ ++#endif // (defined _MSVC_LANG ? _MSVC_LANG : __cplusplus) < 202302L ++ ++]]) From 6f2325b23d2cfa28099c26c299ae774625f1872b Mon Sep 17 00:00:00 2001 From: Mikhail Zadorozhnyi Date: Sun, 12 Oct 2025 17:52:35 +0300 Subject: [PATCH 5/6] mvebu: gl-mv1000: add devicetree patch for sdhci1 GL-MV1000 external SD controller was broken by a recent kernel update due to a mistake in Device Tree: "regulator-gpio" was defined without required "gpios" property. Removing this regulator definition from the device tree fixes this issue without any side effects so far. "main" branch uses upstream devicetree for this device, so add a kernel patch for the "mvebu" kernel family. Relevant discussions: https://github.com/openwrt/openwrt/issues/20309 https://github.com/openwrt/openwrt/pull/20378 Signed-off-by: Mikhail Zadorozhnyi Link: https://github.com/openwrt/openwrt/pull/20390 Signed-off-by: Robert Marko --- ...dts-marvell-glinet-mv1000-fix-sdhci1.patch | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 target/linux/mvebu/patches-6.12/326-arm64-dts-marvell-glinet-mv1000-fix-sdhci1.patch diff --git a/target/linux/mvebu/patches-6.12/326-arm64-dts-marvell-glinet-mv1000-fix-sdhci1.patch b/target/linux/mvebu/patches-6.12/326-arm64-dts-marvell-glinet-mv1000-fix-sdhci1.patch new file mode 100644 index 0000000000..78fe52dcd4 --- /dev/null +++ b/target/linux/mvebu/patches-6.12/326-arm64-dts-marvell-glinet-mv1000-fix-sdhci1.patch @@ -0,0 +1,53 @@ +From 5f20749c2dbbbc0f4f3c5bd1c4067388ab760960 Mon Sep 17 00:00:00 2001 +From: Mikhail Zadorozhnyi +Date: Sat, 11 Oct 2025 20:22:07 +0300 +Subject: [PATCH] arm64: dts: marvell: fix sdhci1 controller for gl-mv1000 + +GL-MV1000 external SD controller was broken by a recent kernel update +due to a mistake in Device Tree: "regulator-gpio" was defined without +required "gpios" property. + +Since "no-1-8-v" property is also defined for this controller +a switchable vqmmc-supply regulator performs no function - a fixed 3.3V +IO voltage will always be used. + +This regulator definition was probably added by mistake from a Device +Tree from another device. + +Remove incomplete vcc_sd_reg1 regulator definition to fix this issue. + +Signed-off-by: Mikhail Zadorozhnyi +--- + .../boot/dts/marvell/armada-3720-gl-mv1000.dts | 14 -------------- + 1 file changed, 14 deletions(-) + +--- a/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts ++++ b/arch/arm64/boot/dts/marvell/armada-3720-gl-mv1000.dts +@@ -26,19 +26,6 @@ + reg = <0x00000000 0x00000000 0x00000000 0x20000000>; + }; + +- vcc_sd_reg1: regulator { +- compatible = "regulator-gpio"; +- regulator-name = "vcc_sd1"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <3300000>; +- regulator-boot-on; +- +- gpios-states = <0>; +- states = <1800000 0x1 +- 3300000 0x0>; +- enable-active-high; +- }; +- + keys { + compatible = "gpio-keys"; + +@@ -135,7 +122,6 @@ + cd-gpios = <&gpionb 17 GPIO_ACTIVE_LOW>; + marvell,pad-type = "sd"; + no-1-8-v; +- vqmmc-supply = <&vcc_sd_reg1>; + status = "okay"; + }; + From cd9229d06126e40226c01a7f354072bdf777f697 Mon Sep 17 00:00:00 2001 From: Hauke Mehrtens Date: Wed, 3 Dec 2025 22:46:44 +0100 Subject: [PATCH 6/6] treewide: Fix const compile errors Fixes compile errors caused by static const arrays; The lantiq firmware is const now. ATTRIBUTE_GROUPS() does not take const. Fixes: 5b263f3360b ("treewide: add const to static arrays") Signed-off-by: Hauke Mehrtens --- package/kernel/lantiq/ltq-atm/src/ifxmips_atm_amazon_se.c | 2 +- package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ar9.c | 2 +- package/kernel/lantiq/ltq-atm/src/ifxmips_atm_danube.c | 2 +- package/kernel/lantiq/ltq-atm/src/ifxmips_atm_vr9.c | 2 +- package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_amazon_se.c | 2 +- package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ar9.c | 2 +- package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_danube.c | 2 +- package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vr9.c | 2 +- ...2-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_amazon_se.c b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_amazon_se.c index 734fe29961..db40bbcaa6 100644 --- a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_amazon_se.c +++ b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_amazon_se.c @@ -220,7 +220,7 @@ static inline void clear_share_buffer(void) * int --- 0: Success * else: Error Code */ -static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +static inline int pp32_download_code(const u32 *code_src, unsigned int code_dword_len, const u32 *data_src, unsigned int data_dword_len) { volatile u32 *dest; diff --git a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ar9.c b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ar9.c index 28ac8f6c7a..e9949d6af3 100644 --- a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ar9.c +++ b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_ar9.c @@ -159,7 +159,7 @@ static inline void clear_share_buffer(void) IFX_REG_W32(0, p++); } -static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +static inline int pp32_download_code(const u32 *code_src, unsigned int code_dword_len, const u32 *data_src, unsigned int data_dword_len) { volatile u32 *dest; diff --git a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_danube.c b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_danube.c index 57a50e322d..81df6386fb 100644 --- a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_danube.c +++ b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_danube.c @@ -106,7 +106,7 @@ static inline void reset_ppe(struct platform_device *pdev) * int --- 0: Success * else: Error Code */ -static inline int danube_pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +static inline int danube_pp32_download_code(const u32 *code_src, unsigned int code_dword_len, const u32 *data_src, unsigned int data_dword_len) { volatile u32 *dest; diff --git a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_vr9.c b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_vr9.c index ffe079f3df..f6602db921 100644 --- a/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_vr9.c +++ b/package/kernel/lantiq/ltq-atm/src/ifxmips_atm_vr9.c @@ -91,7 +91,7 @@ static inline int vr9_reset_ppe(struct platform_device *pdev) return 0; } -static inline int vr9_pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +static inline int vr9_pp32_download_code(int pp32, const u32 *code_src, unsigned int code_dword_len, const u32 *data_src, unsigned int data_dword_len) { unsigned int clr, set; volatile u32 *dest; diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_amazon_se.c b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_amazon_se.c index 7548c6d357..541e3dc094 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_amazon_se.c +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_amazon_se.c @@ -219,7 +219,7 @@ static inline void clear_share_buffer(void) * int --- 0: Success * else: Error Code */ -static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +static inline int pp32_download_code(const u32 *code_src, unsigned int code_dword_len, const u32 *data_src, unsigned int data_dword_len) { volatile u32 *dest; diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ar9.c b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ar9.c index e83268ee36..65a7140284 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ar9.c +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ar9.c @@ -242,7 +242,7 @@ static inline void clear_share_buffer(void) * int --- 0: Success * else: Error Code */ -static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +static inline int pp32_download_code(const u32 *code_src, unsigned int code_dword_len, const u32 *data_src, unsigned int data_dword_len) { volatile u32 *dest; diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_danube.c b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_danube.c index ef20e9cb45..8ddf6f8274 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_danube.c +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_danube.c @@ -214,7 +214,7 @@ static inline void clear_share_buffer(void) * int --- 0: Success * else: Error Code */ -static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +static inline int pp32_download_code(const u32 *code_src, unsigned int code_dword_len, const u32 *data_src, unsigned int data_dword_len) { volatile u32 *dest; diff --git a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vr9.c b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vr9.c index 10e71cb1d9..41a0bbbd9f 100644 --- a/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vr9.c +++ b/package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_vr9.c @@ -202,7 +202,7 @@ static inline void clear_share_buffer(void) * int --- 0: Success * else: Error Code */ -static inline int pp32_download_code(int pp32, u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len) +static inline int pp32_download_code(int pp32, const u32 *code_src, unsigned int code_dword_len, const u32 *data_src, unsigned int data_dword_len) { unsigned int clr, set; volatile u32 *dest; diff --git a/target/linux/mvebu/patches-6.12/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch b/target/linux/mvebu/patches-6.12/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch index e697a64066..6f99497c36 100644 --- a/target/linux/mvebu/patches-6.12/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch +++ b/target/linux/mvebu/patches-6.12/902-drivers-mfd-Add-a-driver-for-IEI-WT61P803-PUZZLE-MCU.patch @@ -820,7 +820,7 @@ Cc: Robert Marko +static IEI_WT61P803_PUZZLE_ATTR_RW(power_loss_recovery, IEI_WT61P803_PUZZLE_POWER_LOSS_RECOVERY, 0); +static IEI_WT61P803_PUZZLE_ATTR_RO(power_status, IEI_WT61P803_PUZZLE_POWER_STATUS, 0); + -+static const struct attribute *iei_wt61p803_puzzle_attrs[] = { ++static struct attribute *iei_wt61p803_puzzle_attrs[] = { + &dev_attr_version.dev_attr.attr, + &dev_attr_build_info.dev_attr.attr, + &dev_attr_bootloader_mode.dev_attr.attr,