Merge Official Source

Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>

config/Config-build.in

@@ -250,6 +250,15 @@ menu "Global build settings"
 
 	comment "Hardening build options"
 
+	config PKG_FANALYZER
+		bool
+		prompt "Enable gcc fanalyzer"
+		default n
+		help
+		  Add -fanalyzer to the CFLAGS. As a result of this option, a static analysis
+		  of the program flow is conducted, allowing interprocedural paths to be
+		  identified and warnings to be issued if problems are identified.
+
 	config PKG_CHECK_FORMAT_SECURITY
 		bool
 		prompt "Enable gcc format-security"

include/hardening.mk

@@ -9,6 +9,7 @@ PKG_SSP ?= 1
 PKG_FORTIFY_SOURCE ?= 1
 PKG_RELRO ?= 1
 PKG_DT_RELR ?= 1
+PKG_FANALYZER ?= 0
 
 ifdef CONFIG_PKG_CHECK_FORMAT_SECURITY
   ifeq ($(strip $(PKG_CHECK_FORMAT_SECURITY)),1)
@@ -77,3 +78,8 @@ ifdef CONFIG_PKG_DT_RELR
   endif
 endif
 
+ifdef CONFIG_PKG_FANALYZER
+  ifeq ($(strip $(PKG_FANALYZER)),1)
+    TARGET_CFLAGS +=  -fanalyzer
+  endif
+endif

include/image-commands.mk

@@ -430,7 +430,7 @@ define Build/initrd_compression
 	$(if $(CONFIG_TARGET_INITRAMFS_COMPRESSION_ZSTD),.zstd)
 endef
 
-define Build/fit
+define Build/fit-its
 	$(if $(findstring with-rootfs,$(word 3,$(1))), \
 		$(call locked,dd if=$(IMAGE_ROOTFS) of=$(IMAGE_ROOTFS).pagesync bs=4096 conv=sync, \
 		  gen-cpio$(if $(TARGET_PER_DEVICE_ROOTFS),.$(ROOTFS_ID/$(DEVICE_NAME)))))
@@ -452,12 +452,20 @@ define Build/fit
 		$(if $(DEVICE_DTS_OVERLAY),$(foreach dtso,$(DEVICE_DTS_OVERLAY), -O $(dtso):$(KERNEL_BUILD_DIR)/image-$(dtso).dtbo)) \
 		-c $(if $(DEVICE_DTS_CONFIG),$(DEVICE_DTS_CONFIG),"config-1") \
 		-A $(LINUX_KARCH) -v $(LINUX_VERSION)
+endef
+
+define Build/fit-image
 	$(call locked,PATH=$(LINUX_DIR)/scripts/dtc:$(PATH) mkimage $(if $(findstring external,$(word 3,$(1))),\
 		-E -B 0x1000 $(if $(findstring static,$(word 3,$(1))),-p 0x1000)) -f $@.its $@.new, \
 	  gen-cpio$(if $(TARGET_PER_DEVICE_ROOTFS),.$(ROOTFS_ID/$(DEVICE_NAME))))
 	@mv $@.new $@
 endef
 
+define Build/fit
+	$(call Build/fit-its,$(1))
+	$(call Build/fit-image,$(1))
+endef
+
 define Build/libdeflate-gzip
 	$(STAGING_DIR_HOST)/bin/libdeflate-gzip -f -12 -c $@ $(1) > $@.new
 	@mv $@.new $@

package/devel/binutils/Makefile

@@ -8,13 +8,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=binutils
-PKG_VERSION:=2.42
+PKG_VERSION:=2.45.1
 PKG_RELEASE:=1
 
 PKG_SOURCE_URL:=@GNU/binutils
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_VERSION:=$(PKG_VERSION)
-PKG_HASH:=f6e4d41fd5fc778b06b7891457b3620da5ecea1006c6a4a41ae998109f85a800
+PKG_HASH:=5fe101e6fe9d18fdec95962d81ed670fdee5f37e3f48f0bef87bddf862513aa5
 
 PKG_FIXUP:=patch-libtool
 PKG_LIBTOOL_PATHS:=. gas bfd opcodes gprof gprofng binutils ld libiberty gold intl libctf libsframe

package/devel/binutils/patches/001-replace-attribute_const.patch

@@ -17,9 +17,9 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
 ----------------------
 --- a/gprofng/common/cpuid.c
 +++ b/gprofng/common/cpuid.c
-@@ -23,7 +23,7 @@
+@@ -25,7 +25,7 @@
- #elif defined(__aarch64__)
  #define ATTRIBUTE_UNUSED __attribute__((unused))
+ #endif
  
 -static inline uint_t __attribute_const__
 +static inline uint_t __attribute__((__const__))
@@ -28,7 +28,7 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
  	     unsigned int *ecx ATTRIBUTE_UNUSED, unsigned int *edx ATTRIBUTE_UNUSED)
 --- a/gprofng/libcollector/unwind.c
 +++ b/gprofng/libcollector/unwind.c
-@@ -237,7 +237,7 @@ typedef uint64_t __u64;
+@@ -236,7 +236,7 @@ typedef uint64_t __u64;
  
  #define FILL_CONTEXT(context) \
      { CALL_UTIL (getcontext) (context);  \
@@ -36,8 +36,8 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
 +      context->uc_mcontext.sp = (uint64_t) __builtin_frame_address(0); \
      }
  
- #endif /* ARCH() */
+ #elif ARCH(RISCV)
-@@ -4583,11 +4583,11 @@ stack_unwind (char *buf, int size, void
+@@ -4588,11 +4588,11 @@ stack_unwind (char *buf, int size, void
    if (buf && bptr && eptr && context && size + mode > 0)
      getByteInstruction ((unsigned char *) eptr);
    int ind = 0;
@@ -54,7 +54,7 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
    unsigned long tbgn = 0;
    unsigned long tend = 0;
  
-@@ -4598,7 +4598,7 @@ stack_unwind (char *buf, int size, void
+@@ -4603,7 +4603,7 @@ stack_unwind (char *buf, int size, void
      {
        stack_base = sp + 0x100000;
        if (stack_base < sp)  // overflow
@@ -63,7 +63,7 @@ unwind.c:490:3: note: in expansion of macro 'FILL_CONTEXT'
      }
    DprintfT (SP_DUMP_UNWIND,
      "unwind.c:%d stack_unwind %2d pc=0x%llx  sp=0x%llx  stack_base=0x%llx\n",
-@@ -4629,17 +4629,17 @@ stack_unwind (char *buf, int size, void
+@@ -4634,17 +4634,17 @@ stack_unwind (char *buf, int size, void
  		      __LINE__, (unsigned long) sp);
  	    break;
  	  }

package/devel/gperf/Makefile

@@ -1,12 +1,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=gperf
-PKG_VERSION:=3.1
+PKG_VERSION:=3.3
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=@GNU/gperf
-PKG_HASH:=588546b945bba4b70b6a3a616e80b4ab466e3f33024a352fc2198112cdbb3ae2
+PKG_HASH:=fd87e0aba7e43ae054837afd6cd4db03a3f2693deb3619085e6ed9d8d9604ad8
 
 PKG_LICENSE:=GPL-3.0
 PKG_LICENSE_FILES:=COPYING

package/libs/jansson/Makefile

@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=jansson
-PKG_VERSION:=2.14
+PKG_VERSION:=2.14.1
-PKG_RELEASE:=3
+PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=https://codeload.github.com/akheron/$(PKG_NAME)/tar.gz/v$(PKG_VERSION)?
-PKG_HASH:=c739578bf6b764aa0752db9a2fdadcfe921c78f1228c7ec0bb47fa804c55d17b
+PKG_HASH:=979210eaffdffbcf54cfc34d047fccde13f21b529a381df26db871d886f729a4
 
 PKG_LICENSE:=MIT
 PKG_LICENSE_FILES:=LICENSE

package/libs/libbpf/Makefile

@@ -8,11 +8,11 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=libbpf
-PKG_VERSION:=1.5.0
+PKG_VERSION:=1.6.2
 PKG_RELEASE:=1
 
 PKG_SOURCE_URL:=https://github.com/libbpf/libbpf
-PKG_MIRROR_HASH:=7699fcfa89bf0f6e756c4555fbd3fdb8cbcfcc770e5944aebdd0e9244031f022
+PKG_MIRROR_HASH:=9620f45b4fc0ee5e0f43502634fe48fbcb34ab49d2553b7275fa92f7e02d3dc7
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_VERSION:=v$(PKG_VERSION)
 PKG_ABI_VERSION:=$(firstword $(subst .,$(space),$(PKG_VERSION)))

package/libs/libbpf/patches/100-bpf_tc_classid.patch

@@ -1,6 +1,6 @@
 --- a/src/libbpf.h
 +++ b/src/libbpf.h
-@@ -1291,9 +1291,10 @@ struct bpf_tc_opts {
+@@ -1332,9 +1332,10 @@ struct bpf_tc_opts {
  	__u32 prog_id;
  	__u32 handle;
  	__u32 priority;
@@ -14,7 +14,7 @@
  LIBBPF_API int bpf_tc_hook_destroy(struct bpf_tc_hook *hook);
 --- a/src/netlink.c
 +++ b/src/netlink.c
-@@ -673,6 +673,8 @@ static int __get_tc_info(void *cookie, s
+@@ -687,6 +687,8 @@ static int __get_tc_info(void *cookie, s
  	OPTS_SET(info->opts, prog_id, libbpf_nla_getattr_u32(tbb[TCA_BPF_ID]));
  	OPTS_SET(info->opts, handle, tc->tcm_handle);
  	OPTS_SET(info->opts, priority, TC_H_MAJ(tc->tcm_info) >> 16);
@@ -23,7 +23,7 @@
  
  	info->processed = true;
  	return unicast ? NL_NEXT : NL_DONE;
-@@ -717,7 +719,7 @@ static int tc_add_fd_and_name(struct lib
+@@ -731,7 +733,7 @@ static int tc_add_fd_and_name(struct lib
  
  int bpf_tc_attach(const struct bpf_tc_hook *hook, struct bpf_tc_opts *opts)
  {
@@ -32,7 +32,7 @@
  	int ret, ifindex, attach_point, prog_fd;
  	struct bpf_cb_ctx info = {};
  	struct libbpf_nla_req req;
-@@ -737,6 +739,7 @@ int bpf_tc_attach(const struct bpf_tc_ho
+@@ -751,6 +753,7 @@ int bpf_tc_attach(const struct bpf_tc_ho
  	prog_fd      = OPTS_GET(opts, prog_fd, 0);
  	prog_id      = OPTS_GET(opts, prog_id, 0);
  	flags        = OPTS_GET(opts, flags, 0);
@@ -40,7 +40,7 @@
  
  	if (ifindex <= 0 || !prog_fd || prog_id)
  		return libbpf_err(-EINVAL);
-@@ -776,6 +779,11 @@ int bpf_tc_attach(const struct bpf_tc_ho
+@@ -790,6 +793,11 @@ int bpf_tc_attach(const struct bpf_tc_ho
  	ret = nlattr_add(&req, TCA_BPF_FLAGS, &bpf_flags, sizeof(bpf_flags));
  	if (ret < 0)
  		return libbpf_err(ret);

package/libs/libbsd/Makefile

@@ -1,12 +1,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=libbsd
-PKG_VERSION:=0.11.8
+PKG_VERSION:=0.12.2
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=https://libbsd.freedesktop.org/releases
-PKG_HASH:=55fdfa2696fb4d55a592fa9ad14a9df897c7b0008ddb3b30c419914841f85f33
+PKG_HASH:=b88cc9163d0c652aaf39a99991d974ddba1c3a9711db8f1b5838af2a14731014
 
 PKG_LICENSE:=BSD-4-Clause
 PKG_LICENSE_FILES:=COPYING

package/libs/libbsd/patches/001-fix-libpath.patch

@@ -2,7 +2,7 @@ do not use host path to fix cross compiling
 
 --- a/src/Makefile.am
 +++ b/src/Makefile.am
-@@ -230,7 +230,7 @@ if NEED_TRANSPARENT_LIBMD
+@@ -385,7 +385,7 @@ if ABI_TRANSPARENT_LIBMD
  	(echo '/* GNU ld script'; \
  	 echo ' * The MD5 functions are provided by the libmd library. */'; \
  	 cat format.ld; \

package/libs/libtool/Makefile

@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=libtool
-PKG_VERSION:=2.4.7
+PKG_VERSION:=2.5.4
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@GNU/libtool
-PKG_HASH:=4f7f217f057ce655ff22559ad221a0fd8ef84ad1fc5fcb6990cecc333aa1635d
+PKG_HASH:=f81f5860666b0bc7d84baddefa60d1cb9fa6fceb2398cc3baca6afaa60266675
 
 PKG_LICENSE:=GPL-2.0+
 PKG_LICENSE_FILES:=COPYING

package/libs/libunistring/Makefile

@@ -1,12 +1,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=libunistring
-PKG_VERSION:=1.2
+PKG_VERSION:=1.4.1
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@GNU/$(PKG_NAME)
-PKG_HASH:=632bd65ed74a881ca8a0309a1001c428bd1cbd5cd7ddbf8cedcd2e65f4dcdc44
+PKG_HASH:=67d88430892527861903788868c77802a217b0959990f7449f2976126a307763
 
 PKG_BUILD_PARALLEL:=1
 PKG_INSTALL:=1

package/libs/libusb/Makefile

@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=libusb
-PKG_VERSION:=1.0.27
+PKG_VERSION:=1.0.29
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
 PKG_SOURCE_URL:=https://github.com/libusb/libusb/releases/download/v$(PKG_VERSION)
-PKG_HASH:=ffaa41d741a8a3bee244ac8e54a72ea05bf2879663c098c82fc5757853441575
+PKG_HASH:=5977fc950f8d1395ccea9bd48c06b3f808fd3c2c961b44b0c2e6e29fc3a70a85
 
 PKG_MAINTAINER:= Felix Fietkau <nbd@nbd.name>
 PKG_LICENSE:=LGPL-2.1-or-later

package/libs/libxml2/Makefile

@@ -1,12 +1,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=libxml2
-PKG_VERSION:=2.14.5
+PKG_VERSION:=2.15.1
-PKG_RELEASE:=2
+PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
 PKG_SOURCE_URL:=@GNOME/libxml2/$(basename $(PKG_VERSION))
-PKG_HASH:=03d006f3537616833c16c53addcdc32a0eb20e55443cba4038307e3fa7d8d44b
+PKG_HASH:=c008bac08fd5c7b4a87f7b8a71f283fa581d80d80ff8d2efd3b26224c39bc54c
 
 PKG_LICENSE:=MIT
 PKG_LICENSE_FILES:=Copyright
@@ -156,7 +156,7 @@ define Build/InstallDev
 	$(CP) $(PKG_INSTALL_DIR)/usr/lib/libxml2.so* $(1)/usr/lib/
 
 	$(INSTALL_DIR) $(1)/usr/lib/cmake/libxml2
-	$(CP) $(PKG_INSTALL_DIR)/usr/lib/cmake/libxml2-$(PKG_VERSION)/*.cmake \
+	$(CP) $(PKG_INSTALL_DIR)/usr/lib/cmake/libxml2/*.cmake \
 		$(1)/usr/lib/cmake/libxml2
 
 	$(INSTALL_DIR) $(1)/usr/lib/pkgconfig

package/libs/mpfr/Makefile

@@ -8,12 +8,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=mpfr
-PKG_VERSION:=4.2.1
+PKG_VERSION:=4.2.2
 PKG_RELEASE:=1
 
 PKG_SOURCE_URL:=@GNU/mpfr http://www.mpfr.org/mpfr-$(PKG_VERSION)
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
-PKG_HASH:=277807353a6726978996945af13e52829e3abd7a9a5b7fb2793894e18f1fcbb2
+PKG_HASH:=b67ba0383ef7e8a8563734e2e889ef5ec3c3b898a01d00fa0a6869ad81c6ce01
 
 PKG_LICENSE:=LGPL-3.0-or-later
 PKG_LICENSE_FILES:=COPYING.LESSER

package/libs/mpfr/patches/001-only-src.patch

@@ -11,7 +11,7 @@
  pkgconfig_DATA = mpfr.pc
 --- a/Makefile.in
 +++ b/Makefile.in
-@@ -401,7 +401,7 @@ AUTOMAKE_OPTIONS = gnu
+@@ -406,7 +406,7 @@ AUTOMAKE_OPTIONS = gnu
  # libtoolize and in case some developer needs to switch back to an
  # old Automake version.
  ACLOCAL_AMFLAGS = -I m4

package/libs/nettle/Makefile

@@ -8,13 +8,13 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=nettle
-PKG_VERSION:=3.10.1
+PKG_VERSION:=3.10.2
 PKG_RELEASE:=1
 PKG_BUILD_FLAGS:=no-mips16
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
 PKG_SOURCE_URL:=@GNU/nettle
-PKG_HASH:=b0fcdd7fc0cdea6e80dcf1dd85ba794af0d5b4a57e26397eee3bc193272d9132
+PKG_HASH:=fe9ff51cb1f2abb5e65a6b8c10a92da0ab5ab6eaf26e7fc2b675c45f1fb519b5
 
 PKG_LICENSE:=GPL-2.0-or-later
 PKG_LICENSE_FILES:=	COPYING.LESSERv3 \

package/libs/pcre2/Config.in

@@ -1,7 +1,7 @@
 config PCRE2_JIT_ENABLED
 	bool
 	depends on PACKAGE_libpcre2 && (aarch64 || aarch64_be || arm || i386 || i686 || x86_64 || mips || mipsel || mips64 || mips64el || powerpc || powerpc64 || powerpcle || sparc)
-	default y if (arm || i686 || x86_64)
+	default y if (aarch64 || arm || i686 || x86_64)
 	prompt "Enable JIT compiler support"
 	help
 		Enable JIT (Just-In-Time) compiler support.

package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/ap.uc

@@ -288,7 +288,7 @@ function iface_vlan(interface, config, vlans) {
 		if (vlan.config.name && vlan.config.vid) {
 			let ifname = `${config.ifname}-${vlan.config.name}`;
 			file.write(`${vlan.config.vid} ${ifname}\n`);
-			netifd.set_vlan(interface, k, ifname);
+			netifd.set_vlan(interface, ifname, k);
 		}
 	file.close();
 
@@ -307,9 +307,6 @@ function iface_vlan(interface, config, vlans) {
 }
 
 function iface_wpa_stations(config, stas) {
-	if (!length(stas))
-		return;
-
 	let path = `/var/run/hostapd-${config.ifname}.psk`;
 
 	let file = fs.open(path, 'w');
@@ -326,9 +323,6 @@ function iface_wpa_stations(config, stas) {
 }
 
 function iface_sae_stations(config, stas) {
-	if (!length(stas))
-		return;
-
 	let path = `/var/run/hostapd-${config.ifname}.sae`;
 
 	let file = fs.open(path, 'w');

package/network/config/wifi-scripts/files-ucode/usr/share/ucode/wifi/iface.uc

@@ -41,8 +41,9 @@ export function parse_encryption(config, dev_config) {
 		break;
 
 	case 'psk':
+	case 'psk2':
 	case 'psk-mixed':
-		config.auth_type = "psk";
+		config.auth_type = 'psk';
 		wpa3_pairwise = null;
 		break;
 
@@ -63,10 +64,6 @@ export function parse_encryption(config, dev_config) {
 		wpa3_pairwise = null;
 		break;
 
-	case 'psk2':
-		wpa3_pairwise = null;
-		break;
-
 	default:
 		config.wpa_pairwise = null;
 		wpa3_pairwise = null;

package/network/config/wifi-scripts/files/lib/netifd/hostapd.sh

@@ -1162,9 +1162,9 @@ hostapd_set_bss_options() {
 		append bss_conf "multicast_to_unicast=$multicast_to_unicast_all" "$N"
 	fi
 	set_default proxy_arp 0
+	set_default na_mcast_to_ucast "$proxy_arp"
 	if [ "$proxy_arp" -gt 0 ]; then
 		append bss_conf "proxy_arp=$proxy_arp" "$N"
-		set_default na_mcast_to_ucast 1
 	fi
 	if [ "$na_mcast_to_ucast" -gt 0 ]; then
 		append bss_conf "na_mcast_to_ucast=$na_mcast_to_ucast" "$N"

package/network/config/wifi-scripts/files/lib/netifd/wireless.uc

@@ -214,10 +214,11 @@ function config_init(uci)
 	}
 
 	for (let name, data in sections.station) {
-		if (!data.iface || !vifs[data.iface])
+		for (let iface, iface_vifs in vifs) {
+			if (data.iface && data.iface != iface)
 				continue;
 
-		for (let vif in vifs[data.iface]) {
+			for (let vif in iface_vifs) {
 				let dev = devices[vif.device];
 				let handler = handlers[vif.device];
 				if (!dev || !handler)
@@ -232,6 +233,7 @@ function config_init(uci)
 				push(vif.sta, sta);
 			}
 		}
+	}
 
 	let udata = ubus.call({
 		object: "service",

package/system/mtd/Makefile

@@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
 include $(INCLUDE_DIR)/kernel.mk
 
 PKG_NAME:=mtd
-PKG_RELEASE:=26
+PKG_RELEASE:=27
 
 PKG_BUILD_DIR := $(KERNEL_BUILD_DIR)/$(PKG_NAME)
 STAMP_PREPARED := $(STAMP_PREPARED)_$(call confvar,CONFIG_MTD_REDBOOT_PARTS)

package/system/mtd/src/fis.c

@@ -67,12 +67,12 @@ fis_open(void)
 	if (fis_fd >= 0)
 		fis_close();
 
-	fis_fd = mtd_check_open("FIS directory");
+	fis_fd = mtd_check_open("FIS directory", true);
 	if (fis_fd < 0)
 		goto error;
 
 	close(fis_fd);
-	fis_fd = mtd_open("FIS directory", true);
+	fis_fd = mtd_open("FIS directory", true, true);
 	if (fis_fd < 0)
 		goto error;
 

package/system/mtd/src/imagetag.c

@@ -195,7 +195,7 @@ trx_fixup(int fd, const char *name)
 		goto err;
 	}
 
-	bfd = mtd_open(name, true);
+	bfd = mtd_open(name, true, true);
 	ptr = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, bfd, 0);
 	if (!ptr || (ptr == (void *) -1)) {
 		perror("mmap");
@@ -269,7 +269,7 @@ trx_check(int imagefd, const char *mtd, char *buf, int *len)
 	}
 
 	/* check if image fits to mtd device */
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		exit(1);
@@ -308,7 +308,7 @@ mtd_fixtrx(const char *mtd, size_t offset, size_t data_size)
 	block_offset = offset & ~(erasesize - 1);
 	offset -= block_offset;
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		exit(1);

package/system/mtd/src/jffs2.c

@@ -287,7 +287,7 @@ int mtd_write_jffs2(const char *mtd, const char *filename, const char *dir)
 {
 	int err = -1, fdeof = 0;
 
-	outfd = mtd_check_open(mtd);
+	outfd = mtd_check_open(mtd, true);
 	if (outfd < 0)
 		return -1;
 

package/system/mtd/src/linksys_bootcount.c

@@ -83,7 +83,7 @@ int mtd_resetbc(const char *mtd)
 
 	DLOG_OPEN();
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 
 	if (ioctl(fd, MEMGETINFO, &mtd_info) < 0) {
 		DLOG_ERR("Unable to obtain mtd_info for given partition name.");

package/system/mtd/src/mtd.c

@@ -96,15 +96,19 @@ int jffs2_skip_bytes=0;
 int mtdtype = 0;
 uint32_t opt_trxmagic = TRX_MAGIC;
 
-int mtd_open(const char *mtd, bool block)
+int mtd_open(const char *mtd, bool block, bool write_mode)
 {
 	FILE *fp;
 	char dev[PATH_MAX];
 	int i;
 	int ret;
-	int flags = O_RDWR | O_SYNC;
+	int flags = O_RDONLY;
 	char name[PATH_MAX];
 
+	if(write_mode) {
+		flags = O_RDWR | O_SYNC;
+	}
+
 	snprintf(name, sizeof(name), "\"%s\"", mtd);
 	if ((fp = fopen("/proc/mtd", "r"))) {
 		while (fgets(dev, sizeof(dev), fp)) {
@@ -124,12 +128,12 @@ int mtd_open(const char *mtd, bool block)
 	return open(mtd, flags);
 }
 
-int mtd_check_open(const char *mtd)
+int mtd_check_open(const char *mtd, bool write_mode)
 {
 	struct mtd_info_user mtdInfo;
 	int fd;
 
-	fd = mtd_open(mtd, false);
+	fd = mtd_open(mtd, false, write_mode);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		return -1;
@@ -253,7 +257,7 @@ static int mtd_check(const char *mtd)
 			next++;
 		}
 
-		fd = mtd_check_open(mtd);
+		fd = mtd_check_open(mtd, true);
 		if (fd < 0)
 			return 0;
 
@@ -290,7 +294,7 @@ mtd_unlock(const char *mtd)
 			next++;
 		}
 
-		fd = mtd_check_open(mtd);
+		fd = mtd_check_open(mtd, true);
 		if(fd < 0) {
 			fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 			exit(1);
@@ -321,7 +325,7 @@ mtd_erase(const char *mtd)
 	if (quiet < 2)
 		fprintf(stderr, "Erasing %s ...\n", mtd);
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		exit(1);
@@ -357,7 +361,7 @@ mtd_dump(const char *mtd, int part_offset, int size)
 	if (quiet < 2)
 		fprintf(stderr, "Dumping %s ...\n", mtd);
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, false);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		return -1;
@@ -416,7 +420,7 @@ mtd_verify(const char *mtd, char *file)
 		return -1;
 	}
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, false);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		return -1;
@@ -551,7 +555,7 @@ resume:
 		next++;
 	}
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		exit(1);
@@ -770,6 +774,7 @@ static void usage(void)
 	fprintf(stderr, "Usage: mtd [<options> ...] <command> [<arguments> ...] <device>[:<device>...]\n\n"
 	"The device is in the format of mtdX (eg: mtd4) or its label.\n"
 	"mtd recognizes these commands:\n"
+	"        dump                    dump mtd device\n"	
 	"        unlock                  unlock the device\n"
 	"        refresh                 refresh mtd partition\n"
 	"        erase                   erase all data on device\n"
@@ -812,7 +817,10 @@ static void usage(void)
 	if (mtd_fixtrx) {
 	    fprintf(stderr,
 	"        -M <magic>              magic number of the image header in the partition (for fixtrx)\n"
-	"        -o offset               offset of the image header in the partition(for fixtrx)\n");
+	"        -o offset               offset of the image header in the partition (for dump / fixtrx)\n");
+	} else {
+	    fprintf(stderr,
+	"        -o offset               offset of the image header in the partition (for dump)\n");
 	}
 	if (mtd_fixtrx || mtd_fixseama || mtd_fixwrg || mtd_fixwrgg) {
 		fprintf(stderr,

package/system/mtd/src/mtd.h

@@ -15,8 +15,8 @@ extern int mtdsize;
 extern int erasesize;
 extern uint32_t opt_trxmagic;
 
-extern int mtd_open(const char *mtd, bool block);
+extern int mtd_open(const char *mtd, bool block, bool write_mode);
-extern int mtd_check_open(const char *mtd);
+extern int mtd_check_open(const char *mtd, bool write_mode);
 extern int mtd_block_is_bad(int fd, int offset);
 extern int mtd_erase_block(int fd, int offset);
 extern int mtd_write_buffer(int fd, const char *buf, int offset, int length);

package/system/mtd/src/seama.c

@@ -121,7 +121,7 @@ mtd_fixseama(const char *mtd, size_t offset, size_t data_size)
 	block_offset = offset & ~(erasesize - 1);
 	offset -= block_offset;
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		exit(1);

package/system/mtd/src/tpl_ramips_recoveryflag.c

@@ -49,7 +49,7 @@ int mtd_tpl_recoverflag_write(const char *mtd, const bool recovery_active)
 		return -1;
 	}
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if (fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		ret = -1;

package/system/mtd/src/trx.c

@@ -83,7 +83,7 @@ trx_fixup(int fd, const char *name)
 		goto err;
 	}
 
-	bfd = mtd_open(name, true);
+	bfd = mtd_open(name, true, true);
 	ptr = mmap(NULL, len, PROT_READ|PROT_WRITE, MAP_SHARED, bfd, 0);
 	if (!ptr || (ptr == (void *) -1)) {
 		perror("mmap");
@@ -138,7 +138,7 @@ trx_check(int imagefd, const char *mtd, char *buf, int *len)
 	}
 
 	/* check if image fits to mtd device */
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		exit(1);
@@ -168,7 +168,7 @@ mtd_fixtrx(const char *mtd, size_t offset, size_t data_size)
 	if (quiet < 2)
 		fprintf(stderr, "Trying to fix trx header in %s at 0x%zx...\n", mtd, offset);
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		exit(1);

package/system/mtd/src/wrg.c

@@ -141,7 +141,7 @@ mtd_fixwrg(const char *mtd, size_t offset, size_t data_size)
 	block_offset = offset & ~(erasesize - 1);
 	offset -= block_offset;
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		exit(1);

package/system/mtd/src/wrgg.c

@@ -119,7 +119,7 @@ mtd_fixwrgg(const char *mtd, size_t offset, size_t data_size)
 	block_offset = offset & ~(erasesize - 1);
 	offset -= block_offset;
 
-	fd = mtd_check_open(mtd);
+	fd = mtd_check_open(mtd, true);
 	if(fd < 0) {
 		fprintf(stderr, "Could not open mtd device: %s\n", mtd);
 		exit(1);

package/system/refpolicy/Makefile

@@ -6,12 +6,12 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=refpolicy
-PKG_VERSION:=2.20200229
+PKG_VERSION:=2.20250923
-PKG_RELEASE:=3
+PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
-PKG_SOURCE_URL:=https://github.com/SELinuxProject/refpolicy/releases/download/RELEASE_2_20200229
+PKG_SOURCE_URL:=https://github.com/SELinuxProject/refpolicy/releases/download/RELEASE_2_20250923
-PKG_HASH:=dec854512ed00cd057408f330c2cea4de7a4405f7a147458f59c994bf578e4b0
+PKG_HASH:=e5b435c934048d01ca4415a1f2670a51e113f26f5d01ad4227c98fbe8dea8d5b
 PKG_INSTALL:=1
 PKG_BUILD_DEPENDS:=checkpolicy/host policycoreutils/host
 

package/system/refpolicy/patches/100-no-docs.patch

@@ -1,10 +1,8 @@
 --- a/Makefile
 +++ b/Makefile
-@@ -648,6 +648,6 @@ ifneq ($(generated_fc),)
+@@ -729,4 +729,4 @@ ifneq ($(generated_fc),)
  endif
  endif
  
--.PHONY: install-src install-appconfig install-headers generate xml conf html bare tags
+-.PHONY: install-src install-appconfig install-headers install-udica-templates build-interface-db generate xml conf html bare tags
-+.PHONY: install-src install-appconfig install-headers generate conf bare tags
++.PHONY: install-src install-appconfig install-headers install-udica-templates build-interface-db generate conf bare tags
- .SUFFIXES:
- .SUFFIXES: .c

package/system/selinux-policy/Makefile

@@ -8,8 +8,8 @@ include $(TOPDIR)/rules.mk
 PKG_NAME:=selinux-policy
 PKG_SOURCE_PROTO:=git
 PKG_SOURCE_URL:=https://git.defensec.nl/selinux-policy.git
-PKG_VERSION:=2.8.2
+PKG_VERSION:=2.8.3
-PKG_MIRROR_HASH:=7e81e6e9e933e6409b7f7bf2d5639960c440c82589c99b199b3540676f88eb8a
+PKG_MIRROR_HASH:=accbb1c7bebfbe48d46ac4060d12a06434ed28d6834b0fb4e22d25d329b277ef
 PKG_SOURCE_VERSION:=v$(PKG_VERSION)
 PKG_BUILD_DEPENDS:=secilc/host policycoreutils/host
 

package/utils/busybox/patches/003-hexdump-fix-regression-for-uint16-on-big-endian-systems.patch

@@ -0,0 +1,41 @@
+From f5c7cae55fc3e19d074198bc12152486067ea8c7 Mon Sep 17 00:00:00 2001
+From: Radoslav Kolev <radoslav.kolev@suse.com>
+Date: Thu, 24 Apr 2025 00:45:25 +0300
+Subject: [PATCH] hexdump: fix regression for uint16 on big endian systems
+
+Commit 34751d8bf introduced a bug in the handling of uint16
+values on big endian systems not considered safe for unaligned
+access when falling back to memcpy.
+
+Signed-off-by: Radoslav Kolev <radoslav.kolev@suse.com>
+Signed-off-by: Denys Vlasenko <vda.linux@googlemail.com>
+---
+ libbb/dump.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/libbb/dump.c
++++ b/libbb/dump.c
+@@ -667,15 +667,21 @@ static NOINLINE void display(priv_dumper
+ 							conv_u(pr, bp);
+ 							break;
+ 						case F_UINT: {
++							union {
++								uint16_t uval16;
++								uint32_t uval32;
++							} u;
+ 							unsigned value = (unsigned char)*bp;
+ 							switch (pr->bcnt) {
+ 							case 1:
+ 								break;
+ 							case 2:
+-								move_from_unaligned16(value, bp);
++								move_from_unaligned16(u.uval16, bp);
++								value = u.uval16;
+ 								break;
+ 							case 4:
+-								move_from_unaligned32(value, bp);
++								move_from_unaligned32(u.uval32, bp);
++								value = u.uval32;
+ 								break;
+ 							/* case 8: no users yet */
+ 							}

package/utils/dtc/Makefile

@@ -5,11 +5,11 @@
 include $(TOPDIR)/rules.mk
 
 PKG_NAME:=dtc
-PKG_VERSION:=1.7.1
+PKG_VERSION:=1.7.2
 PKG_RELEASE:=1
 
 PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.gz
-PKG_HASH:=9532f10098455711a4da37816fd567dfc8523bb01f59ad6c44887a112e553d9e
+PKG_HASH:=f200e5ebd7afd20d4b3804a3085af0870fcf3c194f8d7f0f6985cf8bbb4ac0f4
 PKG_SOURCE_URL:=@KERNEL/software/utils/dtc
 
 PKG_MAINTAINER:=Yousong Zhou <yszhou4tech@gmail.com>

scripts/gen_netgear_rootfs_node.sh

@@ -0,0 +1,39 @@
+#!/bin/sh
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Author: Jascha Sundaresan <flizarthanon@gmail.com>
+#
+# This helper script generates a top-level 'rootfs' node for inclusion
+# in a Flattened Image Tree (FIT) source (.its) file.  The node includes
+# the size and SHA1 hash of a given root filesystem image and is used by
+# certain Netgear devices which expect this metadata at the top level of
+# the FIT structure.
+#
+# The resulting block is written to standard output and can be appended
+# or inserted into an existing .its file by the OpenWrt build system.
+# Example:
+#     scripts/gen_netgear_rootfs_node.sh build_dir/.../root.squashfs > node.txt
+#
+# See also: scripts/mkits.sh, which generates the main FIT .its source.
+
+ROOTFS_FILE="$1"
+ROOTFS_SIZE=$(stat -c %s "${ROOTFS_FILE}")
+ROOTFS_SHA1=$(
+    sha1sum "${ROOTFS_FILE}" | awk '{ print "<0x" substr($0, 1, 8) \
+                                          " 0x" substr($0, 9, 8) \
+                                          " 0x" substr($0, 17, 8) \
+                                          " 0x" substr($0, 25, 8) \
+                                          " 0x" substr($0, 33, 8) ">" }'
+)
+cat <<EOF | sed 's/^/\t/'
+rootfs {
+	size = <${ROOTFS_SIZE}>;
+
+	hash-1 {
+		value = ${ROOTFS_SHA1};
+		algo = "sha1";
+	};
+};
+
+EOF

target/linux/bcm27xx/patches-6.12/950-0132-hid-usb-Add-device-quirks-for-Freeway-Airmouse-T3-an.patch

@@ -32,7 +32,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
  #define USB_VENDOR_ID_BELKIN		0x050d
  #define USB_DEVICE_ID_FLIP_KVM		0x3201
  
-@@ -1466,6 +1469,9 @@
+@@ -1470,6 +1473,9 @@
  #define USB_VENDOR_ID_XIAOMI		0x2717
  #define USB_DEVICE_ID_MI_SILENT_MOUSE	0x5014
  
@@ -52,7 +52,7 @@ Signed-off-by: Jonathan Bell <jonathan@raspberrypi.org>
  	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_MULTI_TOUCH), HID_QUIRK_MULTI_INPUT },
  	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE), HID_QUIRK_ALWAYS_POLL },
  	{ HID_USB_DEVICE(USB_VENDOR_ID_CHICONY, USB_DEVICE_ID_CHICONY_PIXART_USB_OPTICAL_MOUSE2), HID_QUIRK_ALWAYS_POLL },
-@@ -213,6 +214,7 @@ static const struct hid_device_id hid_qu
+@@ -215,6 +216,7 @@ static const struct hid_device_id hid_qu
  	{ HID_USB_DEVICE(USB_VENDOR_ID_WISEGROUP, USB_DEVICE_ID_QUAD_USB_JOYPAD), HID_QUIRK_NOGET | HID_QUIRK_MULTI_INPUT },
  	{ HID_USB_DEVICE(USB_VENDOR_ID_XIN_MO, USB_DEVICE_ID_XIN_MO_DUAL_ARCADE), HID_QUIRK_MULTI_INPUT },
  	{ HID_USB_DEVICE(USB_VENDOR_ID_LOGITECH, USB_DEVICE_ID_LOGITECH_GROUP_AUDIO), HID_QUIRK_NOGET },

target/linux/bcm27xx/patches-6.12/950-0172-spi-Force-CS_HIGH-if-GPIO-descriptors-are-used.patch

@@ -32,7 +32,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
 
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -3897,6 +3897,7 @@ static int spi_set_cs_timing(struct spi_
+@@ -3907,6 +3907,7 @@ static int spi_set_cs_timing(struct spi_
   */
  int spi_setup(struct spi_device *spi)
  {
@@ -40,7 +40,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  	unsigned	bad_bits, ugly_bits;
  	int		status;
  
-@@ -3923,6 +3924,14 @@ int spi_setup(struct spi_device *spi)
+@@ -3933,6 +3934,14 @@ int spi_setup(struct spi_device *spi)
  			"setup: MOSI configured to idle low and high at the same time.\n");
  		return -EINVAL;
  	}

target/linux/econet/base-files/sbin/en75_chboot

@@ -124,6 +124,14 @@ main() {
         code_offset=0
         code_openwrt=30000000
         code_factory=31000000
+    elif [ "$machine" = "Zyxel PMG5617GA" ]; then
+        # 00060fff
+        part=$(part_named '"reservearea"')
+        offset_blocks=3
+        block_size=$((1024 * 128))
+        code_offset=4095
+        code_openwrt=30
+        code_factory=31
     else
         echo "Unsupported machine: $machine"
         exit 1

target/linux/econet/dts/en751221_zyxel_pmg5617ga.dts

@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+#include "en751221.dtsi"
+
+/ {
+	model = "Zyxel PMG5617GA";
+	compatible = "tplink,zyxel-pmg5617ga", "econet,en751221";
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x8000000>;
+	};
+
+	chosen {
+		stdout-path = "/serial@1fbf0000:115200";
+		linux,usable-memory-range = <0x00020000 0x07fe0000>;
+	};
+};
+
+&nand {
+	status = "okay";
+	econet,bmt;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "bootloader";
+			reg = <0x0 0x40000>;
+			read-only;
+		};
+
+		partition@40000 {
+			label = "romfile";
+			reg = <0x40000 0x40000>;
+			read-only;
+		};
+
+		partition@80000 {
+			label = "tclinux";
+			reg = <0x80000 0x3800000>;
+			read-only;
+			econet,enable-remap;
+		};
+
+		/* Nested inside of tclinux */
+		partition@480000 {
+			label = "rootfs";
+			reg = <0x480000 0x3400000>;
+			linux,rootfs;
+			read-only;
+		};
+
+		partition@3880000 {
+			label = "tclinux_alt";
+			reg = <0x3880000 0x0036c0000>;
+		};
+
+		partition@6f40000 {
+			label = "wwan";
+			reg = <0x006f40000 0x000100000>;
+		};
+
+		partition@7040000 {
+			label = "factory_data";
+			reg = <0x007040000 0x000400000>;
+		};
+
+		partition@7440000 {
+			label = "rom-d";
+			reg = <0x007440000 0x000100000>;
+		};
+
+		partition@7540000 {
+			label = "reservearea";
+			reg = <0x007540000 0x000080000>;
+		};
+	};
+};

target/linux/econet/image/en751221.mk

@@ -44,3 +44,13 @@ define Device/tplink_archer-vr1200v-v2
     tplink-v2-header -R 0x400000
 endef
 TARGET_DEVICES += tplink_archer-vr1200v-v2
+
+define Device/zyxel_pmg5617ga
+  DEVICE_VENDOR := Zyxel
+  DEVICE_MODEL := PMG5617GA
+  DEVICE_DTS := en751221_zyxel_pmg5617ga
+  IMAGES := tclinux.trx
+  IMAGE/tclinux.trx := append-kernel | lzma | tclinux-trx
+  DEVICE_PACKAGES := kmod-usb3
+endef
+TARGET_DEVICES += zyxel_pmg5617ga

target/linux/generic/backport-6.12/010-v6.19-nvmem-layouts-u-boot-env-add-optional-env-size-property.patch

@@ -0,0 +1,62 @@
+From 06e92afca89075628b12c9b4085b4cc7320081ac Mon Sep 17 00:00:00 2001
+From: Jascha Sundaresan <flizarthanon@gmail.com>
+Date: Thu, 23 Oct 2025 03:07:41 +0400
+Subject: nvmem: layouts: u-boot-env: add optional "env-size" property
+
+Some devices reserve a larger NVMEM region for the U-Boot environment
+than the actual environment data length used by U-Boot itself. The CRC32
+in the U-Boot header is calculated over the smaller data length, causing
+CRC validation to fail when Linux reads the full partition.
+
+Allow an optional device tree property "env-size" to specify the
+environment data size to use for CRC computation.
+
+v2: add missing $ref line to DT binding
+
+Signed-off-by: Jascha Sundaresan <flizarthanon@gmail.com>
+Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
+Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
+---
+ Documentation/devicetree/bindings/nvmem/layouts/u-boot,env.yaml | 7 +++++++
+ drivers/nvmem/layouts/u-boot-env.c                              | 4 +++-
+ 2 files changed, 10 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/nvmem/layouts/u-boot,env.yaml
++++ b/Documentation/devicetree/bindings/nvmem/layouts/u-boot,env.yaml
+@@ -46,6 +46,12 @@ properties:
+     type: object
+     description: Command to use for automatic booting
+ 
++  env-size:
++    description:
++      Size in bytes of the environment data used by U-Boot for CRC
++      calculation. If omitted, the full NVMEM region size is used.
++    $ref: /schemas/types.yaml#/definitions/uint32
++
+   ethaddr:
+     type: object
+     description: Ethernet interfaces base MAC address.
+@@ -104,6 +110,7 @@ examples:
+ 
+             partition-u-boot-env {
+                 compatible = "brcm,env";
++                env-size = <0x20000>;
+ 
+                 ethaddr {
+                 };
+--- a/drivers/nvmem/layouts/u-boot-env.c
++++ b/drivers/nvmem/layouts/u-boot-env.c
+@@ -99,10 +99,12 @@ int u_boot_env_parse(struct device *dev,
+ 	uint32_t crc32;
+ 	uint32_t calc;
+ 	uint8_t *buf;
++	u32 env_size;
+ 	int bytes;
+ 	int err;
+ 
+-	dev_size = nvmem_dev_size(nvmem);
++	dev_size = device_property_read_u32(dev, "env-size", &env_size) ?
++		nvmem_dev_size(nvmem) : (size_t)env_size;
+ 
+ 	buf = kzalloc(dev_size, GFP_KERNEL);
+ 	if (!buf) {

target/linux/generic/backport-6.12/404-v6.19-mtd-spinand-fmsh-remove-QE-bit-for-FM25S01A-flash.patch

@@ -0,0 +1,28 @@
+From a1d3bc606bf5c3b3ea811cc2019df6285d75b00f Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 3 Nov 2025 04:01:48 +0300
+Subject: [PATCH] mtd: spinand: fmsh: remove QE bit for FM25S01A flash
+
+According to datasheet (http://eng.fmsh.com/nvm/FM25S01A_ds_eng.pdf)
+there is no QE (Quad Enable) bit for FM25S01A flash, so remove it.
+
+Fixes: 5f284dc15ca86 ("mtd: spinand: add support for FudanMicro FM25S01A")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Tested-by: Tianling Shen <cnsztl@gmail.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: Link: https://lore.kernel.org/linux-mtd/176216634975.908445.2776312239779833518.b4-ty@bootlin.com
+---
+ drivers/mtd/nand/spi/fmsh.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mtd/nand/spi/fmsh.c
++++ b/drivers/mtd/nand/spi/fmsh.c
+@@ -58,7 +58,7 @@ static const struct spinand_info fmsh_sp
+ 		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ 					      &write_cache_variants,
+ 					      &update_cache_variants),
+-		     SPINAND_HAS_QE_BIT,
++		     0,
+ 		     SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)),
+ };
+ 

target/linux/generic/backport-6.12/720-09-v6.14-net-phy-Constify-struct-mdio_device_id.patch

@@ -458,7 +458,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	{ }
 --- a/drivers/net/phy/micrel.c
 +++ b/drivers/net/phy/micrel.c
-@@ -5701,7 +5701,7 @@ MODULE_DESCRIPTION("Micrel PHY driver");
+@@ -5826,7 +5826,7 @@ MODULE_DESCRIPTION("Micrel PHY driver");
  MODULE_AUTHOR("David J. Choi");
  MODULE_LICENSE("GPL");
  

target/linux/generic/kernel-6.12

@@ -1,2 +1,2 @@
-LINUX_VERSION-6.12 = .58
+LINUX_VERSION-6.12 = .59
-LINUX_KERNEL_HASH-6.12.58 = 5f1c4c546660a6a81046fdfa6195306bad2c8d17c0d69876dc100a85ad4613ac
+LINUX_KERNEL_HASH-6.12.59 = a1d2cd7327f10eec022615c1bb12c06439bd110d2020164be97f698f43ca58be

target/linux/generic/pending-6.12/403-mtd-spinand-add-support-for-FudanMicro-FM25S01BI3.patch

@@ -0,0 +1,117 @@
+To: Miquel Raynal <miquel.raynal@bootlin.com>,
+ Richard Weinberger <richard@nod.at>, Vignesh Raghavendra <vigneshr@ti.com>,
+ Tudor Ambarus <tudor.ambarus@linaro.org>, Mark Brown <broonie@kernel.org>
+Cc: linux-kernel@vger.kernel.org, linux-mtd@lists.infradead.org
+From: Mikhail Zhilkin <csharper2005@gmail.com>
+Subject: [PATCH] mtd: spinand: add support for FudanMicro FM25S01BI3
+
+Add support for FudanMicro FM25S01BI3 SPI NAND.
+
+Link: https://www.fmsh.com/nvm/FM25S01BI3_ds_eng.pdf
+
+Signed-off-by: Mikhail Zhilkin <csharper2005@gmail.com>
+Link: https://lore.kernel.org/linux-mtd/130e0f3f-93e4-47cf-82f0-93ba58a3a670@gmail.com
+---
+ drivers/mtd/nand/spi/fmsh.c | 72 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 72 insertions(+)
+
+--- a/drivers/mtd/nand/spi/fmsh.c
++++ b/drivers/mtd/nand/spi/fmsh.c
+@@ -9,6 +9,13 @@
+ #include <linux/kernel.h>
+ #include <linux/mtd/spinand.h>
+ 
++#define FM25S01BI3_STATUS_ECC_MASK		(7 << 4)
++	#define FM25S01BI3_STATUS_ECC_NO_BITFLIPS	(0 << 4)
++	#define FM25S01BI3_STATUS_ECC_1_3_BITFLIPS	(1 << 4)
++	#define FM25S01BI3_STATUS_ECC_UNCOR_ERROR	(2 << 4)
++	#define FM25S01BI3_STATUS_ECC_4_6_BITFLIPS	(3 << 4)
++	#define FM25S01BI3_STATUS_ECC_7_8_BITFLIPS	(5 << 4)
++
+ #define SPINAND_MFR_FMSH		0xA1
+ 
+ static SPINAND_OP_VARIANTS(read_cache_variants,
+@@ -45,11 +52,66 @@ static int fm25s01a_ooblayout_free(struc
+ 	return 0;
+ }
+ 
++static int fm25s01bi3_ecc_get_status(struct spinand_device *spinand,
++				     u8 status)
++{
++	switch (status & FM25S01BI3_STATUS_ECC_MASK) {
++	case FM25S01BI3_STATUS_ECC_NO_BITFLIPS:
++		return 0;
++
++	case FM25S01BI3_STATUS_ECC_UNCOR_ERROR:
++		return -EBADMSG;
++
++	case FM25S01BI3_STATUS_ECC_1_3_BITFLIPS:
++		return 3;
++
++	case FM25S01BI3_STATUS_ECC_4_6_BITFLIPS:
++		return 6;
++
++	case FM25S01BI3_STATUS_ECC_7_8_BITFLIPS:
++		return 8;
++
++	default:
++		break;
++	}
++
++	return -EINVAL;
++}
++
++static int fm25s01bi3_ooblayout_ecc(struct mtd_info *mtd, int section,
++				    struct mtd_oob_region *region)
++{
++	if (section)
++		return -ERANGE;
++
++	region->offset = 64;
++	region->length = 64;
++
++	return 0;
++}
++
++static int fm25s01bi3_ooblayout_free(struct mtd_info *mtd, int section,
++				     struct mtd_oob_region *region)
++{
++	if (section > 3)
++		return -ERANGE;
++
++	region->offset = (16 * section) + 4;
++	region->length = 12;
++
++	return 0;
++}
++
+ static const struct mtd_ooblayout_ops fm25s01a_ooblayout = {
+ 	.ecc = fm25s01a_ooblayout_ecc,
+ 	.free = fm25s01a_ooblayout_free,
+ };
+ 
++static const struct mtd_ooblayout_ops fm25s01bi3_ooblayout = {
++	.ecc = fm25s01bi3_ooblayout_ecc,
++	.free = fm25s01bi3_ooblayout_free,
++};
++
+ static const struct spinand_info fmsh_spinand_table[] = {
+ 	SPINAND_INFO("FM25S01A",
+ 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
+@@ -60,6 +122,16 @@ static const struct spinand_info fmsh_sp
+ 					      &update_cache_variants),
+ 		     0,
+ 		     SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)),
++	SPINAND_INFO("FM25S01BI3",
++		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xd4),
++		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
++		     NAND_ECCREQ(8, 512),
++		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
++					      &write_cache_variants,
++					      &update_cache_variants),
++		     SPINAND_HAS_QE_BIT,
++		     SPINAND_ECCINFO(&fm25s01bi3_ooblayout,
++				      fm25s01bi3_ecc_get_status)),
+ };
+ 
+ static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = {

target/linux/generic/pending-6.12/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch

@@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/netfilter/nf_tables_api.c
 +++ b/net/netfilter/nf_tables_api.c
-@@ -8666,7 +8666,7 @@ static int nft_register_flowtable_net_ho
+@@ -8656,7 +8656,7 @@ static int nft_register_flowtable_net_ho
  		err = flowtable->data.type->setup(&flowtable->data,
  						  hook->ops.dev,
  						  FLOW_BLOCK_BIND);

target/linux/mediatek/dts/mt7981b-netgear-eax17.dts

@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+#include "mt7981b.dtsi"
+
+/ {
+	model = "Netgear EAX17";
+	compatible = "netgear,eax17", "mediatek,mt7981-spim-snand-rfb";
+
+	aliases {
+		led-boot = &led_power_green;
+		led-failsafe = &led_power_red;
+		led-running = &led_power_green;
+		led-upgrade = &led_power_red;
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@40000000 {
+		reg = <0 0x40000000 0 0x20000000>;
+		device_type = "memory";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		wps {
+			label = "wps";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 0 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led_power_green: power_green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+		};
+
+		led_power_red: power_red {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+		};
+
+		led_rlink_red: rlink_red {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_LAN;
+			gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+		};
+
+		led_rlink_green: rlink_green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_LAN;
+			gpios = <&pio 7 GPIO_ACTIVE_LOW>;
+		};
+
+		led_clink_red: clink_red {
+			color = <LED_COLOR_ID_RED>;
+			function = LED_FUNCTION_WAN;
+			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+		};
+
+		led_clink_green: clink_green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WAN;
+			gpios = <&pio 11 GPIO_ACTIVE_LOW>;
+		};
+
+		led_wps_green: wps_green {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_WPS;
+			gpios = <&pio 5 GPIO_ACTIVE_LOW>;
+		};
+
+		led_lan_speed_fast: lan_speed_fast {
+			color = <LED_COLOR_ID_GREEN>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&pio 13 GPIO_ACTIVE_LOW>;
+		};
+
+		led_lan_speed_slow: lan_speed_slow {
+			color = <LED_COLOR_ID_YELLOW>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&pio 8 GPIO_ACTIVE_LOW>;
+		};
+
+	};
+
+};
+
+&eth {
+	status = "okay";
+
+	gmac0: mac@0 {
+		status = "disabled";
+	};
+
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "gmii";
+		phy-handle = <&int_gbe_phy>;
+
+		nvmem-cells = <&ethaddr 0>;
+		nvmem-cell-names = "mac-address";
+	};
+};
+
+&crypto {
+	status = "okay";
+};
+
+&pio {
+	spi_flash_pins: spi0-pins {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+
+		conf-pu {
+			pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
+		};
+
+		conf-pd {
+			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
+			drive-strength = <MTK_DRIVE_8mA>;
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_flash_pins>;
+	status = "okay";
+
+	spi_nand_flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-nand";
+		reg = <0>;
+
+		spi-max-frequency = <52000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "fixed-partitions";
+
+			partition@0 {
+				label = "bl2";
+				reg = <0x0 0x100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x0100000 0x0080000>;
+			};
+
+			factory: partition@180000 {
+				label = "factory";
+				reg = <0x180000 0x200000>;
+				compatible = "nvmem-cells";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				eeprom_factory_0: eeprom@0 {
+					reg = <0x0 0x1000>;
+				};
+			};
+
+			partition@380000 {
+				label = "fip";
+				reg = <0x380000 0x0200000>;
+			};
+
+			partition@580000 {
+				label = "ubi";
+				reg = <0x580000 0x5000000>;
+				compatible = "linux,ubi";
+
+				volumes {
+					ubi-volume-u-boot-env {
+						volname = "u-boot-env";
+
+						nvmem-layout {
+							compatible = "u-boot,env";
+							env-size = <0x80000>;
+
+							ethaddr: ethaddr {
+								#nvmem-cell-cells = <1>;
+							};
+						};
+					};
+				};
+			};
+
+			partition@5580000 {
+				label = "facenv";
+				reg = <0x5580000 0x200000>;
+			};
+
+			partition@5780000 {
+				label = "rae";
+				reg = <0x5780000 0x600000>;
+			};
+
+			partition@5D80000 {
+				label = "pot";
+				reg = <0x5D80000 0x020000>;
+			};
+
+			partition@5DA0000 {
+				label = "log";
+				reg = <0x5DA0000 0x040000>;
+			};
+
+		};
+	};
+};
+
+&xhci {
+	status = "disabled";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&wifi {
+	status = "okay";
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
+
+	band@0 {
+		reg = <0>;
+		nvmem-cells = <&ethaddr 2>;
+		nvmem-cell-names = "mac-address";
+	};
+
+	band@1 {
+		reg = <1>;
+		nvmem-cells = <&ethaddr 3>;
+		nvmem-cell-names = "mac-address";
+	};
+};
+
+&pcie {
+	status = "disabled";
+};

target/linux/mediatek/dts/mt7986a-asus-tuf-ax6000.dts

@@ -252,7 +252,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		spi-max-frequency = <20000000>;
+		spi-max-frequency = <52000000>;
 		spi-tx-bus-width = <4>;
 		spi-rx-bus-width = <4>;
 

target/linux/mediatek/dts/mt7986a-iptime-ax7800m-6e.dts

@@ -149,7 +149,7 @@
 				   "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 				   "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 				   "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
+			drive-strength = <MTK_DRIVE_4mA>;
 		};
 	};
 
@@ -166,7 +166,7 @@
 				   "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 				   "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 				   "WF1_TOP_CLK", "WF1_TOP_DATA";
-			drive-strength = <4>;
+			drive-strength = <MTK_DRIVE_4mA>;
 		};
 	};
 };

target/linux/mediatek/dts/mt7986a-wavlink-wl-wn536ax6-a.dts

@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/mt65xx.h>
+
+#include "mt7986a.dtsi"
+
+/ {
+	compatible = "wavlink,wl-wn536ax6-a", "mediatek,mt7986a";
+	model = "WAVLINK WL-WN536AX6 Rev a";
+
+	aliases {
+		serial0 = &uart0;
+		label-mac-device = &wifi;
+		led-boot = &led_status_blue;
+		led-failsafe = &led_status_blue;
+		led-running = &led_status_blue;
+		led-upgrade = &led_status_blue;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		reset {
+			label = "reset";
+			linux,code = <KEY_RESTART>;
+			gpios = <&pio 9 GPIO_ACTIVE_LOW>;
+		};
+
+		pair {
+			label = "pair";
+			linux,code = <KEY_WPS_BUTTON>;
+			gpios = <&pio 10 GPIO_ACTIVE_LOW>;
+		};
+
+		turbo {
+			label = "turbo";
+			linux,code = <BTN_MISC>;
+			gpios = <&pio 12 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led-0 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_WAN;
+			gpios = <&pio 1 GPIO_ACTIVE_LOW>;
+		};
+
+		led-1 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_POWER;
+			gpios = <&pio 14 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_status_blue: led-2 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_STATUS;
+			gpios = <&pio 31 GPIO_ACTIVE_LOW>;
+		};
+
+		led-3 {
+			color = <LED_COLOR_ID_BLUE>;
+			function = LED_FUNCTION_WLAN;
+			gpios = <&pio 32 GPIO_ACTIVE_LOW>;
+			linux,default-trigger = "phy1tpt";
+		};
+	};
+
+	memory@40000000 {
+		reg = <0 0x40000000 0 0x20000000>;
+		device_type = "memory";
+	};
+
+	reg_1p8v: regulator-1p8v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-1.8V";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_3p3v: regulator-3p3v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-3.3V";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	reg_5v: regulator-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "fixed-5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+};
+
+&crypto {
+	status = "okay";
+};
+
+&eth {
+	status = "okay";
+
+	/* LAN */
+	gmac0: mac@0 {
+		compatible = "mediatek,eth-mac";
+		reg = <0>;
+		phy-mode = "2500base-x";
+
+		nvmem-cell-names = "mac-address";
+		nvmem-cells = <&macaddr_hw_44e 0>;
+
+		fixed-link {
+			full-duplex;
+			pause;
+			speed = <2500>;
+		};
+	};
+
+	/* WAN */
+	gmac1: mac@1 {
+		compatible = "mediatek,eth-mac";
+		reg = <1>;
+		phy-mode = "2500base-x";
+		phy-handle = <&phy6>;
+
+		nvmem-cell-names = "mac-address";
+		nvmem-cells = <&macaddr_hw_44e 1>;
+	};
+
+	mdio-bus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* MaxLinear GPY211C 2.5G PHY */
+		phy6: phy@6 {
+			/*
+			 * Force the ID here as the PHY only reports it's
+			 * (C45) ID correctly after a reset (before resetting
+			 * it reports 0xfffffff, which causes only the genphy
+			 * driver to match).
+			 */
+			compatible = "ethernet-phy-id67c9.de10";
+			reg = <6>;
+			reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <600>;
+			reset-deassert-us = <20000>;
+			phy-mode = "2500base-x";
+		};
+
+		switch@1f {
+			compatible = "mediatek,mt7531";
+			reg = <31>;
+			reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				port@0 {
+					reg = <0>;
+					label = "lan4";
+				};
+
+				port@1 {
+					reg = <1>;
+					label = "lan3";
+				};
+
+				port@2 {
+					reg = <2>;
+					label = "lan2";
+				};
+
+				port@3 {
+					reg = <3>;
+					label = "lan1";
+				};
+
+				port@6 {
+					reg = <6>;
+					label = "cpu";
+					ethernet = <&gmac0>;
+					phy-mode = "2500base-x";
+
+					fixed-link {
+						speed = <2500>;
+						full-duplex;
+						pause;
+					};
+				};
+			};
+		};
+	};
+};
+
+&pio {
+	spi_flash_pins: spi-flash-pins-33-to-38 {
+		mux {
+			function = "spi";
+			groups = "spi0", "spi0_wp_hold";
+		};
+
+		conf-pd {
+			pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+			drive-strength = <MTK_DRIVE_8mA>;
+		};
+
+		conf-pu {
+			pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+			bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
+			drive-strength = <MTK_DRIVE_8mA>;
+		};
+	};
+
+	wf_2g_5g_pins: wf_2g_5g-pins {
+		mux {
+			function = "wifi";
+			groups = "wf_2g", "wf_5g";
+		};
+
+		conf {
+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+					"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+					"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+					"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+					"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+					"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+					"WF1_TOP_CLK", "WF1_TOP_DATA";
+			drive-strength = <MTK_DRIVE_4mA>;
+		};
+	};
+
+	wf_dbdc_pins: wf_dbdc-pins {
+		mux {
+			function = "wifi";
+			groups = "wf_dbdc";
+		};
+
+		conf {
+			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
+			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
+			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
+			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
+			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
+			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
+			       "WF1_TOP_CLK", "WF1_TOP_DATA";
+			drive-strength = <MTK_DRIVE_4mA>;
+		};
+	};
+};
+
+&spi0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_flash_pins>;
+	status = "okay";
+
+	/* Macronix SPI NAND (128M) */
+	flash@0 {
+		compatible = "spi-nand";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0>;
+
+		spi-max-frequency = <52000000>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+
+		spi-cal-enable;
+		spi-cal-mode = "read-data";
+		spi-cal-datalen = <7>;
+		spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4e 0x41 0x4e 0x44>;
+		spi-cal-addrlen = <5>;
+		spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				label = "BL2";
+				reg = <0x0 0x100000>;
+				read-only;
+			};
+
+			partition@100000 {
+				label = "u-boot-env";
+				reg = <0x100000 0x80000>;
+			};
+
+			partition@180000 {
+				label = "Factory";
+				reg = <0x180000 0x200000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					eeprom_factory_0: eeprom@0 {
+						reg = <0x0 0x1000>;
+					};
+				};
+			};
+
+			partition@380000 {
+				label = "FIP";
+				reg = <0x380000 0x200000>;
+				read-only;
+			};
+
+			partition@580000 {
+				label = "ubi";
+				reg = <0x580000 0x4000000>;
+			};
+
+			partition@7580000 {
+				label = "HW";
+				reg = <0x4580000 0x80000>;
+				read-only;
+
+				nvmem-layout {
+					compatible = "fixed-layout";
+					#address-cells = <1>;
+					#size-cells = <1>;
+
+					macaddr_hw_44e: macaddr@44e {
+						compatible = "mac-base";
+						reg = <0x44e 0x11>;
+						#nvmem-cell-cells = <1>;
+					};
+				};
+			};
+		};
+	};
+};
+
+&ssusb {
+	status = "okay";
+	vusb33-supply = <&reg_3p3v>;
+	vbus-supply = <&reg_5v>;
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&usb_phy {
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&watchdog {
+	status = "okay";
+};
+
+&wifi {
+	nvmem-cells = <&eeprom_factory_0>;
+	nvmem-cell-names = "eeprom";
+	pinctrl-names = "default", "dbdc";
+	pinctrl-0 = <&wf_2g_5g_pins>;
+	pinctrl-1 = <&wf_dbdc_pins>;
+	status = "okay";
+};

target/linux/mediatek/filogic/base-files/etc/board.d/01_leds

@@ -135,6 +135,17 @@ netcore,n60-pro)
 	ucidef_set_led_netdev "wanact" "WANACT" "mdio-bus:06:green:wan" "eth1" "tx rx"
 	ucidef_set_led_netdev "wanlink" "WANLINK" "blue:wan" "eth1" "link"
 	;;
+netgear,eax17)
+	ucidef_set_led_default power_green "Power (green)" green:power 1
+	ucidef_set_led_default power_red   "Power (red)"   red:power   0
+	ucidef_set_led_default rlink_red   "Client (red)"  red:lan     0
+	ucidef_set_led_default clink_red   "Router (red)"  red:wan     0
+	ucidef_set_led_wps     wps_green   "WPS (green)"   green:wps
+	ucidef_set_led_netdev  lan_speed_fast  "LAN Link (green)"     green:status  eth0
+	uci -q set system.lan_speed_fast.mode='link'
+	ucidef_set_led_netdev  lan_speed_slow  "LAN Activity (yellow)" yellow:status eth0
+	uci -q set system.lan_speed_slow.mode='tx rx'
+	;;
 netgear,wax220)
 	ucidef_set_led_netdev "eth0" "LAN" "green:lan" "eth0"
 	;;
@@ -253,6 +264,10 @@ tplink,tl-7dr7250-v1)
 	ucidef_set_led_netdev "lan2" "LAN2" "mt7530-0:00:green:lan" "lan2"
 	ucidef_set_led_netdev "lan3" "LAN3" "mdio-bus:0f:green:lan" "lan3"
 	;;
+wavlink,wl-wn536ax6-a)
+	ucidef_set_led_netdev "wifi" "wifi" "blue:wlan" "phy1-ap0" "link"
+	ucidef_set_led_netdev "wan" "wan" "blue:wan" "eth1" "link tx rx"
+	;;
 wavlink,wl-wn551x3)
         ucidef_set_led_netdev "lan-1" "lan-1" "green:lan-1" "lan1" "link tx rx"
         ucidef_set_led_netdev "lan-2" "lan-2" "green:lan-2" "lan2" "link tx rx"

target/linux/mediatek/filogic/base-files/etc/board.d/02_network

@@ -73,6 +73,7 @@ mediatek_setup_interfaces()
 	nradio,c8-668gl|\
 	ruijie,rg-x60-pro|\
 	unielec,u7981-01*|\
+	wavlink,wl-wn536ax6-a|\
 	zbtlink,zbt-z8102ax|\
 	zbtlink,zbt-z8102ax-v2)
 		ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
@@ -110,6 +111,7 @@ mediatek_setup_interfaces()
 	cudy,ap3000outdoor-v1|\
 	cudy,ap3000-v1|\
 	cudy,re3000-v1|\
+	netgear,eax17|\
 	netgear,wax220|\
 	openfi,6c|\
 	ubnt,unifi-6-plus|\

target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh

@@ -195,6 +195,17 @@ platform_do_upgrade() {
 		CI_UBIPART="ubi0"
 		nand_do_upgrade "$1"
 		;;
+	netgear,eax17)
+		echo "UPGRADING SECOND SLOT"
+		CI_KERNPART="kernel2"
+		CI_ROOTPART="rootfs2"
+		nand_do_flash_file "$1" || nand_do_upgrade_failed
+		echo "UPGRADING PRIMARY SLOT"
+		CI_KERNPART="kernel"
+		CI_ROOTPART="rootfs"
+		nand_do_flash_file "$1" || nand_do_upgrade_failed
+		nand_do_upgrade_success
+		;;
 	tplink,fr365-v1)
 		CI_UBIPART="ubi"
 		CI_KERNPART="kernel"

target/linux/mediatek/filogic/config-6.12

@@ -337,8 +337,10 @@ CONFIG_NVMEM_AN8855_EFUSE=y
 CONFIG_NVMEM_BLOCK=y
 CONFIG_NVMEM_LAYOUTS=y
 CONFIG_NVMEM_LAYOUT_ADTRAN=y
+CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y
 CONFIG_NVMEM_MTK_EFUSE=y
 CONFIG_NVMEM_SYSFS=y
+CONFIG_NVMEM_U_BOOT_ENV=y
 CONFIG_OF=y
 CONFIG_OF_ADDRESS=y
 CONFIG_OF_DYNAMIC=y

target/linux/mediatek/image/filogic.mk

@@ -8,6 +8,15 @@ define Image/Prepare
 	echo -ne '\xde\xad\xc0\xde' > $(KDIR)/ubi_mark
 endef
 
+define Build/fit-with-netgear-top-level-rootfs-node
+	$(call Build/fit-its,$(1))
+	$(TOPDIR)/scripts/gen_netgear_rootfs_node.sh $(KERNEL_BUILD_DIR)/root.squashfs > $@.rootfs
+	awk '/configurations/ { system("cat $@.rootfs") } 1' $@.its > $@.its.tmp
+	@mv -f $@.its.tmp $@.its
+	@rm -f $@.rootfs
+	$(call Build/fit-image,$(1))
+endef
+
 define Build/mt7981-bl2
 	cat $(STAGING_DIR_IMAGE)/mt7981-$1-bl2.img >> $@
 endef
@@ -408,6 +417,16 @@ define Device/asus_tuf-ax4200
   KERNEL_INITRAMFS := kernel-bin | lzma | \
 	fit lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb with-initrd | pad-to 64k
   IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+ifeq ($(IB),)
+ifneq ($(CONFIG_TARGET_ROOTFS_INITRAMFS),)
+ifeq ($(CONFIG_TARGET_ROOTFS_INITRAMFS_SEPARATE),)
+  # The default boot command of the bootloader does not load the ramdisk from the FIT image
+  ARTIFACTS := initramfs.trx
+  ARTIFACT/initramfs.trx := append-image-stage initramfs-kernel.bin | \
+	uImage none | asus-trx -v 3 -n $$(DEVICE_MODEL)
+endif
+endif
+endif
 endef
 TARGET_DEVICES += asus_tuf-ax4200
 
@@ -2115,6 +2134,48 @@ define Device/netcore_n60-pro
 endef
 TARGET_DEVICES += netcore_n60-pro
 
+define Device/netgear_eax17
+  DEVICE_VENDOR := NETGEAR
+  DEVICE_MODEL := EAX17
+  DEVICE_ALT0_VENDOR := NETGEAR
+  DEVICE_ALT0_MODEL := EAX11
+  DEVICE_ALT0_VARIANT := v3
+  DEVICE_ALT1_VENDOR := NETGEAR
+  DEVICE_ALT1_MODEL := EAX15
+  DEVICE_ALT1_VARIANT := v3
+  DEVICE_ALT2_VENDOR := NETGEAR
+  DEVICE_ALT2_MODEL := EAX14
+  DEVICE_ALT2_VARIANT := v3
+  DEVICE_ALT3_VENDOR := NETGEAR
+  DEVICE_ALT3_MODEL := EAX12
+  DEVICE_ALT3_VARIANT := v2
+  DEVICE_ALT4_VENDOR := NETGEAR
+  DEVICE_ALT4_MODEL := EAX16
+  DEVICE_ALT5_VENDOR := NETGEAR
+  DEVICE_ALT5_MODEL := EAX19
+  DEVICE_DTS := mt7981b-netgear-eax17
+  DEVICE_DTS_DIR := ../dts
+  SUPPORTED_DEVICES += mediatek,mt7981-spim-snand-rfb
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  NETGEAR_ENC_MODEL := EAX17
+  NETGEAR_ENC_REGION := US
+  NETGEAR_ENC_HW_ID_LIST := 1010000013120000_NETGEAR
+  NETGEAR_ENC_MODEL_LIST := EAX17;EAX11v3;EAX15v3;EAX14v3;EAX12v2;EAX16;EAX19
+  DEVICE_PACKAGES := kmod-mt7915e kmod-mt7981-firmware mt7981-wo-firmware
+  KERNEL = kernel-bin | lzma | \
+	fit-with-netgear-top-level-rootfs-node lzma $$(KDIR)/image-$$(firstword $$(DEVICE_DTS)).dtb
+  KERNEL_IN_UBI := 1
+  IMAGE_SIZE := 81920k
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+  IMAGES += factory.img
+  # Padding to 10M seems to be required by OEM web interface
+  IMAGE/factory.img := sysupgrade-tar | \
+	  pad-to 10M | check-size | netgear-encrypted-factory
+endef
+TARGET_DEVICES += netgear_eax17
+
 define Device/netgear_wax220
   DEVICE_VENDOR := NETGEAR
   DEVICE_MODEL := WAX220
@@ -2639,6 +2700,24 @@ define Device/unielec_u7981-01-nand
 endef
 TARGET_DEVICES += unielec_u7981-01-nand
 
+define Device/wavlink_wl-wn536ax6-a
+  DEVICE_VENDOR := WAVLINK
+  DEVICE_MODEL := WL-WN536AX6
+  DEVICE_VARIANT := Rev a
+  DEVICE_DTS := mt7986a-wavlink-wl-wn536ax6-a
+  DEVICE_DTS_DIR := ../dts
+  DEVICE_DTS_LOADADDR := 0x47000000
+  UBINIZE_OPTS := -E 5
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  IMAGE_SIZE := 65536k
+  KERNEL_INITRAMFS_SUFFIX := .itb
+  KERNEL_IN_UBI := 1
+  DEVICE_PACKAGES := kmod-usb3 kmod-mt7915e kmod-mt7986-firmware mt7986-wo-firmware
+  IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata
+endef
+TARGET_DEVICES += wavlink_wl-wn536ax6-a
+
 define Device/wavlink_wl-wn551x3
   DEVICE_VENDOR := WAVLINK
   DEVICE_MODEL := WL-WN551X3

target/linux/realtek/files-6.12/arch/mips/rtl838x/prom.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * prom.c
- * Early intialization code for the Realtek RTL838X SoC
+ * Early initialization code for the Realtek RTL838X SoC
  *
  * based on the original BSP by
  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
@@ -102,9 +102,9 @@ const char *get_system_type(void)
 	return rtl83xx_system_type;
 }
 
-static void __init rtl838x_read_details(uint32_t model)
+static void __init rtl838x_read_details(u32 model)
 {
-	uint32_t chip_info, ext_version, tmp;
+	u32 chip_info, ext_version, tmp;
 
 	sw_w32(0x3, RTL838X_INT_RW_CTRL);
 	sw_w32(0xa << 28, RTL838X_CHIP_INFO);
@@ -128,9 +128,9 @@ static void __init rtl838x_read_details(uint32_t model)
 	}
 }
 
-static void __init rtl839x_read_details(uint32_t model)
+static void __init rtl839x_read_details(u32 model)
 {
-	uint32_t chip_info;
+	u32 chip_info;
 
 	sw_w32(0xa << 28, RTL839X_CHIP_INFO);
 
@@ -143,9 +143,9 @@ static void __init rtl839x_read_details(uint32_t model)
 		soc_info.testchip = true;
 }
 
-static void __init rtl93xx_read_details(uint32_t model)
+static void __init rtl93xx_read_details(u32 model)
 {
-	uint32_t chip_info;
+	u32 chip_info;
 
 	sw_w32(0xa << 16, RTL93XX_CHIP_INFO);
 
@@ -158,9 +158,9 @@ static void __init rtl93xx_read_details(uint32_t model)
 		soc_info.testchip = true;
 }
 
-static uint32_t __init read_model(void)
+static u32 __init read_model(void)
 {
-	uint32_t model, id;
+	u32 model, id;
 
 	model = sw_r32(RTL838X_MODEL_NAME_INFO);
 	id = model >> 16 & 0xffff;
@@ -197,7 +197,7 @@ static uint32_t __init read_model(void)
 	return 0;
 }
 
-static void __init parse_model(uint32_t model)
+static void __init parse_model(u32 model)
 {
 	int val;
 	char suffix = 0;
@@ -212,7 +212,8 @@ static void __init parse_model(uint32_t model)
 	soc_info.name = soc_name;
 }
 
-static void __init rtl83xx_set_system_type(void) {
+static void __init rtl83xx_set_system_type(void)
+{
 	char revision = '?';
 	char *es = "";
 
@@ -229,7 +230,8 @@ static void __init rtl83xx_set_system_type(void) {
 
 void __init prom_init(void)
 {
-	uint32_t model = read_model();
+	u32 model = read_model();
+
 	parse_model(model);
 	rtl83xx_set_system_type();
 

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/common.c

@@ -16,17 +16,7 @@
 
 #include "rtl83xx.h"
 
-extern struct rtl83xx_soc_info soc_info;
+struct phylink_pcs *rtpcs_create(struct device *dev, struct device_node *np, int port);
-
-extern const struct rtl838x_reg rtl838x_reg;
-extern const struct rtl838x_reg rtl839x_reg;
-extern const struct rtl838x_reg rtl930x_reg;
-extern const struct rtl838x_reg rtl931x_reg;
-
-extern const struct dsa_switch_ops rtl83xx_switch_ops;
-extern const struct dsa_switch_ops rtl93xx_switch_ops;
-
-extern struct phylink_pcs *rtpcs_create(struct device *dev, struct device_node *np, int port);
 
 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port)
 {
@@ -99,7 +89,7 @@ struct table_reg *rtl_table_get(rtl838x_tbl_reg_t r, int t)
 	if (r >= RTL_TBL_END)
 		return NULL;
 
-	if (t >= BIT(rtl838x_tbl_regs[r].c_bit-rtl838x_tbl_regs[r].t_bit))
+	if (t >= BIT(rtl838x_tbl_regs[r].c_bit - rtl838x_tbl_regs[r].t_bit))
 		return NULL;
 
 	mutex_lock(&rtl838x_tbl_regs[r].lock);
@@ -461,7 +451,7 @@ int rtl83xx_lag_add(struct dsa_switch *ds, int group, int port, struct netdev_la
 		return -ENOSPC;
 	}
 
-	switch(info->hash_type) {
+	switch (info->hash_type) {
 	case NETDEV_LAG_HASH_L2:
 		algomsk |= TRUNK_DISTRIBUTION_ALGO_DMAC_BIT;
 		algomsk |= TRUNK_DISTRIBUTION_ALGO_SMAC_BIT;
@@ -669,7 +659,7 @@ static int rtl83xx_l2_nexthop_rm(struct rtl838x_switch_priv *priv, struct rtl83x
 	return 0;
 }
 
-int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv)
+int rtl83xx_port_is_under(const struct net_device *dev, struct rtl838x_switch_priv *priv)
 {
 	/* Is the lower network device a DSA user network device of our RTL930X-switch?
 	 * Unfortunately we cannot just follow dev->dsa_prt as this is only set for the
@@ -763,6 +753,7 @@ static int rtl83xx_l3_nexthop_update(struct rtl838x_switch_priv *priv,  __be32 i
 			priv->r->pie_rule_add(priv, &r->pr);
 		} else {
 			int pkts = priv->r->packet_cntr_read(r->pr.packet_cntr);
+
 			pr_debug("%s: total packets: %d\n", __func__, pkts);
 
 			priv->r->pie_rule_write(priv, r->pr.id, &r->pr);
@@ -880,7 +871,6 @@ out_free:
 	return NULL;
 }
 
-
 static struct rtl83xx_route *rtl83xx_host_route_alloc(struct rtl838x_switch_priv *priv, u32 ip)
 {
 	struct rtl83xx_route *r;
@@ -1236,7 +1226,7 @@ static int rtl83xx_netevent_event(struct notifier_block *this,
 		net_work->priv = priv;
 
 		net_work->mac = ether_addr_to_u64(n->ha);
-		net_work->gw_addr = *(__be32 *) n->primary_key;
+		net_work->gw_addr = *(__be32 *)n->primary_key;
 
 		pr_debug("%s: updating neighbour on port %d, mac %016llx\n",
 			 __func__, port, net_work->mac);
@@ -1458,7 +1448,7 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev)
 
 	priv->family_id = soc_info.family;
 	priv->id = soc_info.id;
-	switch(soc_info.family) {
+	switch (soc_info.family) {
 	case RTL8380_FAMILY_ID:
 		priv->ds->ops = &rtl83xx_switch_ops;
 		priv->cpu_port = RTL838X_CPU_PORT;
@@ -1633,7 +1623,7 @@ static int __init rtl83xx_sw_probe(struct platform_device *pdev)
 	priv->fib_nb.notifier_call = rtl83xx_fib_event;
 
 	/* Register Forwarding Information Base notifier to offload routes where
-	 * where possible
+	 * possible
 	 * Only FIBs pointing to our own netdevs are programmed into
 	 * the device, so no need to pass a callback.
 	 */
@@ -1702,7 +1692,6 @@ static const struct of_device_id rtl83xx_switch_of_ids[] = {
 	{ /* sentinel */ }
 };
 
-
 MODULE_DEVICE_TABLE(of, rtl83xx_switch_of_ids);
 
 static struct platform_driver rtl83xx_switch_driver = {

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/debugfs.c

@@ -52,7 +52,7 @@ const char *rtl838x_drop_cntr[] = {
 
 const char *rtl839x_drop_cntr[] = {
 	"ALE_TX_GOOD_PKTS", "ERROR_PKTS", "EGR_ACL_DROP", "EGR_METER_DROP",
-    "OAM", "CFM" "VLAN_IGR_FLTR", "VLAN_ERR",
+	"OAM", "CFM", "VLAN_IGR_FLTR", "VLAN_ERR",
 	"INNER_OUTER_CFI_EQUAL_1", "VLAN_TAG_FORMAT", "SRC_PORT_SPENDING_TREE", "INBW",
 	"RMA", "HW_ATTACK_PREVENTION", "PROTO_STORM", "MCAST_SA",
 	"IGR_ACL_DROP", "IGR_METER_DROP", "DFLT_ACTION_FOR_MISS_ACL_AND_C2SC", "NEW_SA",
@@ -176,6 +176,7 @@ static ssize_t stp_state_write(struct file *filp, const char __user *buffer,
 	struct rtl838x_port *p = filp->private_data;
 	u32 value;
 	size_t res = rtl838x_common_write(buffer, count, ppos, &value);
+
 	if (res < 0)
 		return res;
 
@@ -205,22 +206,26 @@ static ssize_t drop_counter_read(struct file *filp, char __user *buffer, size_t
 	case RTL8380_FAMILY_ID:
 		d = rtl838x_drop_cntr;
 		offset = RTL838X_STAT_PRVTE_DROP_COUNTERS;
-		num = 40;
+		num = ARRAY_SIZE(rtl838x_drop_cntr);
+		BUILD_BUG_ON(num != 40);
 		break;
 	case RTL8390_FAMILY_ID:
 		d = rtl839x_drop_cntr;
 		offset = RTL839X_STAT_PRVTE_DROP_COUNTERS;
-		num = 45;
+		num = ARRAY_SIZE(rtl839x_drop_cntr);
+		BUILD_BUG_ON(num != 45);
 		break;
 	case RTL9300_FAMILY_ID:
 		d = rtl930x_drop_cntr;
 		offset = RTL930X_STAT_PRVTE_DROP_COUNTERS;
-		num = 85;
+		num = ARRAY_SIZE(rtl930x_drop_cntr);
+		BUILD_BUG_ON(num != 85);
 		break;
 	case RTL9310_FAMILY_ID:
 		d = rtl931x_drop_cntr;
 		offset = RTL931X_STAT_PRVTE_DROP_COUNTERS;
-		num = 81;
+		num = ARRAY_SIZE(rtl931x_drop_cntr);
+		BUILD_BUG_ON(num != 81);
 		break;
 	}
 
@@ -375,6 +380,7 @@ static ssize_t age_out_write(struct file *filp, const char __user *buffer,
 	struct rtl838x_port *p = filp->private_data;
 	u32 value;
 	size_t res = rtl838x_common_write(buffer, count, ppos, &value);
+
 	if (res < 0)
 		return res;
 
@@ -397,6 +403,7 @@ static ssize_t port_egress_rate_read(struct file *filp, char __user *buffer, siz
 	struct dsa_switch *ds = p->dp->ds;
 	struct rtl838x_switch_priv *priv = ds->priv;
 	int value;
+
 	if (priv->family_id == RTL8380_FAMILY_ID)
 		value = rtl838x_get_egress_rate(priv, p->dp->index);
 	else
@@ -416,6 +423,7 @@ static ssize_t port_egress_rate_write(struct file *filp, const char __user *buff
 	struct rtl838x_switch_priv *priv = ds->priv;
 	u32 value;
 	size_t res = rtl838x_common_write(buffer, count, ppos, &value);
+
 	if (res < 0)
 		return res;
 
@@ -434,7 +442,6 @@ static const struct file_operations port_egress_fops = {
 	.write = port_egress_rate_write,
 };
 
-
 static const struct debugfs_reg32 port_ctrl_regs[] = {
 	{ .name = "port_isolation", .offset = RTL838X_PORT_ISO_CTRL(0), },
 	{ .name = "mac_force_mode", .offset = RTL838X_MAC_FORCE_MODE_CTRL, },

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/dsa.c

@@ -7,16 +7,21 @@
 
 #include "rtl83xx.h"
 
-static const u8 ipv4_ll_mcast_addr_base[ETH_ALEN] =
+static const u8 ipv4_ll_mcast_addr_base[ETH_ALEN] = {
-{ 0x01, 0x00, 0x5e, 0x00, 0x00, 0x00 };
+	0x01, 0x00, 0x5e, 0x00, 0x00, 0x00
-static const u8 ipv4_ll_mcast_addr_mask[ETH_ALEN] =
+};
-{ 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
-static const u8 ipv6_all_hosts_mcast_addr_base[ETH_ALEN] =
-{ 0x33, 0x33, 0x00, 0x00, 0x00, 0x01 };
-static const u8 ipv6_all_hosts_mcast_addr_mask[ETH_ALEN] =
-{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 
-extern struct rtl83xx_soc_info soc_info;
+static const u8 ipv4_ll_mcast_addr_mask[ETH_ALEN] = {
+	0xff, 0xff, 0xff, 0xff, 0xff, 0x00
+};
+
+static const u8 ipv6_all_hosts_mcast_addr_base[ETH_ALEN] = {
+	0x33, 0x33, 0x00, 0x00, 0x00, 0x01
+};
+
+static const u8 ipv6_all_hosts_mcast_addr_mask[ETH_ALEN] = {
+	0xff, 0xff, 0xff, 0xff, 0xff, 0xff
+};
 
 static void rtldsa_init_counters(struct rtl838x_switch_priv *priv);
 static void rtldsa_port_xstp_state_set(struct rtl838x_switch_priv *priv, int port,
@@ -55,7 +60,7 @@ static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
 	/* PHY update complete, there is no global PHY polling enable bit on the 93xx */
 	if (priv->family_id == RTL8390_FAMILY_ID)
 		sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
-	else if(priv->family_id == RTL8380_FAMILY_ID)
+	else if (priv->family_id == RTL8380_FAMILY_ID)
 		sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL);
 }
 
@@ -416,10 +421,8 @@ const struct rtldsa_mib_desc rtldsa_931x_mib = {
 	.list = rtldsa_931x_mib_list
 };
 
-
 /* DSA callbacks */
 
-
 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
 						      int port,
 						      enum dsa_tag_protocol mprot)
@@ -468,7 +471,7 @@ static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
 	}
 
 	/* Initialize normal VLANs 1-4095 */
-	for (int i = 1; i < MAX_VLANS; i ++)
+	for (int i = 1; i < MAX_VLANS; i++)
 		priv->r->vlan_set_tagged(i, &info);
 
 	/*
@@ -958,9 +961,9 @@ static const struct rtldsa_mib_desc *rtldsa_get_mib_desc(struct rtl838x_switch_p
 
 static bool rtldsa_read_mib_item(struct rtl838x_switch_priv *priv, int port,
 				 const struct rtldsa_mib_item *mib_item,
-				 uint64_t *data)
+				 u64 *data)
 {
-	uint32_t high1, high2;
+	u32 high1, high2;
 	int reg, reg_offset, addr_low;
 
 	switch (mib_item->reg) {
@@ -995,7 +998,7 @@ static bool rtldsa_read_mib_item(struct rtl838x_switch_priv *priv, int port,
 			/* Low must have wrapped and overflowed into high, read again */
 			*data = sw_r32(addr_low);
 		}
-		*data |= (uint64_t)high2 << 32;
+		*data |= (u64)high2 << 32;
 	} else {
 		*data = sw_r32(addr_low);
 	}
@@ -1007,8 +1010,8 @@ static void rtldsa_update_counter(struct rtl838x_switch_priv *priv, int port,
 				  struct rtldsa_counter *counter,
 				  const struct rtldsa_mib_item *mib_item)
 {
-	uint64_t val;
+	u64 val;
-	uint32_t val32, diff;
+	u32 val32, diff;
 
 	if (!rtldsa_read_mib_item(priv, port, mib_item, &val))
 		return;
@@ -1016,7 +1019,7 @@ static void rtldsa_update_counter(struct rtl838x_switch_priv *priv, int port,
 	if (mib_item->size == 2) {
 		counter->val = val;
 	} else {
-		val32 = (uint32_t)val;
+		val32 = (u32)val;
 		diff = val32 - counter->last;
 		counter->val += diff;
 		counter->last = val32;
@@ -1249,7 +1252,7 @@ static void rtldsa_get_strings(struct dsa_switch *ds,
 }
 
 static void rtldsa_get_ethtool_stats(struct dsa_switch *ds, int port,
-				     uint64_t *data)
+				     u64 *data)
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
 	const struct rtldsa_mib_desc *mib_desc;
@@ -1286,7 +1289,6 @@ static int rtldsa_get_sset_count(struct dsa_switch *ds, int port, int sset)
 	return mib_desc->list_count;
 }
 
-
 static void rtldsa_get_eth_phy_stats(struct dsa_switch *ds, int port,
 				     struct ethtool_eth_phy_stats *phy_stats)
 {
@@ -1409,7 +1411,6 @@ static void rtldsa_get_rmon_stats(struct dsa_switch *ds, int port,
 		rmon_stats->hist[i] = counters->rx_pkts[i].val;
 	}
 
-
 	for (int i = 0; i < ARRAY_SIZE(mib_desc->tx_pkts); i++) {
 		if (mib_desc->tx_pkts[i].reg == MIB_REG_INVALID)
 			break;
@@ -1519,7 +1520,7 @@ static int rtldsa_port_enable(struct dsa_switch *ds, int port, struct phy_device
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
 
-	pr_debug("%s: %x %d", __func__, (u32) priv, port);
+	pr_debug("%s: %x %d", __func__, (u32)priv, port);
 	priv->ports[port].enable = true;
 
 	/* enable inner tagging on egress, do not keep any tags */
@@ -2016,7 +2017,7 @@ static void rtldsa_931x_fast_age(struct dsa_switch *ds, int port)
 	val |= BIT(28); /* status - trigger flush */
 	sw_w32(val, RTL931X_L2_TBL_FLUSH_CTRL);
 
-	do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
+	do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT(28));
 
 	mutex_unlock(&priv->reg_mutex);
 }
@@ -2080,8 +2081,7 @@ static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
 		if (port != priv->cpu_port) {
 			priv->r->set_vlan_igr_filter(port, IGR_DROP);
 			priv->r->set_vlan_egr_filter(port, EGR_ENABLE);
-		}
+		} else {
-		else {
 			priv->r->set_vlan_igr_filter(port, IGR_TRAP);
 			priv->r->set_vlan_egr_filter(port, EGR_DISABLE);
 		}
@@ -2137,7 +2137,8 @@ static int rtl83xx_vlan_add(struct dsa_switch *ds, int port,
 		 __func__, port, vlan->vid, vlan->flags);
 
 	/* Let no one mess with our special VLAN 0 */
-	if (!vlan->vid) return 0;
+	if (!vlan->vid)
+		return 0;
 
 	if (vlan->vid > 4095) {
 		dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
@@ -2208,7 +2209,8 @@ static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
 		 __func__, port, vlan->vid, vlan->flags);
 
 	/* Let no one mess with our special VLAN 0 */
-	if (!vlan->vid) return 0;
+	if (!vlan->vid)
+		return 0;
 
 	if (vlan->vid > 4095) {
 		dev_err(priv->dev, "VLAN out of range: %d", vlan->vid);
@@ -2219,9 +2221,9 @@ static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
 	pvid = priv->ports[port].pvid;
 
 	/* Reset to default if removing the current PVID */
-	if (vlan->vid == pvid) {
+	if (vlan->vid == pvid)
 		rtl83xx_vlan_set_pvid(priv, port, 0);
-	}
+
 	/* Get port memberships of this vlan */
 	priv->r->vlan_tables_read(vlan->vid, &info);
 
@@ -2232,6 +2234,7 @@ static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
 	/* VLANs without members are set back (implicitly) to CIST by DSA */
 	if (!info.member_ports) {
 		u16 mst = info.fid;
+
 		info.fid = 0;
 
 		rtldsa_mst_put_slot(priv, mst);
@@ -2765,6 +2768,7 @@ static int rtldsa_port_pre_bridge_flags(struct dsa_switch *ds, int port,
 {
 	struct rtl838x_switch_priv *priv = ds->priv;
 	unsigned long features = BR_ISOLATED;
+
 	pr_debug("%s: %d %lX\n", __func__, port, flags.val);
 	if (priv->r->enable_learning)
 		features |= BR_LEARNING;
@@ -2821,9 +2825,9 @@ static bool rtl83xx_lag_can_offload(struct dsa_switch *ds,
 	if (id < 0 || id >= ds->num_lag_ids)
 		return false;
 
-	if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) {
+	if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
 		return false;
-	}
+
 	if (info->hash_type != NETDEV_LAG_HASH_L2 && info->hash_type != NETDEV_LAG_HASH_L23)
 		return false;
 
@@ -2901,7 +2905,7 @@ static int rtl83xx_port_lag_leave(struct dsa_switch *ds, int port,
 		err = -EINVAL;
 		goto out;
 	}
-	pr_info("port_lag_del: group %d, port %d\n",group, port);
+	pr_info("port_lag_del: group %d, port %d\n", group, port);
 	priv->lagmembers &= ~BIT_ULL(port);
 	priv->lag_primary[group] = -1;
 	priv->lag_non_primary &= ~BIT_ULL(port);

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/qos.c

@@ -7,7 +7,6 @@
 #include "rtl83xx.h"
 
 static struct rtl838x_switch_priv *switch_priv;
-extern struct rtl83xx_soc_info soc_info;
 
 enum scheduler_type {
 	WEIGHTED_FAIR_QUEUE = 0,
@@ -210,7 +209,7 @@ static void rtl839x_egress_rate_queue_limit(struct rtl838x_switch_priv *priv, in
 	sw_w32_mask(0xfffff << start_bit, (rate & 0xfffff) << start_bit,
 		    RTL839X_TBL_ACCESS_DATA_2(low_byte));
 	if (high_mask)
-		sw_w32_mask(high_mask, (rate & 0xfffff) >> (32- start_bit),
+		sw_w32_mask(high_mask, (rate & 0xfffff) >> (32 - start_bit),
 			    RTL839X_TBL_ACCESS_DATA_2(low_byte - 1));
 
 	rtl839x_write_scheduling_table(port);
@@ -251,7 +250,8 @@ static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv)
 	/* Set default burst rates on all ports (the same for 1G / 10G) with a PHY
 	 * for UC, MC and BC
 	 * For 1G port, the minimum burst rate is 1700, maximum 65535,
-	 * For 10G ports it is 2650 and 1048575 respectively */
+	 * For 10G ports it is 2650 and 1048575 respectively
+	 */
 	for (int p = 0; p < priv->cpu_port; p++) {
 		if (priv->ports[p].phy && !priv->ports[p].is10G) {
 			sw_w32_mask(0xffff, 0x8000, RTL839X_STORM_CTRL_PORT_UC_1(p));
@@ -288,7 +288,6 @@ static void rtl839x_rate_control_init(struct rtl838x_switch_priv *priv)
 }
 
 
-
 static void rtl838x_setup_prio2queue_matrix(int *min_queues)
 {
 	u32 v = 0;
@@ -304,6 +303,7 @@ static void rtl839x_setup_prio2queue_matrix(int *min_queues)
 	pr_info("Current Intprio2queue setting: %08x\n", sw_r32(RTL839X_QM_INTPRI2QID_CTRL(0)));
 	for (int i = 0; i < MAX_PRIOS; i++) {
 		int q = min_queues[i];
+
 		sw_w32(i << (q * 3), RTL839X_QM_INTPRI2QID_CTRL(q));
 	}
 }
@@ -323,27 +323,27 @@ static void rtl83xx_setup_prio2queue_cpu_matrix(int *max_queues)
 
 static void rtl83xx_setup_default_prio2queue(void)
 {
-	if (soc_info.family == RTL8380_FAMILY_ID) {
+	if (soc_info.family == RTL8380_FAMILY_ID)
 		rtl838x_setup_prio2queue_matrix(rtldsa_max_available_queue);
-	} else {
+	else
 		rtl839x_setup_prio2queue_matrix(rtldsa_max_available_queue);
-	}
+
 	rtl83xx_setup_prio2queue_cpu_matrix(rtldsa_max_available_queue);
 }
 
 /* Sets the output queue assigned to a port, the port can be the CPU-port */
 void rtl839x_set_egress_queue(int port, int queue)
 {
-	sw_w32(queue << ((port % 10) *3), RTL839X_QM_PORT_QNUM(port));
+	sw_w32(queue << ((port % 10) * 3), RTL839X_QM_PORT_QNUM(port));
 }
 
 /* Sets the priority assigned of an ingress port, the port can be the CPU-port */
 static void rtl83xx_set_ingress_priority(int port, int priority)
 {
 	if (soc_info.family == RTL8380_FAMILY_ID)
-		sw_w32(priority << ((port % 10) *3), RTL838X_PRI_SEL_PORT_PRI(port));
+		sw_w32(priority << ((port % 10) * 3), RTL838X_PRI_SEL_PORT_PRI(port));
 	else
-		sw_w32(priority << ((port % 10) *3), RTL839X_PRI_SEL_PORT_PRI(port));
+		sw_w32(priority << ((port % 10) * 3), RTL839X_PRI_SEL_PORT_PRI(port));
 }
 
 static int rtl839x_get_scheduling_algorithm(struct rtl838x_switch_priv *priv, int port)
@@ -437,7 +437,7 @@ static void rtl839x_set_scheduling_queue_weights(struct rtl838x_switch_priv *pri
 		sw_w32_mask(0x3ff << start_bit, (queue_weights[i] & 0x3ff) << start_bit,
 			    RTL839X_TBL_ACCESS_DATA_2(low_byte));
 		if (high_mask)
-			sw_w32_mask(high_mask, (queue_weights[i] & 0x3ff) >> (32- start_bit),
+			sw_w32_mask(high_mask, (queue_weights[i] & 0x3ff) >> (32 - start_bit),
 				    RTL839X_TBL_ACCESS_DATA_2(low_byte - 1));
 	}
 
@@ -533,9 +533,9 @@ static void rtl839x_config_qos(void)
 	 * low threshold (bits 0-11) to 4095 and high threshold (bits 12-23) to 4095
 	 * Weighted Random Early Detection (WRED) is used
 	 */
-	sw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(0));
+	sw_w32(4095 << 12 | 4095, RTL839X_WRED_PORT_THR_CTRL(0));
-	sw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(1));
+	sw_w32(4095 << 12 | 4095, RTL839X_WRED_PORT_THR_CTRL(1));
-	sw_w32(4095 << 12| 4095, RTL839X_WRED_PORT_THR_CTRL(2));
+	sw_w32(4095 << 12 | 4095, RTL839X_WRED_PORT_THR_CTRL(2));
 
 	/* Set queue-based congestion avoidance properties, register fields are as
 	 * for forward RTL839X_WRED_PORT_THR_CTRL

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.c

@@ -14,14 +14,14 @@
 #define RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE			0xA530
 /* port 0-28 */
 #define RTL838X_VLAN_PORT_TAG_STS_CTRL(port) \
-		RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
+	(RTL838X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2))
 
-#define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK	GENMASK(11,10)
+#define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK	GENMASK(11, 10)
-#define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK	GENMASK(9,8)
+#define RTL838X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK	GENMASK(9, 8)
-#define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK	GENMASK(7,6)
+#define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK	GENMASK(7, 6)
-#define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK	GENMASK(5,4)
+#define RTL838X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK	GENMASK(5, 4)
-#define RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK		GENMASK(3,2)
+#define RTL838X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK		GENMASK(3, 2)
-#define RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK		GENMASK(1,0)
+#define RTL838X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK		GENMASK(1, 0)
 
 /* see_dal_maple_acl_log2PhyTmplteField and src/app/diag_v2/src/diag_acl.c */
 /* Definition of the RTL838X-specific template field IDs as used in the PIE */
@@ -82,8 +82,7 @@ enum template_field_id {
  * TODO: See all src/app/diag_v2/src/diag_pie.c
  */
 #define N_FIXED_TEMPLATES 5
-static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
+static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = {
-{
 	{
 	  TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_OTAG,
 	  TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
@@ -91,7 +90,7 @@ static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS]
 	  TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_RANGE_CHK
 	}, {
 	  TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
-	  TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
+	  TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
 	  TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_ITAG,
 	  TEMPLATE_FIELD_RANGE_CHK, TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1
 	}, {
@@ -278,7 +277,7 @@ static int rtldsa_838x_get_mirror_config(struct rtldsa_mirror_config *config,
 	return 0;
 }
 
-inline static int rtl838x_trk_mbr_ctr(int group)
+static inline int rtl838x_trk_mbr_ctr(int group)
 {
 	return RTL838X_TRK_MBR_CTR + (group << 2);
 }
@@ -323,7 +322,7 @@ static void rtl838x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
 			e->age = (r[0] >> 17) & 0x3;
 			e->valid = true;
 
-			/* A valid entry has one of mutli-cast, aging, sa/da-blocking,
+			/* A valid entry has one of multi-cast, aging, sa/da-blocking,
 			 * next-hop or static entry bit set
 			 */
 			if (!(r[0] & 0x007c0000) && !(r[1] & 0xd0000000))
@@ -414,7 +413,7 @@ static u64 rtl838x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2
 	if (!e->valid)
 		return 0;
 
-	return (((u64) r[1]) << 32) | (r[2]);  /* mac and vid concatenated as hash seed */
+	return (((u64)r[1]) << 32) | (r[2]);  /* mac and vid concatenated as hash seed */
 }
 
 static void rtl838x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
@@ -451,7 +450,7 @@ static u64 rtl838x_read_cam(int idx, struct rtl838x_l2_entry *e)
 	pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
 
 	/* Return MAC with concatenated VID ac concatenated ID */
-	return (((u64) r[1]) << 32) | r[2];
+	return (((u64)r[1]) << 32) | r[2];
 }
 
 static void rtl838x_write_cam(int idx, struct rtl838x_l2_entry *e)
@@ -511,11 +510,13 @@ static void rtl838x_l2_learning_setup(void)
 {
 	/* Set portmask for broadcast traffic and unknown unicast address flooding
 	 * to the reserved entry in the portmask table used also for
-	 * multicast flooding */
+	 * multicast flooding
+	 */
 	sw_w32(UNKNOWN_MC_PMASK << 9 | UNKNOWN_MC_PMASK, RTL838X_L2_FLD_PMSK);
 
 	/* Enable learning constraint system-wide (bit 0), per-port (bit 1)
-	 * and per vlan (bit 2) */
+	 * and per vlan (bit 2)
+	 */
 	sw_w32(0x7, RTL838X_L2_LRN_CONSTRT_EN);
 
 	/* Limit learning to maximum: 16k entries, after that just flood (bits 0-1) */
@@ -546,12 +547,10 @@ static void rtl838x_enable_flood(int port, bool enable)
 
 static void rtl838x_enable_mcast_flood(int port, bool enable)
 {
-
 }
 
 static void rtl838x_enable_bcast_flood(int port, bool enable)
 {
-
 }
 
 static void rtl838x_set_static_move_action(int port, bool forward)
@@ -659,7 +658,7 @@ static void rtl838x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_fro
 {
 	int block_from = index_from / PIE_BLOCK_SIZE;
 	int block_to = index_to / PIE_BLOCK_SIZE;
-	u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
+	u32 v = (index_from << 1) | (index_to << 12) | BIT(0);
 	u32 block_state;
 
 	pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
@@ -1048,33 +1047,33 @@ static void rtl838x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
 
 static void rtl838x_write_pie_fixed_fields(u32 r[],  struct pie_rule *pr)
 {
-	r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 22;
+	r[6] = ((u32)(pr->spmmask_fix & 0x3)) << 22;
-	r[6] |= ((u32) (pr->spn & 0x3f)) << 16;
+	r[6] |= ((u32)(pr->spn & 0x3f)) << 16;
 	r[6] |= pr->mgnt_vlan ? BIT(15) : 0;
 	r[6] |= pr->dmac_hit_sw ? BIT(14) : 0;
 	r[6] |= pr->not_first_frag ? BIT(13) : 0;
-	r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 10;
+	r[6] |= ((u32)(pr->frame_type_l4 & 0x7)) << 10;
-	r[6] |= ((u32) (pr->frame_type & 0x3)) << 8;
+	r[6] |= ((u32)(pr->frame_type & 0x3)) << 8;
 	r[6] |= pr->otag_fmt ? BIT(7) : 0;
 	r[6] |= pr->itag_fmt ? BIT(6) : 0;
 	r[6] |= pr->otag_exist ? BIT(5) : 0;
 	r[6] |= pr->itag_exist ? BIT(4) : 0;
-	r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 2;
+	r[6] |= ((u32)(pr->frame_type_l2 & 0x3)) << 2;
-	r[6] |= ((u32) (pr->tid & 0x3));
+	r[6] |= ((u32)(pr->tid & 0x3));
 
-	r[13] = ((u32) (pr->spmmask_fix_m & 0x3)) << 22;
+	r[13] = ((u32)(pr->spmmask_fix_m & 0x3)) << 22;
-	r[13] |= ((u32) (pr->spn_m & 0x3f)) << 16;
+	r[13] |= ((u32)(pr->spn_m & 0x3f)) << 16;
 	r[13] |= pr->mgnt_vlan_m ? BIT(15) : 0;
 	r[13] |= pr->dmac_hit_sw_m ? BIT(14) : 0;
 	r[13] |= pr->not_first_frag_m ? BIT(13) : 0;
-	r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;
+	r[13] |= ((u32)(pr->frame_type_l4_m & 0x7)) << 10;
-	r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 8;
+	r[13] |= ((u32)(pr->frame_type_m & 0x3)) << 8;
 	r[13] |= pr->otag_fmt_m ? BIT(7) : 0;
 	r[13] |= pr->itag_fmt_m ? BIT(6) : 0;
 	r[13] |= pr->otag_exist_m ? BIT(5) : 0;
 	r[13] |= pr->itag_exist_m ? BIT(4) : 0;
-	r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;
+	r[13] |= ((u32)(pr->frame_type_l2_m & 0x3)) << 2;
-	r[13] |= ((u32) (pr->tid_m & 0x3));
+	r[13] |= ((u32)(pr->tid_m & 0x3));
 
 	r[14] = pr->valid ? BIT(31) : 0;
 	r[14] |= pr->cond_not ? BIT(30) : 0;
@@ -1115,7 +1114,8 @@ static int rtl838x_write_pie_action(u32 r[],  struct pie_rule *pr)
 	 * they have different precedence depending on their type and this precedence
 	 * defines which Action Information Field (0-4) in the IACL table stores
 	 * the additional data of the action (like e.g. the port number a packet is
-	 * forwarded to) */
+	 * forwarded to)
+	 */
 	/* TODO: count bits in selectors to limit to a maximum number of actions */
 	if (pr->fwd_sel) { /* Forwarding action */
 		data = pr->fwd_act << 13;
@@ -1229,7 +1229,7 @@ static void rtl838x_read_pie_action(u32 r[],  struct pie_rule *pr)
 	if (pr->drop)
 		pr_debug("%s: Action Drop: %d", __func__, pr->drop);
 
-	if (pr->fwd_sel){ /* Forwarding action */
+	if (pr->fwd_sel) { /* Forwarding action */
 		pr->fwd_act = *aif >> 13;
 		pr->fwd_data = *aif--;
 		pr->bypass_all = pr->fwd_data & BIT(12);
@@ -1426,6 +1426,7 @@ static int rtl838x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul
 	for (block = 0; block < priv->n_pie_blocks; block++) {
 		for (j = 0; j < 3; j++) {
 			int t = (sw_r32(RTL838X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
+
 			pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
 			idx = rtl838x_pie_verify_template(priv, pr, t, block);
 			if (idx >= 0)
@@ -1625,7 +1626,7 @@ static int rtl838x_set_ageing_time(unsigned long msec)
 
 static void rtl838x_set_igr_filter(int port, enum igr_filter state)
 {
-	sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
+	sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1),
 		    RTL838X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
 }
 
@@ -1645,7 +1646,7 @@ static void rtl838x_set_distribution_algorithm(int group, int algoidx, u32 algom
 
 static void rtl838x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
 {
-	switch(type) {
+	switch (type) {
 	case BPDU:
 		sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
 			    RTL838X_RMA_BPDU_CTRL + ((port >> 4) << 2));
@@ -1805,8 +1806,7 @@ void rtl838x_vlan_profile_dump(int profile)
 
 	p = sw_r32(RTL838X_VLAN_PROFILE(profile));
 
-	pr_debug("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
+	pr_debug("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d\n",
-		UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
 		 profile, p & 1, (p >> 1) & 0x1ff, (p >> 10) & 0x1ff, (p >> 19) & 0x1ff);
 }
 

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl838x.h

@@ -132,39 +132,39 @@
 #define RTL_SPEED_5000				6
 #define RTL_SPEED_10000				4
 
-#define RTL83XX_FORCE_EN			(1 << 0)
+#define RTL83XX_FORCE_EN			BIT(0)
-#define RTL83XX_FORCE_LINK_EN			(1 << 1)
+#define RTL83XX_FORCE_LINK_EN			BIT(1)
 
-#define RTL838X_NWAY_EN				(1 << 2)
+#define RTL838X_NWAY_EN				BIT(2)
-#define RTL838X_DUPLEX_MODE			(1 << 3)
+#define RTL838X_DUPLEX_MODE			BIT(3)
 #define RTL838X_SPEED_SHIFT			(4)
 #define RTL838X_SPEED_MASK			(3 << RTL838X_SPEED_SHIFT)
-#define RTL838X_TX_PAUSE_EN			(1 << 6)
+#define RTL838X_TX_PAUSE_EN			BIT(6)
-#define RTL838X_RX_PAUSE_EN			(1 << 7)
+#define RTL838X_RX_PAUSE_EN			BIT(7)
-#define RTL838X_MAC_FORCE_FC_EN			(1 << 8)
+#define RTL838X_MAC_FORCE_FC_EN			BIT(8)
 
-#define RTL839X_DUPLEX_MODE			(1 << 2)
+#define RTL839X_DUPLEX_MODE			BIT(2)
 #define RTL839X_SPEED_SHIFT			(3)
 #define RTL839X_SPEED_MASK			(3 << RTL839X_SPEED_SHIFT)
-#define RTL839X_TX_PAUSE_EN			(1 << 5)
+#define RTL839X_TX_PAUSE_EN			BIT(5)
-#define RTL839X_RX_PAUSE_EN			(1 << 6)
+#define RTL839X_RX_PAUSE_EN			BIT(6)
-#define RTL839X_MAC_FORCE_FC_EN			(1 << 7)
+#define RTL839X_MAC_FORCE_FC_EN			BIT(7)
 
-#define RTL930X_FORCE_EN			(1 << 0)
+#define RTL930X_FORCE_EN			BIT(0)
-#define RTL930X_FORCE_LINK_EN			(1 << 1)
+#define RTL930X_FORCE_LINK_EN			BIT(1)
-#define RTL930X_DUPLEX_MODE			(1 << 2)
+#define RTL930X_DUPLEX_MODE			BIT(2)
 #define RTL930X_SPEED_SHIFT			(3)
 #define RTL930X_SPEED_MASK			(15 << RTL930X_SPEED_SHIFT)
-#define RTL930X_TX_PAUSE_EN			(1 << 7)
+#define RTL930X_TX_PAUSE_EN			BIT(7)
-#define RTL930X_RX_PAUSE_EN			(1 << 8)
+#define RTL930X_RX_PAUSE_EN			BIT(8)
-#define RTL930X_MAC_FORCE_FC_EN			(1 << 9)
+#define RTL930X_MAC_FORCE_FC_EN			BIT(9)
 
-#define RTL931X_FORCE_EN			(1 << 9)
+#define RTL931X_FORCE_EN			BIT(9)
-#define RTL931X_FORCE_LINK_EN			(1 << 0)
+#define RTL931X_FORCE_LINK_EN			BIT(0)
-#define RTL931X_DUPLEX_MODE			(1 << 2)
+#define RTL931X_DUPLEX_MODE			BIT(2)
-#define RTL931X_MAC_FORCE_FC_EN			(1 << 4)
+#define RTL931X_MAC_FORCE_FC_EN			BIT(4)
-#define RTL931X_TX_PAUSE_EN			(1 << 16)
+#define RTL931X_TX_PAUSE_EN			BIT(16)
-#define RTL931X_RX_PAUSE_EN			(1 << 17)
+#define RTL931X_RX_PAUSE_EN			BIT(17)
 
 /* EEE */
 #define RTL838X_MAC_EEE_ABLTY			(0xa1a8)
@@ -658,7 +658,7 @@ typedef enum {
 #define RTL931X_LED_SETX_1_CTRL(x) (RTL931X_LED_SETX_0_CTRL(x) - 4)
 
 /* get register for given set and led in the set */
-#define RTL931X_LED_SETX_LEDY(x,y) (RTL931X_LED_SETX_0_CTRL(x) - 4 * (y / 2))
+#define RTL931X_LED_SETX_LEDY(x, y) (RTL931X_LED_SETX_0_CTRL(x) - 4 * (y / 2))
 
 /* get shift for given led in any set */
 #define RTL931X_LED_SET_LEDX_SHIFT(x) (16 * (x % 2))
@@ -723,8 +723,8 @@ enum pbvlan_mode {
 };
 
 struct rtldsa_counter {
-	uint64_t val;
+	u64 val;
-	uint32_t last;
+	u32 last;
 };
 
 struct rtldsa_counter_state {
@@ -885,7 +885,8 @@ enum egr_filter {
 /* Intermediate representation of a  Packet Inspection Engine Rule
  * as suggested by the Kernel's tc flower offload subsystem
  * Field meaning is universal across SoC families, but data content is specific
- * to SoC family (e.g. because of different port ranges) */
+ * to SoC family (e.g. because of different port ranges)
+ */
 struct pie_rule {
 	int id;
 	enum pie_phase phase;	/* Phase in which this template is applied */
@@ -1289,16 +1290,16 @@ struct rtl838x_switch_priv {
 	struct notifier_block ne_nb;
 	struct notifier_block fib_nb;
 	bool eee_enabled;
-	unsigned long int mc_group_bm[MAX_MC_GROUPS >> 5];
+	unsigned long mc_group_bm[MAX_MC_GROUPS >> 5];
 	int n_pie_blocks;
 	struct rhashtable tc_ht;
-	unsigned long int pie_use_bm[MAX_PIE_ENTRIES >> 5];
+	unsigned long pie_use_bm[MAX_PIE_ENTRIES >> 5];
 	int n_counters;
-	unsigned long int octet_cntr_use_bm[MAX_COUNTERS >> 5];
+	unsigned long octet_cntr_use_bm[MAX_COUNTERS >> 5];
-	unsigned long int packet_cntr_use_bm[MAX_COUNTERS >> 4];
+	unsigned long packet_cntr_use_bm[MAX_COUNTERS >> 4];
 	struct rhltable routes;
-	unsigned long int route_use_bm[MAX_ROUTES >> 5];
+	unsigned long route_use_bm[MAX_ROUTES >> 5];
-	unsigned long int host_route_use_bm[MAX_HOST_ROUTES >> 5];
+	unsigned long host_route_use_bm[MAX_HOST_ROUTES >> 5];
 	struct rtl838x_l3_intf *interfaces[MAX_INTERFACES];
 	u16 intf_mtus[MAX_INTF_MTUS];
 	int intf_mtu_count[MAX_INTF_MTUS];

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl839x.c

@@ -12,15 +12,13 @@
 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE			0x6828
 /* port 0-52 */
 #define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) \
-		RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
+	(RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2))
-#define RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK		GENMASK(7,6)
+#define RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK		GENMASK(7, 6)
-#define RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK		GENMASK(5,4)
+#define RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK		GENMASK(5, 4)
-#define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK	GENMASK(3,3)
+#define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK	GENMASK(3, 3)
-#define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK	GENMASK(2,2)
+#define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK	GENMASK(2, 2)
-#define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK	GENMASK(1,1)
+#define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK	GENMASK(1, 1)
-#define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK	GENMASK(0,0)
+#define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK	GENMASK(0, 0)
-
-extern struct rtl83xx_soc_info soc_info;
 
 /* Definition of the RTL839X-specific template field IDs as used in the PIE */
 enum template_field_id {
@@ -90,8 +88,7 @@ enum template_field_id {
 
 /* Number of fixed templates predefined in the SoC */
 #define N_FIXED_TEMPLATES 5
-static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
+static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = {
-{
 	{
 	  TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG,
 	  TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
@@ -99,7 +96,7 @@ static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS]
 	  TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
 	}, {
 	  TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
-	  TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
+	  TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
 	  TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_SPM0,
 	  TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
 	}, {
@@ -256,10 +253,10 @@ static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
 	u32 h1, h2, h;
 
 	if (sw_r32(priv->r->l2_ctrl_0) & 1) {
-		h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) ^
+		h1 = (u32)(((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f) ^
 			   ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f) ^
 			   ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
-		h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) ^
+		h2 = (u32)(((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f) ^
 			   ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f) ^
 			   (seed & 0x3f));
 		h = (h1 << 6) | h2;
@@ -556,7 +553,8 @@ static void rtl839x_l2_learning_setup(void)
 {
 	/* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)
 	 * address flooding to the reserved entry in the portmask table used
-	 * also for multicast flooding */
+	 * also for multicast flooding
+	 */
 	sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK);
 
 	/* Limit learning to maximum: 32k entries, after that just flood (bits 0-1) */
@@ -587,12 +585,10 @@ static void rtl839x_enable_flood(int port, bool enable)
 
 static void rtl839x_enable_mcast_flood(int port, bool enable)
 {
-
 }
 
 static void rtl839x_enable_bcast_flood(int port, bool enable)
 {
-
 }
 
 static void rtl839x_set_static_move_action(int port, bool forward)
@@ -670,8 +666,7 @@ void rtl839x_vlan_profile_dump(int profile)
 	p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
 	p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
 
-	pr_debug("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
+	pr_debug("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d\n",
-		UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
 		 profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
 		 (p[0]) & 0xfff);
 	pr_debug("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
@@ -728,7 +723,7 @@ static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
 	pr_debug("Setting up EEE, state: %d\n", enable);
 
 	/* Set wake timer for TX and pause timer both to 0x21 */
-	sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
+	sw_w32_mask(0xff << 20 | 0xff, 0x21 << 20 | 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
 	/* Set pause wake timer for GIGA-EEE to 0x11 */
 	sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
 	/* Set pause wake timer for 10GBit ports to 0x11 */
@@ -752,7 +747,7 @@ static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int inde
 /* Delete a range of Packet Inspection Engine rules */
 static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
 {
-	u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
+	u32 v = (index_from << 1) | (index_to << 13) | BIT(0);
 
 	pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
 	mutex_lock(&priv->reg_mutex);
@@ -1116,33 +1111,33 @@ static void rtl839x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
 
 static void rtl839x_write_pie_fixed_fields(u32 r[],  struct pie_rule *pr)
 {
-	r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 30;
+	r[6] = ((u32)(pr->spmmask_fix & 0x3)) << 30;
-	r[6] |= ((u32) (pr->spn & 0x3f)) << 24;
+	r[6] |= ((u32)(pr->spn & 0x3f)) << 24;
 	r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
 	r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
 	r[6] |= pr->not_first_frag ? BIT(21) : 0;
-	r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
+	r[6] |= ((u32)(pr->frame_type_l4 & 0x7)) << 18;
-	r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
+	r[6] |= ((u32)(pr->frame_type & 0x3)) << 16;
 	r[6] |= pr->otag_fmt ? BIT(15) : 0;
 	r[6] |= pr->itag_fmt ? BIT(14) : 0;
 	r[6] |= pr->otag_exist ? BIT(13) : 0;
 	r[6] |= pr->itag_exist ? BIT(12) : 0;
-	r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
+	r[6] |= ((u32)(pr->frame_type_l2 & 0x3)) << 10;
-	r[6] |= ((u32) (pr->tid & 0x3)) << 8;
+	r[6] |= ((u32)(pr->tid & 0x3)) << 8;
 
-	r[12] |= ((u32) (pr->spmmask_fix_m & 0x3)) << 6;
+	r[12] |= ((u32)(pr->spmmask_fix_m & 0x3)) << 6;
-	r[12] |= (u32) (pr->spn_m & 0x3f);
+	r[12] |= (u32)(pr->spn_m & 0x3f);
 	r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
 	r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
 	r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
-	r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
+	r[13] |= ((u32)(pr->frame_type_l4_m & 0x7)) << 26;
-	r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
+	r[13] |= ((u32)(pr->frame_type_m & 0x3)) << 24;
 	r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
 	r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
 	r[13] |= pr->otag_exist_m ? BIT(21) : 0;
 	r[13] |= pr->itag_exist_m ? BIT(20) : 0;
-	r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
+	r[13] |= ((u32)(pr->frame_type_l2_m & 0x3)) << 18;
-	r[13] |= ((u32) (pr->tid_m & 0x3)) << 16;
+	r[13] |= ((u32)(pr->tid_m & 0x3)) << 16;
 
 	r[13] |= pr->valid ? BIT(15) : 0;
 	r[13] |= pr->cond_not ? BIT(14) : 0;
@@ -1308,6 +1303,7 @@ static bool rtl839x_pie_templ_has(int t, enum template_field_id field_type)
 {
 	for (int i = 0; i < N_FIXED_FIELDS; i++) {
 		enum template_field_id ft = fixed_templates[t][i];
+
 		if (field_type == ft)
 			return true;
 	}
@@ -1600,7 +1596,7 @@ static int rtl839x_set_ageing_time(unsigned long msec)
 
 static void rtl839x_set_igr_filter(int port,  enum igr_filter state)
 {
-	sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
+	sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1),
 		    RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
 }
 
@@ -1619,7 +1615,7 @@ static void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algom
 
 static void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
 {
-	switch(type) {
+	switch (type) {
 	case BPDU:
 		sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
 			    RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2));

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl83xx.h

@@ -6,7 +6,6 @@
 #include <net/dsa.h>
 #include "rtl838x.h"
 
-
 #define RTL8380_VERSION_A 'A'
 #define RTL8390_VERSION_A 'A'
 #define RTL8380_VERSION_B 'B'
@@ -137,7 +136,7 @@ void __init rtl83xx_setup_qos(struct rtl838x_switch_priv *priv);
 void rtl83xx_fast_age(struct dsa_switch *ds, int port);
 int rtl83xx_packet_cntr_alloc(struct rtl838x_switch_priv *priv);
 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv *priv, int port);
-int rtl83xx_port_is_under(const struct net_device * dev, struct rtl838x_switch_priv *priv);
+int rtl83xx_port_is_under(const struct net_device *dev, struct rtl838x_switch_priv *priv);
 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state);
 int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data);
 
@@ -207,4 +206,15 @@ void rtl930x_pie_rule_dump_raw(u32 r[]);
 
 void rtl931x_print_matrix(void);
 
+extern const struct dsa_switch_ops rtl83xx_switch_ops;
+extern const struct dsa_switch_ops rtl93xx_switch_ops;
+
+extern const struct rtl838x_reg rtl838x_reg;
+extern const struct rtl838x_reg rtl839x_reg;
+extern const struct rtl838x_reg rtl930x_reg;
+extern const struct rtl838x_reg rtl931x_reg;
+
+/* TODO actually from arch/mips/rtl838x/prom.c */
+extern struct rtl83xx_soc_info soc_info;
+
 #endif /* _NET_DSA_RTL83XX_H */

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl930x.c

@@ -14,13 +14,13 @@
 #define RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE			0xCE24
 /* port 0-28 */
 #define RTL930X_VLAN_PORT_TAG_STS_CTRL(port) \
-		RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
+	(RTL930X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2))
-#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK	GENMASK(7,6)
+#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_OTAG_STS_MASK	GENMASK(7, 6)
-#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK	GENMASK(5,4)
+#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_ITAG_STS_MASK	GENMASK(5, 4)
-#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK	GENMASK(3,3)
+#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK	GENMASK(3, 3)
-#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK	GENMASK(2,2)
+#define RTL930X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK	GENMASK(2, 2)
-#define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK	GENMASK(1,1)
+#define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK	GENMASK(1, 1)
-#define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK	GENMASK(0,0)
+#define RTL930X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK	GENMASK(0, 0)
 
 #define RTL930X_LED_GLB_ACTIVE_LOW				BIT(22)
 
@@ -28,13 +28,11 @@
 #define RTL930X_LED_SETX_1_CTRL(x) (RTL930X_LED_SETX_0_CTRL(x) - 4)
 
 /* get register for given set and led in the set */
-#define RTL930X_LED_SETX_LEDY(x,y) (RTL930X_LED_SETX_0_CTRL(x) - 4 * (y / 2))
+#define RTL930X_LED_SETX_LEDY(x, y) (RTL930X_LED_SETX_0_CTRL(x) - 4 * (y / 2))
 
 /* get shift for given led in any set */
 #define RTL930X_LED_SET_LEDX_SHIFT(x) (16 * (x % 2))
 
-extern struct rtl83xx_soc_info soc_info;
-
 /* Definition of the RTL930X-specific template field IDs as used in the PIE */
 enum template_field_id {
 	TEMPLATE_FIELD_SPM0 = 0,		/* Source portmask ports 0-15 */
@@ -97,8 +95,7 @@ enum template_field_id {
 /* Number of fixed templates predefined in the RTL9300 SoC */
 #define N_FIXED_TEMPLATES 5
 /* RTL9300 specific predefined templates */
-static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
+static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] = {
-{
 	{
 	  TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
 	  TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
@@ -252,7 +249,7 @@ static int rtldsa_930x_port_rate_police_del(struct dsa_switch *ds, int port,
 	return 0;
 }
 
-inline static int rtl930x_trk_mbr_ctr(int group)
+static inline int rtl930x_trk_mbr_ctr(int group)
 {
 	return RTL930X_TRK_MBR_CTRL + (group << 2);
 }
@@ -455,7 +452,7 @@ static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
 {
 	u32 k0, k1, h1, h2, h;
 
-	k0 = (u32) (((seed >> 55) & 0x1f) ^
+	k0 = (u32)(((seed >> 55) & 0x1f) ^
 		   ((seed >> 44) & 0x7ff) ^
 		   ((seed >> 33) & 0x7ff) ^
 		   ((seed >> 22) & 0x7ff) ^
@@ -466,9 +463,9 @@ static u32 rtl930x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
 	h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
 
 	h2 = (seed >> 33) & 0x7ff;
-	h2 = ((h2 & 0x3f) << 5)| ((h2 >> 6) & 0x3f);
+	h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x3f);
 
-	k1 = (u32) (((seed << 55) & 0x1f) ^
+	k1 = (u32)(((seed << 55) & 0x1f) ^
 		   ((seed >> 44) & 0x7ff) ^
 		   h2 ^
 		   ((seed >> 22) & 0x7ff) ^
@@ -664,7 +661,7 @@ static void rtl930x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_
 
 	pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
 	pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
-		e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
+		 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5]);
 
 	rtl930x_fill_l2_row(r, e);
 
@@ -756,7 +753,7 @@ static void rtldsa_930x_set_receive_management_action(int port, rma_ctrl_t type,
 		return;
 	}
 
-	switch(action) {
+	switch (action) {
 	case FORWARD:
 		value = 0;
 		break;
@@ -776,7 +773,7 @@ static void rtldsa_930x_set_receive_management_action(int port, rma_ctrl_t type,
 		return;
 	}
 
-	switch(type) {
+	switch (type) {
 	case BPDU:
 		reg = RTL930X_RMA_BPDU_CTRL + (port / 10) * 4;
 		shift = (port % 10) * 3;
@@ -830,6 +827,7 @@ static void rtl930x_traffic_set(int source, u64 dest_matrix)
 static void rtl930x_traffic_enable(int source, int dest)
 {
 	struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
+
 	rtl_table_read(r, source);
 	sw_w32_mask(0, BIT(dest + 3), rtl_table_data(r, 0));
 	rtl_table_write(r, source);
@@ -839,6 +837,7 @@ static void rtl930x_traffic_enable(int source, int dest)
 static void rtl930x_traffic_disable(int source, int dest)
 {
 	struct table_reg *r = rtl_table_get(RTL9300_TBL_0, 6);
+
 	rtl_table_read(r, source);
 	sw_w32_mask(BIT(dest + 3), 0, rtl_table_data(r, 0));
 	rtl_table_write(r, source);
@@ -849,7 +848,7 @@ void rtl9300_dump_debug(void)
 {
 	u16 r = RTL930X_STAT_PRVTE_DROP_COUNTER0;
 
-	for (int i = 0; i < 10; i ++) {
+	for (int i = 0; i < 10; i++) {
 		pr_debug("# %d %08x %08x %08x %08x %08x %08x %08x %08x\n", i * 8,
 			 sw_r32(r), sw_r32(r + 4), sw_r32(r + 8), sw_r32(r + 12),
 			 sw_r32(r + 16), sw_r32(r + 20), sw_r32(r + 24), sw_r32(r + 28));
@@ -1099,7 +1098,7 @@ static void rtl930x_route_read(int idx, struct rtl83xx_route *rt)
 		rt->prefix_len = host_route ? 128 : 0;
 		rt->prefix_len = (rt->prefix_len < 0 && default_route) ? 0 : -1;
 		if (rt->prefix_len < 0)
-			rt->prefix_len = find_last_bit((unsigned long int *)&ip6_m.s6_addr32,
+			rt->prefix_len = find_last_bit((unsigned long *)&ip6_m.s6_addr32,
 						       128);
 		break;
 	case 1: /* IPv4 Multicast route */
@@ -1401,7 +1400,6 @@ static void rtl930x_route_write(int idx, struct rtl83xx_route *rt)
 	rtl_table_release(r);
 }
 
-
 /* Get the destination MAC and L3 egress interface ID of a nexthop entry from
  * the SoC's L3_NEXTHOP table
  */
@@ -1472,11 +1470,11 @@ static void rtl930x_get_l3_nexthop(int idx, u16 *dmac_id, u16 *interface)
 
 
 // Currently not used
-// /* Creates an interface for a route by setting up the HW tables in the SoC
+// /* Creates an interface for a route by setting up the HW tables in the SoC */
 // static int rtl930x_l3_intf_add(struct rtl838x_switch_priv *priv, struct rtl838x_l3_intf *intf)
 // {
 // 	int i, intf_id, mtu_id;
-// 	/* number of MTU-values < 16384 *\/
+// 	/* number of MTU-values < 16384 */
 
 // 	/* Use the same IPv6 mtu as the ip4 mtu for this route if unset */
 // 	intf->ip6_mtu = intf->ip6_mtu ? intf->ip6_mtu : intf->ip4_mtu;
@@ -1520,7 +1518,7 @@ static void rtl930x_set_l3_nexthop(int idx, u16 dmac_id, u16 interface)
 		 __func__, idx, dmac_id, interface);
 	sw_w32(((dmac_id & 0x7fff) << 7) | (interface & 0x7f), rtl_table_data(r, 0));
 
-	pr_debug("%s: %08x\n", __func__, sw_r32(rtl_table_data(r,0)));
+	pr_debug("%s: %08x\n", __func__, sw_r32(rtl_table_data(r, 0)));
 	rtl_table_write(r, idx);
 	rtl_table_release(r);
 }
@@ -1746,40 +1744,40 @@ static void rtl930x_write_pie_templated(u32 r[], struct pie_rule *pr, enum templ
 static void rtl930x_write_pie_fixed_fields(u32 r[],  struct pie_rule *pr)
 {
 	r[6] = pr->stacking_port ? BIT(31) : 0;
-	r[6] |= ((u32) (pr->spn & 0x7f)) << 24;
+	r[6] |= ((u32)(pr->spn & 0x7f)) << 24;
 	r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
 	if (pr->phase == PHASE_IACL)
 		r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
 	else
 		r[6] |= pr->content_too_deep ? BIT(22) : 0;
 	r[6] |= pr->not_first_frag ? BIT(21) : 0;
-	r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
+	r[6] |= ((u32)(pr->frame_type_l4 & 0x7)) << 18;
-	r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
+	r[6] |= ((u32)(pr->frame_type & 0x3)) << 16;
 	r[6] |= pr->otag_fmt ? BIT(15) : 0;
 	r[6] |= pr->itag_fmt ? BIT(14) : 0;
 	r[6] |= pr->otag_exist ? BIT(13) : 0;
 	r[6] |= pr->itag_exist ? BIT(12) : 0;
-	r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
+	r[6] |= ((u32)(pr->frame_type_l2 & 0x3)) << 10;
 	r[6] |= pr->igr_normal_port ? BIT(9) : 0;
-	r[6] |= ((u32) (pr->tid & 0x1)) << 8;
+	r[6] |= ((u32)(pr->tid & 0x1)) << 8;
 
 	r[12] |= pr->stacking_port_m ? BIT(7) : 0;
-	r[12] |= (u32) (pr->spn_m & 0x7f);
+	r[12] |= (u32)(pr->spn_m & 0x7f);
 	r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
 	if (pr->phase == PHASE_IACL)
 		r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
 	else
 		r[13] |= pr->content_too_deep_m ? BIT(30) : 0;
 	r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
-	r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
+	r[13] |= ((u32)(pr->frame_type_l4_m & 0x7)) << 26;
-	r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
+	r[13] |= ((u32)(pr->frame_type_m & 0x3)) << 24;
 	r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
 	r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
 	r[13] |= pr->otag_exist_m ? BIT(21) : 0;
 	r[13] |= pr->itag_exist_m ? BIT(20) : 0;
-	r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
+	r[13] |= ((u32)(pr->frame_type_l2_m & 0x3)) << 18;
 	r[13] |= pr->igr_normal_port_m ? BIT(17) : 0;
-	r[13] |= ((u32) (pr->tid_m & 0x1)) << 16;
+	r[13] |= ((u32)(pr->tid_m & 0x1)) << 16;
 
 	r[13] |= pr->valid ? BIT(15) : 0;
 	r[13] |= pr->cond_not ? BIT(14) : 0;
@@ -1884,6 +1882,7 @@ static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)
 {
 	for (int i = 0; i < N_FIXED_FIELDS; i++) {
 		enum template_field_id ft = fixed_templates[t][i];
+
 		if (field_type == ft)
 			return true;
 	}
@@ -1891,7 +1890,7 @@ static bool rtl930x_pie_templ_has(int t, enum template_field_id field_type)
 	return false;
 }
 
-/* Verify that the rule pr is compatible with a given template t in block block
+/* Verify that the rule pr is compatible with a given template t in block
  * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
  * depend on the SoC
  */
@@ -1988,7 +1987,7 @@ static int rtl930x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul
 /* Delete a range of Packet Inspection Engine rules */
 static int rtl930x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
 {
-	u32 v = (index_from << 1)| (index_to << 12 ) | BIT(0);
+	u32 v = (index_from << 1) | (index_to << 12) | BIT(0);
 
 	pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
 	mutex_lock(&priv->reg_mutex);
@@ -2051,7 +2050,6 @@ static void rtl930x_pie_init(struct rtl838x_switch_priv *priv)
 	template_selectors = 2 | (3 << 4);
 	for (int i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
 		sw_w32(template_selectors, RTL930X_PIE_BLK_TMPLTE_CTRL(i));
-
 }
 
 #ifdef CONFIG_NET_DSA_RTL83XX_RTL930X_L3_OFFLOAD
@@ -2077,7 +2075,7 @@ static void rtl930x_set_l3_egress_intf(int idx, struct rtl838x_l3_intf *intf)
 	v |= (intf->ttl_scope & 0xff) << 20;
 	v |= (intf->hl_scope & 0xff) << 12;
 	v |= (intf->ip4_icmp_redirect & 0x7) << 9;
-	v |= (intf->ip6_icmp_redirect & 0x7)<< 6;
+	v |= (intf->ip6_icmp_redirect & 0x7) << 6;
 	v |= (intf->ip4_pbr_icmp_redirect & 0x7) << 3;
 	v |= (intf->ip6_pbr_icmp_redirect & 0x7);
 
@@ -2318,7 +2316,7 @@ static void rtl930x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum
 	if (type == PBVLAN_TYPE_INNER)
 		sw_w32_mask(0x3, mode, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
 	else
-		sw_w32_mask(0x3 << 14, mode << 14 ,RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
+		sw_w32_mask(0x3 << 14, mode << 14, RTL930X_VLAN_PORT_PB_VLAN + (port << 2));
 }
 
 static void rtl930x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
@@ -2365,7 +2363,7 @@ static int rtl930x_set_ageing_time(unsigned long msec)
 
 static void rtl930x_set_igr_filter(int port,  enum igr_filter state)
 {
-	sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
+	sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1),
 		    RTL930X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
 }
 
@@ -2506,7 +2504,7 @@ static void rtl930x_led_init(struct rtl838x_switch_priv *priv)
 			priv->ports[i].leds_on_this_port = forced_leds_per_port[i];
 
 		/* 0x0 = 1 led, 0x1 = 2 leds, 0x2 = 3 leds, 0x3 = 4 leds per port */
-		sw_w32_mask(0x3 << pos, (priv->ports[i].leds_on_this_port -1) << pos, RTL930X_LED_PORT_NUM_CTRL(i));
+		sw_w32_mask(0x3 << pos, (priv->ports[i].leds_on_this_port - 1) << pos, RTL930X_LED_PORT_NUM_CTRL(i));
 
 		pm |= BIT(i);
 

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/rtl931x.c

@@ -13,19 +13,17 @@
 #define RTL931X_VLAN_PORT_TAG_CTRL_BASE				0x4860
 /* port 0-56 */
 #define RTL931X_VLAN_PORT_TAG_CTRL(port) \
-		RTL931X_VLAN_PORT_TAG_CTRL_BASE + (port << 2)
+	(RTL931X_VLAN_PORT_TAG_CTRL_BASE + (port << 2))
-#define RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK			GENMASK(13,12)
+#define RTL931X_VLAN_PORT_TAG_EGR_OTAG_STS_MASK			GENMASK(13, 12)
-#define RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK			GENMASK(11,10)
+#define RTL931X_VLAN_PORT_TAG_EGR_ITAG_STS_MASK			GENMASK(11, 10)
-#define RTL931X_VLAN_PORT_TAG_EGR_OTAG_KEEP_MASK		GENMASK(9,9)
+#define RTL931X_VLAN_PORT_TAG_EGR_OTAG_KEEP_MASK		GENMASK(9, 9)
-#define RTL931X_VLAN_PORT_TAG_EGR_ITAG_KEEP_MASK		GENMASK(8,8)
+#define RTL931X_VLAN_PORT_TAG_EGR_ITAG_KEEP_MASK		GENMASK(8, 8)
-#define RTL931X_VLAN_PORT_TAG_IGR_OTAG_KEEP_MASK		GENMASK(7,7)
+#define RTL931X_VLAN_PORT_TAG_IGR_OTAG_KEEP_MASK		GENMASK(7, 7)
-#define RTL931X_VLAN_PORT_TAG_IGR_ITAG_KEEP_MASK		GENMASK(6,6)
+#define RTL931X_VLAN_PORT_TAG_IGR_ITAG_KEEP_MASK		GENMASK(6, 6)
-#define RTL931X_VLAN_PORT_TAG_OTPID_IDX_MASK			GENMASK(5,4)
+#define RTL931X_VLAN_PORT_TAG_OTPID_IDX_MASK			GENMASK(5, 4)
-#define RTL931X_VLAN_PORT_TAG_OTPID_KEEP_MASK			GENMASK(3,3)
+#define RTL931X_VLAN_PORT_TAG_OTPID_KEEP_MASK			GENMASK(3, 3)
-#define RTL931X_VLAN_PORT_TAG_ITPID_IDX_MASK			GENMASK(2,1)
+#define RTL931X_VLAN_PORT_TAG_ITPID_IDX_MASK			GENMASK(2, 1)
-#define RTL931X_VLAN_PORT_TAG_ITPID_KEEP_MASK			GENMASK(0,0)
+#define RTL931X_VLAN_PORT_TAG_ITPID_KEEP_MASK			GENMASK(0, 0)
-
-extern struct rtl83xx_soc_info soc_info;
 
 /* Definition of the RTL931X-specific template field IDs as used in the PIE */
 enum template_field_id {
@@ -83,8 +81,7 @@ enum template_field_id {
 /* Number of fixed templates predefined in the RTL9300 SoC */
 #define N_FIXED_TEMPLATES 5
 /* RTL931x specific predefined templates */
-static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] =
+static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS_RTL931X] = {
-{
 	{
 		TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
 		TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
@@ -150,9 +147,8 @@ static void rtl931x_vlan_profile_dump(int index)
 	profile[3] = (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 20) & 0x1FFFFFFFULL) << 32 |
 		     (sw_r32(RTL931X_VLAN_PROFILE_SET(index) + 24) & 0xFFFFFFFF);
 
-	pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, \
+	pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %llx, IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx\n",
-		IPv4 Unknown MultiCast Field %llx, IPv6 Unknown MultiCast Field: %llx",
+		 index, (u32)(profile[0] & (3 << 14)), profile[1], profile[2], profile[3]);
-		index, (u32) (profile[0] & (3 << 14)), profile[1], profile[2], profile[3]);
 }
 
 static void rtl931x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
@@ -178,7 +174,7 @@ static void rtl931x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port
 	priv->r->exec_tbl0_cmd(cmd);
 }
 
-inline static int rtldsa_931x_trk_mbr_ctr(int group)
+static inline int rtldsa_931x_trk_mbr_ctr(int group)
 {
 	return RTL931X_TRK_MBR_CTRL + (group << 3);
 }
@@ -197,7 +193,7 @@ static void rtl931x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
 	rtl_table_release(r);
 
 	pr_debug("VLAN_READ %d: %08x %08x %08x %08x\n", vlan, v, w, x, y);
-	info->member_ports = ((u64) v) << 25 | (w >> 7);
+	info->member_ports = ((u64)v) << 25 | (w >> 7);
 	info->profile_id = (x >> 16) & 0xf;
 	info->fid = w & 0x7f;				/* AKA MSTI depending on context */
 	info->hash_uc_fid = !!(x & BIT(31));
@@ -407,7 +403,7 @@ static void rtldsa_931x_set_receive_management_action(int port, rma_ctrl_t type,
 		return;
 	}
 
-	switch(action) {
+	switch (action) {
 	case FORWARD:
 		value = 0;
 		break;
@@ -427,7 +423,7 @@ static void rtldsa_931x_set_receive_management_action(int port, rma_ctrl_t type,
 		return;
 	}
 
-	switch(type) {
+	switch (type) {
 	case BPDU:
 		reg = RTL931X_RMA_BPDU_CTRL + (port / 10) * 4;
 		shift = (port % 10) * 3;
@@ -482,6 +478,7 @@ static void rtl931x_traffic_set(int source, u64 dest_matrix)
 static void rtl931x_traffic_enable(int source, int dest)
 {
 	struct table_reg *r = rtl_table_get(RTL9310_TBL_2, 1);
+
 	rtl_table_read(r, source);
 	sw_w32_mask(0, BIT((dest + 7) % 32), rtl_table_data(r, (dest + 7) / 32 ? 0 : 1));
 	rtl_table_write(r, source);
@@ -491,6 +488,7 @@ static void rtl931x_traffic_enable(int source, int dest)
 static void rtl931x_traffic_disable(int source, int dest)
 {
 	struct table_reg *r = rtl_table_get(RTL9310_TBL_2, 1);
+
 	rtl_table_read(r, source);
 	sw_w32_mask(BIT((dest + 7) % 32), 0, rtl_table_data(r, (dest + 7) / 32 ? 0 : 1));
 	rtl_table_write(r, source);
@@ -632,7 +630,7 @@ static void rtl931x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
 
 	r[0] |= e->is_open_flow ? BIT(30) : 0;
 	r[0] |= e->is_pe_forward ? BIT(29) : 0;
-	r[0] |= e->hash_msb ? BIT(28): 0;
+	r[0] |= e->hash_msb ? BIT(28) : 0;
 	r[2] = e->next_hop ? BIT(30) : 0;
 	r[0] |= (e->rvid & 0xfff) << 16;
 
@@ -720,8 +718,9 @@ static u64 rtl931x_read_cam(int idx, struct rtl838x_l2_entry *e)
 {
 	u32 r[4];
 	struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 1);
+
 	rtl_table_read(q, idx);
-	for ( int i = 0; i < 4; i++)
+	for (int i = 0; i < 4; i++)
 		r[i] = sw_r32(rtl_table_data(q, i));
 
 	rtl_table_release(q);
@@ -737,6 +736,7 @@ static void rtl931x_write_cam(int idx, struct rtl838x_l2_entry *e)
 {
 	u32 r[4];
 	struct table_reg *q = rtl_table_get(RTL9310_TBL_0, 1);
+
 	rtl931x_fill_l2_row(r, e);
 
 	for (int i = 0; i < 4; i++)
@@ -754,7 +754,7 @@ static void rtl931x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_
 
 	pr_debug("%s: hash %d, pos %d\n", __func__, hash, pos);
 	pr_debug("%s: index %d -> mac %02x:%02x:%02x:%02x:%02x:%02x\n", __func__, idx,
-		e->mac[0], e->mac[1], e->mac[2], e->mac[3],e->mac[4],e->mac[5]);
+		 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5]);
 
 	if (idx < 0x4000)
 		hash_algo_id = sw_r32(RTL931X_L2_CTRL) & BIT(0);
@@ -877,7 +877,6 @@ static void rtl931x_write_mcast_pmask(int idx, u64 portmask)
 	rtl_table_release(q);
 }
 
-
 static int rtl931x_set_ageing_time(unsigned long msec)
 {
 	int t = sw_r32(RTL931X_L2_AGE_CTRL);
@@ -1132,15 +1131,15 @@ static void rtl931x_write_pie_fixed_fields(u32 r[],  struct pie_rule *pr)
 	else
 		r[7] |= pr->content_too_deep ? BIT(30) : 0;
 	r[7] |= pr->not_first_frag ? BIT(29) : 0;
-	r[7] |= ((u32) (pr->frame_type_l4 & 0x7)) << 26;
+	r[7] |= ((u32)(pr->frame_type_l4 & 0x7)) << 26;
-	r[7] |= ((u32) (pr->frame_type & 0x3)) << 24;
+	r[7] |= ((u32)(pr->frame_type & 0x3)) << 24;
 	r[7] |= pr->otag_fmt ? BIT(23) : 0;
 	r[7] |= pr->itag_fmt ? BIT(22) : 0;
 	r[7] |= pr->otag_exist ? BIT(21) : 0;
 	r[7] |= pr->itag_exist ? BIT(20) : 0;
-	r[7] |= ((u32) (pr->frame_type_l2 & 0x3)) << 18;
+	r[7] |= ((u32)(pr->frame_type_l2 & 0x3)) << 18;
 	r[7] |= pr->igr_normal_port ? BIT(17) : 0;
-	r[7] |= ((u32) (pr->tid & 0x1)) << 16;
+	r[7] |= ((u32)(pr->tid & 0x1)) << 16;
 
 	r[14] |= pr->mgnt_vlan_m ? BIT(15) : 0;
 	if (pr->phase == PHASE_IACL)
@@ -1148,15 +1147,15 @@ static void rtl931x_write_pie_fixed_fields(u32 r[],  struct pie_rule *pr)
 	else
 		r[14] |= pr->content_too_deep_m ? BIT(14) : 0;
 	r[14] |= pr->not_first_frag_m ? BIT(13) : 0;
-	r[14] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 10;
+	r[14] |= ((u32)(pr->frame_type_l4_m & 0x7)) << 10;
-	r[14] |= ((u32) (pr->frame_type_m & 0x3)) << 8;
+	r[14] |= ((u32)(pr->frame_type_m & 0x3)) << 8;
 	r[14] |= pr->otag_fmt_m ? BIT(7) : 0;
 	r[14] |= pr->itag_fmt_m ? BIT(6) : 0;
 	r[14] |= pr->otag_exist_m ? BIT(5) : 0;
 	r[14] |= pr->itag_exist_m ? BIT(4) : 0;
-	r[14] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 2;
+	r[14] |= ((u32)(pr->frame_type_l2_m & 0x3)) << 2;
 	r[14] |= pr->igr_normal_port_m ? BIT(1) : 0;
-	r[14] |= (u32) (pr->tid_m & 0x1);
+	r[14] |= (u32)(pr->tid_m & 0x1);
 
 	r[15] |= pr->valid ? BIT(31) : 0;
 	r[15] |= pr->cond_not ? BIT(30) : 0;
@@ -1262,6 +1261,7 @@ static bool rtl931x_pie_templ_has(int t, enum template_field_id field_type)
 {
 	for (int i = 0; i < N_FIXED_FIELDS_RTL931X; i++) {
 		enum template_field_id ft = fixed_templates[t][i];
+
 		if (field_type == ft)
 			return true;
 	}
@@ -1269,7 +1269,7 @@ static bool rtl931x_pie_templ_has(int t, enum template_field_id field_type)
 	return false;
 }
 
-/* Verify that the rule pr is compatible with a given template t in block block
+/* Verify that the rule pr is compatible with a given template t in block
  * Note that this function is SoC specific since the values of e.g. TEMPLATE_FIELD_SIP0
  * depend on the SoC
  */
@@ -1332,6 +1332,7 @@ static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul
 	for (block = min_block; block < max_block; block++) {
 		for (j = 0; j < 2; j++) {
 			int t = (sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)) >> (j * 4)) & 0xf;
+
 			pr_debug("Testing block %d, template %d, template id %d\n", block, j, t);
 			pr_debug("%s: %08x\n",
 				 __func__, sw_r32(RTL931X_PIE_BLK_TMPLTE_CTRL(block)));
@@ -1367,7 +1368,7 @@ static int rtl931x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rul
 /* Delete a range of Packet Inspection Engine rules */
 static int rtl931x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
 {
-	u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
+	u32 v = (index_from << 1) | (index_to << 13) | BIT(0);
 
 	pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
 	mutex_lock(&priv->reg_mutex);
@@ -1443,7 +1444,6 @@ static void rtl931x_pie_init(struct rtl838x_switch_priv *priv)
 	template_selectors = 2 | (3 << 4);
 	for (int i = priv->n_pie_blocks * 3 / 4; i < priv->n_pie_blocks; i++)
 		sw_w32(template_selectors, RTL931X_PIE_BLK_TMPLTE_CTRL(i));
-
 }
 
 static void rtl931x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
@@ -1484,14 +1484,14 @@ static int rtldsa_931x_vlan_port_fast_age(struct rtl838x_switch_priv *priv, int
 	val |= BIT(28); /* status - trigger flush */
 	sw_w32(val, RTL931X_L2_TBL_FLUSH_CTRL);
 
-	do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT (28));
+	do { } while (sw_r32(RTL931X_L2_TBL_FLUSH_CTRL) & BIT(28));
 
 	return 0;
 }
 
 static void rtl931x_set_igr_filter(int port, enum igr_filter state)
 {
-	sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
+	sw_w32_mask(0x3 << ((port & 0xf) << 1), state << ((port & 0xf) << 1),
 		    RTL931X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
 }
 

target/linux/realtek/files-6.12/drivers/net/dsa/rtl83xx/tc.c

@@ -291,7 +291,7 @@ out:
 }
 
 static int rtl83xx_delete_flower(struct rtl838x_switch_priv *priv,
-				 struct flow_cls_offload * cls_flower)
+				 struct flow_cls_offload *cls_flower)
 {
 	struct rtl83xx_flow *flow;
 
@@ -315,13 +315,13 @@ static int rtl83xx_delete_flower(struct rtl838x_switch_priv *priv,
 }
 
 static int rtl83xx_stats_flower(struct rtl838x_switch_priv *priv,
-				struct flow_cls_offload * cls_flower)
+				struct flow_cls_offload *cls_flower)
 {
 	struct rtl83xx_flow *flow;
 	unsigned long lastused = 0;
 	int total_packets, new_packets;
 
-	pr_debug("%s: \n", __func__);
+	pr_debug("%s:\n", __func__);
 	flow = rhashtable_lookup_fast(&priv->tc_ht, &cls_flower->cookie, tc_ht_params);
 	if (!flow)
 		return -1;
@@ -356,7 +356,6 @@ static int rtl83xx_setup_tc_cls_flower(struct rtl838x_switch_priv *priv,
 	}
 }
 
-
 static int rtl83xx_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
 				     void *cb_priv)
 {
@@ -382,7 +381,7 @@ int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type
 
 	pr_debug("%s: %d\n", __func__, type);
 
-	if(!netdev_uses_dsa(dev)) {
+	if (!netdev_uses_dsa(dev)) {
 		pr_err("%s: no DSA\n", __func__);
 		return 0;
 	}

target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.c

@@ -3,6 +3,7 @@
  * Copyright (C) 2020 B. Koblitz
  */
 
+#include <linux/cacheflush.h>
 #include <linux/dma-mapping.h>
 #include <linux/etherdevice.h>
 #include <linux/interrupt.h>
@@ -18,14 +19,11 @@
 #include <linux/pkt_sched.h>
 #include <net/dsa.h>
 #include <net/switchdev.h>
-#include <asm/cacheflush.h>
 
 #include <asm/mach-rtl838x/mach-rtl83xx.h>
 #include "rtl838x_eth.h"
 
-extern struct rtl83xx_soc_info soc_info;
+int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data);
-
-extern int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, void *type_data);
 
 /* Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
  * The ring is assigned by switch based on packet/port priortity
@@ -53,33 +51,33 @@ extern int rtl83xx_setup_tc(struct net_device *dev, enum tc_setup_type type, voi
 #define RING_BUFFER	1600
 
 struct p_hdr {
-	uint8_t		*buf;
+	u8	*buf;
-	uint16_t	reserved;
+	u16	reserved;
-	uint16_t	size;		/* buffer size */
+	u16	size;		/* buffer size */
-	uint16_t	offset;
+	u16	offset;
-	uint16_t	len;		/* pkt len */
+	u16	len;		/* pkt len */
-	/* cpu_tag[0] is a reserved uint16_t on RTL83xx */
+	/* cpu_tag[0] is a reserved u16 on RTL83xx */
-	uint16_t	cpu_tag[10];
+	u16	cpu_tag[10];
 } __packed __aligned(1);
 
 struct n_event {
-	uint32_t	type:2;
+	u32	type:2;
-	uint32_t	fidVid:12;
+	u32	fidVid:12;
-	uint64_t	mac:48;
+	u64	mac:48;
-	uint32_t	slp:6;
+	u32	slp:6;
-	uint32_t	valid:1;
+	u32	valid:1;
-	uint32_t	reserved:27;
+	u32	reserved:27;
 } __packed __aligned(1);
 
 struct ring_b {
-	uint32_t	rx_r[MAX_RXRINGS][MAX_RXLEN];
+	u32	rx_r[MAX_RXRINGS][MAX_RXLEN];
-	uint32_t	tx_r[TXRINGS][TXRINGLEN];
+	u32	tx_r[TXRINGS][TXRINGLEN];
 	struct	p_hdr	rx_header[MAX_RXRINGS][MAX_RXLEN];
 	struct	p_hdr	tx_header[TXRINGS][TXRINGLEN];
-	uint32_t	c_rx[MAX_RXRINGS];
+	u32	c_rx[MAX_RXRINGS];
-	uint32_t	c_tx[TXRINGS];
+	u32	c_tx[TXRINGS];
-	uint8_t		tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
+	u8		tx_space[TXRINGS * TXRINGLEN * RING_BUFFER];
-	uint8_t		*rx_space;
+	u8		*rx_space;
 };
 
 struct notify_block {
@@ -352,10 +350,9 @@ static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv *priv)
 		int i;
 
 		w = kzalloc(sizeof(*w), GFP_ATOMIC);
-		if (!w) {
+		if (!w)
-			pr_err("Out of memory: %s", __func__);
 			return;
-		}
+
 		INIT_WORK(&w->work, rtl838x_fdb_sync);
 
 		for (i = 0; i < NOTIFY_EVENTS; i++) {
@@ -786,7 +783,7 @@ static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv *priv)
 	for (int i = 0; i < NOTIFY_BLOCKS; i++)
 		b->ring[i] = KSEG1ADDR(&b->blocks[i]) | 1 | (i == (NOTIFY_BLOCKS - 1) ? WRAP : 0);
 
-	sw_w32((u32) b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
+	sw_w32((u32)b->ring, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL);
 	sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL);
 
 	/* Setup notification events */
@@ -908,9 +905,9 @@ static void rtl838x_hw_stop(struct rtl838x_eth_priv *priv)
 	if (priv->family_id == RTL8380_FAMILY_ID || priv->family_id == RTL8390_FAMILY_ID)
 		sw_w32(force_mac, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
 	else if (priv->family_id == RTL9300_FAMILY_ID)
-		sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
+		sw_w32_mask(0x3, 0, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
 	else if (priv->family_id == RTL9310_FAMILY_ID)
-		sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port *4);
+		sw_w32_mask(BIT(0) | BIT(9), 0, priv->r->mac_force_mode_ctrl + priv->cpu_port * 4);
 	mdelay(100);
 
 	/* Disable all TX/RX interrupts */
@@ -1080,7 +1077,6 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
 
 	/* We can send this packet if CPU owns the descriptor */
 	if (!(ring->tx_r[q][ring->c_tx[q]] & 0x1)) {
-
 		/* Set descriptor for tx */
 		h = &ring->tx_header[q][ring->c_tx[q]];
 		h->size = len;
@@ -1106,6 +1102,7 @@ static int rtl838x_eth_tx(struct sk_buff *skb, struct net_device *dev)
 		if (priv->family_id == RTL8380_FAMILY_ID) {
 			for (int i = 0; i < 10; i++) {
 				u32 val = sw_r32(priv->r->dma_if_ctrl);
+
 				if ((val & 0xc) == 0xc)
 					break;
 			}
@@ -1144,7 +1141,7 @@ txdone:
 static u16 rtl83xx_pick_tx_queue(struct net_device *dev, struct sk_buff *skb,
 				 struct net_device *sb_dev)
 {
-	static u8 last = 0;
+	static u8 last;
 
 	last++;
 	return last % TXRINGS;
@@ -1184,7 +1181,7 @@ static int rtl838x_hw_receive(struct net_device *dev, int r, int budget)
 		if ((ring->rx_r[r][ring->c_rx[r]] & 0x1)) {
 			if (&ring->rx_r[r][ring->c_rx[r]] != last) {
 				netdev_warn(dev, "Ring contention: r: %x, last %x, cur %x\n",
-				    r, (uint32_t)last, (u32) &ring->rx_r[r][ring->c_rx[r]]);
+					    r, (u32)last, (u32)&ring->rx_r[r][ring->c_rx[r]]);
 			}
 			break;
 		}
@@ -1280,6 +1277,7 @@ static int rtl838x_poll_rx(struct napi_struct *napi, int budget)
 
 	while (work_done < budget) {
 		int work = rtl838x_hw_receive(priv->netdev, ring, budget - work_done);
+
 		if (!work)
 			break;
 		work_done += work;
@@ -1429,7 +1427,7 @@ static int rtl838x_set_mac_address(struct net_device *dev, void *p)
 {
 	struct rtl838x_eth_priv *priv = netdev_priv(dev);
 	const struct sockaddr *addr = p;
-	u8 *mac = (u8 *) (addr->sa_data);
+	u8 *mac = (u8 *)(addr->sa_data);
 
 	if (!is_valid_ether_addr(addr->sa_data))
 		return -EADDRNOTAVAIL;
@@ -1657,7 +1655,7 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev)
 	struct ring_b *ring;
 
 	pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
-		(u32)pdev, (u32)(&(pdev->dev)));
+		(u32)pdev, (u32)(&pdev->dev));
 
 	if (!dn) {
 		dev_err(&pdev->dev, "No DT found\n");
@@ -1801,7 +1799,8 @@ static int __init rtl838x_eth_probe(struct platform_device *pdev)
 	}
 	pr_info("Using MAC %08x%08x\n", sw_r32(priv->r->mac),
 		sw_r32(priv->r->mac + 4));
-	strcpy(dev->name, "eth%d");
+	strscpy(dev->name, "eth%d", sizeof(dev->name));
+
 	priv->pdev = pdev;
 	priv->netdev = dev;
 

target/linux/realtek/files-6.12/drivers/net/ethernet/rtl838x_eth.h

@@ -151,12 +151,12 @@
 #define RTL930X_L2_PORT_DABLK_CTRL		(0x9060)
 
 /* MAC link state bits */
-#define FORCE_EN				(1 << 0)
+#define FORCE_EN				BIT(0)
-#define FORCE_LINK_EN				(1 << 1)
+#define FORCE_LINK_EN				BIT(1)
-#define NWAY_EN					(1 << 2)
+#define NWAY_EN					BIT(2)
-#define DUPLX_MODE				(1 << 3)
+#define DUPLX_MODE				BIT(3)
-#define TX_PAUSE_EN				(1 << 6)
+#define TX_PAUSE_EN				BIT(6)
-#define RX_PAUSE_EN				(1 << 7)
+#define RX_PAUSE_EN				BIT(7)
 
 /* L2 Notification DMA interface */
 #define RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL	(0x785C)
@@ -374,7 +374,6 @@ inline u32 rtl839x_get_mac_link_spd_sts(int port)
 	return (speed & 0x3);
 }
 
-
 inline u32 rtl930x_get_mac_link_spd_sts(int port)
 {
 	int r = RTL930X_MAC_LINK_SPD_STS + ((port >> 3) << 2);
@@ -469,4 +468,7 @@ struct rtl838x_eth_reg {
 	bool (*decode_tag)(struct p_hdr *h, struct dsa_tag *tag);
 };
 
+/* TODO actually from arch/mips/rtl838x/prom.c */
+extern struct rtl83xx_soc_info soc_info;
+
 #endif /* _RTL838X_ETH_H */

target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto-serdes.c

@@ -449,7 +449,7 @@ static int rtsds_probe(struct platform_device *pdev)
 	ctrl->cfg = (const struct rtsds_config *)device_get_match_data(ctrl->dev);
 	ctrl->bus = bus;
 
-	snprintf(bus->id, MII_BUS_ID_SIZE, "realtek-serdes-mdio") ;
+	snprintf(bus->id, MII_BUS_ID_SIZE, "realtek-serdes-mdio");
 	bus->name = "Realtek SerDes MDIO bus";
 	bus->parent = dev;
 	bus->read_c45 = rtsds_read;

target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c

@@ -89,15 +89,6 @@
 #define sw_w32(val, reg)			writel(val, RTMDIO_SW_BASE + reg)
 #define sw_w32_mask(clear, set, reg)		sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
 
-int rtmdio_930x_read_sds_phy(int sds, int page, int regnum);
-int rtmdio_930x_write_sds_phy(int sds, int page, int regnum, u16 val);
-
-int rtsds_931x_read(int sds, int page, int regnum);
-int rtsds_931x_read_field(int sds, int page, int regnum, int end_bit, int start_bit);
-
-int rtsds_931x_write(int sds, int page, int regnum, u16 val);
-int rtsds_931x_write_field(int sds, int page, int regnum, int end_bit, int start_bit, u16 val);
-
 /*
  * On all Realtek switch platforms the hardware periodically reads the link status of all
  * PHYs. This is to some degree programmable, so that one can tell the hardware to read
@@ -622,7 +613,7 @@ errout:
  * - SerDes 10-11 are 10GBase-R capable
  */
 
-int rtmdio_930x_read_sds_phy(int sds, int page, int regnum)
+static int rtmdio_930x_read_sds_phy(int sds, int page, int regnum)
 {
 	int i, ret = -EIO;
 	u32 cmd;
@@ -649,7 +640,7 @@ int rtmdio_930x_read_sds_phy(int sds, int page, int regnum)
 	return ret;
 }
 
-int rtmdio_930x_write_sds_phy(int sds, int page, int regnum, u16 val)
+static int rtmdio_930x_write_sds_phy(int sds, int page, int regnum, u16 val)
 {
 	int i, ret = -EIO;
 	u32 cmd;
@@ -725,7 +716,7 @@ static int rtmdio_930x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
 
 	do {
 		v = sw_r32(RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1);
-	} while ( v & 0x1);
+	} while (v & 0x1);
 
 	if (v & BIT(25)) {
 		pr_debug("Error reading phy %d, register %d\n", port, reg);
@@ -848,7 +839,7 @@ static int rtsds_931x_get_backing_sds(int sds, int page)
 	return back;
 }
 
-int rtsds_931x_read(int sds, int page, int regnum)
+static int rtsds_931x_read(int sds, int page, int regnum)
 {
 	int backsds, i, cmd, ret = -EIO;
 	int backpage = page & 0x3f;
@@ -878,7 +869,7 @@ int rtsds_931x_read(int sds, int page, int regnum)
 	return ret;
 }
 
-int rtsds_931x_write(int sds, int page, int regnum, u16 val)
+static int rtsds_931x_write(int sds, int page, int regnum, u16 val)
 {
 	int backsds, i, cmd, ret = -EIO;
 	int backpage = page & 0x3f;
@@ -909,7 +900,8 @@ int rtsds_931x_write(int sds, int page, int regnum, u16 val)
 	return ret;
 }
 
-int rtsds_931x_write_field(int sds, int page, int reg, int end_bit, int start_bit, u16 val)
+__always_unused
+static int rtsds_931x_write_field(int sds, int page, int reg, int end_bit, int start_bit, u16 val)
 {
 	int l = end_bit - start_bit + 1;
 	u32 data = val;
@@ -925,7 +917,8 @@ int rtsds_931x_write_field(int sds, int page, int reg, int end_bit, int start_bi
 	return rtsds_931x_write(sds, page, reg, data);
 }
 
-int rtsds_931x_read_field(int sds, int page, int reg, int end_bit, int start_bit)
+__always_unused
+static int rtsds_931x_read_field(int sds, int page, int reg, int end_bit, int start_bit)
 {
 	int l = end_bit - start_bit + 1;
 	u32 v = rtsds_931x_read(sds, page, reg);
@@ -956,7 +949,7 @@ static int rtmdio_931x_write_phy(u32 port, u32 page, u32 reg, u32 val)
 
 	sw_w32_mask(0xffff, val, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3);
 
-	v = reg << 6 | page << 11 ;
+	v = reg << 6 | page << 11;
 	sw_w32(v, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0);
 
 	sw_w32(0x1ff, RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1);
@@ -1448,12 +1441,12 @@ static int rtmdio_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	priv = bus->priv;
-	for (i=0; i < RTMDIO_MAX_PORT; i++) {
+	for (i = 0; i < RTMDIO_MAX_PORT; i++) {
 		priv->page[i] = 0;
 		priv->raw[i] = false;
 	}
 
-	switch(family) {
+	switch (family) {
 	case RTMDIO_838X_FAMILY_ID:
 		bus->name = "rtl838x-eth-mdio";
 		bus->read = rtmdio_read;
@@ -1573,7 +1566,7 @@ static int rtmdio_probe(struct platform_device *pdev)
 		if (pcs_node)
 			of_property_read_u32(pcs_node, "reg", &priv->sds_id[pn]);
 		if (priv->phy_is_internal[pn] && priv->sds_id[pn] >= 0)
-			priv->smi_bus[pn]= -1;
+			priv->smi_bus[pn] = -1;
 		if (priv->sds_id[pn] >= 0)
 			dev_dbg(dev, "PHY %d has SDS %d\n", pn, priv->sds_id[pn]);
 	}

target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c

@@ -238,7 +238,7 @@ static void rtpcs_930x_sds_set(struct rtpcs_ctrl *ctrl, int sds_num, u32 mode)
 	mdelay(10);
 }
 
-__attribute__((unused))
+__always_unused
 static u32 rtpcs_930x_sds_mode_get(struct rtpcs_ctrl *ctrl, int sds_num)
 {
 	u32 v;
@@ -254,7 +254,7 @@ static u32 rtpcs_930x_sds_mode_get(struct rtpcs_ctrl *ctrl, int sds_num)
 	return v & RTL930X_SDS_MASK;
 }
 
-__attribute__((unused))
+__always_unused
 static u32 rtpcs_930x_sds_submode_get(struct rtpcs_ctrl *ctrl, int sds_num)
 {
 	u32 v;
@@ -599,7 +599,7 @@ static void rtpcs_930x_sds_mode_set(struct rtpcs_ctrl *ctrl, int sds,
 		return;
 	}
 
-	switch(phy_mode) {
+	switch (phy_mode) {
 	case PHY_INTERFACE_MODE_SGMII:
 	case PHY_INTERFACE_MODE_1000BASEX:
 	case PHY_INTERFACE_MODE_2500BASEX:
@@ -622,12 +622,10 @@ static void rtpcs_930x_sds_mode_set(struct rtpcs_ctrl *ctrl, int sds,
 	rtpcs_930x_sds_set(ctrl, sds, mode);
 
 	/* Set the submode if needed. */
-	if (phy_mode == PHY_INTERFACE_MODE_10G_QXGMII) {
+	if (phy_mode == PHY_INTERFACE_MODE_10G_QXGMII)
 		rtpcs_930x_sds_submode_set(ctrl, sds, submode);
-	}
 }
 
-
 static void rtpcs_930x_sds_tx_config(struct rtpcs_ctrl *ctrl, int sds,
 				     phy_interface_t phy_if)
 {
@@ -640,7 +638,7 @@ static void rtpcs_930x_sds_tx_config(struct rtpcs_ctrl *ctrl, int sds,
 	int post_en = 0x1;
 	int page;
 
-	switch(phy_if) {
+	switch (phy_if) {
 	case PHY_INTERFACE_MODE_1000BASEX:
 	case PHY_INTERFACE_MODE_SGMII:
 		pre_amp = 0x1;
@@ -681,28 +679,29 @@ static void rtpcs_930x_sds_tx_config(struct rtpcs_ctrl *ctrl, int sds,
 /* Wait for clock ready, this assumes the SerDes is in XGMII mode
  * timeout is in ms
  */
-__attribute__((unused))
+__always_unused
 static int rtpcs_930x_sds_clock_wait(struct rtpcs_ctrl *ctrl, int timeout)
 {
 	u32 v;
 	unsigned long start = jiffies;
+	unsigned long end = start + (HZ / 1000) * timeout;
 
 	do {
 		rtpcs_sds_write_bits(ctrl, 2, 0x1f, 0x2, 15, 0, 53);
 		v = rtpcs_sds_read_bits(ctrl, 2, 0x1f, 20, 5, 4);
 		if (v == 3)
 			return 0;
-	} while (jiffies < start + (HZ / 1000) * timeout);
+	} while (time_before(jiffies, end));
 
 	return 1;
 }
 
-__attribute__((unused))
+__always_unused
 static void rtpcs_930x_sds_rxcal_dcvs_manual(struct rtpcs_ctrl *ctrl, u32 sds_num,
 					     u32 dcvs_id, bool manual, u32 dvcs_list[])
 {
 	if (manual) {
-		switch(dcvs_id) {
+		switch (dcvs_id) {
 		case 0:
 			rtpcs_sds_write_bits(ctrl, sds_num, 0x2e, 0x1e, 14, 14, 0x1);
 			rtpcs_sds_write_bits(ctrl, sds_num, 0x2f, 0x03,  5,  5, dvcs_list[0]);
@@ -737,7 +736,7 @@ static void rtpcs_930x_sds_rxcal_dcvs_manual(struct rtpcs_ctrl *ctrl, u32 sds_nu
 			break;
 		}
 	} else {
-		switch(dcvs_id) {
+		switch (dcvs_id) {
 		case 0:
 			rtpcs_sds_write_bits(ctrl, sds_num, 0x2e, 0x1e, 14, 14, 0x0);
 			break;
@@ -763,7 +762,7 @@ static void rtpcs_930x_sds_rxcal_dcvs_manual(struct rtpcs_ctrl *ctrl, u32 sds_nu
 	}
 }
 
-__attribute__((unused))
+__always_unused
 static void rtpcs_930x_sds_rxcal_dcvs_get(struct rtpcs_ctrl *ctrl, u32 sds_num,
 					  u32 dcvs_id, u32 dcvs_list[])
 {
@@ -781,7 +780,7 @@ static void rtpcs_930x_sds_rxcal_dcvs_get(struct rtpcs_ctrl *ctrl, u32 sds_num,
 	/* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
 	rtpcs_sds_write_bits(ctrl, sds_num, 0x21, 0x06, 11, 6, 0x20);
 
-	switch(dcvs_id) {
+	switch (dcvs_id) {
 	case 0:
 		rtpcs_sds_write_bits(ctrl, sds_num, 0x2f, 0x0c, 5, 0, 0x22);
 		mdelay(1);
@@ -889,20 +888,20 @@ static u32 rtpcs_930x_sds_rxcal_gray_to_binary(u32 gray_code)
 	u32 c[GRAY_BITS];
 	u32 leq_binary = 0;
 
-	for(i = 0; i < GRAY_BITS; i++)
+	for (i = 0; i < GRAY_BITS; i++)
 		g[i] = (gray_code & BIT(i)) >> i;
 
 	m = GRAY_BITS - 1;
 
 	c[m] = g[m];
 
-	for(i = 0; i < m; i++) {
+	for (i = 0; i < m; i++) {
 		c[i] = g[i];
-		for(j  = i + 1; j < GRAY_BITS; j++)
+		for (j  = i + 1; j < GRAY_BITS; j++)
 			c[i] = c[i] ^ g[j];
 	}
 
-	for(i = 0; i < GRAY_BITS; i++)
+	for (i = 0; i < GRAY_BITS; i++)
 		leq_binary += c[i] << i;
 
 	return leq_binary;
@@ -985,7 +984,7 @@ static void rtpcs_930x_sds_rxcal_tap_manual(struct rtpcs_ctrl *ctrl, u32 sds_num
 					    int tap_id, bool manual, u32 tap_list[])
 {
 	if (manual) {
-		switch(tap_id) {
+		switch (tap_id) {
 		case 0:
 			/* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */
 			rtpcs_sds_write_bits(ctrl, sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
@@ -1069,7 +1068,7 @@ static void rtpcs_930x_sds_rxcal_tap_get(struct rtpcs_ctrl *ctrl, u32 sds_num,
 		tap_list[1] = tap0_coef_bin;
 
 		tap_manual = !!rtpcs_sds_read_bits(ctrl, sds_num, 0x2e, 0x0f, 7, 7);
-		pr_info("tap0 manual = %u",tap_manual);
+		pr_info("tap0 manual = %u", tap_manual);
 	} else {
 		/* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
 		rtpcs_sds_write_bits(ctrl, sds_num, 0x2f, 0x0c, 5, 0, tap_id);
@@ -1096,7 +1095,7 @@ static void rtpcs_930x_sds_rxcal_tap_get(struct rtpcs_ctrl *ctrl, u32 sds_num,
 		else
 			pr_info("Tap %u odd sign: +", tap_id);
 
-		pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
+		pr_info("Tap %u odd coefficient = %u", tap_id, tap_coef_bin_odd);
 
 		tap_list[0] = tap_sign_out_even;
 		tap_list[1] = tap_coef_bin_even;
@@ -1104,11 +1103,11 @@ static void rtpcs_930x_sds_rxcal_tap_get(struct rtpcs_ctrl *ctrl, u32 sds_num,
 		tap_list[3] = tap_coef_bin_odd;
 
 		tap_manual = rtpcs_sds_read_bits(ctrl, sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
-		pr_info("tap %u manual = %d",tap_id, tap_manual);
+		pr_info("tap %u manual = %d", tap_id, tap_manual);
 	}
 }
 
-__attribute__((unused))
+__always_unused
 static void rtpcs_930x_sds_do_rx_calibration_1(struct rtpcs_ctrl *ctrl, int sds,
 					       phy_interface_t phy_mode)
 {
@@ -1236,7 +1235,7 @@ static void rtpcs_930x_sds_do_rx_calibration_2_3(struct rtpcs_ctrl *ctrl,
 
 	pr_info("start_1.2.3 Foreground Calibration\n");
 
-	while(1) {
+	while (1) {
 		if (!(sds_num % 2))
 			rtpcs_sds_write(ctrl, sds_num, 0x1f, 0x2, 0x2f);
 		else
@@ -1260,23 +1259,22 @@ static void rtpcs_930x_sds_do_rx_calibration_2_3(struct rtpcs_ctrl *ctrl,
 
 		offset_range = rtpcs_sds_read_bits(ctrl, sds_num, 0x2e, 0x15, 15, 14);
 
-		if (fgcal_binary > 60 || fgcal_binary < 3) {
+		if (fgcal_binary <= 60 && fgcal_binary >= 3)
+			break;
+
 		if (offset_range == 3) {
 			pr_info("%s: Foreground Calibration result marginal!", __func__);
 			break;
-			} else {
+		}
+
 		offset_range++;
 		rtpcs_sds_write_bits(ctrl, sds_num, 0x2e, 0x15, 15, 14, offset_range);
 		rtpcs_930x_sds_do_rx_calibration_2_2(ctrl, sds_num);
 	}
-		} else {
-			break;
-		}
-	}
 	pr_info("%s: end_1.2.3\n", __func__);
 }
 
-__attribute__((unused))
+__always_unused
 static void rtpcs_930x_sds_do_rx_calibration_2(struct rtpcs_ctrl *ctrl, int sds)
 {
 	rtpcs_930x_sds_rx_reset(ctrl, sds, PHY_INTERFACE_MODE_10GBASER);
@@ -1327,7 +1325,7 @@ static void rtpcs_930x_sds_rxcal_3_2(struct rtpcs_ctrl *ctrl, int sds_num,
 
 	pr_info("start_1.3.2");
 
-	for(i = 0; i < 10; i++) {
+	for (i = 0; i < 10; i++) {
 		sum10 += rtpcs_930x_sds_rxcal_leq_read(ctrl, sds_num);
 		mdelay(10);
 	}
@@ -1363,12 +1361,12 @@ static void rtpcs_930x_sds_rxcal_3_2(struct rtpcs_ctrl *ctrl, int sds_num,
 		}
 	}
 
-	pr_info("Sds:%u LEQ = %u",sds_num, rtpcs_930x_sds_rxcal_leq_read(ctrl, sds_num));
+	pr_info("Sds:%u LEQ = %u", sds_num, rtpcs_930x_sds_rxcal_leq_read(ctrl, sds_num));
 
 	pr_info("end_1.3.2");
 }
 
-__attribute__((unused))
+__always_unused
 static void rtpcs_930x_sds_do_rx_calibration_3(struct rtpcs_ctrl *ctrl, int sds_num,
 					       phy_interface_t phy_mode)
 {
@@ -1445,7 +1443,6 @@ static void rtpcs_930x_sds_do_rx_calibration_5(struct rtpcs_ctrl *ctrl, u32 sds_
 		rtpcs_930x_sds_do_rx_calibration_5_2(ctrl, sds_num);
 }
 
-
 static void rtpcs_930x_sds_do_rx_calibration_dfe_disable(struct rtpcs_ctrl *ctrl, u32 sds_num)
 {
 	u32 tap1_list[4] = {0};
@@ -1643,8 +1640,7 @@ static int rtpcs_930x_sds_set_polarity(struct rtpcs_ctrl *ctrl, u32 sds,
 	return rtpcs_sds_write_bits(ctrl, sds, 0x0, 0x0, 9, 8, val);
 }
 
-static const sds_config rtpcs_930x_sds_cfg_10gr_even[] =
+static const sds_config rtpcs_930x_sds_cfg_10gr_even[] = {
-{
 	/* 1G */
 	{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
 	{0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
@@ -1691,8 +1687,7 @@ static const sds_config rtpcs_930x_sds_cfg_10gr_even[] =
 	{0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
 };
 
-static const sds_config rtpcs_930x_sds_cfg_10gr_odd[] =
+static const sds_config rtpcs_930x_sds_cfg_10gr_odd[] = {
-{
 	/* 1G */
 	{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
 	{0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
@@ -1734,8 +1729,7 @@ static const sds_config rtpcs_930x_sds_cfg_10gr_odd[] =
 	{0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
 };
 
-static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_even[] =
+static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_even[] = {
-{
 	{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100},
 	{0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
 	{0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008},
@@ -1757,8 +1751,7 @@ static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_even[] =
 	{0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x66E1},
 };
 
-static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_odd[] =
+static const sds_config rtpcs_930x_sds_cfg_10g_2500bx_odd[] = {
-{
 	{0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100},
 	{0x21, 0x03, 0x8206}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
 	{0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
@@ -1844,9 +1837,8 @@ static void rtpcs_930x_sds_patch(struct rtpcs_ctrl *ctrl, int sds, phy_interface
 		return;
 	}
 
-	for (size_t i = 0; i < count; ++i) {
+	for (size_t i = 0; i < count; ++i)
 		rtpcs_sds_write(ctrl, sds, config[i].page, config[i].reg, config[i].data);
-	}
 
 	if (mode == PHY_INTERFACE_MODE_10G_QXGMII) {
 		/* Default configuration */
@@ -1854,7 +1846,7 @@ static void rtpcs_930x_sds_patch(struct rtpcs_ctrl *ctrl, int sds, phy_interface
 	}
 }
 
-__attribute__((unused))
+__always_unused
 static int rtpcs_930x_sds_cmu_band_get(struct rtpcs_ctrl *ctrl, int sds)
 {
 	u32 page;
@@ -1869,7 +1861,7 @@ static int rtpcs_930x_sds_cmu_band_get(struct rtpcs_ctrl *ctrl, int sds)
 	rtpcs_sds_write_bits(ctrl, sds + 1, page, 0x1c, 15, 15, 1);
 
 	en = rtpcs_sds_read_bits(ctrl, sds, page, 27, 1, 1);
-	if(!en) { /* Auto mode */
+	if (!en) { /* Auto mode */
 		rtpcs_sds_write(ctrl, sds, 0x1f, 0x02, 31);
 
 		cmu_band = rtpcs_sds_read_bits(ctrl, sds, 0x1f, 0x15, 5, 1);
@@ -1970,7 +1962,6 @@ static void rtpcs_931x_sds_disable(struct rtpcs_ctrl *ctrl, u32 sds)
 static void rtpcs_931x_sds_symerr_clear(struct rtpcs_ctrl *ctrl, u32 sds,
 					phy_interface_t mode)
 {
-
 	switch (mode) {
 	case PHY_INTERFACE_MODE_NA:
 		break;
@@ -1995,11 +1986,9 @@ static void rtpcs_931x_sds_symerr_clear(struct rtpcs_ctrl *ctrl, u32 sds,
 	default:
 		break;
 	}
-
-	return;
 }
 
-__attribute__((unused))
+__always_unused
 static void rtpcs_931x_sds_fiber_disable(struct rtpcs_ctrl *ctrl, u32 sds)
 {
 	u32 v = 0x3F;
@@ -2035,7 +2024,6 @@ static void rtpcs_931x_sds_fiber_mode_set(struct rtpcs_ctrl *ctrl, u32 sds,
 		val = 0x39;
 		break; */
 
-
 	case PHY_INTERFACE_MODE_USXGMII:
 		val = 0x1B;
 		break;
@@ -2045,8 +2033,6 @@ static void rtpcs_931x_sds_fiber_mode_set(struct rtpcs_ctrl *ctrl, u32 sds,
 
 	pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
 	rtpcs_sds_write_bits(ctrl, sds, 0x1F, 0x9, 11, 6, val);
-
-	return;
 }
 
 static int rtpcs_931x_sds_cmu_page_get(phy_interface_t mode)
@@ -2148,9 +2134,8 @@ static void rtpcs_931x_sds_cmu_type_set(struct rtpcs_ctrl *ctrl, u32 sds,
 		pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x28, 0x7));
 		rtpcs_sds_write_bits(ctrl, sds, cmu_page, 0x7, 15, 15, 0);
 		pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x28, 0x7));
-		if (chiptype) {
+		if (chiptype)
 			rtpcs_sds_write_bits(ctrl, sds, cmu_page, 0xd, 14, 14, 0);
-		}
 
 		rtpcs_sds_write_bits(ctrl, evenSds, 0x20, 0x12, 3, 2, 0x3);
 		rtpcs_sds_write_bits(ctrl, evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
@@ -2160,7 +2145,6 @@ static void rtpcs_931x_sds_cmu_type_set(struct rtpcs_ctrl *ctrl, u32 sds,
 	}
 
 	pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtpcs_sds_read(ctrl, sds, 0x28, 0x7));
-	return;
 }
 
 static void rtpcs_931x_sds_rx_reset(struct rtpcs_ctrl *ctrl, u32 sds)
@@ -2251,11 +2235,12 @@ static int rtpcs_931x_sds_cmu_band_get(struct rtpcs_ctrl *ctrl, int sds,
 	return band;
 }
 
-__attribute__((unused))
+__always_unused
 static int rtpcs_931x_sds_link_sts_get(struct rtpcs_ctrl *ctrl, u32 sds)
 {
 	u32 sts, sts1, latch_sts, latch_sts1;
-	if (0){
+
+	if (0) {
 		sts = rtpcs_sds_read_bits(ctrl, sds, 0x41, 29, 8, 0);
 		sts1 = rtpcs_sds_read_bits(ctrl, sds, 0x81, 29, 8, 0);
 		latch_sts = rtpcs_sds_read_bits(ctrl, sds, 0x41, 30, 8, 0);
@@ -2320,7 +2305,6 @@ static sds_config sds_config_10p3125g_cmu_type1[] = {
 	{ 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
 };
 
-__attribute__((unused))
 static int rtpcs_931x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
 				   phy_interface_t mode)
 {
@@ -2402,7 +2386,6 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
 
 			rtpcs_sds_write_bits(ctrl, sds, 0x81, 0x1, 7, 4, 0xf);
 			rtpcs_sds_write_bits(ctrl, sds, 0x81, 0x1, 3, 0, 0xf);
-
 		}
 
 		rtpcs_sds_write_bits(ctrl, sds, 0x40, 0xE, 12, 12, 1);
@@ -2434,7 +2417,6 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
 
 			rtpcs_sds_write_bits(ctrl, sds, 0x6, 0x2, 12, 12, 0);
 		} else {
-
 			rtpcs_sds_write_bits(ctrl, sds, 0x2e, 0xd, 6, 0, 0x0);
 			rtpcs_sds_write_bits(ctrl, sds, 0x2e, 0xd, 7, 7, 0x1);
 
@@ -2507,12 +2489,12 @@ static int rtpcs_931x_setup_serdes(struct rtpcs_ctrl *ctrl, int sds,
 			val = 0xa0000;
 			regmap_write(ctrl->map, RTL93XX_CHIP_INFO, val);
 			regmap_read(ctrl->map, RTL93XX_CHIP_INFO, &val);
+
 			if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
-			{
 				rtpcs_sds_write(ctrl, sds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
-			} else {
+			else
 				rtpcs_sds_write(ctrl, sds, 0x2E, 0x1, board_sds_tx[sds - 2]);
-			}
+
 			val = 0;
 			regmap_write(ctrl->map, RTL93XX_CHIP_INFO, val);
 		}
@@ -2700,7 +2682,7 @@ struct phylink_pcs *rtpcs_create(struct device *dev, struct device_node *np, int
 	if (port < 0 || port > ctrl->cfg->cpu_port)
 		return ERR_PTR(-EINVAL);
 
-	if (sds !=-1 && rtpcs_sds_read(ctrl, sds, 0 , 0) < 0)
+	if (sds !=  -1 && rtpcs_sds_read(ctrl, sds, 0, 0) < 0)
 		return ERR_PTR(-EINVAL);
 
 	link = kzalloc(sizeof(*link), GFP_KERNEL);

target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.c

@@ -205,7 +205,7 @@ static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
 	struct device *dev = &phydev->mdio.dev;
 	int err;
 	struct fw_header *h;
-	uint32_t checksum, my_checksum;
+	u32 checksum, my_checksum;
 
 	err = request_firmware(&fw, name, dev);
 	if (err < 0)
@@ -217,7 +217,7 @@ static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
 		goto out;
 	}
 
-	h = (struct fw_header *) fw->data;
+	h = (struct fw_header *)fw->data;
 	pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
 
 	if (h->magic != 0x83808380) {
@@ -252,7 +252,7 @@ static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool
 	/* select page 0x266 */
 	phy_write_paged(phydev, RTL838X_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
 	/* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
-	phy_write_paged(phydev, RTL838X_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
+	phy_write_paged(phydev, RTL838X_PAGE_RAW, 0x16, (enable ? 0xff00 : 0x00) | mac);
 	/* return to main page 0 */
 	phy_write_paged(phydev, RTL838X_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
 	/* write to 0x0 to register 0x1d on main page 0 */

target/linux/realtek/files-6.12/drivers/net/phy/rtl83xx-phy.h

@@ -1,16 +1,16 @@
-// SPDX-License-Identifier: GPL-2.0-only
+/* SPDX-License-Identifier: GPL-2.0-only */
 
-struct __attribute__ ((__packed__)) part {
+struct __packed part {
-	uint16_t start;
+	u16 start;
-	uint8_t wordsize;
+	u8 wordsize;
-	uint8_t words;
+	u8 words;
 };
 
-struct __attribute__ ((__packed__)) fw_header {
+struct __packed fw_header {
-	uint32_t magic;
+	u32 magic;
-	uint32_t phy;
+	u32 phy;
-	uint32_t checksum;
+	u32 checksum;
-	uint32_t version;
+	u32 version;
 	struct part parts[10];
 };
 

target/linux/realtek/patches-6.12/700-dsa-mdio-increase-max-ports-for-rtl839x-rtl931x.patch

@@ -132,7 +132,7 @@ Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
  	return 0;
 --- a/drivers/net/phy/mdio_bus.c
 +++ b/drivers/net/phy/mdio_bus.c
-@@ -612,7 +612,7 @@ static int mdiobus_scan_bus_c22(struct m
+@@ -615,7 +615,7 @@ static int mdiobus_scan_bus_c22(struct m
  	int i;
  
  	for (i = 0; i < PHY_MAX_ADDR; i++) {
@@ -141,7 +141,7 @@ Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
  			struct phy_device *phydev;
  
  			phydev = mdiobus_scan_c22(bus, i);
-@@ -628,7 +628,7 @@ static int mdiobus_scan_bus_c45(struct m
+@@ -631,7 +631,7 @@ static int mdiobus_scan_bus_c45(struct m
  	int i;
  
  	for (i = 0; i < PHY_MAX_ADDR; i++) {

toolchain/binutils/Config.version

@@ -17,4 +17,4 @@ config BINUTILS_VERSION
 	default "2.42"			if BINUTILS_VERSION_2_42
 	default "2.43.1"		if BINUTILS_VERSION_2_43
 	default "2.44"			if BINUTILS_VERSION_2_44
-	default "2.45"			if BINUTILS_VERSION_2_45
+	default "2.45.1"		if BINUTILS_VERSION_2_45

toolchain/binutils/Makefile

@@ -28,8 +28,8 @@ ifeq ($(PKG_VERSION),2.44)
   PKG_HASH:=ce2017e059d63e67ddb9240e9d4ec49c2893605035cd60e92ad53177f4377237
 endif
 
-ifeq ($(PKG_VERSION),2.45)
+ifeq ($(PKG_VERSION),2.45.1)
-  PKG_HASH:=c50c0e7f9cb188980e2cc97e4537626b1672441815587f1eab69d2a1bfbef5d2
+  PKG_HASH:=5fe101e6fe9d18fdec95962d81ed670fdee5f37e3f48f0bef87bddf862513aa5
 endif
 
 HOST_BUILD_PARALLEL:=1