diff --git a/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-Fix-typo-in-function-names.patch b/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-Fix-typo-in-function-names.patch index b857134e20..9495dd2b10 100644 --- a/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-Fix-typo-in-function-names.patch +++ b/target/linux/rockchip/patches-6.6/032-05-v6.10-phy-rockchip-Fix-typo-in-function-names.patch @@ -17,7 +17,7 @@ Signed-off-by: Vinod Koul --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c -@@ -245,7 +245,7 @@ static int rockchip_combphy_exit(struct +@@ -248,7 +248,7 @@ static int rockchip_combphy_exit(struct return 0; } @@ -26,7 +26,7 @@ Signed-off-by: Vinod Koul .init = rockchip_combphy_init, .exit = rockchip_combphy_exit, .owner = THIS_MODULE, -@@ -352,7 +352,7 @@ static int rockchip_combphy_probe(struct +@@ -364,7 +364,7 @@ static int rockchip_combphy_probe(struct return ret; } @@ -37,7 +37,7 @@ Signed-off-by: Vinod Koul return PTR_ERR(priv->phy); --- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c +++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -187,7 +187,7 @@ static const struct rockchip_p3phy_ops r +@@ -182,7 +182,7 @@ static const struct rockchip_p3phy_ops r .phy_init = rockchip_p3phy_rk3588_init, }; @@ -46,7 +46,7 @@ Signed-off-by: Vinod Koul { struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); int ret; -@@ -210,7 +210,7 @@ static int rochchip_p3phy_init(struct ph +@@ -205,7 +205,7 @@ static int rochchip_p3phy_init(struct ph return ret; } @@ -55,7 +55,7 @@ Signed-off-by: Vinod Koul { struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy); -@@ -219,9 +219,9 @@ static int rochchip_p3phy_exit(struct ph +@@ -214,9 +214,9 @@ static int rochchip_p3phy_exit(struct ph return 0; } @@ -68,7 +68,7 @@ Signed-off-by: Vinod Koul .set_mode = rockchip_p3phy_set_mode, .owner = THIS_MODULE, }; -@@ -280,7 +280,7 @@ static int rockchip_p3phy_probe(struct p +@@ -275,7 +275,7 @@ static int rockchip_p3phy_probe(struct p return priv->num_lanes; } diff --git a/target/linux/rockchip/patches-6.6/032-06-v6.10-phy-rockchip-snps-pcie3-fix-bifurcation-on-rk3588.patch b/target/linux/rockchip/patches-6.6/032-06-v6.10-phy-rockchip-snps-pcie3-fix-bifurcation-on-rk3588.patch deleted file mode 100644 index acf3ab3df1..0000000000 --- a/target/linux/rockchip/patches-6.6/032-06-v6.10-phy-rockchip-snps-pcie3-fix-bifurcation-on-rk3588.patch +++ /dev/null @@ -1,95 +0,0 @@ -From f8020dfb311d2b6cf657668792aaa5fa8863a7dd Mon Sep 17 00:00:00 2001 -From: Michal Tomek -Date: Thu, 4 Apr 2024 19:11:26 +0200 -Subject: [PATCH] phy: rockchip-snps-pcie3: fix bifurcation on rk3588 - -So far all RK3588 boards use fully aggregated PCIe. CM3588 is one -of the few boards using this feature and apparently it is broken. - -The PHY offers the following mapping options: - - port 0 lane 0 - always mapped to controller 0 (4L) - port 0 lane 1 - to controller 0 or 2 (1L0) - port 1 lane 0 - to controller 0 or 1 (2L) - port 1 lane 1 - to controller 0, 1 or 3 (1L1) - -The data-lanes DT property maps these as follows: - - 0 = no controller (unsupported by the HW) - 1 = 4L - 2 = 2L - 3 = 1L0 - 4 = 1L1 - -That allows the following configurations with first column being the -mainline data-lane mapping, second column being the downstream name, -third column being PCIE3PHY_GRF_CMN_CON0 and PHP_GRF_PCIESEL register -values and final column being the user visible lane setup: - - <1 1 1 1> = AGGREG = [4 0] = x4 (aggregation) - <1 1 2 2> = NANBNB = [0 0] = x2 x2 (no bif.) - <1 3 2 2> = NANBBI = [1 1] = x2 x1x1 (bif. of port 0) - <1 1 2 4> = NABINB = [2 2] = x1x1 x2 (bif. of port 1) - <1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports) - -The driver currently does not program PHP_GRF_PCIESEL correctly, which -is fixed by this patch. As a side-effect the new logic is much simpler -than the old logic. - -Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3") -Signed-off-by: Michal Tomek -Signed-off-by: Sebastian Reichel -Acked-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-1-9907136eeafd@kernel.org -Signed-off-by: Vinod Koul ---- - .../phy/rockchip/phy-rockchip-snps-pcie3.c | 24 +++++++------------ - 1 file changed, 8 insertions(+), 16 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -132,7 +132,7 @@ static const struct rockchip_p3phy_ops r - static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv) - { - u32 reg = 0; -- u8 mode = 0; -+ u8 mode = RK3588_LANE_AGGREGATION; /* default */ - int ret; - - /* Deassert PCIe PMA output clamp mode */ -@@ -140,28 +140,20 @@ static int rockchip_p3phy_rk3588_init(st - - /* Set bifurcation if needed */ - for (int i = 0; i < priv->num_lanes; i++) { -- if (!priv->lanes[i]) -- mode |= (BIT(i) << 3); -- - if (priv->lanes[i] > 1) -- mode |= (BIT(i) >> 1); -- } -- -- if (!mode) -- reg = RK3588_LANE_AGGREGATION; -- else { -- if (mode & (BIT(0) | BIT(1))) -- reg |= RK3588_BIFURCATION_LANE_0_1; -- -- if (mode & (BIT(2) | BIT(3))) -- reg |= RK3588_BIFURCATION_LANE_2_3; -+ mode &= ~RK3588_LANE_AGGREGATION; -+ if (priv->lanes[i] == 3) -+ mode |= RK3588_BIFURCATION_LANE_0_1; -+ if (priv->lanes[i] == 4) -+ mode |= RK3588_BIFURCATION_LANE_2_3; - } - -+ reg = mode; - regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); - - /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ - if (!IS_ERR(priv->pipe_grf)) { -- reg = (mode & (BIT(6) | BIT(7))) >> 6; -+ reg = mode & 3; - if (reg) - regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, - (reg << 16) | reg); diff --git a/target/linux/rockchip/patches-6.6/032-07-v6.10-phy-rockchip-snps-pcie3-fix-clearing-PHP_GRF_PCIESEL_CON.patch b/target/linux/rockchip/patches-6.6/032-07-v6.10-phy-rockchip-snps-pcie3-fix-clearing-PHP_GRF_PCIESEL_CON.patch deleted file mode 100644 index 0ef1395f46..0000000000 --- a/target/linux/rockchip/patches-6.6/032-07-v6.10-phy-rockchip-snps-pcie3-fix-clearing-PHP_GRF_PCIESEL_CON.patch +++ /dev/null @@ -1,52 +0,0 @@ -From 55491a5fa163bf15158f34f3650b3985f25622b9 Mon Sep 17 00:00:00 2001 -From: Sebastian Reichel -Date: Thu, 4 Apr 2024 19:11:27 +0200 -Subject: [PATCH] phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON - bits - -Currently the PCIe v3 PHY driver only sets the pcie1ln_sel bits, but -does not clear them because of an incorrect write mask. This fixes up -the issue by using a newly introduced constant for the write mask. - -While at it also introduces a proper GENMASK based constant for the -PCIE30_PHY_MODE. - -Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3") -Signed-off-by: Sebastian Reichel -Reviewed-by: Heiko Stuebner -Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-2-9907136eeafd@kernel.org -Signed-off-by: Vinod Koul ---- - drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 9 ++++++--- - 1 file changed, 6 insertions(+), 3 deletions(-) - ---- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c -@@ -40,6 +40,8 @@ - #define RK3588_BIFURCATION_LANE_0_1 BIT(0) - #define RK3588_BIFURCATION_LANE_2_3 BIT(1) - #define RK3588_LANE_AGGREGATION BIT(2) -+#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16) -+#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16) - - struct rockchip_p3phy_ops; - -@@ -149,14 +151,15 @@ static int rockchip_p3phy_rk3588_init(st - } - - reg = mode; -- regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg); -+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, -+ RK3588_PCIE30_PHY_MODE_EN | reg); - - /* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */ - if (!IS_ERR(priv->pipe_grf)) { -- reg = mode & 3; -+ reg = mode & (RK3588_BIFURCATION_LANE_0_1 | RK3588_BIFURCATION_LANE_2_3); - if (reg) - regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON, -- (reg << 16) | reg); -+ RK3588_PCIE1LN_SEL_EN | reg); - } - - reset_control_deassert(priv->p30phy); diff --git a/target/linux/rockchip/patches-6.6/034-13-v6.8-drm-gpuvm-add-an-abstraction-for-a-VM-BO-combination.patch b/target/linux/rockchip/patches-6.6/034-13-v6.8-drm-gpuvm-add-an-abstraction-for-a-VM-BO-combination.patch index b5151bf88b..37aa2f633d 100644 --- a/target/linux/rockchip/patches-6.6/034-13-v6.8-drm-gpuvm-add-an-abstraction-for-a-VM-BO-combination.patch +++ b/target/linux/rockchip/patches-6.6/034-13-v6.8-drm-gpuvm-add-an-abstraction-for-a-VM-BO-combination.patch @@ -715,7 +715,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231108001259.15123-11-dakr --- a/include/drm/drm_gem.h +++ b/include/drm/drm_gem.h -@@ -571,7 +571,7 @@ int drm_gem_evict(struct drm_gem_object +@@ -584,7 +584,7 @@ static inline bool drm_gem_object_is_sha * drm_gem_gpuva_init() - initialize the gpuva list of a GEM object * @obj: the &drm_gem_object * @@ -724,7 +724,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231108001259.15123-11-dakr * * Calling this function is only necessary for drivers intending to support the * &drm_driver_feature DRIVER_GEM_GPUVA. -@@ -584,28 +584,28 @@ static inline void drm_gem_gpuva_init(st +@@ -597,28 +597,28 @@ static inline void drm_gem_gpuva_init(st } /** diff --git a/target/linux/rockchip/patches-6.6/701-apply-rockchip-3588001-erratum-workaround-to-rk356x-as-we.patch b/target/linux/rockchip/patches-6.6/701-apply-rockchip-3588001-erratum-workaround-to-rk356x-as-we.patch index dc8fc4b3f3..4005d502a5 100644 --- a/target/linux/rockchip/patches-6.6/701-apply-rockchip-3588001-erratum-workaround-to-rk356x-as-we.patch +++ b/target/linux/rockchip/patches-6.6/701-apply-rockchip-3588001-erratum-workaround-to-rk356x-as-we.patch @@ -1,6 +1,6 @@ --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c -@@ -4761,7 +4761,9 @@ static bool __maybe_unused its_enable_rk +@@ -4756,7 +4756,9 @@ static bool __maybe_unused its_enable_rk { struct its_node *its = data; diff --git a/target/linux/rockchip/patches-6.6/702-irqchip-gic-v3-its-add-GFP_DMA32-flag-for-memory-allocate.patch b/target/linux/rockchip/patches-6.6/702-irqchip-gic-v3-its-add-GFP_DMA32-flag-for-memory-allocate.patch index c18a4075a5..655a3f99ad 100644 --- a/target/linux/rockchip/patches-6.6/702-irqchip-gic-v3-its-add-GFP_DMA32-flag-for-memory-allocate.patch +++ b/target/linux/rockchip/patches-6.6/702-irqchip-gic-v3-its-add-GFP_DMA32-flag-for-memory-allocate.patch @@ -83,7 +83,7 @@ Signed-off-by: XiaoDong Huang if (alloc_lpis) { lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis); if (lpi_map) -@@ -5096,6 +5112,7 @@ static int __init its_probe_one(struct i +@@ -5091,6 +5107,7 @@ static int __init its_probe_one(struct i struct page *page; u32 ctlr; int err; @@ -91,7 +91,7 @@ Signed-off-by: XiaoDong Huang its_enable_quirks(its); -@@ -5129,7 +5146,10 @@ static int __init its_probe_one(struct i +@@ -5124,7 +5141,10 @@ static int __init its_probe_one(struct i } } diff --git a/target/linux/sunxi/cortexa53/config-6.6 b/target/linux/sunxi/cortexa53/config-6.6 index 948faf82ef..747e929edf 100644 --- a/target/linux/sunxi/cortexa53/config-6.6 +++ b/target/linux/sunxi/cortexa53/config-6.6 @@ -24,6 +24,7 @@ CONFIG_ARM64_VA_BITS=39 CONFIG_ARM64_VA_BITS_39=y CONFIG_ARM_AMBA=y CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y +# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set CONFIG_ARM_GIC_V3=y CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_SMCCC_SOC_ID=y