Furong Xu 335c1e7cfd mediatek: enable sel_clk for spi-mt65xx ... Without explicitly enabling sel_clk, clk_disable_unused() will disable it when boot is done, causing CPU hang on SPI1 register access on MT7986. Explicitly enable sel_clk to make SPI1 functional. Signed-off-by: Furong Xu <xfr@outlook.com> Signed-off-by: Chuanhong Guo <gch981213@gmail.com>		2022-12-16 21:42:02 +08:00
..
base-files
dts	mediatek: also move &slot0 from dtsi down to board dts	2022-12-07 01:45:14 +00:00
files/drivers/net/phy
files-5.15
filogic
image	mediatek: add support for reyee AX3200-E5	2022-12-06 12:43:15 +00:00
mt7622	mediatek: add support for reyee AX3200-E5	2022-12-06 12:43:15 +00:00
mt7623
mt7629
patches-5.15	mediatek: enable sel_clk for spi-mt65xx	2022-12-16 21:42:02 +08:00
Makefile
modules.mk