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Felix Fietkau 0b296d3808 ar71xx: use correct PLL configuration register bitmask for QCA956x SoC. 
Incorrect value causes clock inaccuracy as huge as 1/60.

Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 47363
2015-11-02 18:20:51 +00:00
..
imagebuilder
linux ar71xx: use correct PLL configuration register bitmask for QCA956x SoC. 2015-11-02 18:20:51 +00:00
sdk
toolchain
Config.in
Makefile