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1949fb996a
This series improve network reliability. Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Link: https://github.com/openwrt/openwrt/pull/20295 Signed-off-by: Robert Marko <robimarko@gmail.com>
108 lines
3.7 KiB
Diff
108 lines
3.7 KiB
Diff
From 8fce1cfe775e1f3b5d7cecb8bdcc8271bf9f799c Mon Sep 17 00:00:00 2001
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From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Date: Wed, 9 Jul 2025 12:28:08 +0300
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Subject: [PATCH 2/5] drivers/net/airoha_eth: fix packet transmission errors
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The dma_map_single() function calls one of the functions
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* invalidate_dcache_range(),
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* flush_dcache_range().
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Both of them expect that 'vaddr' is aligned to the ARCH_DMA_MINALIGN
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boundary. Unfortunately, RX/TX descriptors are 32-byte long. Thus they
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might not be aligned to the ARCH_DMA_MINALIGN boundary. Data flushing
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(or invalidating) might do nothing in this case.
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The same applies to dma_unmap_single() function.
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In the TX path case the issue might prevent package transmission (filled
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TX descriptor was not flushed).
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To fix an issue a special wrappers for
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* dma_map_single(),
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* dma_unmap_single()
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functions were created. The patch fix flushing/invalidatiog for the
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RX path as well.
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The bug appears on 32-bit airoha platform, but should be present on
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64-bit as well.
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The code was tested both on 32-bit and 64-bit airoha boards.
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Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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---
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drivers/net/airoha_eth.c | 33 +++++++++++++++++++++++++++------
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1 file changed, 27 insertions(+), 6 deletions(-)
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diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c
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index db34ec48c81..aae6922f3c7 100644
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--- a/drivers/net/airoha_eth.c
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+++ b/drivers/net/airoha_eth.c
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@@ -397,6 +397,27 @@ static u32 airoha_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
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#define airoha_switch_rmw(eth, offset, mask, val) \
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airoha_rmw((eth)->switch_regs, (offset), (mask), (val))
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+static inline dma_addr_t dma_map_unaligned(void *vaddr, size_t len,
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+ enum dma_data_direction dir)
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+{
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+ uintptr_t start, end;
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+
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+ start = ALIGN_DOWN((uintptr_t)vaddr, ARCH_DMA_MINALIGN);
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+ end = ALIGN((uintptr_t)(vaddr + len), ARCH_DMA_MINALIGN);
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+
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+ return dma_map_single((void *)start, end - start, dir);
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+}
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+
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+static inline void dma_unmap_unaligned(dma_addr_t addr, size_t len,
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+ enum dma_data_direction dir)
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+{
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+ uintptr_t start, end;
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+
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+ start = ALIGN_DOWN((uintptr_t)addr, ARCH_DMA_MINALIGN);
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+ end = ALIGN((uintptr_t)(addr + len), ARCH_DMA_MINALIGN);
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+ dma_unmap_single(start, end - start, dir);
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+}
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+
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static void airoha_fe_maccr_init(struct airoha_eth *eth)
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{
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int p;
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@@ -434,7 +455,7 @@ static void airoha_qdma_reset_rx_desc(struct airoha_queue *q, int index,
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val = FIELD_PREP(QDMA_DESC_LEN_MASK, PKTSIZE_ALIGN);
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WRITE_ONCE(desc->ctrl, cpu_to_le32(val));
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- dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE);
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+ dma_map_unaligned(desc, sizeof(*desc), DMA_TO_DEVICE);
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}
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static void airoha_qdma_init_rx_desc(struct airoha_queue *q)
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@@ -916,14 +937,14 @@ static int airoha_eth_send(struct udevice *dev, void *packet, int length)
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WRITE_ONCE(desc->msg1, cpu_to_le32(msg1));
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WRITE_ONCE(desc->msg2, cpu_to_le32(0xffff));
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- dma_map_single(desc, sizeof(*desc), DMA_TO_DEVICE);
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+ dma_map_unaligned(desc, sizeof(*desc), DMA_TO_DEVICE);
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airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
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FIELD_PREP(TX_RING_CPU_IDX_MASK, index));
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for (i = 0; i < 100; i++) {
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- dma_unmap_single(virt_to_phys(desc), sizeof(*desc),
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- DMA_FROM_DEVICE);
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+ dma_unmap_unaligned(virt_to_phys(desc), sizeof(*desc),
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+ DMA_FROM_DEVICE);
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if (desc->ctrl & QDMA_DESC_DONE_MASK)
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break;
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@@ -954,8 +975,8 @@ static int airoha_eth_recv(struct udevice *dev, int flags, uchar **packetp)
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q = &qdma->q_rx[qid];
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desc = &q->desc[q->head];
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- dma_unmap_single(virt_to_phys(desc), sizeof(*desc),
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- DMA_FROM_DEVICE);
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+ dma_unmap_unaligned(virt_to_phys(desc), sizeof(*desc),
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+ DMA_FROM_DEVICE);
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if (!(desc->ctrl & QDMA_DESC_DONE_MASK))
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return -EAGAIN;
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--
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2.51.0
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