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https://github.com/LiBwrt-op/openwrt-6.x.git
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b8742b1ae0
Changes: * removed upstreamed patches, * rebased local patches, * fix en7581_evb/an7583_evb booting issues * enable position independent code Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu> Link: https://github.com/openwrt/openwrt/pull/20400 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
90 lines
2.9 KiB
Diff
90 lines
2.9 KiB
Diff
From 2ebbccfa053993d0fe90bee523020a8f796e8988 Mon Sep 17 00:00:00 2001
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From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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Date: Sun, 8 Jun 2025 05:30:22 +0300
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Subject: [PATCH 5/5] spi: airoha: support of dualio/quadio flash reading
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commands
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Airoha snfi spi controller supports acceleration of DUAL/QUAD
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operations, but does not supports DUAL_IO/QUAD_IO operations.
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Luckily DUAL/QUAD operations do the same as DUAL_IO/QUAD_IO ones,
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so we can issue corresponding DUAL/QUAD operation instead of
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DUAL_IO/QUAD_IO one.
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Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
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---
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drivers/spi/airoha_snfi_spi.c | 27 +++++++++++++++++++++------
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1 file changed, 21 insertions(+), 6 deletions(-)
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--- a/drivers/spi/airoha_snfi_spi.c
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+++ b/drivers/spi/airoha_snfi_spi.c
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@@ -141,6 +141,7 @@
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#define SPI_NFI_CUS_SEC_SIZE_EN BIT(16)
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#define REG_SPI_NFI_RD_CTL2 0x0510
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+#define SPI_NFI_DATA_READ_CMD GENMASK(7, 0)
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#define REG_SPI_NFI_RD_CTL3 0x0514
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@@ -175,7 +176,9 @@
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#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE 0x03
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#define SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST 0x0b
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#define SPI_NAND_OP_READ_FROM_CACHE_DUAL 0x3b
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+#define SPI_NAND_OP_READ_FROM_CACHE_DUALIO 0xbb
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#define SPI_NAND_OP_READ_FROM_CACHE_QUAD 0x6b
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+#define SPI_NAND_OP_READ_FROM_CACHE_QUADIO 0xeb
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#define SPI_NAND_OP_WRITE_ENABLE 0x06
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#define SPI_NAND_OP_WRITE_DISABLE 0x04
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#define SPI_NAND_OP_PROGRAM_LOAD_SINGLE 0x02
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@@ -639,25 +642,37 @@ static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
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static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
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u64 offs, size_t len, void *buf)
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{
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- struct spi_mem_op *op = &desc->info.op_tmpl;
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struct spi_slave *slave = desc->slave;
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struct udevice *bus = slave->dev->parent;
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struct airoha_snand_priv *priv = dev_get_priv(bus);
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u8 *txrx_buf = priv->txrx_buf;
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dma_addr_t dma_addr;
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- u32 val, rd_mode;
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+ u32 val, rd_mode, opcode;
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int err;
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- switch (op->cmd.opcode) {
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+ /*
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+ * DUALIO and QUADIO opcodes are not supported by the spi controller,
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+ * replace them with supported opcodes.
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+ */
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+ opcode = desc->info.op_tmpl.cmd.opcode;
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+ switch (opcode) {
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+ case SPI_NAND_OP_READ_FROM_CACHE_SINGLE:
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+ case SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST:
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+ rd_mode = 0;
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+ break;
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case SPI_NAND_OP_READ_FROM_CACHE_DUAL:
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+ case SPI_NAND_OP_READ_FROM_CACHE_DUALIO:
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+ opcode = SPI_NAND_OP_READ_FROM_CACHE_DUAL;
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rd_mode = 1;
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break;
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case SPI_NAND_OP_READ_FROM_CACHE_QUAD:
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+ case SPI_NAND_OP_READ_FROM_CACHE_QUADIO:
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+ opcode = SPI_NAND_OP_READ_FROM_CACHE_QUAD;
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rd_mode = 2;
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break;
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default:
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- rd_mode = 0;
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- break;
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+ /* unknown opcode */
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+ return -EOPNOTSUPP;
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}
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err = airoha_snand_set_mode(priv, SPI_MODE_DMA);
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@@ -688,7 +703,7 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
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/* set read command */
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err = regmap_write(priv->regmap_nfi, REG_SPI_NFI_RD_CTL2,
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- op->cmd.opcode);
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+ FIELD_PREP(SPI_NFI_DATA_READ_CMD, opcode));
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if (err)
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goto error_dma_unmap;
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