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https://github.com/LiBwrt-op/openwrt-6.x.git
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919e0001b4
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.12.56 Removed upstreamed: - airoha/patches-6.12/028-v6.13-spi-airoha-do-not-keep-tx-rx-dma-buffer-always-mappe.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=ad00df9ee321e87639a740e6e372f11bfe5af52c - airoha/patches-6.12/029-01-spi-airoha-return-an-error-for-continuous-mode-di.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/spi?h=v6.12.56&id=f5dc5baa5b04ceb0fca2460bc2863921f0e7ede5 - airoha/patches-6.12/029-03-spi-airoha-add-support-of-dual-quad-wires-spi-mod.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=182221d35c1427630ea6d9de9953c2280848c851 - airoha/patches-6.12/029-05-spi-airoha-switch-back-to-non-dma-mode-in-the-cas.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=8063828625359826316c5a1885e9ea341bbdb1b3 - airoha/patches-6.12/029-06-spi-airoha-fix-reading-writing-of-flashes-with-mo.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=4e9a2d592d91b902f918158c1049eef19f9cce90 - mediatek/patches-6.12/810-tty-serial-8250_mtk-enable-baud-clock.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=7cbf5ed24a26d4d80dcc19eb2259fdb9b179d5cf All other patches automatically rebased. Build system: x86/64 Build-tested: mediatek/filogic Run-tested: mediatek/filogic Signed-off-by: Edoardo Pinci <epinci@outlook.com> Link: https://github.com/openwrt/openwrt/pull/20589 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
240 lines
6.4 KiB
Diff
240 lines
6.4 KiB
Diff
From d1b83761cef13adca83c97dea088e883862a721d Mon Sep 17 00:00:00 2001
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From: Dave Stevenson <dave.stevenson@raspberrypi.com>
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Date: Fri, 21 Jun 2024 16:59:51 +0100
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Subject: [PATCH] arm64: dts: broadcom: Add display pipeline support to BCM2712
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Adds the HVS and associated hardware blocks to support the HDMI
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and writeback connectors on BCM2712 / Pi5.
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Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
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---
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.../boot/dts/broadcom/bcm2712-rpi-5-b.dts | 14 ++
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arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 189 ++++++++++++++++++
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2 files changed, 203 insertions(+)
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--- a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
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+++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts
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@@ -732,5 +732,19 @@ spi10_cs_pins: &spi10_cs_gpio1 {};
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firmware = <&firmware>;
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#power-domain-cells = <1>;
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};
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+};
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+
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+&hvs {
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+ clocks = <&firmware_clocks 4>, <&firmware_clocks 16>;
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+ clock-names = "core", "disp";
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+};
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+
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+&hdmi0 {
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+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 0>, <&clk_27MHz>;
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+ clock-names = "hdmi", "bvb", "audio", "cec";
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+};
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+&hdmi1 {
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+ clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
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+ clock-names = "hdmi", "bvb", "audio", "cec";
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};
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--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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@@ -268,6 +268,172 @@
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IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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};
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+
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+ aon_intr: interrupt-controller@7d510600 {
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+ compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
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+ reg = <0x7d510600 0x30>;
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+ interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ };
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+
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+ pixelvalve0: pixelvalve@7c410000 {
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+ compatible = "brcm,bcm2712-pixelvalve0";
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+ reg = <0x7c410000 0x100>;
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+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ pixelvalve1: pixelvalve@7c411000 {
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+ compatible = "brcm,bcm2712-pixelvalve1";
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+ reg = <0x7c411000 0x100>;
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+ interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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+ };
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+
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+ mop: mop@7c500000 {
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+ compatible = "brcm,bcm2712-mop";
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+ reg = <0x7c500000 0x28>;
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+ interrupt-parent = <&disp_intr>;
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+ interrupts = <1>;
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+ };
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+
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+ moplet: moplet@7c501000 {
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+ compatible = "brcm,bcm2712-moplet";
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+ reg = <0x7c501000 0x20>;
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+ interrupt-parent = <&disp_intr>;
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+ interrupts = <0>;
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+ };
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+
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+ disp_intr: interrupt-controller@7c502000 {
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+ compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
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+ reg = <0x7c502000 0x30>;
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+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ };
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+
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+ dvp: clock@7c700000 {
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+ compatible = "brcm,brcm2711-dvp";
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+ reg = <0x7c700000 0x10>;
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+ clocks = <&clk_108MHz>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ ddc0: i2c@7d508200 {
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+ compatible = "brcm,brcmstb-i2c";
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+ reg = <0x7d508200 0x58>;
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+ interrupt-parent = <&bsc_irq>;
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+ interrupts = <1>;
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+ clock-frequency = <97500>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ ddc1: i2c@7d508280 {
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+ compatible = "brcm,brcmstb-i2c";
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+ reg = <0x7d508280 0x58>;
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+ interrupt-parent = <&bsc_irq>;
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+ interrupts = <2>;
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+ clock-frequency = <97500>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ bsc_irq: intc@7d508380 {
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+ compatible = "brcm,bcm7271-l2-intc";
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+ reg = <0x7d508380 0x10>;
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+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ };
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+
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+ main_irq: intc@7d508400 {
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+ compatible = "brcm,bcm7271-l2-intc";
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+ reg = <0x7d508400 0x10>;
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+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-controller;
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+ #interrupt-cells = <1>;
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+ };
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+
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+ hdmi0: hdmi@7ef00700 {
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+ compatible = "brcm,bcm2712-hdmi0";
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+ reg = <0x7c701400 0x300>,
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+ <0x7c701000 0x200>,
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+ <0x7c701d00 0x300>,
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+ <0x7c702000 0x80>,
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+ <0x7c703800 0x200>,
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+ <0x7c704000 0x800>,
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+ <0x7c700100 0x80>,
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+ <0x7d510800 0x100>,
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+ <0x7c720000 0x100>;
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+ reg-names = "hdmi",
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+ "dvp",
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+ "phy",
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+ "rm",
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+ "packet",
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+ "metadata",
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+ "csc",
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+ "cec",
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+ "hd";
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+ resets = <&dvp 1>;
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+ interrupt-parent = <&aon_intr>;
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+ interrupts = <1>, <2>, <3>,
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+ <7>, <8>;
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+ interrupt-names = "cec-tx", "cec-rx", "cec-low",
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+ "hpd-connected", "hpd-removed";
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+ ddc = <&ddc0>;
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+ };
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+
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+ hdmi1: hdmi@7ef05700 {
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+ compatible = "brcm,bcm2712-hdmi1";
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+ reg = <0x7c706400 0x300>,
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+ <0x7c706000 0x200>,
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+ <0x7c706d00 0x300>,
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+ <0x7c707000 0x80>,
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+ <0x7c708800 0x200>,
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+ <0x7c709000 0x800>,
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+ <0x7c700180 0x80>,
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+ <0x7d511000 0x100>,
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+ <0x7c720000 0x100>;
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+ reg-names = "hdmi",
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+ "dvp",
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+ "phy",
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+ "rm",
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+ "packet",
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+ "metadata",
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+ "csc",
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+ "cec",
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+ "hd";
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+ resets = <&dvp 2>;
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+ interrupt-parent = <&aon_intr>;
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+ interrupts = <11>, <12>, <13>,
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+ <14>, <15>;
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+ interrupt-names = "cec-tx", "cec-rx", "cec-low",
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+ "hpd-connected", "hpd-removed";
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+ ddc = <&ddc1>;
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+ };
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+ };
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+
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+ axi: axi {
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+ compatible = "simple-bus";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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+ <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
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+ <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
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+ <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
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+ <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
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+
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+ dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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+ <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
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+ <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
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+ <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
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+ <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
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+
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+ vc4: gpu {
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+ compatible = "brcm,bcm2712-vc6";
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+ };
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};
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timer {
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@@ -283,4 +449,27 @@
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<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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+
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+ clk_27MHz: clk-27M {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <27000000>;
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+ clock-output-names = "27MHz-clock";
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+ };
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+
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+ clk_108MHz: clk-108M {
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+ #clock-cells = <0>;
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+ compatible = "fixed-clock";
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+ clock-frequency = <108000000>;
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+ clock-output-names = "108MHz-clock";
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+ };
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+
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+ hvs: hvs@107c580000 {
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+ compatible = "brcm,bcm2712-hvs";
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+ reg = <0x10 0x7c580000 0x0 0x1a000>;
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+ interrupt-parent = <&disp_intr>;
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+ interrupts = <2>, <9>, <16>;
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+ interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";
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+ //iommus = <&iommu4>;
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+ };
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};
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