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https://github.com/LiBwrt-op/openwrt-6.x.git
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919e0001b4
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.12.56 Removed upstreamed: - airoha/patches-6.12/028-v6.13-spi-airoha-do-not-keep-tx-rx-dma-buffer-always-mappe.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=ad00df9ee321e87639a740e6e372f11bfe5af52c - airoha/patches-6.12/029-01-spi-airoha-return-an-error-for-continuous-mode-di.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/spi?h=v6.12.56&id=f5dc5baa5b04ceb0fca2460bc2863921f0e7ede5 - airoha/patches-6.12/029-03-spi-airoha-add-support-of-dual-quad-wires-spi-mod.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=182221d35c1427630ea6d9de9953c2280848c851 - airoha/patches-6.12/029-05-spi-airoha-switch-back-to-non-dma-mode-in-the-cas.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=8063828625359826316c5a1885e9ea341bbdb1b3 - airoha/patches-6.12/029-06-spi-airoha-fix-reading-writing-of-flashes-with-mo.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=4e9a2d592d91b902f918158c1049eef19f9cce90 - mediatek/patches-6.12/810-tty-serial-8250_mtk-enable-baud-clock.patch https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.12.56&id=7cbf5ed24a26d4d80dcc19eb2259fdb9b179d5cf All other patches automatically rebased. Build system: x86/64 Build-tested: mediatek/filogic Run-tested: mediatek/filogic Signed-off-by: Edoardo Pinci <epinci@outlook.com> Link: https://github.com/openwrt/openwrt/pull/20589 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
184 lines
6.0 KiB
Diff
184 lines
6.0 KiB
Diff
From 6c62e56fc0d4e9ac273cee980847a227b77851b6 Mon Sep 17 00:00:00 2001
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From: Stanimir Varbanov <svarbanov@suse.de>
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Date: Mon, 20 Jan 2025 15:01:18 +0200
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Subject: [PATCH] arm64: dts: broadcom: bcm2712: Add PCIe DT nodes
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Add PCIe devicetree nodes, plus needed reset and mip MSI-X
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controllers.
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Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
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---
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arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 147 ++++++++++++++++++++++
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1 file changed, 147 insertions(+)
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--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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@@ -192,6 +192,12 @@
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#address-cells = <1>;
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#size-cells = <1>;
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+ pcie_rescal: reset-controller@119500 {
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+ compatible = "brcm,bcm7216-pcie-sata-rescal";
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+ reg = <0x00119500 0x10>;
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+ #reset-cells = <0>;
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+ };
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+
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sdio1: mmc@fff000 {
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compatible = "brcm,bcm2712-sdhci",
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"brcm,sdhci-brcmstb";
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@@ -204,6 +210,12 @@
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mmc-ddr-3_3v;
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};
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+ bcm_reset: reset-controller@1504318 {
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+ compatible = "brcm,brcmstb-reset";
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+ reg = <0x01504318 0x30>;
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+ #reset-cells = <1>;
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+ };
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+
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system_timer: timer@7c003000 {
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compatible = "brcm,bcm2835-system-timer";
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reg = <0x7c003000 0x1000>;
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@@ -434,6 +446,141 @@
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vc4: gpu {
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compatible = "brcm,bcm2712-vc6";
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};
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+
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+ pcie0: pcie@1000100000 {
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+ compatible = "brcm,bcm2712-pcie";
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+ reg = <0x10 0x00100000 0x00 0x9310>;
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+ device_type = "pci";
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+ linux,pci-domain = <0>;
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+ max-link-speed = <2>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #interrupt-cells = <1>;
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+ #size-cells = <2>;
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+ interrupt-parent = <&gicv2>;
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+ interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie", "msi";
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+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&pcie_rescal>, <&bcm_reset 42>;
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+ reset-names = "rescal", "bridge";
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+ msi-controller;
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+ msi-parent = <&pcie0>;
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+
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+ ranges =
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+ /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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+ <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>,
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+ /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
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+ <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>;
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+
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+ dma-ranges =
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+ /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
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+ <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
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+
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+ status = "disabled";
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+ };
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+
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+ pcie1: pcie@1000110000 {
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+ compatible = "brcm,bcm2712-pcie";
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+ reg = <0x10 0x00110000 0x00 0x9310>;
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+ device_type = "pci";
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+ linux,pci-domain = <1>;
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+ max-link-speed = <2>;
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+ num-lanes = <1>;
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+ #address-cells = <3>;
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+ #interrupt-cells = <1>;
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+ #size-cells = <2>;
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+ interrupt-parent = <&gicv2>;
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+ interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie", "msi";
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+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&pcie_rescal>, <&bcm_reset 43>;
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+ reset-names = "rescal", "bridge";
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+ msi-controller;
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+ msi-parent = <&mip1>;
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+
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+ ranges =
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+ /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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+ <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>,
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+ /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
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+ <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>;
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+
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+ dma-ranges =
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+ /* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */
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+ <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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+ /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */
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+ <0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>;
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+
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+ status = "disabled";
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+ };
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+
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+ pcie2: pcie@1000120000 {
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+ compatible = "brcm,bcm2712-pcie";
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+ reg = <0x10 0x00120000 0x00 0x9310>;
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+ device_type = "pci";
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+ linux,pci-domain = <2>;
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+ max-link-speed = <2>;
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+ num-lanes = <4>;
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+ #address-cells = <3>;
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+ #interrupt-cells = <1>;
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+ #size-cells = <2>;
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+ interrupt-parent = <&gicv2>;
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+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie", "msi";
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+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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+ interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
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+ <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
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+ resets = <&pcie_rescal>, <&bcm_reset 44>;
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+ reset-names = "rescal", "bridge";
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+ msi-controller;
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+ msi-parent = <&mip0>;
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+
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+ ranges =
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+ /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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+ <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>,
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+ /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
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+ <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>;
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+
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+ dma-ranges =
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+ /* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
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+ <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>,
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+ /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
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+ <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
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+ /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */
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+ <0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>;
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+
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+ status = "disabled";
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+ };
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+
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+ mip0: msi-controller@1000130000 {
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+ compatible = "brcm,bcm2712-mip";
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+ reg = <0x10 0x00130000 0x00 0xc0>,
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+ <0xff 0xfffff000 0x00 0x1000>;
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+ msi-controller;
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+ msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
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+ brcm,msi-offset = <0>;
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+ };
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+
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+ mip1: msi-controller@1000131000 {
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+ compatible = "brcm,bcm2712-mip";
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+ reg = <0x10 0x00131000 0x00 0xc0>,
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+ <0xff 0xfffff000 0x00 0x1000>;
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+ msi-controller;
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+ msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
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+ brcm,msi-offset = <8>;
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+ };
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};
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timer {
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