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3a35a2cff1
Backport core dts updates for rk3576. Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org> Link: https://github.com/openwrt/openwrt/pull/20041 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
172 lines
5.5 KiB
Diff
172 lines
5.5 KiB
Diff
From 23ec57a32da448cb3415d6abad3457b14c69af25 Mon Sep 17 00:00:00 2001
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From: Frank Wang <frank.wang@rock-chips.com>
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Date: Tue, 7 Jan 2025 15:49:08 +0800
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Subject: [PATCH] arm64: dts: rockchip: add usb related nodes for rk3576
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This adds USB and USB-PHY related nodes for RK3576 SoC.
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Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
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Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
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Link: https://lore.kernel.org/r/20250107074911.550057-5-kever.yang@rock-chips.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3576.dtsi | 133 +++++++++++++++++++++++
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1 file changed, 133 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
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@@ -445,6 +445,58 @@
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#size-cells = <2>;
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ranges;
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+ usb_drd0_dwc3: usb@23000000 {
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+ compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
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+ reg = <0x0 0x23000000 0x0 0x400000>;
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+ clocks = <&cru CLK_REF_USB3OTG0>,
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+ <&cru CLK_SUSPEND_USB3OTG0>,
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+ <&cru ACLK_USB3OTG0>;
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+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
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+ interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
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+ power-domains = <&power RK3576_PD_USB>;
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+ resets = <&cru SRST_A_USB3OTG0>;
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+ dr_mode = "otg";
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+ phys = <&u2phy0_otg>, <&usbdp_phy PHY_TYPE_USB3>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ phy_type = "utmi_wide";
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u1-entry-quirk;
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+ snps,dis-u2-entry-quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ snps,parkmode-disable-hs-quirk;
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+ snps,parkmode-disable-ss-quirk;
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+ status = "disabled";
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+ };
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+
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+ usb_drd1_dwc3: usb@23400000 {
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+ compatible = "rockchip,rk3576-dwc3", "snps,dwc3";
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+ reg = <0x0 0x23400000 0x0 0x400000>;
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+ clocks = <&cru CLK_REF_USB3OTG1>,
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+ <&cru CLK_SUSPEND_USB3OTG1>,
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+ <&cru ACLK_USB3OTG1>;
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+ clock-names = "ref_clk", "suspend_clk", "bus_clk";
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+ interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
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+ power-domains = <&power RK3576_PD_PHP>;
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+ resets = <&cru SRST_A_USB3OTG1>;
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+ dr_mode = "otg";
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+ phys = <&u2phy1_otg>, <&combphy1_psu PHY_TYPE_USB3>;
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+ phy-names = "usb2-phy", "usb3-phy";
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+ phy_type = "utmi_wide";
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+ snps,dis_enblslpm_quirk;
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+ snps,dis-u1-entry-quirk;
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+ snps,dis-u2-entry-quirk;
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+ snps,dis-u2-freeclk-exists-quirk;
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+ snps,dis-del-phy-power-chg-quirk;
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+ snps,dis-tx-ipgap-linecheck-quirk;
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+ snps,dis_rxdet_inp3_quirk;
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+ snps,parkmode-disable-hs-quirk;
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+ snps,parkmode-disable-ss-quirk;
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+ dma-coherent;
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+ status = "disabled";
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+ };
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+
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sys_grf: syscon@2600a000 {
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compatible = "rockchip,rk3576-sys-grf", "syscon";
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reg = <0x0 0x2600a000 0x0 0x2000>;
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@@ -515,6 +567,65 @@
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reg = <0x0 0x2602c000 0x0 0x2000>;
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};
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+ usb2phy_grf: syscon@2602e000 {
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+ compatible = "rockchip,rk3576-usb2phy-grf", "syscon", "simple-mfd";
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+ reg = <0x0 0x2602e000 0x0 0x4000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ u2phy0: usb2-phy@0 {
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+ compatible = "rockchip,rk3576-usb2phy";
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+ reg = <0x0 0x10>;
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+ resets = <&cru SRST_OTGPHY_0>, <&cru SRST_P_USBPHY_GRF_0>;
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+ reset-names = "phy", "apb";
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+ clocks = <&cru CLK_PHY_REF_SRC>,
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+ <&cru ACLK_MMU2>,
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+ <&cru ACLK_SLV_MMU2>;
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+ clock-names = "phyclk", "aclk", "aclk_slv";
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+ clock-output-names = "usb480m_phy0";
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+ #clock-cells = <0>;
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+ status = "disabled";
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+
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+ u2phy0_otg: otg-port {
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+ #phy-cells = <0>;
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+ interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "otg-bvalid", "otg-id", "linestate";
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+ status = "disabled";
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+ };
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+ };
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+
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+ u2phy1: usb2-phy@2000 {
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+ compatible = "rockchip,rk3576-usb2phy";
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+ reg = <0x2000 0x10>;
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+ resets = <&cru SRST_OTGPHY_1>, <&cru SRST_P_USBPHY_GRF_1>;
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+ reset-names = "phy", "apb";
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+ clocks = <&cru CLK_PHY_REF_SRC>,
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+ <&cru ACLK_MMU1>,
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+ <&cru ACLK_SLV_MMU1>;
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+ clock-names = "phyclk", "aclk", "aclk_slv";
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+ clock-output-names = "usb480m_phy1";
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+ #clock-cells = <0>;
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+ status = "disabled";
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+
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+ u2phy1_otg: otg-port {
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+ #phy-cells = <0>;
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+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "otg-bvalid", "otg-id", "linestate";
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+ status = "disabled";
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+ };
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+ };
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+ };
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+
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+ vo1_grf: syscon@26036000 {
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+ compatible = "rockchip,rk3576-vo1-grf", "syscon";
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+ reg = <0x0 0x26036000 0x0 0x100>;
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+ clocks = <&cru PCLK_VO1_ROOT>;
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+ };
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+
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sdgmac_grf: syscon@26038000 {
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compatible = "rockchip,rk3576-sdgmac-grf", "syscon";
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reg = <0x0 0x26038000 0x0 0x1000>;
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@@ -1623,6 +1734,28 @@
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status = "disabled";
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};
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+ usbdp_phy: phy@2b010000 {
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+ compatible = "rockchip,rk3576-usbdp-phy";
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+ reg = <0x0 0x2b010000 0x0 0x10000>;
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+ #phy-cells = <1>;
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+ clocks = <&cru CLK_PHY_REF_SRC >,
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+ <&cru CLK_USBDP_COMBO_PHY_IMMORTAL>,
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+ <&cru PCLK_USBDPPHY>,
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+ <&u2phy0>;
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+ clock-names = "refclk", "immortal", "pclk", "utmi";
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+ resets = <&cru SRST_USBDP_COMBO_PHY_INIT>,
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+ <&cru SRST_USBDP_COMBO_PHY_CMN>,
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+ <&cru SRST_USBDP_COMBO_PHY_LANE>,
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+ <&cru SRST_USBDP_COMBO_PHY_PCS>,
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+ <&cru SRST_P_USBDPPHY>;
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+ reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
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+ rockchip,u2phy-grf = <&usb2phy_grf>;
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+ rockchip,usb-grf = <&usb_grf>;
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+ rockchip,usbdpphy-grf = <&usbdpphy_grf>;
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+ rockchip,vo-grf = <&vo1_grf>;
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+ status = "disabled";
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+ };
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+
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sram: sram@3ff88000 {
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compatible = "mmio-sram";
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reg = <0x0 0x3ff88000 0x0 0x78000>;
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