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openwrt-6.x/target/linux/rockchip/patches-6.12/610-arm64-rockchip-add-OF-node-for-eth.patch
Tianling Shen c008a8bf79
Merge Official Source 
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
2025-11-17 20:07:40 +08:00

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From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
From: David Bauer <mail@david-bauer.net>
Date: Sun, 26 Jul 2020 13:32:59 +0200
Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
NanoPi R2S. Add the correct value for the RTL8153 LED configuration
register to match the blink behavior of the other port on the device.
Signed-off-by: David Bauer <mail@david-bauer.net>
---
arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
1 file changed, 7 insertions(+)
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
@@ -35,6 +35,29 @@
reset-assert-us = <10000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+ };
};
};
};
+
+&rtl8153 {
+ realtek,led-data = <0x78>;
+};
--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
@@ -410,9 +410,11 @@
#size-cells = <0>;
/* Second port is for USB 3.0 */
- rtl8153: device@2 {
- compatible = "usbbda,8153";
+ rtl8153: usb-eth@2 {
+ compatible = "realtek,rtl8153";
reg = <2>;
+
+ realtek,led-data = <0x87>;
};
};
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
@@ -363,9 +363,11 @@
#size-cells = <0>;
/* Second port is for USB 3.0 */
- rtl8153: device@2 {
- compatible = "usbbda,8153";
+ rtl8153: usb-eth@2 {
+ compatible = "realtek,rtl8153";
reg = <2>;
+
+ realtek,led-data = <0x87>;
};
};
--- a/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
@@ -39,6 +39,29 @@
reset-assert-us = <15000>;
reset-deassert-us = <50000>;
reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+ };
};
};
};
+
+&rtl8153 {
+ realtek,led-data = <0x78>;
+};
--- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
@@ -83,6 +83,19 @@
max-link-speed = <1>;
num-lanes = <1>;
vpcie3v3-supply = <&vcc3v3_sys>;
+
+ pcie@0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie-eth@0,0 {
+ compatible = "pci10ec,8168";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x870>;
+ };
+ };
};
&pinctrl {
--- a/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3528-radxa-e20c.dts
@@ -244,6 +244,25 @@
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
@@ -253,6 +272,18 @@
reset-gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8168: pcie-eth@0,0 {
+ compatible = "pci10ec,8168";
+ reg = <0x000000 0 0 0 0>;
+ realtek,led-data = <0x87>;
+ };
+ };
};
&pinctrl {
--- a/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-nanopi-r3s.dts
@@ -417,6 +417,25 @@
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+ };
};
};
@@ -425,6 +444,18 @@
pinctrl-0 = <&pcie_reset_h>;
reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8168: pcie-eth@1,0 {
+ compatible = "pci10ec,8168";
+ reg = <0x000000 0 0 0 0>;
+ realtek,led-data = <0x870>;
+ };
+ };
};
&pinctrl {
--- a/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-easepi-r1.dts
@@ -465,6 +465,25 @@
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+ };
};
};
@@ -477,6 +496,25 @@
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
@@ -485,6 +523,19 @@
reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie-eth@1,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x200 0x2b>;
+ };
+ };
};
&pcie30phy {
@@ -498,6 +549,19 @@
reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_sys>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00100000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ pcie-eth@10,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x200 0x2b>;
+ };
+ };
};
/* M.2 Key for 2280 NVMe */
--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
@@ -369,6 +369,19 @@
reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00100000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_1: pcie-eth@10,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x200 0x2b 0x0 0x0>;
+ };
+ };
};
&pcie3x2 {
@@ -376,6 +389,19 @@
reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00200000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_2: pcie-eth@20,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x200 0x2b 0x0 0x0>;
+ };
+ };
};
&pinctrl {
--- a/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
@@ -31,6 +31,7 @@
assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
+ label = "eth0";
phy-handle = <&rgmii_phy0>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
@@ -47,6 +48,7 @@
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
+ label = "eth1";
phy-handle = <&rgmii_phy1>;
phy-mode = "rgmii-id";
pinctrl-names = "default";
@@ -67,6 +69,25 @@
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
@@ -79,6 +100,25 @@
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
@@ -100,6 +140,14 @@
vccio3-supply = <&vcc_3v3>;
};
+&rtl8125_1 {
+ label = "eth3";
+};
+
+&rtl8125_2 {
+ label = "eth2";
+};
+
&sdhci {
bus-width = <8>;
max-frequency = <200000000>;
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
@@ -69,6 +69,19 @@
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00100000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_1: pcie-eth@10,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x2b 0x200>;
+ };
+ };
};
&pcie3x2 {
@@ -76,6 +89,19 @@
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00200000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_2: pcie-eth@20,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x2b 0x200>;
+ };
+ };
};
&pinctrl {
--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
@@ -78,6 +78,25 @@
reg = <1>;
pinctrl-0 = <&eth_phy0_reset_pin>;
pinctrl-names = "default";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
@@ -85,6 +104,19 @@
num-lanes = <1>;
reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_1: pcie-eth@1,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x2b 0x200>;
+ };
+ };
};
&pcie30phy {
@@ -97,6 +129,19 @@
reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc3v3_pcie>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00100000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_2: pcie-eth@10,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x2b 0x200>;
+ };
+ };
};
&pcie3x2 {
--- a/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-photonicat.dts
@@ -3,6 +3,7 @@
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/soc/rockchip,vop2.h>
#include "rk3568.dtsi"
@@ -287,6 +288,7 @@
&gmac0 {
assigned-clocks = <&cru SCLK_GMAC0_RX_TX>;
assigned-clock-parents = <&gmac0_xpcsclk>;
+ label = "eth1";
power-domains = <&power RK3568_PD_PIPE>;
phys = <&combphy2 PHY_TYPE_SGMII>;
phy-handle = <&sgmii_phy>;
@@ -305,6 +307,7 @@
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
assigned-clock-rates = <0>, <125000000>;
clock_in_out = "output";
+ label = "eth0";
phy-handle = <&rgmii_phy>;
phy-mode = "rgmii-id";
phy-supply = <&vcc_3v3>;
@@ -386,6 +389,25 @@
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
@@ -398,6 +420,25 @@
reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;
rx-internal-delay-ps = <1500>;
tx-internal-delay-ps = <1500>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_WAN;
+ default-state = "keep";
+ };
+ };
};
};
--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
@@ -591,6 +591,25 @@
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@2 {
+ reg = <2>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
--- a/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3576-nanopi-r76s.dts
@@ -663,6 +663,22 @@
reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_s3>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00000000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+
+ pcie-eth@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x200 0x2b>;
+ label = "eth0";
+ };
+ };
};
&pcie1 {
@@ -671,6 +687,22 @@
reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
vpcie3v3-supply = <&vcc_3v3_s3>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00200000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ device_type = "pci";
+
+ pcie-eth@0,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x200 0x2b>;
+ label = "eth1";
+ };
+ };
};
&pinctrl {
--- a/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-armsom-sige7.dts
@@ -267,6 +267,19 @@
&pcie2x1l0 {
reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00200000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_1: pcie-eth@20,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x2b 0x200 0x0>;
+ };
+ };
};
/* phy2 - WiFi */
@@ -297,6 +310,19 @@
&pcie2x1l2 {
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00400000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_2: pcie-eth@40,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x2b 0x200 0x0>;
+ };
+ };
};
&pcie30phy {
--- a/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopc-t6.dtsi
@@ -508,6 +508,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie2_0_rst>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00200000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_1: pcie-eth@20,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x2b 0x200>;
+ label = "eth2";
+ };
+ };
};
&pcie2x1l1 {
@@ -524,6 +538,20 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie2_2_rst>;
status = "okay";
+
+ pcie@0,0 {
+ reg = <0x00400000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ rtl8125_2: pcie-eth@40,0 {
+ compatible = "pci10ec,8125";
+ reg = <0x000000 0 0 0 0>;
+
+ realtek,led-data = <0x0 0x0 0x2b 0x200>;
+ label = "eth1";
+ };
+ };
};
&pcie30phy {
--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5c.dts
@@ -417,6 +417,25 @@
reset-assert-us = <20000>;
reset-deassert-us = <100000>;
reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+
+ led@1 {
+ reg = <1>;
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_LAN;
+ default-state = "keep";
+ };
+ };
};
};
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