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airoha: refresh PCS patch for recent changes
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
This commit is contained in:
Christian Marangi 2025-12-11 12:26:42 +01:00
parent 1fcb55a534
commit ffab14c7eb
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GPG Key ID: AC001D09ADBFEAD7
2 changed files with 215 additions and 128 deletions
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277
target/linux/airoha/patches-6.6/116-09-net-pcs-airoha-add-PCS-driver-for-Airoha-SoC.patch
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@ -1,9 +1,9 @@
From 2d788bba94a95a44fd246cecc5cbed0a4f28e609 Mon Sep 17 00:00:00 2001
From 5e44fed5780b0b09a089791d72e28c3b808e49bb Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Fri, 17 Jan 2025 12:40:32 +0100
Subject: [PATCH 2/7] net: pcs: airoha: add PCS driver for Airoha AN7581 SoC
Subject: [PATCH 3/8] net: pcs: airoha: add PCS driver for Airoha AN7581 SoC
Add PCS driver for Airoha AN7581 SoC for ethernet SERDES and permit usage of
Add PCS driver for Airoha AN7581 SoC for Ethernet/PON/USB SERDES and permit usage of
external PHY or connected SFP cage. Supported modes are USXGMII,
10G-BASER, 2500BASE-X, 1000BASE-X and SGMII.
@ -17,11 +17,11 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
drivers/net/pcs/Makefile | 2 +
drivers/net/pcs/airoha/Kconfig | 11 +
drivers/net/pcs/airoha/Makefile | 7 +
drivers/net/pcs/airoha/pcs-airoha-common.c | 1052 +++++++++++++++
drivers/net/pcs/airoha/pcs-airoha.h | 822 ++++++++++++
drivers/net/pcs/airoha/pcs-an7581.c | 1419 ++++++++++++++++++++
drivers/net/pcs/airoha/pcs-airoha-common.c | 1047 ++++++++++++++
drivers/net/pcs/airoha/pcs-airoha.h | 869 ++++++++++++
drivers/net/pcs/airoha/pcs-an7581.c | 1470 ++++++++++++++++++++
include/linux/pcs/pcs-airoha.h | 9 +
8 files changed, 3324 insertions(+)
8 files changed, 3417 insertions(+)
create mode 100644 drivers/net/pcs/airoha/Kconfig
create mode 100644 drivers/net/pcs/airoha/Makefile
create mode 100644 drivers/net/pcs/airoha/pcs-airoha-common.c
@ -82,10 +82,10 @@ index 000000000000..25cb8f090c21
+endif
diff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/airoha/pcs-airoha-common.c
new file mode 100644
index 000000000000..f61e291bc325
index 000000000000..61258211d974
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c
@@ -0,0 +1,1052 @@
@@ -0,0 +1,1047 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
@ -170,6 +170,8 @@ index 000000000000..f61e291bc325
+ case AIROHA_PCS_PON:
+ airoha_pcs_setup_scu_pon(priv, interface);
+ break;
+ case AIROHA_PCS_USB:
+ break;
+ }
+
+ /* TODO better handle reset from MAC */
@ -205,8 +207,12 @@ index 000000000000..f61e291bc325
+ regmap_clear_bits(priv->multi_sgmii, AIROHA_PCS_MULTI_SGMII_MSG_RX_CTRL_0,
+ AIROHA_PCS_HSGMII_XFI_SEL);
+
+ regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE);
+ if (priv->data->port_type != AIROHA_PCS_USB)
+ regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE);
+ else
+ regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_CTROL_1,
+ AIROHA_PCS_TBI_10B_MODE);
+}
+
+static void airoha_pcs_init_sgmii(struct airoha_pcs_priv *priv)
@ -249,7 +255,7 @@ index 000000000000..f61e291bc325
+static void airoha_pcs_interrupt_init_sgmii(struct airoha_pcs_priv *priv)
+{
+ /* Disable every interrupt */
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT |
@ -257,14 +263,14 @@ index 000000000000..f61e291bc325
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT);
+
+ /* Clear interrupt */
+ regmap_set_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ regmap_set_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_RX_SYN_DONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_DONE_INT_CLEAR);
+
+ regmap_clear_bits(priv->usxgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ regmap_clear_bits(priv->hsgmii_pcs, AIROHA_PCS_HSGMII_PCS_HSGMII_MODE_INTERRUPT,
+ AIROHA_PCS_HSGMII_MODE2_REMOVE_FAULT_OCCUR_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_CL37_TIMERDONE_INT_CLEAR |
+ AIROHA_PCS_HSGMII_MODE2_AN_MIS_INT_CLEAR |
@ -659,6 +665,11 @@ index 000000000000..f61e291bc325
+ AIROHA_PCS_HSGMII_AN_FORCE_AN_DONE);
+ }
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_set_bits(priv->hsgmii_an, AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0,
+ AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY);
+ }
+
+ /* Configure Flow Control on XFI */
+ regmap_update_bits(priv->xfi_mac, AIROHA_PCS_XFI_MAC_XFI_GIB_CFG,
+ AIROHA_PCS_XFI_TX_FC_EN | AIROHA_PCS_XFI_RX_FC_EN,
@ -978,19 +989,31 @@ index 000000000000..f61e291bc325
+}
+EXPORT_SYMBOL(airoha_pcs_destroy);
+
+static const struct regmap_config airoha_pcs_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+};
+static int airoha_pcs_init_named_regmap(struct platform_device *pdev,
+ const char *name, struct regmap **regmap)
+{
+ struct regmap_config regmap_config = { };
+ void *base;
+
+ base = devm_platform_ioremap_resource_byname(pdev, name);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ regmap_config.name = name;
+ regmap_config.reg_bits = 32,
+ regmap_config.val_bits = 32,
+ regmap_config.reg_stride = 4,
+
+ *regmap = devm_regmap_init_mmio(&pdev->dev, base, &regmap_config);
+
+ return PTR_ERR_OR_ZERO(*regmap);
+}
+
+static int airoha_pcs_probe(struct platform_device *pdev)
+{
+ struct regmap_config syscon_config = airoha_pcs_regmap_config;
+ const struct airoha_pcs_match_data *data;
+ struct device *dev = &pdev->dev;
+ struct airoha_pcs_priv *priv;
+ void *base;
+ int ret;
+
+ data = of_device_get_match_data(dev);
@ -1002,77 +1025,43 @@ index 000000000000..f61e291bc325
+ priv->dev = dev;
+ priv->data = data;
+
+ base = devm_platform_ioremap_resource_byname(pdev, "xfi_mac");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+ ret = airoha_pcs_init_named_regmap(pdev, "xfi_mac", &priv->xfi_mac);
+ if (ret)
+ return ret;
+
+ syscon_config.name = "xfi_mac";
+ priv->xfi_mac = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->xfi_mac))
+ return PTR_ERR(priv->xfi_mac);
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_an", &priv->hsgmii_an);
+ if (ret)
+ return ret;
+
+ base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_an");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_pcs", &priv->hsgmii_pcs);
+ if (ret)
+ return ret;
+
+ syscon_config.name = "hsgmii_an";
+ priv->hsgmii_an = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->hsgmii_an))
+ return PTR_ERR(priv->hsgmii_an);
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_rate_adp", &priv->hsgmii_rate_adp);
+ if (ret)
+ return ret;
+
+ base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_pcs");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+ ret = airoha_pcs_init_named_regmap(pdev, "multi_sgmii", &priv->multi_sgmii);
+ if (ret)
+ return ret;
+
+ syscon_config.name = "hsgmii_pcs";
+ priv->hsgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->hsgmii_pcs))
+ return PTR_ERR(priv->hsgmii_pcs);
+ if (data->port_type == AIROHA_PCS_USB) {
+ ret = airoha_pcs_init_named_regmap(pdev, "hsgmii_ana", &priv->hsgmii_ana);
+ if (ret)
+ return ret;
+ } else {
+ ret = airoha_pcs_init_named_regmap(pdev, "usxgmii", &priv->usxgmii_pcs);
+ if (ret)
+ return ret;
+
+ base = devm_platform_ioremap_resource_byname(pdev, "hsgmii_rate_adp");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+ ret = airoha_pcs_init_named_regmap(pdev, "xfi_pma", &priv->xfi_pma);
+ if (ret)
+ return ret;
+
+ syscon_config.name = "hsgmii_rate_adp";
+ priv->hsgmii_rate_adp = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->hsgmii_rate_adp))
+ return PTR_ERR(priv->hsgmii_rate_adp);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "multi_sgmii");
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ syscon_config.name = "multi_sgmii";
+ priv->multi_sgmii = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->multi_sgmii))
+ return PTR_ERR(priv->multi_sgmii);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "usxgmii");
+ if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+ return PTR_ERR(base);
+
+ syscon_config.name = "usxgmii";
+ priv->usxgmii_pcs = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->usxgmii_pcs))
+ return PTR_ERR(priv->usxgmii_pcs);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "xfi_pma");
+ if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+ return PTR_ERR(base);
+
+ syscon_config.name = "xfi_pma";
+ priv->xfi_pma = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->xfi_pma))
+ return PTR_ERR(priv->xfi_pma);
+
+ base = devm_platform_ioremap_resource_byname(pdev, "xfi_ana");
+ if (IS_ERR(base) && PTR_ERR(base) != -ENOENT)
+ return PTR_ERR(base);
+
+ syscon_config.name = "xfi_ana";
+ priv->xfi_ana = devm_regmap_init_mmio(dev, base, &syscon_config);
+ if (IS_ERR(priv->xfi_ana))
+ return PTR_ERR(priv->xfi_ana);
+ ret = airoha_pcs_init_named_regmap(pdev, "xfi_ana", &priv->xfi_ana);
+ if (ret)
+ return ret;
+ }
+
+ /* SCU is used to toggle XFI or HSGMII in global SoC registers */
+ priv->scu = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,scu");
@ -1081,8 +1070,8 @@ index 000000000000..f61e291bc325
+
+ priv->rsts[0].id = "mac";
+ priv->rsts[1].id = "phy";
+ ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ ret = devm_reset_control_bulk_get_optional_exclusive(dev, ARRAY_SIZE(priv->rsts),
+ priv->rsts);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to get bulk reset lines\n");
+
@ -1090,7 +1079,7 @@ index 000000000000..f61e291bc325
+ * manual rx calibration is needed. This is only limited to
+ * any SoC revision before E2.
+ */
+ if (data->port_type == AIROHA_PCS_ETH) {
+ if (device_is_compatible(dev, "airoha,an7581-pcs-eth")) {
+ u32 val;
+
+ ret = regmap_read(priv->scu, AIROHA_SCU_PDIDR, &val);
@ -1119,9 +1108,15 @@ index 000000000000..f61e291bc325
+ .link_up = an7581_pcs_phya_link_up,
+};
+
+static const struct airoha_pcs_match_data an7581_pcs_usb = {
+ .port_type = AIROHA_PCS_USB,
+ .bringup = an7581_pcs_usb_bringup,
+};
+
+static const struct of_device_id airoha_pcs_of_table[] = {
+ { .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
+ { .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
+ { .compatible = "airoha,an7581-pcs-usb", .data = &an7581_pcs_usb },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
@ -1140,10 +1135,10 @@ index 000000000000..f61e291bc325
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
diff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/pcs-airoha.h
new file mode 100644
index 000000000000..93ddec60d6dd
index 000000000000..16afd6f47130
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-airoha.h
@@ -0,0 +1,822 @@
@@ -0,0 +1,869 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
@ -1195,6 +1190,7 @@ index 000000000000..93ddec60d6dd
+
+/* HSGMII_AN */
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_0 0x0
+#define AIROHA_PCS_HSGMII_AN_SGMII_RESET_PHY BIT(15)
+#define AIROHA_PCS_HSGMII_AN_SGMII_RA_ENABLE BIT(12)
+#define AIROHA_PCS_HSGMII_AN_SGMII_AN_RESTART BIT(9)
+#define AIROHA_PCS_HSGMII_AN_SGMII_REG_AN_1 0x4 /* BMSR */
@ -1269,6 +1265,42 @@ index 000000000000..93ddec60d6dd
+#define AIROHA_PCS_HSGMII_PCS_MODE2_RX_SYNC BIT(1)
+#define AIROHA_PCS_HSGMII_PCS_MODE2_AN_DONE BIT(0)
+
+/* HSGMII_ANA */
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6 0x18
+#define AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC BIT(20)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8 0x20
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR GENMASK(11, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 GENMASK(7, 4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0 GENMASK(3, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11 0x2c
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED GENMASK(3, 2)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_TPHY_SPEED, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_TPHY_MODE GENMASK(1, 0)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18 0x48
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV GENMASK(28, 27)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19 0x4c
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE GENMASK(25, 10)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV GENMASK(15, 8)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_LV GENMASK(7, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG GENMASK(2, 0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_GND FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONFBK_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONREF_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x3)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_CKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x4)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_SYSPLL_FBCKMON FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x5)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_TX2500M_A FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_SSUSB_CDR_250M_CK FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_MONCKBG, 0x7)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24 0x60
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE GENMASK(31, 24)
+#define AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26 0x68
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY GENMASK(7, 6)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x0)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_64 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x1)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_128 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x2)
+#define AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_216 FIELD_PREP_CONST(AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY, 0x3)
+
+/* MULTI_SGMII */
+#define AIROHA_PCS_MULTI_SGMII_INTERRUPT_EN_0 0x14
+#define AIROHA_PCS_MULTI_SGMII_PCS_INT_EN_0 BIT(0)
@ -1903,6 +1935,7 @@ index 000000000000..93ddec60d6dd
+enum xfi_port_type {
+ AIROHA_PCS_ETH,
+ AIROHA_PCS_PON,
+ AIROHA_PCS_USB,
+};
+
+struct airoha_pcs_priv {
@ -1916,6 +1949,7 @@ index 000000000000..93ddec60d6dd
+ struct regmap *hsgmii_an;
+ struct regmap *hsgmii_pcs;
+ struct regmap *hsgmii_rate_adp;
+ struct regmap *hsgmii_ana;
+ struct regmap *multi_sgmii;
+ struct regmap *usxgmii_pcs;
+
@ -1947,6 +1981,8 @@ index 000000000000..93ddec60d6dd
+#ifdef CONFIG_PCS_AIROHA_AN7581
+int an7581_pcs_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface);
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface);
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv);
+int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv);
@ -1957,6 +1993,12 @@ index 000000000000..93ddec60d6dd
+ return -EOPNOTSUPP;
+}
+
+static inline int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ return -EOPNOTSUPP;
+}
+
+static inline void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv)
+{
+}
@ -1968,10 +2010,10 @@ index 000000000000..93ddec60d6dd
+#endif
diff --git a/drivers/net/pcs/airoha/pcs-an7581.c b/drivers/net/pcs/airoha/pcs-an7581.c
new file mode 100644
index 000000000000..4e817639ed1d
index 000000000000..9ad177fc3f06
--- /dev/null
+++ b/drivers/net/pcs/airoha/pcs-an7581.c
@@ -0,0 +1,1419 @@
@@ -0,0 +1,1470 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2024 AIROHA Inc
@ -3335,6 +3377,57 @@ index 000000000000..4e817639ed1d
+ return an7581_pcs_phya_bringup(priv, interface);
+}
+
+int an7581_pcs_usb_bringup(struct airoha_pcs_priv *priv,
+ phy_interface_t interface)
+{
+ /* TODROP */
+ regmap_clear_bits(priv->scu, AIROHA_SCU_SSR3, BIT(29));
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ regmap_update_bits(priv->hsgmii_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_8,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1 |
+ AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTR, 0xf) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD1, 0xc) |
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_CDR_BICLTD0, 0x3));
+
+ regmap_set_bits(priv->hsgmii_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ } else {
+ regmap_clear_bits(priv->hsgmii_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_6,
+ AIROHA_PCS_HSGMII_ANA_FORCE_CDR_BIC);
+ }
+
+ regmap_update_bits(priv->hsgmii_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_26,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RST_DLY_32);
+
+ regmap_clear_bits(priv->hsgmii_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_24,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_LN0_CDR_RESERVE);
+
+ regmap_update_bits(priv->hsgmii_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_18,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_BG_DIV, 0x1));
+
+ regmap_update_bits(priv->hsgmii_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_19,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE,
+ FIELD_PREP(AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_HV,
+ AIROHA_PCS_HSGMII_ANA_SSUSB_XTAL_TOP_RESERVE_NS_MONPLL_CK)));
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ regmap_update_bits(priv->hsgmii_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_HSGMII);
+ else
+ regmap_update_bits(priv->hsgmii_ana, AIROHA_PCS_HSGMII_ANA_SGMII_PHYA_11,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED,
+ AIROHA_PCS_HSGMII_ANA_TPHY_SPEED_SGMII);
+
+ return 0;
+}
+
+void an7581_pcs_phya_link_up(struct airoha_pcs_priv *priv)
+{
+ /* Reset TXPCS on link up */

66
target/linux/airoha/patches-6.6/604-01-net-pcs-airoha-add-support-for-AN7583.patch
View File

@ -1,4 +1,4 @@
From 500f525a21bfc18605b23e7b39fc1d8f74393b30 Mon Sep 17 00:00:00 2001
From 0b407c66b393e76252630b1cb348a7c2e221801b Mon Sep 17 00:00:00 2001
From: Christian Marangi <ansuelsmth@gmail.com>
Date: Wed, 25 Jun 2025 00:00:59 +0200
Subject: [PATCH 6/8] net: pcs: airoha: add support for Airoha AN7583 SoC
@ -44,7 +44,7 @@ index 25cb8f090c21..69b8b0a0266b 100644
+pcs-airoha-objs += pcs-an7583.o
+endif
diff --git a/drivers/net/pcs/airoha/pcs-airoha-common.c b/drivers/net/pcs/airoha/pcs-airoha-common.c
index 916f03c259bd..f9ba4a47da1d 100644
index 61258211d974..d8e0e68dd339 100644
--- a/drivers/net/pcs/airoha/pcs-airoha-common.c
+++ b/drivers/net/pcs/airoha/pcs-airoha-common.c
@@ -19,6 +19,7 @@
@ -96,7 +96,7 @@ index 916f03c259bd..f9ba4a47da1d 100644
}
static void airoha_pcs_init_hsgmii(struct airoha_pcs_priv *priv)
@@ -434,6 +449,13 @@ static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
@@ -449,6 +464,13 @@ static int airoha_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7,
AIROHA_PCS_USXGMII_RATE_UPDATE_MODE);
}
@ -110,17 +110,7 @@ index 916f03c259bd..f9ba4a47da1d 100644
}
/* Clear any force bit that my be set by bootloader */
@@ -985,7 +1007,8 @@ static int airoha_pcs_probe(struct platform_device *pdev)
* manual rx calibration is needed. This is only limited to
* any SoC revision before E2.
*/
- if (data->port_type == AIROHA_PCS_ETH) {
+ if (device_is_compatible(dev, "airoha,an7581-pcs-eth") &&
+ data->port_type == AIROHA_PCS_ETH) {
u32 val;
ret = regmap_read(priv->scu, AIROHA_SCU_PDIDR, &val);
@@ -1003,6 +1026,8 @@ static int airoha_pcs_probe(struct platform_device *pdev)
@@ -1009,6 +1031,8 @@ static int airoha_pcs_probe(struct platform_device *pdev)
static const struct airoha_pcs_match_data an7581_pcs_eth = {
.port_type = AIROHA_PCS_ETH,
@ -129,7 +119,7 @@ index 916f03c259bd..f9ba4a47da1d 100644
.bringup = an7581_pcs_bringup,
.link_up = an7581_pcs_phya_link_up,
.rxlock_workaround = an7581_pcs_rxlock_workaround,
@@ -1008,13 +1032,33 @@ static const struct airoha_pcs_match_data an7581_pcs_eth = {
@@ -1016,6 +1040,8 @@ static const struct airoha_pcs_match_data an7581_pcs_eth = {
static const struct airoha_pcs_match_data an7581_pcs_pon = {
.port_type = AIROHA_PCS_PON,
@ -138,6 +128,9 @@ index 916f03c259bd..f9ba4a47da1d 100644
.bringup = an7581_pcs_bringup,
.link_up = an7581_pcs_phya_link_up,
};
@@ -1025,10 +1051,28 @@ static const struct airoha_pcs_match_data an7581_pcs_usb = {
.bringup = an7581_pcs_usb_bringup,
};
+static const struct airoha_pcs_match_data an7583_pcs_eth = {
+ .port_type = AIROHA_PCS_ETH,
@ -158,13 +151,14 @@ index 916f03c259bd..f9ba4a47da1d 100644
static const struct of_device_id airoha_pcs_of_table[] = {
{ .compatible = "airoha,an7581-pcs-eth", .data = &an7581_pcs_eth },
{ .compatible = "airoha,an7581-pcs-pon", .data = &an7581_pcs_pon },
{ .compatible = "airoha,an7581-pcs-usb", .data = &an7581_pcs_usb },
+ { .compatible = "airoha,an7583-pcs-eth", .data = &an7583_pcs_eth },
+ { .compatible = "airoha,an7583-pcs-pon", .data = &an7583_pcs_pon },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, airoha_pcs_of_table);
diff --git a/drivers/net/pcs/airoha/pcs-airoha.h b/drivers/net/pcs/airoha/pcs-airoha.h
index 93ddec60d6dd..790adbe5179c 100644
index 16afd6f47130..c09b0b6828d5 100644
--- a/drivers/net/pcs/airoha/pcs-airoha.h
+++ b/drivers/net/pcs/airoha/pcs-airoha.h
@@ -14,6 +14,9 @@
@ -177,7 +171,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_SCU_WAN_SEL GENMASK(7, 0)
#define AIROHA_SCU_WAN_SEL_SGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x10)
#define AIROHA_SCU_WAN_SEL_HSGMII FIELD_PREP_CONST(AIROHA_SCU_WAN_SEL, 0x11)
@@ -244,6 +247,8 @@
@@ -281,6 +284,8 @@
#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_6 0x31c
#define AIROHA_PCS_USXGMII_TOG_PCS_AUTONEG_STS BIT(0)
#define AIROHA_PCS_USXGMII_PCS_AN_CONTROL_7 0x320
@ -186,7 +180,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_USXGMII_RATE_UPDATE_MODE BIT(12)
#define AIROHA_PCS_USXGMII_MODE GENMASK(10, 8)
#define AIROHA_PCS_USXGMII_MODE_10000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x0)
@@ -251,9 +256,27 @@
@@ -288,9 +293,27 @@
#define AIROHA_PCS_USXGMII_MODE_2500 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x2)
#define AIROHA_PCS_USXGMII_MODE_1000 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x3)
#define AIROHA_PCS_USXGMII_MODE_100 FIELD_PREP_CONST(AIROHA_PCS_USXGMII_MODE, 0x4)
@ -214,7 +208,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_ANA_CMN_EN BIT(0)
#define AIROHA_PCS_ANA_PXP_JCPLL_IB_EXT_EN 0x4
#define AIROHA_PCS_ANA_JCPLL_CHP_IOFST GENMASK(29, 24)
@@ -347,6 +370,8 @@
@@ -384,6 +407,8 @@
#define AIROHA_PCS_ANA_JCPLL_TCL_KBAND_VREF GENMASK(20, 16)
#define AIROHA_PCS_ANA_JCPLL_SPARE_L GENMASK(15, 8)
#define AIROHA_PCS_ANA_JCPLL_SPARE_L_LDO FIELD_PREP_CONST(AIROHA_PCS_ANA_JCPLL_SPARE_L, BIT(5))
@ -223,7 +217,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_ANA_PXP_TXPLL_CHP_IBIAS 0x50
#define AIROHA_PCS_ANA_TXPLL_LPF_BC GENMASK(28, 24)
#define AIROHA_PCS_ANA_TXPLL_LPF_BR GENMASK(20, 16)
@@ -370,6 +395,9 @@
@@ -407,6 +432,9 @@
#define AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE_1 FIELD_PREP_CONST(AIROHA_PCS_ANA_TXPLL_MMD_PREDIV_MODE, 0x3)
#define AIROHA_PCS_ANA_TXPLL_POSTDIV_EN BIT(8)
#define AIROHA_PCS_ANA_TXPLL_KBAND_KS GENMASK(1, 0)
@ -233,7 +227,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_ANA_PXP_TXPLL_REFIN_INTERNAL 0x64
#define AIROHA_PCS_ANA_TXPLL_PLL_RSTB BIT(24)
#define AIROHA_PCS_ANA_TXPLL_RST_DLY GENMASK(18, 16)
@@ -435,16 +463,41 @@
@@ -472,16 +500,41 @@
#define AIROHA_PCS_ANA_TXPLL_LDO_VCO_OUT GENMASK(25, 24)
#define AIROHA_PCS_ANA_TXPLL_LDO_OUT GENMASK(17, 16)
#define AIROHA_PCS_ANA_TXPLL_SSC_PERIOD GENMASK(15, 0)
@ -275,7 +269,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_ANA_PXP_RX_REV_0 0xd4
#define AIROHA_PCS_ANA_RX_REV_1 GENMASK(31, 16)
#define AIROHA_PCS_ANA_REV_1_FE_EQ_BIAS_CTRL GENMASK(30, 28)
@@ -452,6 +505,16 @@
@@ -489,6 +542,16 @@
#define AIROHA_PCS_ANA_REV_1_FE_BUF2_BIAS_CTRL GENMASK(22, 20)
#define AIROHA_PCS_ANA_REV_1_SIGDET_ILEAK GENMASK(19, 18)
#define AIROHA_PCS_ANA_REV_1_FECUR_PWDB BIT(16)
@ -292,7 +286,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_ANA_PXP_RX_PHYCK_DIV 0xd8
#define AIROHA_PCS_ANA_RX_TDC_CK_SEL BIT(24)
#define AIROHA_PCS_ANA_RX_PHYCK_RSTB BIT(16)
@@ -460,6 +523,8 @@
@@ -497,6 +560,8 @@
#define AIROHA_PCS_ANA_PXP_CDR_PD_PICAL_CKD8_INV 0xdc
#define AIROHA_PCS_ANA_CDR_PD_EDGE_DIS BIT(8)
#define AIROHA_PCS_ANA_CDR_PD_PICAL_CKD8_INV BIT(0)
@ -301,7 +295,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_ANA_PXP_CDR_LPF_RATIO 0xe8
#define AIROHA_PCS_ANA_CDR_LPF_TOP_LIM GENMASK(26, 8)
#define AIROHA_PCS_ANA_CDR_LPF_RATIO GENMASK(1, 0)
@@ -475,6 +540,19 @@
@@ -512,6 +577,19 @@
#define AIROHA_PCS_ANA_CDR_PR_DAC_BAND GENMASK(20, 16)
#define AIROHA_PCS_ANA_CDR_PR_VREG_CKBUF_VAL GENMASK(10, 8)
#define AIROHA_PCS_ANA_CDR_PR_VREG_IBAND_VAL GENMASK(2, 0)
@ -321,7 +315,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_ANA_PXP_CDR_PR_MONPR_EN 0x10c
#define AIROHA_PCS_ANA_RX_DAC_MON GENMASK(28, 24)
#define AIROHA_PCS_ANA_CDR_PR_CAP_EN BIT(19)
@@ -484,6 +562,7 @@
@@ -521,6 +599,7 @@
#define AIROHA_PCS_ANA_CDR_PR_MONDPR_EN BIT(0)
#define AIROHA_PCS_ANA_PXP_RX_DAC_RANGE 0x110
#define AIROHA_PCS_ANA_RX_SIGDET_LPF_CTRL GENMASK(25, 24)
@ -329,7 +323,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_ANA_PXP_RX_SIGDET_NOVTH 0x114
#define AIROHA_PCS_ANA_RX_FE_50OHMS_SEL GENMASK(25, 24)
#define AIROHA_PCS_ANA_RX_SIGDET_VTH_SEL GENMASK(20, 16)
@@ -532,7 +611,70 @@
@@ -569,7 +648,70 @@
#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_0 0x0
#define AIROHA_PCS_PMA_SW_LCPLL_EN BIT(24)
#define AIROHA_PCS_PMA_SS_LCPLL_PWCTL_SETTING_1 0x4
@ -400,7 +394,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_PMA_RX_EYE_TOP_EYECNT_CTRL_2 0x88
#define AIROHA_PCS_PMA_DATA_SHIFT BIT(8)
#define AIROHA_PCS_PMA_EYECNT_FAST BIT(0)
@@ -564,14 +706,49 @@
@@ -601,14 +743,49 @@
#define AIROHA_PCS_PMA_RX_BLWC_RDY_EN GENMASK(15, 0)
#define AIROHA_PCS_PMA_RX_CTRL_SEQUENCE_CTRL_6 0x104
#define AIROHA_PCS_PMA_RX_OS_END GENMASK(15, 0)
@ -450,7 +444,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_PMA_SS_RX_FREQ_DET_1 0x14c
#define AIROHA_PCS_PMA_UNLOCK_CYCLECNT GENMASK(31, 16)
#define AIROHA_PCS_PMA_LOCK_CYCLECNT GENMASK(15, 0)
@@ -590,31 +767,182 @@
@@ -627,31 +804,182 @@
#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_WAIT FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x2)
#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_NORMAL FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x3)
#define AIROHA_PCS_PMA_FREQLOCK_DET_EN_RX_STATE FIELD_PREP_CONST(AIROHA_PCS_PMA_FREQLOCK_DET_EN, 0x7)
@ -633,7 +627,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_PMA_SS_DA_XPON_PWDB_0 0x34c
#define AIROHA_PCS_PMA_XPON_CDR_PD_PWDB BIT(24)
#define AIROHA_PCS_PMA_XPON_CDR_PR_PIEYE_PWDB BIT(16)
@@ -637,7 +965,32 @@
@@ -674,7 +1002,32 @@
#define AIROHA_PCS_PMA_PLL_LOCK_TARGET_BEG GENMASK(15, 0)
#define AIROHA_PCS_PMA_PLL_TDC_FREQDET_3 0x39c
#define AIROHA_PCS_PMA_PLL_LOCK_LOCKTH GENMASK(11, 8)
@ -666,7 +660,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_PMA_SW_HSG_RXPCS_RST_N BIT(11)
#define AIROHA_PCS_PMA_SW_HSG_TXPCS_RST_N BIT(10)
#define AIROHA_PCS_PMA_SW_XFI_RXPCS_BIST_RST_N BIT(9)
@@ -650,17 +1003,32 @@
@@ -687,17 +1040,32 @@
#define AIROHA_PCS_PMA_SW_TX_RST_N BIT(2)
#define AIROHA_PCS_PMA_SW_RX_RST_N BIT(1)
#define AIROHA_PCS_PMA_SW_RX_FIFO_RST_N BIT(0)
@ -699,7 +693,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_PMA_PXP_JCPLL_SDM_SCAN 0x768
#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PEAKING_CTRL BIT(24)
#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PEAKING_CTRL GENMASK(19, 16)
@@ -683,8 +1051,13 @@
@@ -720,8 +1088,13 @@
#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_FIR_C1 BIT(8)
#define AIROHA_PCS_PMA_FORCE_DA_TX_FIR_C1 GENMASK(5, 0)
#define AIROHA_PCS_PMA_PXP_TX_RATE_CTRL 0x784
@ -713,7 +707,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_PMA_PXP_CDR_PR_IDAC 0x794
#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_SDM_PCW BIT(24)
#define AIROHA_PCS_PMA_FORCE_SEL_DA_CDR_PR_IDAC BIT(16)
@@ -729,6 +1102,14 @@
@@ -766,6 +1139,14 @@
#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_EN BIT(16)
#define AIROHA_PCS_PMA_FORCE_SEL_DA_JCPLL_CKOUT_EN BIT(8)
#define AIROHA_PCS_PMA_FORCE_DA_JCPLL_CKOUT_EN BIT(0)
@ -728,7 +722,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_PMA_PXP_RX_SCAN_RST_B 0x84c
#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_SIGDET_PWDB BIT(24)
#define AIROHA_PCS_PMA_FORCE_DA_RX_SIGDET_PWDB BIT(16)
@@ -739,6 +1120,12 @@
@@ -776,6 +1157,12 @@
#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_EN BIT(16)
#define AIROHA_PCS_PMA_FORCE_SEL_DA_TXPLL_CKOUT_EN BIT(8)
#define AIROHA_PCS_PMA_FORCE_DA_TXPLL_CKOUT_EN BIT(0)
@ -741,7 +735,7 @@ index 93ddec60d6dd..790adbe5179c 100644
#define AIROHA_PCS_PMA_PXP_TX_ACJTAG_EN 0x874
#define AIROHA_PCS_PMA_FORCE_SEL_DA_TX_CKIN_SEL BIT(24)
#define AIROHA_PCS_PMA_FORCE_DA_TX_CKIN_SEL BIT(16)
@@ -750,10 +1137,31 @@
@@ -787,10 +1174,31 @@
#define AIROHA_PCS_PMA_FORCE_DA_RX_PDOSCAL_EN BIT(16)
#define AIROHA_PCS_PMA_FORCE_SEL_DA_RX_FE_PWDB BIT(8)
#define AIROHA_PCS_PMA_FORCE_DA_RX_FE_PWDB BIT(0)
@ -773,7 +767,7 @@ index 93ddec60d6dd..790adbe5179c 100644
enum xfi_port_type {
AIROHA_PCS_ETH,
AIROHA_PCS_PON,
@@ -790,6 +1198,11 @@ struct airoha_pcs_port {
@@ -829,6 +1237,11 @@ struct airoha_pcs_port {
struct airoha_pcs_match_data {
enum xfi_port_type port_type;
@ -785,7 +779,7 @@ index 93ddec60d6dd..790adbe5179c 100644
int (*bringup)(struct airoha_pcs_priv *priv,
phy_interface_t interface);
void (*link_up)(struct airoha_pcs_priv *priv);
@@ -820,3 +1233,20 @@ static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv)
@@ -867,3 +1280,20 @@ static inline int an7581_pcs_rxlock_workaround(struct airoha_pcs_priv *priv)
return 0;
}
#endif