mirror of
https://github.com/breeze303/openwrt-ipq.git
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140b5e96e1
NSS patches should always get applied last as to avoid fuzzing issues with upstream patches. Also cleanup patches that introduced spaces as indents vs. tabs Signed-off-by: Sean Khan <datapronix@protonmail.com> ath11k_nss: drop upstreamed patch A variation of this patch 'wifi: mac80211: Use flexible array in struct ieee80211_tim_ie' was upstreamed in commit 'e6e4d90b69027d74ba7e9a0a586b95a5714e10c0'. Remove it to avoid compilation issues. Signed-off-by: Sean Khan <datapronix@protonmail.com> ath11k_nss: Fix patch conflict Signed-off-by: Sean Khan <datapronix@protonmail.com>
312 lines
8.2 KiB
Diff
312 lines
8.2 KiB
Diff
From 6504bc9edeb1a2a54d813f4bb5d0267e7bf827f9 Mon Sep 17 00:00:00 2001
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From: Praveenkumar I <ipkumar@codeaurora.org>
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Date: Thu, 6 Feb 2020 17:35:42 +0530
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Subject: [PATCH 4/8] clk: ipq8074: Support added for necessary clocks and
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reset
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Change-Id: I21a76a44185f766e9b6dcba274392ea8e599718b
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Signed-off-by: Praveenkumar I <ipkumar@codeaurora.org>
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Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
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---
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drivers/clk/qcom/gcc-ipq8074.c | 238 ++++++++++++++++++-
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include/dt-bindings/clock/qcom,gcc-ipq8074.h | 35 ++-
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2 files changed, 258 insertions(+), 15 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -48,6 +48,22 @@ enum {
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P_UNIPHY2_TX,
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};
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+static const char * const gcc_xo_gpll4_gpll0_gpll6_gpll0_div2[] = {
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+ "xo",
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+ "gpll4",
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+ "gpll0",
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+ "gpll6",
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+ "gpll0_out_main_div2",
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+};
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+
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+static const struct parent_map gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map[] = {
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+ { P_XO, 0 },
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+ { P_GPLL4, 1 },
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+ { P_GPLL0, 2 },
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+ { P_GPLL6, 3 },
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+ { P_GPLL0_DIV2, 4 },
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+};
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+
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static struct clk_alpha_pll gpll0_main = {
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.offset = 0x21000,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
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@@ -629,6 +645,12 @@ static const struct freq_tbl ftbl_pcie_a
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{ }
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};
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+struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
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+ F(19200000, P_XO, 1, 0, 0),
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+ F(100000000, P_GPLL0, 8, 0, 0),
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+ { }
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+};
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+
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static struct clk_rcg2 pcie0_axi_clk_src = {
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.cmd_rcgr = 0x75054,
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.freq_tbl = ftbl_pcie_axi_clk_src,
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@@ -2031,6 +2053,78 @@ static struct clk_rcg2 gp3_clk_src = {
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},
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};
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+struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {
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+ F(160000000, P_GPLL0_DIV2, 2.5, 0, 0),
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+ F(320000000, P_GPLL0, 2.5, 0, 0),
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+ F(600000000, P_GPLL6, 2, 0, 0),
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+ { }
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+};
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+
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+struct clk_rcg2 qdss_tsctr_clk_src = {
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+ .cmd_rcgr = 0x29064,
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+ .freq_tbl = ftbl_qdss_tsctr_clk_src,
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+ .hid_width = 5,
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+ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .name = "qdss_tsctr_clk_src",
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+ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
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+ .num_parents = 5,
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+ .ops = &clk_rcg2_ops,
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+ },
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+};
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+
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+static struct clk_fixed_factor qdss_dap_sync_clk_src = {
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+ .mult = 1,
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+ .div = 4,
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+ .hw.init = &(struct clk_init_data){
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+ .name = "qdss_dap_sync_clk_src",
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+ .parent_names = (const char *[]){
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+ "qdss_tsctr_clk_src"
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+ },
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+ .num_parents = 1,
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+ .ops = &clk_fixed_factor_ops,
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+ },
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+};
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+
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+struct freq_tbl ftbl_qdss_at_clk_src[] = {
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+ F(66670000, P_GPLL0_DIV2, 6, 0, 0),
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+ F(240000000, P_GPLL6, 6, 0, 0),
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+ { }
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+};
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+
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+struct clk_rcg2 qdss_at_clk_src = {
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+ .cmd_rcgr = 0x2900c,
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+ .freq_tbl = ftbl_qdss_at_clk_src,
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+ .hid_width = 5,
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+ .parent_map = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2_map,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .name = "qdss_at_clk_src",
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+ .parent_names = gcc_xo_gpll4_gpll0_gpll6_gpll0_div2,
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+ .num_parents = 5,
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+ .ops = &clk_rcg2_ops,
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+ },
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+};
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+
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+
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+struct freq_tbl ftbl_adss_pwm_clk_src[] = {
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+ F(19200000, P_XO, 1, 0, 0),
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+ F(200000000, P_GPLL0, 4, 0, 0),
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+ { }
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+};
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+
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+struct clk_rcg2 adss_pwm_clk_src = {
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+ .cmd_rcgr = 0x1c008,
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+ .freq_tbl = ftbl_adss_pwm_clk_src,
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+ .hid_width = 5,
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+ .parent_map = gcc_xo_gpll0_map,
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+ .clkr.hw.init = &(struct clk_init_data){
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+ .name = "adss_pwm_clk_src",
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+ .parent_data = gcc_xo_gpll0,
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+ .num_parents = 2,
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+ .ops = &clk_rcg2_ops,
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+ },
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+};
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+
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static struct clk_branch gcc_blsp1_ahb_clk = {
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.halt_reg = 0x01008,
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.clkr = {
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@@ -4226,13 +4320,7 @@ static struct clk_branch gcc_gp3_clk = {
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},
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};
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-static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {
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- F(19200000, P_XO, 1, 0, 0),
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- F(100000000, P_GPLL0, 8, 0, 0),
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- { }
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-};
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-
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-static struct clk_rcg2 pcie0_rchng_clk_src = {
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+struct clk_rcg2 pcie0_rchng_clk_src = {
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.cmd_rcgr = 0x75070,
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.freq_tbl = ftbl_pcie_rchng_clk_src,
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.hid_width = 5,
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@@ -4324,6 +4412,114 @@ static const struct alpha_pll_config nss
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.alpha_en_mask = BIT(24),
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};
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+static struct clk_branch gcc_snoc_bus_timeout2_ahb_clk = {
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+ .halt_reg = 0x4700c,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x4700c,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_snoc_bus_timeout2_ahb_clk",
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+ .parent_names = (const char *[]){
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+ "usb0_master_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch gcc_snoc_bus_timeout3_ahb_clk = {
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+ .halt_reg = 0x47014,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x47014,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_snoc_bus_timeout3_ahb_clk",
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+ .parent_names = (const char *[]){
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+ "usb1_master_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch gcc_dcc_clk = {
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+ .halt_reg = 0x77004,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x77004,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_dcc_clk",
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+ .parent_names = (const char *[]){
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+ "pcnoc_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch gcc_qdss_at_clk = {
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+ .halt_reg = 0x29024,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x29024,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_qdss_at_clk",
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+ .parent_names = (const char *[]){
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+ "qdss_at_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch gcc_qdss_dap_clk = {
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+ .halt_reg = 0x29084,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x29084,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_qdss_dap_clk",
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+ .parent_names = (const char *[]){
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+ "qdss_dap_sync_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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+static struct clk_branch gcc_adss_pwm_clk = {
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+ .halt_reg = 0x1c020,
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+ .halt_bit = 31,
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+ .clkr = {
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+ .enable_reg = 0x1c020,
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+ .enable_mask = BIT(0),
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+ .hw.init = &(struct clk_init_data){
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+ .name = "gcc_adss_pwm_clk",
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+ .parent_names = (const char *[]){
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+ "adss_pwm_clk_src"
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+ },
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+ .num_parents = 1,
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+ .flags = CLK_SET_RATE_PARENT,
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+ .ops = &clk_branch2_ops,
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+ },
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+ },
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+};
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+
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static struct clk_hw *gcc_ipq8074_hws[] = {
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&gpll0_out_main_div2.hw,
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&gpll6_out_main_div2.hw,
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@@ -4332,6 +4528,7 @@ static struct clk_hw *gcc_ipq8074_hws[]
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&gcc_xo_div4_clk_src.hw,
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&nss_noc_clk_src.hw,
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&nss_ppe_cdiv_clk_src.hw,
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+ &qdss_dap_sync_clk_src.hw,
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};
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static struct clk_regmap *gcc_ipq8074_clks[] = {
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@@ -4563,6 +4760,15 @@ static struct clk_regmap *gcc_ipq8074_cl
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[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,
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[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,
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[GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr,
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+ [GCC_SNOC_BUS_TIMEOUT2_AHB_CLK] = &gcc_snoc_bus_timeout2_ahb_clk.clkr,
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+ [GCC_SNOC_BUS_TIMEOUT3_AHB_CLK] = &gcc_snoc_bus_timeout3_ahb_clk.clkr,
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+ [GCC_DCC_CLK] = &gcc_dcc_clk.clkr,
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+ [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,
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+ [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,
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+ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,
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+ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,
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+ [ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,
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+ [GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,
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};
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static const struct qcom_reset_map gcc_ipq8074_resets[] = {
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--- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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+++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h
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@@ -230,10 +230,19 @@
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#define GCC_GP1_CLK 221
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#define GCC_GP2_CLK 222
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#define GCC_GP3_CLK 223
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-#define GCC_PCIE0_AXI_S_BRIDGE_CLK 224
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-#define GCC_PCIE0_RCHNG_CLK_SRC 225
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-#define GCC_PCIE0_RCHNG_CLK 226
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-#define GCC_CRYPTO_PPE_CLK 227
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+#define GCC_CRYPTO_PPE_CLK 224
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+#define GCC_PCIE0_RCHNG_CLK_SRC 225
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+#define GCC_PCIE0_RCHNG_CLK 226
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+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 227
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+#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 228
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+#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 229
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+#define GCC_DCC_CLK 230
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+#define ADSS_PWM_CLK_SRC 231
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+#define GCC_ADSS_PWM_CLK 232
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+#define QDSS_TSCTR_CLK_SRC 233
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+#define QDSS_AT_CLK_SRC 234
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+#define GCC_QDSS_AT_CLK 235
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+#define GCC_QDSS_DAP_CLK 236
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#define GCC_BLSP1_BCR 0
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#define GCC_BLSP1_QUP1_BCR 1
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