ipq50xx: Add CMCC RAX3000Q support

package/boot/uboot-envtools/files/ipq50xx

@@ -9,6 +9,7 @@ touch /etc/config/ubootenv
 
 board=$(board_name)
 case "$board" in
+	cmcc,rax3000q|\
 	redmi,ax3000|\
 	xiaomi,cr881x)
 		ubootenv_add_uci_config "/dev/mtd10" "0x0" "0x10000" "0x20000"

package/firmware/ipq-wifi/Makefile

@@ -29,6 +29,7 @@ endef
 
 ALLWIFIBOARDS:= \
 	buffalo_wxr-5950ax12 \
+	cmcc_rax3000q \
 	compex_wpq873 \
 	dynalink_dl-wrx36 \
 	edgecore_eap102 \
@@ -124,6 +125,7 @@ endef
 # Add $(eval $(call generate-ipq-wifi-package,<devicename>,<display name>))
 
 $(eval $(call generate-ipq-wifi-package,buffalo_wxr-5950ax12,Buffalo WXR-5950AX12))
+$(eval $(call generate-ipq-wifi-package,cmcc_rax3000q,CMCC RAX3000Q))
 $(eval $(call generate-ipq-wifi-package,compex_wpq873,Compex WPQ-873))
 $(eval $(call generate-ipq-wifi-package,dynalink_dl-wrx36,Dynalink DL-WRX36))
 $(eval $(call generate-ipq-wifi-package,edgecore_eap102,Edgecore EAP102))

target/linux/ipq50xx/base-files/etc/board.d/02_network

@@ -18,6 +18,12 @@ ipq50xx_setup_interfaces()
 				"0:lan:1" "1:lan:2" "2:lan:3" \
 				"3:wan"
 			;;
+		cmcc,rax3000q)
+			ucidef_add_switch "switch1" \
+				"6u@eth1" "3u@eth0" \
+				"2:lan:1" "4:lan:2" "5:lan:3" \
+				"1:wan"
+			;;
 	esac
 }
 

target/linux/ipq50xx/base-files/etc/hotplug.d/firmware/11-ath11k-caldata

@@ -9,6 +9,7 @@ board=$(board_name)
 case "$FIRMWARE" in
 	"ath11k/IPQ5018/hw1.0/caldata.bin")
 		case "$board" in
+			cmcc,rax3000q|\
 			redmi,ax3000|\
 			xiaomi,cr881x)
 				caldata_extract "0:ART" 0x1000 0x20000
@@ -17,6 +18,7 @@ case "$FIRMWARE" in
 		;;
 	"ath11k/qcn6122/hw1.0/caldata_1.bin")
 		case "$board" in
+			cmcc,rax3000q|\
 			redmi,ax3000|\
 			xiaomi,cr881x)
 				caldata_extract "0:ART" 0x26800 0x20000

target/linux/ipq50xx/dts/ipq5000-rax3000q.dts

@@ -0,0 +1,541 @@
+// SPDX-License-Identifier: (GPL-2.0+)
+
+/dts-v1/;
+
+#include "ipq5018.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+	model = "CMCC RAX3000Q";
+	compatible = "cmcc,rax3000q", "qcom,ipq5018";
+
+	#address-cells = <2>;
+	#size-cells = <2>;
+	interrupt-parent = <&intc>;
+
+	aliases {
+		serial0 = &blsp1_uart1;
+
+		ethernet0 = &mac0;
+		ethernet1 = &mac1;
+
+		led-boot = &led_status_green;
+		led-failsafe = &led_status_red;
+		led-running = &led_status_green;
+		led-upgrade = &led_status_blue;
+	};
+
+	chosen {
+		// Override the root parameter from u-boot
+		// Increase coherent_pool size for WiFi
+		bootargs-append = " root=/dev/ubiblock0_1 coherent_pool=2M";
+		stdout-path = "serial0:115200n8";
+	};
+
+	reserved-memory {
+		// Not sure why but without this, WiFi will crash
+		tz_apps@4a400000 {
+			no-map;
+			// The size is incorrent, but it works
+			reg = <0x0 0x4a400000 0x0 0x700000>;
+		};
+
+		q6_mem_regions: q6_mem_regions@4b000000 {
+			no-map;
+			// reg = <0x0 0x4b000000 0x0 0x3b00000>;
+			reg = <0x0 0x4b000000 0x0 0x3000000>;
+		};
+	};
+
+	thermal-zones {
+		status = "ok";
+	};
+};
+
+&tlmm {
+	blsp_uart0_pins: blsp_uart0_pins {
+		pins =
+			"gpio28", // RX
+			"gpio29"; // TX
+		function = "blsp0_uart1";
+		drive-strength = <8>;
+		bias-disable;
+	};
+
+	qspi_nand_pins: qspi_nand_pins {
+		clock {
+			pins = "gpio9";
+			function = "qspi_clk";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		cs {
+			pins = "gpio8";
+			function = "qspi_cs";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		data0 {
+			pins = "gpio7";
+			function = "qspi0";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		data1 {
+			pins = "gpio6";
+			function = "qspi1";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		data2 {
+			pins = "gpio5";
+			function = "qspi2";
+			drive-strength = <8>;
+			bias-disable;
+		};
+
+		data3 {
+			pins = "gpio4";
+			function = "qspi3";
+			drive-strength = <8>;
+			bias-disable;
+		};
+	};
+
+	mdio1_pins: mdio1_pins {
+		mdc {
+			pins = "gpio36";
+			function = "mdc";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		mdio {
+			pins = "gpio37";
+			function = "mdio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+
+	leds_pins: leds_pins {
+		led_status_red {
+			pins = "gpio24";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_status_green {
+			pins = "gpio19";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+
+		led_status_blue {
+			pins = "gpio17";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-down;
+		};
+	};
+
+	button_pins: button_pins {
+		button_reset {
+			pins = "gpio23";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+
+		button_mesh {
+			pins = "gpio38";
+			function = "gpio";
+			drive-strength = <8>;
+			bias-pull-up;
+		};
+	};
+};
+
+&blsp1_uart1 {
+	pinctrl-0 = <&blsp_uart0_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&qpic_bam {
+	status = "ok";
+};
+
+&nand {
+	pinctrl-0 = <&qspi_nand_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+};
+
+&soc {
+	leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&leds_pins>;
+		pinctrl-names = "default";
+
+		led_status_red: led_status_red {
+			label = "blue:system";
+			gpio = <&tlmm 24 GPIO_ACTIVE_HIGH>;
+			default-state = "on";
+		};
+
+		led_status_green: led_status_green {
+			label = "yellow:system";
+			gpio = <&tlmm 19 GPIO_ACTIVE_HIGH>;
+		};
+
+		led_status_blue: led_status_blue {
+			label = "blue:internet";
+			gpio = <&tlmm 17 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	button {
+		compatible = "gpio-keys";
+		pinctrl-0 = <&button_pins>;
+		pinctrl-names = "default";
+
+		button_reset {
+			label = "reset";
+			gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_RESTART>;
+			debounce-interval = <60>;
+		};
+
+		button_mesh {
+			label = "mesh";
+			gpios = <&tlmm 38 GPIO_ACTIVE_LOW>;
+			linux,input-type = <EV_KEY>;
+			linux,code = <KEY_WPS_BUTTON>;
+			debounce-interval = <60>;
+		};
+	};
+
+	ess-instance {
+		num_devices = <2>;
+
+		// Dummy switch, to describe how the external ports connects to the MAC
+		// For example, some chips have PSGMII ports which combine 5 MAC into
+		// 1 external port.
+		// For IPQ50xx, this is used to choose SGMII or SGMII-plus
+		ess-switch@0x39c00000 {
+			compatible = "qcom,ess-switch-ipq50xx";
+			device_id = <0>;
+
+			cmnblk_clk = "internal_96MHz";
+
+			// MAC1 Mode
+			// switch_mac_mode = <0xc>; // PORT_WRAPPER_SGMII_PLUS
+			switch_mac_mode = <0xf>; // PORT_WRAPPER_SGMII_CHANNEL0
+
+			qcom,port_phyinfo {
+				// MAC0 -> GE Phy -> QCA8337 Phy2
+				port@0 {
+					port_id = <1>;
+
+					mdiobus = <&mdio0>;
+					phy_address = <7>;
+
+					phy_dac = <0x10 0x10>;
+				};
+
+				// MAC1 ---SGMII---> QCA8337 SerDes
+				port@1 {
+					port_id = <2>;
+
+					forced-speed = <1000>;
+					forced-duplex = <1>;
+				};
+			};
+		};
+
+		// QCA8337
+		ess-switch1@1 {
+			compatible = "qcom,ess-switch-qca83xx";
+			device_id = <1>;
+
+			reset_gpio = <26>;
+
+			switch_access_mode = "mdio";
+			mdio-bus = <&mdio1>;
+
+			qca,ar8327-initvals = <
+				0x000c 0x00000080  // PAD6_MODE = MAC6_SGMII_EN
+				0x0010 0x002613a0  // PWS_REG = DEFAULT_VALUE | SERDES_AEN
+				0x0094 0x000010ce  // PORT6_STATUS = DEFAULT_VALUE | DUPLEX_MODE_6 | RXMAC_EN_6 |
+						   //                TXMAC_EN_6 | SPEED_6(1000M)
+				0x00e0 0xc74164de  // SGMII_CTRL = DEFAULT_VALUE | MODE_CTRL_25M(SGMII_PHY) | SGMII_EN_SD |
+						   //              SGMII_EN_TX | SGMII_EN_RX | SGMII_EN_PLL
+			>;
+
+			switch_cpu_bmp = <0x48>;  // CPU port bitmap: 3 6
+			switch_lan_bmp = <0x34>;  // LAN port bitmap: 2 4 5
+			switch_wan_bmp = <0x02>;  // WAN port bitmap: 1
+
+			qcom,port_phyinfo {
+				// MAC1 -> Phy0 -> WAN
+				port@1 {
+					port_id = <1>;
+					phy_address = <0>;
+				};
+
+				// MAC2 -> Phy1 -> LAN1
+				port@2 {
+					port_id = <2>;
+					phy_address = <1>;
+				};
+
+				// MAC3 -> Phy2 -> IPQ5000 GE Phy
+				port@3 {
+					port_id = <3>;
+					phy_address = <2>;
+				};
+
+				// MAC4 -> Phy3 -> LAN2
+				port@4 {
+					port_id = <4>;
+					phy_address = <3>;
+				};
+
+				// MAC5 -> Phy4 -> LAN3
+				port@5 {
+					port_id = <5>;
+					phy_address = <4>;
+				};
+
+				// MAC6 ---SGMII---> IPQ5000 MAC1
+				port@6 {
+					port_id = <6>;
+
+					forced-speed = <1000>;
+					forced-duplex = <1>;
+				};
+			};
+		};
+	};
+
+	// MAC0 -> GE Phy
+	mac0: dp1 {
+		compatible = "qcom,nss-dp";
+		device_type = "network";
+		qcom,id = <1>;
+
+		reg = <0x39C00000 0x10000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&gcc GCC_SNOC_GMAC0_AXI_CLK>;
+		clock-names = "nss-snoc-gmac-axi-clk";
+
+		qcom,mactype = <2>; // GMAC_HAL_TYPE_SYN_GMAC
+		local-mac-address = [000000000000];
+		phy-handle = <&ge_phy>;
+		phy-mode = "internal";
+	};
+
+	// MAC1 ---SGMII---> QCA8337 SerDes
+	mac1: dp2 {
+		compatible = "qcom,nss-dp";
+		device_type = "network";
+		qcom,id = <2>;
+
+		reg = <0x39D00000 0x10000>;
+		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&gcc GCC_SNOC_GMAC1_AXI_CLK>;
+		clock-names = "nss-snoc-gmac-axi-clk";
+
+		qcom,mactype = <2>; // GMAC_HAL_TYPE_SYN_GMAC
+		local-mac-address = [000000000000];
+		phy-mode = "sgmii";
+	};
+};
+
+&mdio0 {
+	status = "ok";
+
+	resets = <&gcc GCC_GEPHY_MDC_SW_ARES>;
+	reset-names = "phy";
+
+	// IPQ5018 GE Phy -> QCA8337 Phy2
+	ge_phy: ethernet-phy@0 {
+		reg = <7>;
+	};
+};
+
+&mdio1 {
+	pinctrl-0 = <&mdio1_pins>;
+	pinctrl-names = "default";
+	status = "ok";
+
+	reset-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
+
+	// QCA8337 Phy0 -> WAN
+	ethernet-phy@0 {
+		reg = <0>;
+	};
+
+	// QCA8337 Phy1 -> LAN1
+	ethernet-phy@1 {
+		reg = <1>;
+	};
+
+	// QCA8337 Phy2 -> IPQ5018 GE Phy
+	ethernet-phy@2 {
+		reg = <2>;
+	};
+
+	// QCA8337 Phy3 -> LAN2
+	ethernet-phy@3 {
+		reg = <3>;
+	};
+
+	// QCA8337 Phy4 -> LAN3
+	ethernet-phy@4 {
+		reg = <4>;
+	};
+};
+
+&q6v5_wcss {
+	memory-region = <&q6_mem_regions>;
+
+	qcom,rproc = <&q6v5_wcss>;
+	firmware = "IPQ5018/q6_fw.mdt";
+
+	qcom,bootargs_smem = <507>;
+	boot-args = </*       type: */ 0x2 /* PCIE1 */
+		     /*     length: */ 4
+		     /*      PD id: */ 2
+		     /* reset GPIO: */ 27
+		     /*   reserved: */ 0 0>;
+
+	status = "ok";
+
+	// IPQ5018
+	q6_wcss_pd1: remoteproc_pd1@4ab000 {
+		compatible = "qcom,ipq5018-wcss-ahb-mpd";
+
+		resets =
+			<&gcc GCC_WCSSAON_RESET>,
+			<&gcc GCC_WCSS_BCR>,
+			<&gcc GCC_CE_BCR>;
+		reset-names =
+			"wcss_aon_reset",
+			"wcss_reset",
+			"ce_reset";
+
+		clocks =
+			<&gcc GCC_WCSS_AHB_S_CLK>,
+			<&gcc GCC_WCSS_ACMT_CLK>,
+			<&gcc GCC_WCSS_AXI_M_CLK>;
+		clock-names =
+			"gcc_wcss_ahb_s_clk",
+					"gcc_wcss_acmt_clk",
+					"gcc_wcss_axi_m_clk";
+
+		reg = <0x4ab000 0x20>;
+		reg-names = "rmb";
+
+		// qcom,halt-regs = <&tcsr_q6_block 0xa000 0xd000 0x0>;
+
+		interrupts-extended =
+			<&wcss_smp2p_in 8 0>,
+			<&wcss_smp2p_in 9 0>,
+			<&wcss_smp2p_in 12 0>,
+			<&wcss_smp2p_in 11 0>;
+		interrupt-names =
+			"fatal",
+			"ready",
+			"spawn-ack",
+			"stop-ack";
+
+		qcom,smem-states =
+			<&wcss_smp2p_out 8>,
+			<&wcss_smp2p_out 9>,
+			<&wcss_smp2p_out 10>;
+		qcom,smem-state-names =
+			"shutdown",
+			"stop",
+			"spawn";
+
+		firmware = "IPQ5018/q6_fw.mdt";
+		m3_firmware = "IPQ5018/m3_fw.mdt";
+	};
+
+	// QCN6102
+	q6_wcss_pd2: remoteproc_pd2 {
+		compatible = "qcom,ipq5018-wcss-pcie-mpd";
+
+		interrupts-extended =
+			<&wcss_smp2p_in 16 0>,
+			<&wcss_smp2p_in 17 0>,
+			<&wcss_smp2p_in 20 0>,
+			<&wcss_smp2p_in 19 0>;
+		interrupt-names =
+			"fatal",
+			"ready",
+			"spawn-ack",
+			"stop-ack";
+
+		qcom,smem-states =
+			<&wcss_smp2p_out 16>,
+			<&wcss_smp2p_out 17>,
+			<&wcss_smp2p_out 18>;
+		qcom,smem-state-names =
+			"shutdown",
+			"stop",
+			"spawn";
+
+		firmware = "IPQ5018/q6_fw.mdt";
+		m3_firmware = "qcn6122/m3_fw.mdt";
+	};
+};
+
+&wifi0 {
+	// IPQ5000
+	qcom,multipd_arch;
+	qcom,rproc = <&q6_wcss_pd1>;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd1";
+
+	qcom,board_id = <0x24>;
+
+	// qcom,ath11k-fw-memory-mode = <0>;
+	// qcom,bdf-addr = <0x4c400000>;
+	// qcom,caldb-addr = <0x4d200000>;
+	// qcom,m3-dump-addr = <0x4d400000>;
+
+	qcom,ath11k-fw-memory-mode = <2>;
+	qcom,bdf-addr = <0x4c400000>;
+
+	status = "ok";
+};
+
+&wifi1 {
+	// QCN6102
+	qcom,multipd_arch;
+	qcom,rproc = <&q6_wcss_pd2>;
+	qcom,userpd-subsys-name = "q6v5_wcss_userpd2";
+
+	qcom,board_id = <0x60>;
+
+	// qcom,ath11k-fw-memory-mode = <0>;
+	// qcom,bdf-addr = <0x4d500000>;
+	// qcom,caldb-addr = <0x4e500000>;
+	// qcom,m3-dump-addr = <0x4ea00000>;
+
+	qcom,ath11k-fw-memory-mode = <2>;
+	qcom,bdf-addr = <0x4d100000>;
+	qcom,m3-dump-addr = <0x4df00000>;
+
+	status = "ok";
+};

target/linux/ipq50xx/image/Makefile

@@ -31,6 +31,23 @@ define Device/UbiFit
   IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
 endef
 
+define Device/cmcc_rax3000q
+  $(call Device/FitImage)
+  $(call Device/UbiFit)
+  SOC := ipq5000
+  DEVICE_VENDOR := CMCC
+  DEVICE_MODEL := RAX3000Q
+  BLOCKSIZE := 128k
+  PAGESIZE := 2048
+  DEVICE_DTS_CONFIG := config@mp02.1
+  IMAGES := nand-factory.ubi
+  DEVICE_PACKAGES := \
+	ath11k-firmware-ipq5018 \
+	ath11k-firmware-qcn6122 \
+	ipq-wifi-cmcc_rax3000q
+endef
+TARGET_DEVICES += cmcc_rax3000q
+
 define Device/redmi_ax3000
   $(call Device/FitImage)
   $(call Device/UbiFit)