From e121f8e1b8f2d7cd07cbc93dec55c5d55f612277 Mon Sep 17 00:00:00 2001 From: hzy Date: Thu, 29 Jun 2023 04:53:33 +0000 Subject: [PATCH] ipq50xx: Add Qualcomm Atheros IPQ50xx target --- target/linux/ipq50xx/Makefile | 20 + target/linux/ipq50xx/aarch64/config-default | 73 + target/linux/ipq50xx/aarch64/target.mk | 5 + target/linux/ipq50xx/arm/config-default | 7 + target/linux/ipq50xx/arm/target.mk | 6 + .../base-files/lib/upgrade/platform.sh | 20 + target/linux/ipq50xx/config-5.15 | 1297 ++++++ target/linux/ipq50xx/dts/ipq5018.dtsi | 10 + target/linux/ipq50xx/image/Makefile | 34 + ...pha-pll-Add-support-for-Stromer-PLLs.patch | 256 ++ ...4-ipq5018-Add-binding-descriptions-f.patch | 360 ++ ...bal-Clock-controller-GCC-driver-for-.patch | 3910 +++++++++++++++++ ...trl-qcom-Add-ipq5018-pinctrl-binding.patch | 172 + ...ctrl-qcom-Add-IPQ5018-pinctrl-driver.patch | 964 ++++ ...d-ipq5018-SoC-and-MP03-board-support.patch | 314 ++ ...nfig-Enable-IPQ5018-SoC-base-configs.patch | 39 + ...-arm64-dts-qcom-ipq5018-Add-scm-node.patch | 30 + .../312-arm64-Kconfig-enable-qcom-scm.patch | 25 + .../321-firmware-qcom_scm-Disable-SDI.patch | 60 + ...4-dts-qcom-ipq5018-set-download-mode.patch | 37 + ...RM-mach-qcom-Add-support-for-IPQ50xx.patch | 42 + ...332-arm-dts-qcom-Add-ipq5018-support.patch | 52 + ...e-the-ecc-strength-from-device-param.patch | 51 + ...-compatible-used-in-linux-older-vers.patch | 37 + ...om-Add-initial-support-for-qspi-nand.patch | 397 ++ ...4-mtd-rawnand-qcom-Read-QPIC-version.patch | 60 + ...-Enable-support-for-erase-read-write.patch | 66 + ...-Update-bits-of-QPIC_NAND_FLASH_SPI_.patch | 88 + ...rivers-mtd-nand-add-SPI-NAND-devices.patch | 75 + ...arm64-dts-qcom-ipq5018-Add-nand-node.patch | 65 + 30 files changed, 8572 insertions(+) create mode 100644 target/linux/ipq50xx/Makefile create mode 100644 target/linux/ipq50xx/aarch64/config-default create mode 100644 target/linux/ipq50xx/aarch64/target.mk create mode 100644 target/linux/ipq50xx/arm/config-default create mode 100644 target/linux/ipq50xx/arm/target.mk create mode 100644 target/linux/ipq50xx/base-files/lib/upgrade/platform.sh create mode 100644 target/linux/ipq50xx/config-5.15 create mode 100644 target/linux/ipq50xx/dts/ipq5018.dtsi create mode 100644 target/linux/ipq50xx/image/Makefile create mode 100644 target/linux/ipq50xx/patches/301-clk-qcom-clk-alpha-pll-Add-support-for-Stromer-PLLs.patch create mode 100644 target/linux/ipq50xx/patches/302-dt-bindings-arm64-ipq5018-Add-binding-descriptions-f.patch create mode 100644 target/linux/ipq50xx/patches/303-clk-qcom-Add-Global-Clock-controller-GCC-driver-for-.patch create mode 100644 target/linux/ipq50xx/patches/304-dt-bindings-pinctrl-qcom-Add-ipq5018-pinctrl-binding.patch create mode 100644 target/linux/ipq50xx/patches/305-pinctrl-qcom-Add-IPQ5018-pinctrl-driver.patch create mode 100644 target/linux/ipq50xx/patches/306-arm64-dts-Add-ipq5018-SoC-and-MP03-board-support.patch create mode 100644 target/linux/ipq50xx/patches/307-arm64-defconfig-Enable-IPQ5018-SoC-base-configs.patch create mode 100644 target/linux/ipq50xx/patches/311-arm64-dts-qcom-ipq5018-Add-scm-node.patch create mode 100644 target/linux/ipq50xx/patches/312-arm64-Kconfig-enable-qcom-scm.patch create mode 100644 target/linux/ipq50xx/patches/321-firmware-qcom_scm-Disable-SDI.patch create mode 100644 target/linux/ipq50xx/patches/322-arm64-dts-qcom-ipq5018-set-download-mode.patch create mode 100644 target/linux/ipq50xx/patches/331-ARM-mach-qcom-Add-support-for-IPQ50xx.patch create mode 100644 target/linux/ipq50xx/patches/332-arm-dts-qcom-Add-ipq5018-support.patch create mode 100644 target/linux/ipq50xx/patches/401-mtd-nand-qcom-use-the-ecc-strength-from-device-param.patch create mode 100644 target/linux/ipq50xx/patches/402-mtd-nand-ipq-add-compatible-used-in-linux-older-vers.patch create mode 100644 target/linux/ipq50xx/patches/403-mtd-rawnand-qcom-Add-initial-support-for-qspi-nand.patch create mode 100644 target/linux/ipq50xx/patches/404-mtd-rawnand-qcom-Read-QPIC-version.patch create mode 100644 target/linux/ipq50xx/patches/405-mtd-rawnand-qcom-Enable-support-for-erase-read-write.patch create mode 100644 target/linux/ipq50xx/patches/406-mtd-rawnand-qcom-Update-bits-of-QPIC_NAND_FLASH_SPI_.patch create mode 100644 target/linux/ipq50xx/patches/407-drivers-mtd-nand-add-SPI-NAND-devices.patch create mode 100644 target/linux/ipq50xx/patches/411-arm64-dts-qcom-ipq5018-Add-nand-node.patch diff --git a/target/linux/ipq50xx/Makefile b/target/linux/ipq50xx/Makefile new file mode 100644 index 0000000000..10704315a2 --- /dev/null +++ b/target/linux/ipq50xx/Makefile @@ -0,0 +1,20 @@ +include $(TOPDIR)/rules.mk + +BOARD:=ipq50xx +BOARDNAME:=Qualcomm Atheros IPQ50XX +SUBTARGETS:=arm aarch64 + +CPU_TYPE:=cortex-a53 +FEATURES:=fpu ramdisk nand squashfs pcie + +KERNEL_PATCHVER:=5.15 + +include $(INCLUDE_DIR)/target.mk + +KERNELNAME:=Image dtbs + +DEFAULT_PACKAGES += \ + kmod-gpio-button-hotplug \ + uboot-envtools + +$(eval $(call BuildTarget)) diff --git a/target/linux/ipq50xx/aarch64/config-default b/target/linux/ipq50xx/aarch64/config-default new file mode 100644 index 0000000000..82b48c06fe --- /dev/null +++ b/target/linux/ipq50xx/aarch64/config-default @@ -0,0 +1,73 @@ +# CONFIG_32BIT is not set +CONFIG_64BIT=y +# CONFIG_ACPI is not set +# CONFIG_ARCH_BCM_IPROC is not set +# CONFIG_ARCH_EXYNOS7 is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y +# CONFIG_ARCH_LAYERSCAPE is not set +CONFIG_ARCH_PHYS_ADDR_T_64BIT=y +# CONFIG_ARCH_SEATTLE is not set +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +# CONFIG_ARCH_SPRD is not set +# CONFIG_ARCH_STRATIX10 is not set +# CONFIG_ARCH_THUNDER is not set +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_FRAME_POINTERS=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +# CONFIG_ARCH_XGENE is not set +# CONFIG_ARCH_ZYNQMP is not set +CONFIG_ARM64=y +# CONFIG_ARM64_16K_PAGES is not set +CONFIG_ARM64_4K_PAGES=y +# CONFIG_ARM64_64K_PAGES is not set +# CONFIG_ARM64_CRYPTO is not set +# CONFIG_ARM64_ERRATUM_819472 is not set +# CONFIG_ARM64_ERRATUM_824069 is not set +# CONFIG_ARM64_ERRATUM_826319 is not set +# CONFIG_ARM64_ERRATUM_827319 is not set +# CONFIG_ARM64_ERRATUM_832075 is not set +# CONFIG_ARM64_ERRATUM_843419 is not set +# CONFIG_ARM64_ERRATUM_845719 is not set +CONFIG_ARM64_HW_AFDBM=y +# CONFIG_ARM64_LSE_ATOMICS is not set +CONFIG_ARM64_PAN=y +# CONFIG_ARM64_PTDUMP is not set +# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +CONFIG_ARM64_VA_BITS=39 +CONFIG_ARM64_VA_BITS_39=y +# CONFIG_ARM64_VA_BITS_48 is not set +# CONFIG_ARMV8_DEPRECATED is not set +# CONFIG_CAVIUM_ERRATUM_22375 is not set +# CONFIG_CAVIUM_ERRATUM_23154 is not set +# CONFIG_CAVIUM_ERRATUM_27456 is not set +# CONFIG_COMMON_CLK_VERSATILE is not set +CONFIG_COMMON_CLK_XGENE=y +CONFIG_COMPAT=y +CONFIG_COMPAT_BINFMT_ELF=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_DEBUG_ALIGN_RODATA is not set +CONFIG_FRAME_WARN=2048 +# CONFIG_GPIO_XGENE is not set +# CONFIG_HUGETLBFS is not set +CONFIG_IPQ_APSS_5018=y +# CONFIG_I2C_CADENCE is not set +# CONFIG_KASAN is not set +# CONFIG_KVM is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_PCI_HISI is not set +CONFIG_PHYS_ADDR_T_64BIT=y +# CONFIG_PHY_XGENE is not set +# CONFIG_POWER_RESET_XGENE is not set +CONFIG_QCOM_SCM_64=y +# CONFIG_RTC_DRV_EFI is not set +CONFIG_SPARSEMEM=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_VIRTUALIZATION=y + +CONFIG_ZONE_DMA32=y diff --git a/target/linux/ipq50xx/aarch64/target.mk b/target/linux/ipq50xx/aarch64/target.mk new file mode 100644 index 0000000000..2eb8c9d2fe --- /dev/null +++ b/target/linux/ipq50xx/aarch64/target.mk @@ -0,0 +1,5 @@ +SUBTARGET:=aarch64 +BOARDNAME:=AArch64 64Bit + +ARCH:=aarch64 +CPU_TYPE:=cortex-a53 diff --git a/target/linux/ipq50xx/arm/config-default b/target/linux/ipq50xx/arm/config-default new file mode 100644 index 0000000000..45bbd44183 --- /dev/null +++ b/target/linux/ipq50xx/arm/config-default @@ -0,0 +1,7 @@ +CONFIG_ARCH_IPQ5018=y +CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_IPQ_APSS_5018=y +CONFIG_PCIE_DW_PLAT=y +# CONFIG_USB_QCOM_DIAG_BRIDGE is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_3G is not set diff --git a/target/linux/ipq50xx/arm/target.mk b/target/linux/ipq50xx/arm/target.mk new file mode 100644 index 0000000000..446a54e581 --- /dev/null +++ b/target/linux/ipq50xx/arm/target.mk @@ -0,0 +1,6 @@ +SUBTARGET:=arm +BOARDNAME:=ARM 32Bit + +ARCH:=arm +CPU_TYPE:=cortex-a7 +CPU_SUBTYPE:=neon-vfpv4 diff --git a/target/linux/ipq50xx/base-files/lib/upgrade/platform.sh b/target/linux/ipq50xx/base-files/lib/upgrade/platform.sh new file mode 100644 index 0000000000..adff896d2c --- /dev/null +++ b/target/linux/ipq50xx/base-files/lib/upgrade/platform.sh @@ -0,0 +1,20 @@ +. /lib/functions.sh + +platform_check_image() { + local board=$(board_name) + case $board in + *) + v "Sysupgrade is not supported on your board($board) yet." + return 1 + ;; + esac +} + +platform_do_upgrade() { + local board=$(board_name) + case $board in + *) + default_do_upgrade "$1" + ;; + esac +} diff --git a/target/linux/ipq50xx/config-5.15 b/target/linux/ipq50xx/config-5.15 new file mode 100644 index 0000000000..dc3fe7b76d --- /dev/null +++ b/target/linux/ipq50xx/config-5.15 @@ -0,0 +1,1297 @@ +# CONFIG_AC97_BUS is not set +# CONFIG_AC97_BUS_NEW is not set +# CONFIG_AD7124 is not set +# CONFIG_AD7606_IFACE_PARALLEL is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7768_1 is not set +# CONFIG_AD7949 is not set +# CONFIG_ADF4371 is not set +# CONFIG_ADIN_PHY is not set +# CONFIG_ADIS16460 is not set +# CONFIG_ADXL345_I2C is not set +# CONFIG_ADXL345_SPI is not set +# CONFIG_ADXL372_I2C is not set +# CONFIG_ADXL372_SPI is not set +# CONFIG_AHCI_IPQ is not set +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS is not set +# CONFIG_ALLOC_SKB_PAGE_FRAG_DISABLE is not set +# CONFIG_AL_FIC is not set +# CONFIG_AMBA_PL08X is not set +# CONFIG_ANDROID is not set +# CONFIG_ANDROID_LOW_MEMORY_KILLER is not set +# CONFIG_ANDROID_TIMED_OUTPUT is not set +# CONFIG_APM_EMULATION is not set +# CONFIG_APQ_GCC_8084 is not set +# CONFIG_APQ_MMCC_8084 is not set +CONFIG_AQUANTIA_PHY=y +# CONFIG_AR8216_PHY is not set +# CONFIG_ARCHES is not set +CONFIG_ARCH_32BIT_OFF_T=y +# CONFIG_ARCH_AGILEX is not set +# CONFIG_ARCH_BITMAIN is not set +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +CONFIG_ARCH_HAS_DMA_COHERENT_TO_PFN=y +CONFIG_ARCH_HAS_DMA_PREP_COHERENT=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# CONFIG_ARCH_HAS_KCOV is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_ARCH_HAS_PHYS_TO_DMA=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SG_CHAIN=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU=y +CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +# CONFIG_ARCH_IPQ6018 is not set +# CONFIG_ARCH_IPQ9574 is not set +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +# CONFIG_ARCH_MDM9615 is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +# CONFIG_ARCH_MILBEAUT is not set +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +# CONFIG_ARCH_MSM8960 is not set +# CONFIG_ARCH_MSM8974 is not set +CONFIG_ARCH_MSM8X60=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_NR_GPIO=0 +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_QCOM=y +# CONFIG_ARCH_RDA is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_ARCH_SUPPORTS_BIG_ENDIAN=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_ARM=y +# CONFIG_ARM64_CNP is not set +# CONFIG_ARM64_ERRATUM_1165522 is not set +# CONFIG_ARM64_ERRATUM_1286807 is not set +# CONFIG_ARM64_ERRATUM_1418040 is not set +# CONFIG_ARM64_ERRATUM_1542419 is not set +# CONFIG_ARM64_MODULE_PLTS is not set +# CONFIG_ARM64_PMEM is not set +# CONFIG_ARM64_PSEUDO_NMI is not set +# CONFIG_ARM64_PTDUMP_DEBUGFS is not set +# CONFIG_ARM64_PTR_AUTH is not set +# CONFIG_ARM64_SSBD is not set +# CONFIG_ARM64_SVE is not set +# CONFIG_ARM64_TAGGED_ADDR_ABI is not set +# CONFIG_ARM64_UAO is not set +# CONFIG_ARM64_VHE is not set +CONFIG_ARM_AMBA=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +# CONFIG_ARM_ATAG_DTB_COMPAT is not set +# CONFIG_ARM_CCI is not set +# CONFIG_ARM_CCI400_COMMON is not set +# CONFIG_ARM_CCI400_PMU is not set +# CONFIG_ARM_CCI_PMU is not set +CONFIG_ARM_CPUIDLE=y +CONFIG_ARM_CPU_SUSPEND=y +# CONFIG_ARM_ERRATA_814220 is not set +# CONFIG_ARM_ERRATA_857272 is not set +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_SG_CHAIN=y +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +# CONFIG_ARM_LPAE is not set +CONFIG_ARM_MODULE_PLTS=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_ARM_PMU=y +CONFIG_ARM_PSCI=y +# CONFIG_ARM_PSCI_CPUIDLE is not set +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_QCOM_CPUFREQ=y +# CONFIG_ARM_QCOM_CPUFREQ_HW is not set +# CONFIG_ARM_QCOM_CPUFREQ_NVMEM is not set +# CONFIG_ARM_SCMI_PROTOCOL is not set +# CONFIG_ARM_SMMU is not set +# CONFIG_ARM_SP805_WATCHDOG is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +# CONFIG_ASHMEM is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_AT803X_PHY=y +# CONFIG_ATA is not set +# CONFIG_BACKLIGHT_CLASS_DEVICE is not set +# CONFIG_BATTERY_RT5033 is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_NVME=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_BOUNCE=y +# CONFIG_BPFILTER is not set +# CONFIG_BPF_KPROBE_OVERRIDE is not set +# CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BT_HCIBTUSB_MTK is not set +# CONFIG_BT_MTKSDIO is not set +CONFIG_BUILD_BIN2C=y +# CONFIG_BUS_TOPOLOGY_ADHOC is not set +# CONFIG_CACHE_L2X0 is not set +# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_CC_STACKPROTECTOR=y +# CONFIG_CC_STACKPROTECTOR_NONE is not set +CONFIG_CC_STACKPROTECTOR_REGULAR=y +# CONFIG_CHARGER_LT3651 is not set +# CONFIG_CHARGER_QCOM_SMBB is not set +# CONFIG_CHARGER_UCS1002 is not set +CONFIG_CLEANCACHE=y +CONFIG_CLKDEV_LOOKUP=y +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_PROBE=y +CONFIG_CLKSRC_QCOM=y +CONFIG_CLONE_BACKWARDS=y +# CONFIG_CMA is not set +# CONFIG_CMA_ALIGNMENT is not set +# CONFIG_CMA_AREAS is not set +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SIZE_MBYTES is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +# CONFIG_CMA_SIZE_SEL_MBYTES is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +CONFIG_CNSS2=y +# CONFIG_CNSS2_CALIBRATION_SUPPORT is not set +# CONFIG_CNSS2_DEBUG is not set +CONFIG_CNSS2_GENL=y +# CONFIG_CNSS2_PCI_DRIVER is not set +# CONFIG_CNSS2_PM is not set +# CONFIG_CNSS2_RAMDUMP is not set +# CONFIG_CNSS2_SMMU is not set +# CONFIG_CNSS2_QCA9574_SUPPORT is not set +CONFIG_CNSS_QCN9000=y +CONFIG_COMMON_CLK=y +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +CONFIG_COMMON_CLK_QCOM=y +# CONFIG_COMMON_CLK_SI5341 is not set +CONFIG_CONFIGFS_FS=y +CONFIG_COREDUMP=y +CONFIG_CORESIGHT=y +# CONFIG_CORESIGHT_BYTE_CNTR is not set +# CONFIG_CORESIGHT_CATU is not set +# CONFIG_CORESIGHT_CPU_DEBUG is not set +CONFIG_CORESIGHT_CSR=y +CONFIG_CORESIGHT_CTI=y +# CONFIG_CORESIGHT_CTI_SAVE_DISABLE is not set +# CONFIG_CORESIGHT_DUMMY is not set +CONFIG_CORESIGHT_HWEVENT=y +CONFIG_CORESIGHT_LINKS_AND_SINKS=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +# CONFIG_CORESIGHT_REMOTE_ETM is not set +# CONFIG_CORESIGHT_SINK_ETBV10 is not set +# CONFIG_CORESIGHT_SINK_TPIU is not set +# CONFIG_CORESIGHT_SOURCE_ETM3X is not set +CONFIG_CORESIGHT_SOURCE_ETM4X=y +CONFIG_CORESIGHT_STM=y +CONFIG_CORESIGHT_TPDA=y +CONFIG_CORESIGHT_TPDM=y +# CONFIG_CORESIGHT_TPDM_DEFAULT_ENABLE is not set +# CONFIG_COUNTER is not set +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +# CONFIG_CPU_SW_DOMAIN_PAN is not set +# CONFIG_CPU_THERMAL is not set +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +# CONFIG_CRC32_SARWATE is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CRYPTO_ADIANTUM is not set +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_AES_586=y +# CONFIG_CRYPTO_ALL_CASES is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=y +CONFIG_CRYPTO_DISABLE_AES192_TEST=y +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_HISI_ZIP is not set +# CONFIG_CRYPTO_DEV_OTA_CRYPTO is not set +# CONFIG_CRYPTO_DEV_QCOM_ICE is not set +# CONFIG_CRYPTO_DEV_QCOM_MSM_QCE is not set +# CONFIG_CRYPTO_DEV_QCOM_RNG is not set +CONFIG_CRYPTO_DISABLE_AHASH_LARGE_KEY_TEST=y +CONFIG_CRYPTO_DISABLE_AHASH_TYPE1_TESTS=y +CONFIG_CRYPTO_DISABLE_AHASH_TYPE2_TESTS=y +CONFIG_CRYPTO_DISABLE_AHASH_TYPE3_TESTS=y +CONFIG_CRYPTO_DISABLE_AUTH_SPLIT_TESTS=y +CONFIG_CRYPTO_DISABLE_HW_UNSUPPORTED_TESTS=y +CONFIG_CRYPTO_DRBG_HMAC=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECHAINIV=y +# CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_ESSIV is not set +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +CONFIG_CRYPTO_JITTERENTROPY=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_SHA256=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set +CONFIG_CRYPTO_MD5_PPC=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_NO_ZERO_LEN_HASH=y +# CONFIG_CRYPTO_NO_AES_XTS_ZERO_KEY_SUPPORT is not set +# CONFIG_CRYPTO_NO_AES_CTR_UNEVEN_DATA_LEN_SUPPORT is not set +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +CONFIG_CRYPTO_OFB=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA1_PPC=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_STREEBOG is not set +CONFIG_CRYPTO_WORKQUEUE=y +CONFIG_CRYPTO_XTS=y +# CONFIG_CRYPTO_XXHASH is not set +CONFIG_CRYPTO_XZ=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_EFI is not set +CONFIG_DEBUG_GPIO=y +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN is not set +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +# CONFIG_DEBUG_MISC is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_UART_8250 is not set +# CONFIG_DEBUG_USER is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEVMEM=y +# CONFIG_DIAGFWD_BRIDGE_CODE is not set +CONFIG_DIAG_OVER_QRTR=y +# CONFIG_DIAG_OVER_USB is not set +CONFIG_DMADEVICES=y +# CONFIG_DMA_CMA is not set +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +# CONFIG_DMA_SOUND is not set +CONFIG_DMA_VIRTUAL_CHANNELS=y +# CONFIG_DMI is not set +# CONFIG_DMIID is not set +# CONFIG_DMI_SYSFS is not set +# CONFIG_DM_INIT is not set +# CONFIG_DP83640_PHY is not set +# CONFIG_DPS310 is not set +CONFIG_DTC=y +# CONFIG_DWMAC_GENERIC is not set +# CONFIG_DWMAC_IPQ806X is not set +# CONFIG_DWMAC_SUNXI is not set +# CONFIG_DW_DMAC_PCI is not set +CONFIG_DYNAMIC_DEBUG=y +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EEPROM_EE1004 is not set +# CONFIG_EFI_ARMSTUB_DTB_LOADER is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_ENERGY_MODEL is not set +# CONFIG_EP_PCIE is not set +CONFIG_ETHERNET_PACKET_MANGLE=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_EXT4_FS=y +# CONFIG_EXT4_USE_FOR_EXT2 is not set +# CONFIG_EXTCON_FSA9480 is not set +CONFIG_FB=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_CMDLINE=y +# CONFIG_FB_EFI is not set +CONFIG_FB_QTI_QPIC=y +CONFIG_FB_QTI_QPIC_ER_SSD1963_PANEL=y +CONFIG_FB_SYS_FOPS=y +# CONFIG_FIPS_ENABLE is not set +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +# CONFIG_FSL_MC_BUS is not set +# CONFIG_FSL_QDMA is not set +CONFIG_FS_MBCACHE=y +# CONFIG_FS_VERITY is not set +# CONFIG_FUJITSU_ERRATUM_010001 is not set +CONFIG_FW_AUTH=y +CONFIG_FW_AUTH_TEST=m +# CONFIG_FW_LOADER_COMPRESS is not set +# CONFIG_FXAS21002C is not set +# CONFIG_FXOS8700_I2C is not set +# CONFIG_FXOS8700_SPI is not set +# CONFIG_GCC_PLUGINS is not set +# CONFIG_GCC_PLUGIN_CYC_COMPLEXITY is not set +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL is not set +# CONFIG_GCC_PLUGIN_STRUCTLEAK_USER is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +# CONFIG_GENERIC_CPUFREQ_KRAIT is not set +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IO=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +# CONFIG_GEN_RTC is not set +# CONFIG_GLACIER is not set +# CONFIG_GLINK_DEBUG_FS is not set +CONFIG_GPIOLIB=y +CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_GPIO_AMD_FCH is not set +# CONFIG_GPIO_CADENCE is not set +CONFIG_GPIO_DEVRES=y +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_LATCH is not set +# CONFIG_GPIO_NXP_74HC153 is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +CONFIG_GPIO_SYSFS=y +# CONFIG_GPIO_USB_DETECT is not set +# CONFIG_GSI is not set +# CONFIG_HABANA_AI is not set +CONFIG_HANDLE_DOMAIN_IRQ=y +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_HAVE_ARCH_BITREVERSE=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_ARM_ARCH_TIMER=y +# CONFIG_HAVE_ARM_SMCCC is not set +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_HAVE_BPF_JIT=y +CONFIG_HAVE_CC_STACKPROTECTOR=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_IDE=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_XZ=y +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +CONFIG_HAVE_MEMBLOCK=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_HAVE_NET_DSA=y +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_OPTPROBES is not set +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_SMP=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_UID16=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_HEADERS_INSTALL is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_VIEWSONIC is not set +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +# CONFIG_HIST_TRIGGERS is not set +CONFIG_HOTPLUG_CPU=y +CONFIG_HWSPINLOCK=y +CONFIG_HWSPINLOCK_QCOM=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_MSM_LEGACY=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_HELPER_AUTO=y +# CONFIG_I2C_NVIDIA_GPU is not set +CONFIG_I2C_QUP=y +# CONFIG_I3C is not set +# CONFIG_IGC is not set +CONFIG_IIO=y +# CONFIG_IIO_BUFFER is not set +# CONFIG_IIO_TRIGGER is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +# CONFIG_IKHEADERS is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INPUT_GPIO_VIBRA is not set +# CONFIG_INPUT_MSM_VIBRATOR is not set +# CONFIG_INPUT_PM8941_PWRKEY is not set +# CONFIG_INPUT_PM8XXX_VIBRATOR is not set +# CONFIG_INTERCONNECT is not set +CONFIG_IOMMU_HELPER=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set +# CONFIG_ION is not set +# CONFIG_ION_DUMMY is not set +# CONFIG_ION_MSM is not set +# CONFIG_ION_TEST is not set +# CONFIG_IO_URING is not set +# CONFIG_IPA is not set +# CONFIG_IPA3 is not set +# CONFIG_IPC_LOGGING is not set +# CONFIG_IPC_ROUTER is not set +# CONFIG_IPC_ROUTER_SECURITY is not set +# CONFIG_IPQ807X_REMOTEPROC is not set +# CONFIG_IPQ_ADCC_4019 is not set +# CONFIG_IPQ_ADSS_8074 is not set +# CONFIG_IPQ_APSS_PLL is not set +CONFIG_IPQ_APSS_5018=y +# CONFIG_IPQ_APSS_6018 is not set +# CONFIG_IPQ_APSS_8074 is not set +# CONFIG_IPQ_DWC3_QTI_EXTCON is not set +# CONFIG_IPQ_FLASH_16M_PROFILE is not set +# CONFIG_IPQ_GCC_4019 is not set +CONFIG_IPQ_GCC_5018=y +# CONFIG_IPQ_GCC_6018 is not set +# CONFIG_IPQ_GCC_806X is not set +# CONFIG_IPQ_GCC_8074 is not set +# CONFIG_IPQ_GCC_9574 is not set +# CONFIG_IPQ_LCC_806X is not set +# CONFIG_IPQ_REMOTEPROC_ADSP is not set +CONFIG_IPQ_SUBSYSTEM_DUMP=y +CONFIG_IPQ_SUBSYSTEM_RAMDUMP=y +# CONFIG_IPQ_SUBSYSTEM_RESTART is not set +# CONFIG_IPQ_SUBSYSTEM_RESTART_TEST is not set +CONFIG_IPQ_TCSR=y +CONFIG_IRQCHIP=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +# CONFIG_KCOV is not set +CONFIG_KEYS=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_KPSS_XCC is not set +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +# CONFIG_KRAITCC is not set +# CONFIG_KRAIT_CLOCKS is not set +# CONFIG_KRAIT_L2_ACCESSORS is not set +# CONFIG_LCD_CLASS_DEVICE is not set +# CONFIG_LEDS_AN30259A is not set +CONFIG_LEDS_IPQ=y +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_PCA9956B is not set +CONFIG_LEDS_TLC591XX=y +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +CONFIG_LIBFDT=y +CONFIG_LOCKUP_DETECTOR=y +# CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LSM="lockdown,yama,loadpin,safesetid,integrity" +# CONFIG_LTC1660 is not set +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_MAILBOX=y +# CONFIG_MAILBOX_TEST is not set +# CONFIG_MAP_E_SUPPORT is not set +# CONFIG_MAX31856 is not set +# CONFIG_MAX44009 is not set +# CONFIG_MAX5432 is not set +# CONFIG_MB1232 is not set +# CONFIG_MCP3911 is not set +# CONFIG_MCP41010 is not set +CONFIG_MDIO=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BOARDINFO=y +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_GPIO=y +CONFIG_MDIO_QCA=y +# CONFIG_MDM_GCC_9615 is not set +# CONFIG_MDM_LCC_9615 is not set +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_MAX77650 is not set +# CONFIG_MFD_QCOM_RPM is not set +# CONFIG_MFD_ROHM_BD70528 is not set +# CONFIG_MFD_SPMI_PMIC is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_STPMIC1 is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TQMX86 is not set +CONFIG_MHI_BUS=y +CONFIG_MHI_BUS_DEBUG=y +CONFIG_MHI_NETDEV=y +CONFIG_MHI_QTI=y +# CONFIG_MHI_SATELLITE is not set +CONFIG_MHI_UCI=y +CONFIG_MHI_WWAN_CTRL=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_MIGRATION=y +# CONFIG_MIKROTIK is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MMAP_ALLOW_UNINITIALIZED is not set +CONFIG_MMC=y +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=32 +CONFIG_MMC_QCOM_DML=y +CONFIG_MMC_SDHCI=y +# CONFIG_MMC_SDHCI_AM654 is not set +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +CONFIG_MMC_SDHCI_MSM=y +# CONFIG_MMC_SDHCI_MSM_ICE is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_ASPEED is not set +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +# CONFIG_MMC_STM32_SDMMC is not set +# CONFIG_MMC_TIFM_SD is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_MODULES_USE_ELF_REL=y +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_MPLS_ROUTING is not set +# CONFIG_MSM_ADSPRPC is not set +# CONFIG_MSM_BUS_SCALING is not set +# CONFIG_MSM_GCC_8660 is not set +# CONFIG_MSM_GCC_8916 is not set +# CONFIG_MSM_GCC_8960 is not set +# CONFIG_MSM_GCC_8974 is not set +# CONFIG_MSM_GCC_8994 is not set +# CONFIG_MSM_GCC_8996 is not set +# CONFIG_MSM_GCC_8998 is not set +# CONFIG_MSM_GLINK is not set +# CONFIG_MSM_GLINK_LOOPBACK_SERVER is not set +# CONFIG_MSM_GLINK_PKT is not set +# CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT is not set +# CONFIG_MSM_IPC_ROUTER_GLINK_XPRT is not set +# CONFIG_MSM_IPC_ROUTER_MHI_XPRT is not set +# CONFIG_MSM_LCC_8960 is not set +# CONFIG_MSM_MHI is not set +# CONFIG_MSM_MHI_DEBUG is not set +# CONFIG_MSM_MHI_DEV is not set +# CONFIG_MSM_MHI_UCI is not set +# CONFIG_MSM_MMCC_8960 is not set +# CONFIG_MSM_MMCC_8974 is not set +# CONFIG_MSM_MMCC_8996 is not set +# CONFIG_MSM_QMI_INTERFACE is not set +# CONFIG_MSM_RPM_GLINK is not set +# CONFIG_MSM_RPM_LOG is not set +CONFIG_MSM_RPM_RPMSG=y +# CONFIG_MSM_RPM_SMD is not set +# CONFIG_MSM_SECURE_BUFFER is not set +# CONFIG_MSM_SMEM is not set +# CONFIG_MSM_TEST_QMI_CLIENT is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_HYPERBUS is not set +CONFIG_MTD_M25P80=y +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_QCOM=y +# CONFIG_MTD_NAND_QCOM_SERIAL is not set +CONFIG_MTD_RAW_NAND=y +# CONFIG_MTD_ROUTERBOOT_PARTS is not set +CONFIG_MTD_SPINAND_GIGADEVICE=y +CONFIG_MTD_SPINAND_MT29F=y +CONFIG_MTD_SPINAND_ONDIEECC=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y +CONFIG_MTD_SPI_NOR_USE_4K_SECTORS_LIMIT=65536 +# CONFIG_MTD_SPLIT_BCM_WFI_FW is not set +# CONFIG_MTD_SPLIT_ELF_FW is not set +CONFIG_MTD_SPLIT_FIRMWARE=y +CONFIG_MTD_SPLIT_FIT_FW=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BEB_LIMIT=20 +CONFIG_MTD_UBI_BLOCK=y +# CONFIG_MTD_UBI_FASTMAP is not set +CONFIG_MTD_UBI_GLUEBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MULTI_IRQ_HANDLER=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEON=y +CONFIG_NET=y +# CONFIG_NET_DSA_MV88E6063 is not set +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NF_CONNTRACK_DSCPREMARK_EXT is not set +# CONFIG_NF_IPV6_DUMMY_HEADER is not set +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +# CONFIG_NOA1305 is not set +CONFIG_NO_BOOTMEM=y +CONFIG_NO_HZ=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +# CONFIG_NULL_TTY is not set +# CONFIG_NUMA is not set +CONFIG_NUM_ALT_PARTITION=16 +CONFIG_NVMEM=y +# CONFIG_NVMEM_REBOOT_MODE is not set +# CONFIG_NVMEM_SYSFS is not set +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_TCP is not set +# CONFIG_OCTEONTX2_AF is not set +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_ADDRESS_PCI=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_MTD=y +CONFIG_OF_NET=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_RESERVED_MEM=y +# CONFIG_OF_SLIMBUS is not set +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +# CONFIG_OPTIMIZE_INLINING is not set +# CONFIG_PACKING is not set +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PANIC_ON_OOPS=y +CONFIG_PANIC_ON_OOPS_VALUE=1 +CONFIG_PANIC_TIMEOUT=5 +CONFIG_PCI=y +# CONFIG_PCIEAER is not set +# CONFIG_PCIE_AL is not set +# CONFIG_PCIE_CADENCE_EP is not set +CONFIG_PCIE_DW=y +CONFIG_PHY_IPQ_UNIPHY_PCIE=y +# CONFIG_PCIE_DW_PLAT is not set +# CONFIG_PCIE_PME is not set +CONFIG_PCIE_QCOM=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_DOMAINS_GENERIC=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MSI=y +CONFIG_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y +# CONFIG_PFT is not set +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +# CONFIG_PHY_CADENCE_DP is not set +# CONFIG_PHY_CADENCE_DPHY is not set +# CONFIG_PHY_CADENCE_SIERRA is not set +# CONFIG_PHY_FSL_IMX8MQ_USB is not set +# CONFIG_PHY_IPQ_BALDUR_USB is not set +# CONFIG_PHY_IPQ_UNIPHY_USB is not set +# CONFIG_PHY_MIXEL_MIPI_DPHY is not set +# CONFIG_PHY_OCELOT_SERDES is not set +# CONFIG_PHY_QCA_PCIE_QMP is not set +# CONFIG_PHY_QCOM_APQ8064_SATA is not set +# CONFIG_PHY_QCOM_IPQ806X_SATA is not set +# CONFIG_PHY_QCOM_PCIE2 is not set +# CONFIG_PHY_QCOM_QMP is not set +# CONFIG_PHY_QCOM_QUSB2 is not set +# CONFIG_PHY_QCOM_UFS is not set +CONFIG_PINCTRL=y +# CONFIG_PINCTRL_APQ8064 is not set +# CONFIG_PINCTRL_APQ8084 is not set +# CONFIG_PINCTRL_IPQ4019 is not set +CONFIG_PINCTRL_IPQ5018=y +# CONFIG_PINCTRL_IPQ6018 is not set +# CONFIG_PINCTRL_IPQ8064 is not set +# CONFIG_PINCTRL_IPQ8074 is not set +# CONFIG_PINCTRL_IPQ9574 is not set +# CONFIG_PINCTRL_MDM9615 is not set +CONFIG_PINCTRL_MSM=y +# CONFIG_PINCTRL_MSM8660 is not set +# CONFIG_PINCTRL_MSM8916 is not set +# CONFIG_PINCTRL_MSM8960 is not set +# CONFIG_PINCTRL_MSM8994 is not set +# CONFIG_PINCTRL_MSM8996 is not set +# CONFIG_PINCTRL_MSM8998 is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set +# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set +# CONFIG_PINCTRL_QCS404 is not set +# CONFIG_PINCTRL_SC7180 is not set +# CONFIG_PINCTRL_SDM660 is not set +# CONFIG_PINCTRL_SDM845 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SM8150 is not set +# CONFIG_PINCTRL_STMFX is not set +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_PKCS7_MESSAGE_PARSER is not set +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +# CONFIG_PL330_DMA is not set +CONFIG_PM=y +# CONFIG_PM8916_WATCHDOG is not set +CONFIG_PM_CLK=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_RESET_MSM is not set +# CONFIG_POWER_RESET_QCOM_PON is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_PPS=y +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_RCU=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_PRINTK_TIME=y +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_PROC_STRIPPED is not set +# CONFIG_PSI is not set +CONFIG_PTP_1588_CLOCK=y +CONFIG_PUBLIC_KEY_ALGO_RSA=y +# CONFIG_PVPANIC is not set +CONFIG_PWM=y +CONFIG_PWM_IPQ=y +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_SYSFS=y +# CONFIG_PWRSEQ_EMMC is not set +CONFIG_PWRSEQ_IPQ=y +# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_QCA_MINIDUMP=y +# CONFIG_QCA_MINIDUMP_DEBUG is not set +# CONFIG_QCOM_A53PLL is not set +CONFIG_QCOM_ADM=y +# CONFIG_QCOM_AOSS_QMP is not set +CONFIG_QCOM_APCS_IPC=y +# CONFIG_QCOM_APM is not set +# CONFIG_QCOM_APR is not set +CONFIG_QCOM_BAM_DMA=y +CONFIG_QCOM_CACHE_DUMP=y +CONFIG_QCOM_CACHE_DUMP_ON_PANIC=y +# CONFIG_QCOM_CLK_APCS_MSM8916 is not set +# CONFIG_QCOM_CLK_RPM is not set +# CONFIG_QCOM_COINCELL is not set +# CONFIG_QCOM_COMMAND_DB is not set +CONFIG_QCOM_DLOAD_MODE=y +CONFIG_QCOM_DLOAD_MODE_APPSBL=y +# CONFIG_QCOM_EBI2 is not set +# CONFIG_QCOM_FASTRPC is not set +CONFIG_QCOM_GDSC=y +# CONFIG_QCOM_GENI_SE is not set +CONFIG_QCOM_GLINK_SSR=y +# CONFIG_QCOM_GSBI is not set +# CONFIG_QCOM_HFPLL is not set +# CONFIG_QCOM_LLCC is not set +# CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PM is not set +# CONFIG_QCOM_Q6V5_ADSP is not set +CONFIG_QCOM_Q6V5_MPD=y +# CONFIG_QCOM_Q6V5_MSS is not set +# CONFIG_QCOM_Q6V5_PAS is not set +CONFIG_QCOM_Q6V5_WCSS=y +CONFIG_QCOM_QFPROM=y +CONFIG_QCOM_QMI_HELPERS=y +CONFIG_QCOM_RESTART_REASON=y +# CONFIG_QCOM_RMTFS_MEM is not set +# CONFIG_QCOM_RPMH is not set +CONFIG_QCOM_RPM_CLK=y +# CONFIG_QCOM_RTB is not set +CONFIG_QCOM_SCM=y +CONFIG_QCOM_SCM_32=y +# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set +# CONFIG_QCOM_SMD is not set +# CONFIG_QCOM_SMD_RPM is not set +CONFIG_QCOM_SMEM=y +CONFIG_QCOM_SMEM_STATE=y +CONFIG_QCOM_SMP2P=y +# CONFIG_QCOM_SMSM is not set +CONFIG_QCOM_SOCINFO=y +# CONFIG_QCOM_SPMI_ADC5 is not set +# CONFIG_QCOM_SPMI_TEMP_ALARM is not set +# CONFIG_QCOM_SPMI_VADC is not set +CONFIG_QCOM_SYSMON=y +CONFIG_QCOM_TSENS=y +# CONFIG_QCOM_WCNSS_CTRL is not set +# CONFIG_QCOM_WCNSS_PIL is not set +CONFIG_QCOM_WDT=y +# CONFIG_QCS_GCC_404 is not set +# CONFIG_QCS_TURING_404 is not set +CONFIG_QMI_ENCDEC=y +# CONFIG_QPNP_REVID is not set +CONFIG_QRTR=y +# CONFIG_QRTR_FIFO is not set +CONFIG_QRTR_MHI=y +CONFIG_QRTR_SMD=y +# CONFIG_QRTR_TUN is not set +# CONFIG_QRTR_USB is not set +CONFIG_QSEECOM=m +# CONFIG_QTI_APSS_ACC is not set +CONFIG_QTI_CTXT_SAVE=y +CONFIG_QTI_DCC=y +CONFIG_QTI_EUD=y +# CONFIG_EUD_EXTCON_SUPPORT is not set +# CONFIG_QTI_DCC_V2 is not set +# CONFIG_QTI_MEMORY_DUMP_V2 is not set +CONFIG_QTI_SCM_RESTART_REASON=y +CONFIG_QTI_TZ_LOG=y +# CONFIG_RANDOMIZE_BASE is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set +CONFIG_RATIONAL=y +# CONFIG_RCU_BOOST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +# CONFIG_RCU_EXPERT is not set +CONFIG_RCU_STALL_COMMON=y +CONFIG_RD_GZIP=y +# CONFIG_REED_SOLOMON_TEST is not set +CONFIG_REGMAP=y +CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_CPR3 is not set +# CONFIG_REGULATOR_CPR3_NPU is not set +# CONFIG_REGULATOR_CPR4_APSS is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_IPQ40XX is not set +# CONFIG_REGULATOR_QCOM_RPM is not set +# CONFIG_REGULATOR_QCOM_SPMI is not set +CONFIG_REGULATOR_RPM_GLINK=y +# CONFIG_REGULATOR_RPM_SMD is not set +CONFIG_RELAY=y +CONFIG_REMOTEPROC=y +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_QCOM_AOSS is not set +# CONFIG_RESET_QCOM_PDC is not set +CONFIG_RFS_ACCEL=y +# CONFIG_RMNET is not set +# CONFIG_RMNET_DATA is not set +# CONFIG_RMNET_DATA_DEBUG_PKT is not set +# CONFIG_RMNET_DATA_FC is not set +# CONFIG_RODATA_FULL_DEFAULT_ENABLED is not set +CONFIG_RPMSG=y +CONFIG_RPMSG_CHAR=y +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +CONFIG_RPMSG_QCOM_GLINK_SMEM=y +CONFIG_RPMSG_QCOM_SMD=y +# CONFIG_RPMSG_VIRTIO is not set +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_PM8XXX is not set +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_RWSEM_XCHGADD_ALGORITHM=y +CONFIG_SAMPLES=y +# CONFIG_SAMPLE_CONFIGFS is not set +# CONFIG_SAMPLE_HW_BREAKPOINT is not set +# CONFIG_SAMPLE_KFIFO is not set +# CONFIG_SAMPLE_KOBJECT is not set +# CONFIG_SAMPLE_KPROBES is not set +# CONFIG_SAMPLE_KRETPROBES is not set +CONFIG_SAMPLE_QMI_CLIENT=m +# CONFIG_SAMPLE_RPMSG_CLIENT is not set +CONFIG_SAMPLE_TRACE_EVENTS=y +# CONFIG_SAMPLE_TRACE_PRINTK is not set +# CONFIG_SAMPLE_VFIO_MDEV_MDPY_FB is not set +# CONFIG_SATA_AHCI is not set +CONFIG_SCHED_HRTICK=y +# CONFIG_SCHED_INFO is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_MYRS is not set +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SDM_CAMCC_845 is not set +# CONFIG_SDM_DISPCC_845 is not set +# CONFIG_SDM_GCC_660 is not set +# CONFIG_SDM_GCC_845 is not set +# CONFIG_SDM_GPUCC_845 is not set +# CONFIG_SDM_LPASSCC_845 is not set +# CONFIG_SDM_VIDEOCC_845 is not set +# CONFIG_SEEMP_CORE is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSORS_DRIVETEMP is not set +# CONFIG_SENSORS_OCC_P8_I2C is not set +# CONFIG_SENSORS_RM3100_I2C is not set +# CONFIG_SENSORS_RM3100_SPI is not set +# CONFIG_SERIAL_8250 is not set +# CONFIG_SERIAL_8250_CONSOLE is not set +# CONFIG_SERIAL_8250_DMA is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +CONFIG_SERIAL_MSM=y +CONFIG_SERIAL_MSM_CONSOLE=y +# CONFIG_SERIAL_SIFIVE is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SKB_RECYCLER=y +CONFIG_SKB_RECYCLER_MULTI_CPU=y +# CONFIG_SKB_RECYCLER_PREALLOC is not set +# CONFIG_SLIMBUS is not set +# CONFIG_SLIMBUS_MSM_CTRL is not set +# CONFIG_SLIMBUS_MSM_NGD is not set +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +# CONFIG_SM_GCC_8150 is not set +CONFIG_SND=y +# CONFIG_SND_AOA is not set +# CONFIG_SND_COMPRESS_OFFLOAD is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_PCM is not set +# CONFIG_SND_PROC_FS is not set +CONFIG_SND_SOC=y +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_APQ8016_SBC is not set +# CONFIG_SND_SOC_CS35L36 is not set +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CX2072X is not set +# CONFIG_SND_SOC_DMIC is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_I2C_AND_SPI is not set +CONFIG_SND_SOC_IPQ=y +# CONFIG_SND_SOC_IPQ_ADSS is not set +# CONFIG_SND_SOC_IPQ_CODEC is not set +# CONFIG_SND_SOC_IPQ_CPU_DAI is not set +# CONFIG_SND_SOC_IPQ_MBOX is not set +CONFIG_SND_SOC_IPQ_LPASS=y +CONFIG_SND_SOC_IPQ_LPASS_PCM_RAW=y +# CONFIG_SND_SOC_IPQ_PCM_I2S is not set +# CONFIG_SND_SOC_IPQ_PCM_TDM is not set +# CONFIG_SND_SOC_IPQ_PCM_RAW is not set +# CONFIG_SND_SOC_IPQ_STEREO is not set +# CONFIG_SND_SOC_MAX98088 is not set +# CONFIG_SND_SOC_MAX98357A is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_NAU8822 is not set +# CONFIG_SND_SOC_PCM3060_I2C is not set +# CONFIG_SND_SOC_PCM3060_SPI is not set +CONFIG_SND_SOC_QCOM=y +# CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_SOF_TOPLEVEL is not set +# CONFIG_SND_SOC_STORM is not set +# CONFIG_SND_SOC_UDA1334 is not set +# CONFIG_SND_SOC_WM8904 is not set +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE_PRECLAIM is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPI=y +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +# CONFIG_SPI_MTK_QUADSPI is not set +# CONFIG_SPI_QCOM_QSPI is not set +CONFIG_SPI_QUP=y +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_VSC7385 is not set +# CONFIG_SPMI is not set +# CONFIG_SPMI_MSM_PMIC_ARB is not set +# CONFIG_SPMI_PMIC_CLKDIV is not set +CONFIG_SPS=y +# CONFIG_SPS30 is not set +# CONFIG_SPS_SUPPORT_BAMDMA is not set +CONFIG_SPS_SUPPORT_NDP_BAM=y +CONFIG_SRCU=y +# CONFIG_SRD_TRACE is not set +# CONFIG_STAGING is not set +# CONFIG_STM_PROTO_BASIC is not set +# CONFIG_STM_PROTO_SYS_T is not set +# CONFIG_STM_SOURCE_FTRACE is not set +# CONFIG_STM_SOURCE_HEARTBEAT is not set +# CONFIG_STOPWATCH is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +CONFIG_SUSPEND=y +# CONFIG_SWAP is not set +CONFIG_SWCONFIG=y +CONFIG_SWIOTLB=y +CONFIG_SWP_EMULATE=y +# CONFIG_SW_SYNC is not set +# CONFIG_SYNC is not set +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +# CONFIG_TEST_BLACKHOLE_DEV is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_VMALLOC is not set +# CONFIG_TEST_XARRAY is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_GOV_STEP_WISE=y +CONFIG_THERMAL_GOV_USER_SPACE=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_OF=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +# CONFIG_THUMB2_KERNEL is not set +# CONFIG_TICK_CPU_ACCOUNTING is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS8344 is not set +# CONFIG_TI_CPSW_PHY_SEL is not set +# CONFIG_TI_DAC7311 is not set +# CONFIG_TI_DAC7612 is not set +CONFIG_TRACING_EVENTS_GPIO=y +# CONFIG_TRUSTED_FOUNDATIONS is not set +CONFIG_UBIFS_FS=y +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_XATTR=y +CONFIG_UBIFS_FS_XZ=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_ZSTD is not set +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_UNICODE is not set +CONFIG_UNINLINE_SPIN_UNLOCK=y +# CONFIG_UNMAP_KERNEL_AT_EL0 is not set +CONFIG_UNWINDER_ARM=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +# CONFIG_USB_BAM is not set +CONFIG_USB_CONFIGFS=y +# CONFIG_USB_CONFIGFS_ACM is not set +# CONFIG_USB_CONFIGFS_ECM is not set +# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set +# CONFIG_USB_CONFIGFS_EEM is not set +# CONFIG_USB_CONFIGFS_F_DIAG is not set +# CONFIG_USB_CONFIGFS_F_FS is not set +# CONFIG_USB_CONFIGFS_F_HID is not set +# CONFIG_USB_CONFIGFS_F_LB_SS is not set +# CONFIG_USB_CONFIGFS_F_MIDI is not set +# CONFIG_USB_CONFIGFS_F_PRINTER is not set +# CONFIG_USB_CONFIGFS_F_QDSS is not set +# CONFIG_USB_CONFIGFS_F_UAC1 is not set +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +# CONFIG_USB_CONFIGFS_F_UAC2 is not set +# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set +# CONFIG_USB_CONFIGFS_NCM is not set +# CONFIG_USB_CONFIGFS_OBEX is not set +# CONFIG_USB_CONFIGFS_RNDIS is not set +# CONFIG_USB_CONFIGFS_SERIAL is not set +# CONFIG_USB_CONN_GPIO is not set +# CONFIG_USB_DWC3_OF_SIMPLE is not set +# CONFIG_USB_EHCI_FSL is not set +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_GADGET is not set +# CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_OHCI_LITTLE_ENDIAN is not set +CONFIG_USB_QCA_M31_PHY=y +# CONFIG_USB_QCOM_8X16_PHY is not set +# CONFIG_USB_QCOM_QMP_PHY is not set +# CONFIG_USB_QCOM_QUSB_PHY is not set +CONFIG_USB_SUPPORT=y +CONFIG_USE_OF=y +# CONFIG_U_SERIAL_CONSOLE is not set +# CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCNL4035 is not set +CONFIG_VDSO=y +CONFIG_VECTORS_BASE=0xffff0000 +# CONFIG_VFIO is not set +CONFIG_VFP=y +CONFIG_VFPv3=y +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +# CONFIG_VHOST_NET is not set +# CONFIG_VIRT_WIFI is not set +# CONFIG_VIRTIO_BLK is not set +# CONFIG_VIRTIO_CONSOLE is not set +# CONFIG_VIRTIO_FS is not set +# CONFIG_VIRTIO_NET is not set +# CONFIG_VL53L0X_I2C is not set +# CONFIG_VMAP_STACK is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WL_TI is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_WWAN=y +CONFIG_WWAN_CORE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_XILINX_SDFEC is not set +# CONFIG_XILINX_XADC is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0 +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA_FLAG=0 +# CONFIG_DEBUG_MEM_USAGE is not set + +# CONFIG_ARCH_IPQ40XX is not set +# CONFIG_ARM_QCOM_SPM_CPUIDLE is not set +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_FW_CACHE=y +# CONFIG_MTD_QCOMSMEM_PARTS is not set +# CONFIG_I2C_QCOM_CCI is not set +# CONFIG_PINCTRL_MSM8226 is not set +# CONFIG_PINCTRL_MSM8976 is not set +# CONFIG_PINCTRL_SM8250 is not set +# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set +# CONFIG_SND_SOC_SC7180 is not set +# CONFIG_QCOM_CLK_APCS_SDX55 is not set +# CONFIG_MSM_GCC_8939 is not set +# CONFIG_MSM_GPUCC_8998 is not set +# CONFIG_MSM_MMCC_8998 is not set +# CONFIG_SC_DISPCC_7180 is not set +# CONFIG_SC_GCC_7180 is not set +# CONFIG_SC_LPASS_CORECC_7180 is not set +# CONFIG_SC_GPUCC_7180 is not set +# CONFIG_SC_MSS_7180 is not set +# CONFIG_SC_VIDEOCC_7180 is not set +# CONFIG_QCS_Q6SSTOP_404 is not set +# CONFIG_SM_GCC_8250 is not set +# CONFIG_SM_GPUCC_8150 is not set +# CONFIG_SM_GPUCC_8250 is not set +# CONFIG_SM_VIDEOCC_8150 is not set +# CONFIG_SM_VIDEOCC_8250 is not set +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_QCOM_IPCC is not set +# CONFIG_REMOTEPROC_CDEV is not set +# CONFIG_RPMSG_NS is not set +# CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_OCMEM is not set +# CONFIG_PHY_QCOM_IPQ4019_USB is not set +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_SS is not set +# CONFIG_NVMEM_QCOM_QFPROM is not set +# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set +# CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE is not set +# CONFIG_SAMPLE_AUXDISPLAY is not set +# CONFIG_SAMPLE_WATCHDOG is not set +# CONFIG_CORESIGHT_CTI_INTEGRATION_REGS is not set + +CONFIG_ARCH_IPQ50XX=y +CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT=y +# CONFIG_MTD_UBI_GLUEBI is not set diff --git a/target/linux/ipq50xx/dts/ipq5018.dtsi b/target/linux/ipq50xx/dts/ipq5018.dtsi new file mode 100644 index 0000000000..cd150613ea --- /dev/null +++ b/target/linux/ipq50xx/dts/ipq5018.dtsi @@ -0,0 +1,10 @@ +#ifdef __ARM32__ + // Search in arch/arm/boot/dts/ + #include <../../../arm64/boot/dts/qcom/ipq5018.dtsi> + #include +#elif __AARCH64__ + // Search in arch/arm64/boot/dts/ + #include +#else + #error "Please define __ARM32__ or __AARCH64__ when compiling dts" +#endif diff --git a/target/linux/ipq50xx/image/Makefile b/target/linux/ipq50xx/image/Makefile new file mode 100644 index 0000000000..c0b1271f91 --- /dev/null +++ b/target/linux/ipq50xx/image/Makefile @@ -0,0 +1,34 @@ +include $(TOPDIR)/rules.mk +include $(INCLUDE_DIR)/image.mk + +ifeq ($(SUBTARGET),arm) + KERNEL_LOADADDR := 0x41208000 + DTS_CPPFLAGS-y += -D__ARM32__ +else + KERNEL_LOADADDR := 0x41000000 + DTS_CPPFLAGS-y += -D__AARCH64__ +endif + +define Device/Default + PROFILES := Default + DEVICE_DTS_DIR := ../dts + DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1))) + DTS_CPPFLAGS += $(DTS_CPPFLAGS-y) + IMAGES := sysupgrade.tar + IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata +endef + +define Device/FitImage + KERNEL_SUFFIX := -fit-uImage.itb + KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb + KERNEL_NAME := Image +endef + +define Device/UbiFit + KERNEL_IN_UBI := 1 + IMAGES := nand-factory.ubi nand-sysupgrade.bin + IMAGE/nand-factory.ubi := append-ubi + IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata +endef + +$(eval $(call BuildImage)) diff --git a/target/linux/ipq50xx/patches/301-clk-qcom-clk-alpha-pll-Add-support-for-Stromer-PLLs.patch b/target/linux/ipq50xx/patches/301-clk-qcom-clk-alpha-pll-Add-support-for-Stromer-PLLs.patch new file mode 100644 index 0000000000..a656770ca8 --- /dev/null +++ b/target/linux/ipq50xx/patches/301-clk-qcom-clk-alpha-pll-Add-support-for-Stromer-PLLs.patch @@ -0,0 +1,256 @@ +From 5f016bd100af39ca781d4adb4123447378b2f9ac Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Mon, 28 Sep 2020 10:45:34 +0530 +Subject: [PATCH 1/7] clk: qcom: clk-alpha-pll: Add support for Stromer PLLs + +Add programming sequence support for managing the Stromer +PLLs. + +Signed-off-by: Varadarajan Narayanan + +Pick from <1601270140-4306-2-git-send-email-varada@codeaurora.org> + +Add missing test_ctl_val and test_ctl_hi_val member variables. + +Signed-off-by: hzy +--- + drivers/clk/qcom/clk-alpha-pll.c | 156 ++++++++++++++++++++++++++++++- + drivers/clk/qcom/clk-alpha-pll.h | 7 ++ + 2 files changed, 162 insertions(+), 1 deletion(-) + +diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c +index a69f53e435ed..ed8a26fac199 100644 +--- a/drivers/clk/qcom/clk-alpha-pll.c ++++ b/drivers/clk/qcom/clk-alpha-pll.c +@@ -114,6 +114,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { + [PLL_OFF_OPMODE] = 0x38, + [PLL_OFF_ALPHA_VAL] = 0x40, + }, ++ ++ [CLK_ALPHA_PLL_TYPE_STROMER] = { ++ [PLL_OFF_L_VAL] = 0x08, ++ [PLL_OFF_ALPHA_VAL] = 0x10, ++ [PLL_OFF_ALPHA_VAL_U] = 0x14, ++ [PLL_OFF_USER_CTL] = 0x18, ++ [PLL_OFF_USER_CTL_U] = 0x1c, ++ [PLL_OFF_CONFIG_CTL] = 0x20, ++ [PLL_OFF_CONFIG_CTL_U] = 0xff, ++ [PLL_OFF_TEST_CTL] = 0x30, ++ [PLL_OFF_TEST_CTL_U] = 0x34, ++ [PLL_OFF_STATUS] = 0x28, ++ }, + }; + EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); + +@@ -125,6 +138,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); + #define ALPHA_BITWIDTH 32U + #define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH) + ++#define PLL_STATUS_REG_SHIFT 8 ++ + #define PLL_HUAYRA_M_WIDTH 8 + #define PLL_HUAYRA_M_SHIFT 8 + #define PLL_HUAYRA_M_MASK 0xff +@@ -206,7 +221,7 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse, + void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + const struct alpha_pll_config *config) + { +- u32 val, mask; ++ u32 val, val_u, mask, mask_u; + + regmap_write(regmap, PLL_L_VAL(pll), config->l); + regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha); +@@ -236,14 +251,143 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, + mask |= config->pre_div_mask; + mask |= config->post_div_mask; + mask |= config->vco_mask; ++ mask |= config->alpha_en_mask; ++ mask |= config->alpha_mode_mask; + + regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val); + ++ /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */ ++ val_u = config->status_reg_val << PLL_STATUS_REG_SHIFT; ++ val_u |= config->lock_det; ++ ++ mask_u = config->status_reg_mask; ++ mask_u |= config->lock_det; ++ ++ if (val_u != 0) ++ regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u); ++ ++ if (config->test_ctl_val != 0) ++ regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val); ++ ++ if (config->test_ctl_hi_val != 0) ++ regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val); ++ + if (pll->flags & SUPPORTS_FSM_MODE) + qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0); + } + EXPORT_SYMBOL_GPL(clk_alpha_pll_configure); + ++static unsigned long ++alpha_pll_stromer_calc_rate(u64 prate, u32 l, u64 a) ++{ ++ return (prate * l) + ((prate * a) >> ALPHA_REG_BITWIDTH); ++} ++ ++static unsigned long ++alpha_pll_stromer_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a) ++{ ++ u64 remainder; ++ u64 quotient; ++ ++ quotient = rate; ++ remainder = do_div(quotient, prate); ++ *l = quotient; ++ ++ if (!remainder) { ++ *a = 0; ++ return rate; ++ } ++ ++ quotient = remainder << ALPHA_REG_BITWIDTH; ++ ++ remainder = do_div(quotient, prate); ++ ++ if (remainder) ++ quotient++; ++ ++ *a = quotient; ++ return alpha_pll_stromer_calc_rate(prate, *l, *a); ++} ++ ++static unsigned long ++clk_alpha_pll_stromer_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) ++{ ++ u32 l, low, high, ctl; ++ u64 a = 0, prate = parent_rate; ++ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); ++ ++ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l); ++ ++ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl); ++ if (ctl & PLL_ALPHA_EN) { ++ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low); ++ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), ++ &high); ++ a = (u64)high << ALPHA_BITWIDTH | low; ++ } ++ ++ return alpha_pll_stromer_calc_rate(prate, l, a); ++} ++ ++static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw, ++ struct clk_rate_request *req) ++{ ++ unsigned long rate = req->rate; ++ u32 l; ++ u64 a; ++ ++ rate = alpha_pll_stromer_round_rate(rate, req->best_parent_rate, &l, &a); ++ ++ return 0; ++} ++ ++static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate, ++ unsigned long prate) ++{ ++ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw); ++ u32 l; ++ int ret; ++ u64 a; ++ ++ rate = alpha_pll_stromer_round_rate(rate, prate, &l, &a); ++ ++ /* Write desired values to registers */ ++ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l); ++ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); ++ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll), ++ a >> ALPHA_BITWIDTH); ++ ++ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll), ++ PLL_ALPHA_EN, PLL_ALPHA_EN); ++ ++ if (!clk_hw_is_enabled(hw)) ++ return 0; ++ ++ /* Stromer PLL supports Dynamic programming. ++ * It allows the PLL frequency to be changed on-the-fly without first ++ * execution of a shutdown procedure followed by a bring up procedure. ++ */ ++ ++ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE, ++ PLL_UPDATE); ++ /* Make sure PLL_UPDATE request goes through */ ++ mb(); ++ ++ /* Wait for PLL_UPDATE to be cleared */ ++ ret = wait_for_pll_update(pll); ++ if (ret) ++ return ret; ++ ++ /* Wait 11or more PLL clk_ref ticks[to be explored more on wait] */ ++ ++ /* Poll LOCK_DET for one */ ++ ret = wait_for_pll_enable_lock(pll); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ + static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw) + { + int ret; +@@ -905,6 +1049,16 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = { + .set_rate = clk_alpha_pll_hwfsm_set_rate, + }; + EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops); ++ ++const struct clk_ops clk_alpha_pll_stromer_ops = { ++ .enable = clk_alpha_pll_enable, ++ .disable = clk_alpha_pll_disable, ++ .is_enabled = clk_alpha_pll_is_enabled, ++ .recalc_rate = clk_alpha_pll_stromer_recalc_rate, ++ .determine_rate = clk_alpha_pll_stromer_determine_rate, ++ .set_rate = clk_alpha_pll_stromer_set_rate, ++}; ++EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops); + + const struct clk_ops clk_trion_fixed_pll_ops = { + .enable = clk_trion_pll_enable, +diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h +index 15f27f4b06df..68a2d2494f5d 100644 +--- a/drivers/clk/qcom/clk-alpha-pll.h ++++ b/drivers/clk/qcom/clk-alpha-pll.h +@@ -14,6 +14,7 @@ enum { + CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION, + CLK_ALPHA_PLL_TYPE_AGERA, + CLK_ALPHA_PLL_TYPE_ZONDA, ++ CLK_ALPHA_PLL_TYPE_STROMER, + CLK_ALPHA_PLL_TYPE_MAX, + }; + +@@ -106,6 +107,9 @@ struct alpha_pll_config { + u32 post_div_mask; + u32 vco_val; + u32 vco_mask; ++ u32 status_reg_val; ++ u32 status_reg_mask; ++ u32 lock_det; + }; + + extern const struct clk_ops clk_alpha_pll_ops; +@@ -113,6 +119,7 @@ extern const struct clk_ops clk_alpha_pll_hwfsm_ops; + extern const struct clk_ops clk_alpha_pll_postdiv_ops; + extern const struct clk_ops clk_alpha_pll_huayra_ops; + extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops; ++extern const struct clk_ops clk_alpha_pll_stromer_ops; + + extern const struct clk_ops clk_alpha_pll_fabia_ops; + extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops; +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/302-dt-bindings-arm64-ipq5018-Add-binding-descriptions-f.patch b/target/linux/ipq50xx/patches/302-dt-bindings-arm64-ipq5018-Add-binding-descriptions-f.patch new file mode 100644 index 0000000000..e894a16472 --- /dev/null +++ b/target/linux/ipq50xx/patches/302-dt-bindings-arm64-ipq5018-Add-binding-descriptions-f.patch @@ -0,0 +1,360 @@ +From 519997f7779e6a40b327ffab1b1629f2b3320176 Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Mon, 28 Sep 2020 10:45:35 +0530 +Subject: [PATCH 2/7] dt-bindings: arm64: ipq5018: Add binding descriptions for + clock and reset + +This patch adds support for the global clock controller found on +the IPQ5018 based devices. + +Signed-off-by: Varadarajan Narayanan + +Pick from <1601270140-4306-3-git-send-email-varada@codeaurora.org> + +Signed-off-by: hzy +--- + .../devicetree/bindings/clock/qcom,gcc.yaml | 1 + + include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 ++++++++++++++++++ + include/dt-bindings/reset/qcom,gcc-ipq5018.h | 119 ++++++++++++ + 3 files changed, 303 insertions(+) + create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h + create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h + +diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +index d14362ad4132..530a8fe2687c 100644 +--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml ++++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml +@@ -17,6 +17,8 @@ + - dt-bindings/clock/qcom,gcc-apq8084.h + - dt-bindings/reset/qcom,gcc-apq8084.h + - dt-bindings/clock/qcom,gcc-ipq4019.h ++ - dt-bindings/clock/qcom,gcc-ipq5018.h ++ - dt-bindings/reset/qcom,gcc-ipq5018.h + - dt-bindings/clock/qcom,gcc-ipq6018.h + - dt-bindings/reset/qcom,gcc-ipq6018.h + - dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064) +@@ -39,6 +40,7 @@ Required properties : + enum: + - qcom,gcc-apq8084 + - qcom,gcc-ipq4019 ++ - qcom,gcc-ipq5018 + - qcom,gcc-ipq6018 + - qcom,gcc-ipq8064 + - qcom,gcc-mdm9607 +diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h +new file mode 100644 +index 000000000000..069165f73d0b +--- /dev/null ++++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h +@@ -0,0 +1,183 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H ++#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H ++ ++#define GPLL0_MAIN 0 ++#define GPLL0 1 ++#define GPLL2_MAIN 2 ++#define GPLL2 3 ++#define GPLL4_MAIN 4 ++#define GPLL4 5 ++#define UBI32_PLL_MAIN 6 ++#define UBI32_PLL 7 ++#define APSS_AHB_CLK_SRC 9 ++#define APSS_AHB_POSTDIV_CLK_SRC 10 ++#define APSS_AXI_CLK_SRC 11 ++#define BLSP1_QUP1_I2C_APPS_CLK_SRC 12 ++#define BLSP1_QUP1_SPI_APPS_CLK_SRC 13 ++#define BLSP1_QUP2_I2C_APPS_CLK_SRC 14 ++#define BLSP1_QUP2_SPI_APPS_CLK_SRC 15 ++#define BLSP1_QUP3_I2C_APPS_CLK_SRC 16 ++#define BLSP1_QUP3_SPI_APPS_CLK_SRC 17 ++#define BLSP1_UART1_APPS_CLK_SRC 18 ++#define BLSP1_UART2_APPS_CLK_SRC 19 ++#define CRYPTO_CLK_SRC 20 ++#define GCC_APSS_AHB_CLK 23 ++#define GCC_APSS_AXI_CLK 24 ++#define GCC_BLSP1_AHB_CLK 25 ++#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26 ++#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27 ++#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28 ++#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29 ++#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30 ++#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31 ++#define GCC_BLSP1_UART1_APPS_CLK 33 ++#define GCC_BLSP1_UART2_APPS_CLK 34 ++#define GCC_BTSS_LPO_CLK 36 ++#define GCC_CMN_BLK_AHB_CLK 40 ++#define GCC_CMN_BLK_SYS_CLK 41 ++#define GCC_CRYPTO_AHB_CLK 44 ++#define GCC_CRYPTO_AXI_CLK 45 ++#define GCC_CRYPTO_CLK 46 ++#define GCC_CRYPTO_PPE_CLK 47 ++#define GCC_DCC_CLK 48 ++#define GCC_GEPHY_RX_CLK 53 ++#define GCC_GEPHY_TX_CLK 54 ++#define GCC_GMAC0_CFG_CLK 55 ++#define GCC_GMAC0_PTP_CLK 56 ++#define GCC_GMAC0_RX_CLK 57 ++#define GCC_GMAC0_SYS_CLK 58 ++#define GCC_GMAC0_TX_CLK 59 ++#define GCC_GMAC1_CFG_CLK 60 ++#define GCC_GMAC1_PTP_CLK 61 ++#define GCC_GMAC1_RX_CLK 62 ++#define GCC_GMAC1_SYS_CLK 63 ++#define GCC_GMAC1_TX_CLK 64 ++#define GCC_GP1_CLK 65 ++#define GCC_GP2_CLK 66 ++#define GCC_GP3_CLK 67 ++#define GCC_LPASS_CORE_AXIM_CLK 69 ++#define GCC_LPASS_SWAY_CLK 70 ++#define GCC_MDIO0_AHB_CLK 71 ++#define GCC_MDIO1_AHB_CLK 72 ++#define GCC_PCIE0_AHB_CLK 74 ++#define GCC_PCIE0_AUX_CLK 75 ++#define GCC_PCIE0_AXI_M_CLK 76 ++#define GCC_PCIE0_AXI_S_BRIDGE_CLK 77 ++#define GCC_PCIE0_AXI_S_CLK 78 ++#define GCC_PCIE1_AHB_CLK 79 ++#define GCC_PCIE1_AUX_CLK 80 ++#define GCC_PCIE1_AXI_M_CLK 81 ++#define GCC_PCIE1_AXI_S_BRIDGE_CLK 82 ++#define GCC_PCIE1_AXI_S_CLK 83 ++#define GCC_PRNG_AHB_CLK 84 ++#define GCC_Q6_AXIM_CLK 85 ++#define GCC_Q6_AXIM2_CLK 86 ++#define GCC_Q6_AXIS_CLK 87 ++#define GCC_Q6_AHB_CLK 88 ++#define GCC_Q6_AHB_S_CLK 89 ++#define GCC_Q6_TSCTR_1TO2_CLK 90 ++#define GCC_Q6SS_ATBM_CLK 91 ++#define GCC_Q6SS_PCLKDBG_CLK 92 ++#define GCC_Q6SS_TRIG_CLK 93 ++#define GCC_QDSS_AT_CLK 94 ++#define GCC_QDSS_CFG_AHB_CLK 95 ++#define GCC_QDSS_DAP_AHB_CLK 96 ++#define GCC_QDSS_DAP_CLK 97 ++#define GCC_QDSS_ETR_USB_CLK 98 ++#define GCC_QDSS_EUD_AT_CLK 99 ++#define GCC_QDSS_STM_CLK 100 ++#define GCC_QDSS_TRACECLKIN_CLK 101 ++#define GCC_QDSS_TSCTR_DIV8_CLK 102 ++#define GCC_QPIC_AHB_CLK 103 ++#define GCC_QPIC_CLK 104 ++#define GCC_QPIC_IO_MACRO_CLK 105 ++#define GCC_SDCC1_AHB_CLK 107 ++#define GCC_SDCC1_APPS_CLK 108 ++#define GCC_SLEEP_CLK_SRC 109 ++#define GCC_SNOC_GMAC0_AHB_CLK 110 ++#define GCC_SNOC_GMAC0_AXI_CLK 111 ++#define GCC_SNOC_GMAC1_AHB_CLK 112 ++#define GCC_SNOC_GMAC1_AXI_CLK 113 ++#define GCC_SNOC_LPASS_AXIM_CLK 114 ++#define GCC_SNOC_LPASS_SWAY_CLK 115 ++#define GCC_SNOC_UBI0_AXI_CLK 118 ++#define GCC_SYS_NOC_PCIE0_AXI_CLK 119 ++#define GCC_SYS_NOC_PCIE1_AXI_CLK 120 ++#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 121 ++#define GCC_SYS_NOC_USB0_AXI_CLK 123 ++#define GCC_SYS_NOC_WCSS_AHB_CLK 124 ++#define GCC_UBI0_AXI_CLK 128 ++#define GCC_UBI0_CFG_CLK 129 ++#define GCC_UBI0_CORE_CLK 130 ++#define GCC_UBI0_DBG_CLK 131 ++#define GCC_UBI0_NC_AXI_CLK 132 ++#define GCC_UBI0_UTCM_CLK 133 ++#define GCC_UNIPHY_AHB_CLK 134 ++#define GCC_UNIPHY_RX_CLK 135 ++#define GCC_UNIPHY_SYS_CLK 136 ++#define GCC_UNIPHY_TX_CLK 137 ++#define GCC_USB0_AUX_CLK 138 ++#define GCC_USB0_EUD_AT_CLK 139 ++#define GCC_USB0_LFPS_CLK 140 ++#define GCC_USB0_MASTER_CLK 141 ++#define GCC_USB0_MOCK_UTMI_CLK 142 ++#define GCC_USB0_PHY_CFG_AHB_CLK 143 ++#define GCC_USB0_SLEEP_CLK 144 ++#define GCC_WCSS_ACMT_CLK 145 ++#define GCC_WCSS_AHB_S_CLK 146 ++#define GCC_WCSS_AXI_M_CLK 147 ++#define GCC_WCSS_AXI_S_CLK 148 ++#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 149 ++#define GCC_WCSS_DBG_IFC_APB_CLK 150 ++#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 151 ++#define GCC_WCSS_DBG_IFC_ATB_CLK 152 ++#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 153 ++#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 154 ++#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155 ++#define GCC_WCSS_DBG_IFC_NTS_CLK 156 ++#define GCC_WCSS_ECAHB_CLK 157 ++#define GCC_XO_CLK 158 ++#define GCC_XO_CLK_SRC 159 ++#define GMAC0_RX_CLK_SRC 161 ++#define GMAC0_TX_CLK_SRC 162 ++#define GMAC1_RX_CLK_SRC 163 ++#define GMAC1_TX_CLK_SRC 164 ++#define GMAC_CLK_SRC 165 ++#define GP1_CLK_SRC 166 ++#define GP2_CLK_SRC 167 ++#define GP3_CLK_SRC 168 ++#define LPASS_AXIM_CLK_SRC 169 ++#define LPASS_SWAY_CLK_SRC 170 ++#define PCIE0_AUX_CLK_SRC 171 ++#define PCIE0_AXI_CLK_SRC 172 ++#define PCIE1_AUX_CLK_SRC 173 ++#define PCIE1_AXI_CLK_SRC 174 ++#define PCNOC_BFDCD_CLK_SRC 175 ++#define Q6_AXI_CLK_SRC 176 ++#define QDSS_AT_CLK_SRC 177 ++#define QDSS_STM_CLK_SRC 178 ++#define QDSS_TSCTR_CLK_SRC 179 ++#define QDSS_TRACECLKIN_CLK_SRC 180 ++#define QPIC_IO_MACRO_CLK_SRC 181 ++#define SDCC1_APPS_CLK_SRC 182 ++#define SYSTEM_NOC_BFDCD_CLK_SRC 184 ++#define UBI0_AXI_CLK_SRC 185 ++#define UBI0_CORE_CLK_SRC 186 ++#define USB0_AUX_CLK_SRC 187 ++#define USB0_LFPS_CLK_SRC 188 ++#define USB0_MASTER_CLK_SRC 189 ++#define USB0_MOCK_UTMI_CLK_SRC 190 ++#define WCSS_AHB_CLK_SRC 191 ++#define PCIE0_PIPE_CLK_SRC 192 ++#define PCIE1_PIPE_CLK_SRC 193 ++#define GCC_PCIE0_PIPE_CLK 194 ++#define GCC_PCIE1_PIPE_CLK 195 ++#define USB0_PIPE_CLK_SRC 196 ++#define GCC_USB0_PIPE_CLK 197 ++#define GMAC0_RX_DIV_CLK_SRC 198 ++#define GMAC0_TX_DIV_CLK_SRC 199 ++#define GMAC1_RX_DIV_CLK_SRC 200 ++#define GMAC1_TX_DIV_CLK_SRC 201 ++#endif +diff --git a/include/dt-bindings/reset/qcom,gcc-ipq5018.h b/include/dt-bindings/reset/qcom,gcc-ipq5018.h +new file mode 100644 +index 000000000000..cd9c4e1d19e8 +--- /dev/null ++++ b/include/dt-bindings/reset/qcom,gcc-ipq5018.h +@@ -0,0 +1,119 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++ ++#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H ++#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H ++ ++#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0 ++#define GCC_BLSP1_BCR 1 ++#define GCC_BLSP1_QUP1_BCR 2 ++#define GCC_BLSP1_QUP2_BCR 3 ++#define GCC_BLSP1_QUP3_BCR 4 ++#define GCC_BLSP1_UART1_BCR 5 ++#define GCC_BLSP1_UART2_BCR 6 ++#define GCC_BOOT_ROM_BCR 7 ++#define GCC_BTSS_BCR 8 ++#define GCC_CMN_BLK_BCR 9 ++#define GCC_CMN_LDO_BCR 10 ++#define GCC_CE_BCR 11 ++#define GCC_CRYPTO_BCR 12 ++#define GCC_DCC_BCR 13 ++#define GCC_DCD_BCR 14 ++#define GCC_DDRSS_BCR 15 ++#define GCC_EDPD_BCR 16 ++#define GCC_GEPHY_BCR 17 ++#define GCC_GEPHY_MDC_SW_ARES 18 ++#define GCC_GEPHY_DSP_HW_ARES 19 ++#define GCC_GEPHY_RX_ARES 20 ++#define GCC_GEPHY_TX_ARES 21 ++#define GCC_GMAC0_BCR 22 ++#define GCC_GMAC0_CFG_ARES 23 ++#define GCC_GMAC0_SYS_ARES 24 ++#define GCC_GMAC1_BCR 25 ++#define GCC_GMAC1_CFG_ARES 26 ++#define GCC_GMAC1_SYS_ARES 27 ++#define GCC_IMEM_BCR 28 ++#define GCC_LPASS_BCR 29 ++#define GCC_MDIO0_BCR 30 ++#define GCC_MDIO1_BCR 31 ++#define GCC_MPM_BCR 32 ++#define GCC_PCIE0_BCR 33 ++#define GCC_PCIE0_LINK_DOWN_BCR 34 ++#define GCC_PCIE0_PHY_BCR 35 ++#define GCC_PCIE0PHY_PHY_BCR 36 ++#define GCC_PCIE0_PIPE_ARES 37 ++#define GCC_PCIE0_SLEEP_ARES 38 ++#define GCC_PCIE0_CORE_STICKY_ARES 39 ++#define GCC_PCIE0_AXI_MASTER_ARES 40 ++#define GCC_PCIE0_AXI_SLAVE_ARES 41 ++#define GCC_PCIE0_AHB_ARES 42 ++#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43 ++#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44 ++#define GCC_PCIE1_BCR 45 ++#define GCC_PCIE1_LINK_DOWN_BCR 46 ++#define GCC_PCIE1_PHY_BCR 47 ++#define GCC_PCIE1PHY_PHY_BCR 48 ++#define GCC_PCIE1_PIPE_ARES 49 ++#define GCC_PCIE1_SLEEP_ARES 50 ++#define GCC_PCIE1_CORE_STICKY_ARES 51 ++#define GCC_PCIE1_AXI_MASTER_ARES 52 ++#define GCC_PCIE1_AXI_SLAVE_ARES 53 ++#define GCC_PCIE1_AHB_ARES 54 ++#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55 ++#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56 ++#define GCC_PCNOC_BCR 57 ++#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 ++#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 ++#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 ++#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 ++#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 ++#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 ++#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 ++#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 ++#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 ++#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 ++#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68 ++#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69 ++#define GCC_PRNG_BCR 70 ++#define GCC_Q6SS_DBG_ARES 71 ++#define GCC_Q6_AHB_S_ARES 72 ++#define GCC_Q6_AHB_ARES 73 ++#define GCC_Q6_AXIM2_ARES 74 ++#define GCC_Q6_AXIM_ARES 75 ++#define GCC_Q6_AXIS_ARES 76 ++#define GCC_QDSS_BCR 77 ++#define GCC_QPIC_BCR 78 ++#define GCC_QUSB2_0_PHY_BCR 79 ++#define GCC_SDCC1_BCR 80 ++#define GCC_SEC_CTRL_BCR 81 ++#define GCC_SPDM_BCR 82 ++#define GCC_SYSTEM_NOC_BCR 83 ++#define GCC_TCSR_BCR 84 ++#define GCC_TLMM_BCR 85 ++#define GCC_UBI0_AXI_ARES 86 ++#define GCC_UBI0_AHB_ARES 87 ++#define GCC_UBI0_NC_AXI_ARES 88 ++#define GCC_UBI0_DBG_ARES 89 ++#define GCC_UBI0_UTCM_ARES 90 ++#define GCC_UBI0_CORE_ARES 91 ++#define GCC_UBI32_BCR 92 ++#define GCC_UNIPHY_BCR 93 ++#define GCC_UNIPHY_AHB_ARES 94 ++#define GCC_UNIPHY_SYS_ARES 95 ++#define GCC_UNIPHY_RX_ARES 96 ++#define GCC_UNIPHY_TX_ARES 97 ++#define GCC_USB0_BCR 98 ++#define GCC_USB0_PHY_BCR 99 ++#define GCC_WCSS_BCR 100 ++#define GCC_WCSS_DBG_ARES 101 ++#define GCC_WCSS_ECAHB_ARES 102 ++#define GCC_WCSS_ACMT_ARES 103 ++#define GCC_WCSS_DBG_BDG_ARES 104 ++#define GCC_WCSS_AHB_S_ARES 105 ++#define GCC_WCSS_AXI_M_ARES 106 ++#define GCC_WCSS_AXI_S_ARES 107 ++#define GCC_WCSS_Q6_BCR 108 ++#define GCC_WCSSAON_RESET 109 ++#define GCC_UNIPHY_SOFT_RESET 110 ++#define GCC_GEPHY_MISC_ARES 111 ++ ++#endif +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/303-clk-qcom-Add-Global-Clock-controller-GCC-driver-for-.patch b/target/linux/ipq50xx/patches/303-clk-qcom-Add-Global-Clock-controller-GCC-driver-for-.patch new file mode 100644 index 0000000000..ce19296399 --- /dev/null +++ b/target/linux/ipq50xx/patches/303-clk-qcom-Add-Global-Clock-controller-GCC-driver-for-.patch @@ -0,0 +1,3910 @@ +From 089d3f914b109ac1b79ee3219e36ae17d977db3e Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Mon, 28 Sep 2020 10:45:36 +0530 +Subject: [PATCH 3/7] clk: qcom: Add Global Clock controller (GCC) driver for + IPQ5018 + +Add support for the global clock controller found on IPQ5018 +based devices. + +Signed-off-by: Varadarajan Narayanan + +Pick from <1601270140-4306-4-git-send-email-varada@codeaurora.org> + +Signed-off-by: hzy +--- + drivers/clk/qcom/Kconfig | 8 + + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/gcc-ipq5018.c | 3833 ++++++++++++++++++++++++++++++++ + include/linux/clk-provider.h | 4 +- + 4 files changed, 3844 insertions(+), 2 deletions(-) + create mode 100644 drivers/clk/qcom/gcc-ipq5018.c + +diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig +index 32dbb4f09492..ce3de9009f79 100644 +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -118,6 +118,14 @@ config IPQ_GCC_8074 + i2c, USB, SD/eMMC, etc. Select this for the root clock + of ipq8074. + ++config IPQ_GCC_5018 ++ tristate "IPQ5018 Global Clock Controller" ++ help ++ Support for global clock controller on ipq5018 devices. ++ Say Y if you want to use peripheral devices such as UART, SPI, ++ i2c, USB, SD/eMMC, etc. Select this for the root clock ++ of ipq5018. ++ + config MSM_GCC_8660 + tristate "MSM8660 Global Clock Controller" + help +diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile +index 4a813b4055d0..61cedb49646c 100644 +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -22,6 +22,7 @@ obj-$(CONFIG_APQ_MMCC_8084) += mmcc-apq8084.o + obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o + obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o + obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o ++obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o + obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o + obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o + obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o +diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c +new file mode 100644 +index 000000000000..9056386ae134 +--- /dev/null ++++ b/drivers/clk/qcom/gcc-ipq5018.c +@@ -0,0 +1,3833 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "common.h" ++#include "clk-regmap.h" ++#include "clk-pll.h" ++#include "clk-rcg.h" ++#include "clk-branch.h" ++#include "clk-alpha-pll.h" ++#include "clk-regmap-divider.h" ++#include "clk-regmap-mux.h" ++#include "reset.h" ++ ++#define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) } ++ ++enum { ++ P_XO, ++ P_GPLL0, ++ P_GPLL0_DIV2, ++ P_GPLL2, ++ P_GPLL4, ++ P_UBI32_PLL, ++ P_GEPHY_RX, ++ P_GEPHY_TX, ++ P_UNIPHY_RX, ++ P_UNIPHY_TX, ++ P_CORE_PI_SLEEP_CLK, ++ P_PCIE20_PHY0_PIPE, ++ P_PCIE20_PHY1_PIPE, ++ P_USB3PHY_0_PIPE, ++}; ++ ++static const char * const gcc_xo_gpll0_gpll0_out_main_div2[] = { ++ "xo", ++ "gpll0", ++ "gpll0_out_main_div2", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const char * const gcc_xo_gpll0[] = { ++ "xo", ++ "gpll0", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++}; ++ ++static const char * const gcc_xo_gpll0_out_main_div2_gpll0[] = { ++ "xo", ++ "gpll0_out_main_div2", ++ "gpll0", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0_DIV2, 2 }, ++ { P_GPLL0, 1 }, ++}; ++ ++static const char * const gcc_xo_ubi32_gpll0[] = { ++ "xo", ++ "ubi32_pll", ++ "gpll0", ++}; ++ ++static const struct parent_map gcc_xo_ubi32_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_UBI32_PLL, 1 }, ++ { P_GPLL0, 2 }, ++}; ++ ++static const char * const gcc_xo_gpll0_gpll2[] = { ++ "xo", ++ "gpll0", ++ "gpll2", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL2, 2 }, ++}; ++ ++static const char * const gcc_xo_gpll0_gpll2_gpll4[] = { ++ "xo", ++ "gpll0", ++ "gpll2", ++ "gpll4", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL2, 2 }, ++ { P_GPLL4, 3 }, ++}; ++ ++static const char * const gcc_xo_gpll0_out_main_div2[] = { ++ "xo", ++ "gpll0_out_main_div2", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_out_main_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0_DIV2, 1 }, ++}; ++ ++static const char * const gcc_xo_gpll0_gpll4[] = { ++ "xo", ++ "gpll0", ++ "gpll4", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll4_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL4, 2 }, ++}; ++ ++static const char * const gcc_xo_gpll0_core_pi_sleep_clk[] = { ++ "xo", ++ "gpll0", ++ "sleep_clk", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 2 }, ++ { P_CORE_PI_SLEEP_CLK, 6 }, ++}; ++ ++static const char * const gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = { ++ "xo", ++ "gpll0", ++ "gpll0_out_main_div2", ++ "sleep_clk", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL0_DIV2, 4 }, ++ { P_CORE_PI_SLEEP_CLK, 6 }, ++}; ++ ++static const char * const gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = { ++ "xo", ++ "gpll0", ++ "gpll2", ++ "gpll0_out_main_div2", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL2, 2 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const char * const gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = { ++ "xo", ++ "gpll4", ++ "gpll0", ++ "gpll0_out_main_div2", ++}; ++ ++static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = { ++ { P_XO, 0 }, ++ { P_GPLL4, 1 }, ++ { P_GPLL0, 2 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = { ++ { P_XO, 0 }, ++ { P_GPLL4, 1 }, ++ { P_GPLL0, 3 }, ++ { P_GPLL0_DIV2, 4 }, ++}; ++ ++static const char * const gcc_xo_gpll0_gpll4_gpll2[] = { ++ "xo", ++ "gpll0", ++ "gpll4", ++ "gpll2", ++}; ++ ++static const struct parent_map gcc_xo_gpll0_gpll4_gpll2_map[] = { ++ { P_XO, 0 }, ++ { P_GPLL0, 1 }, ++ { P_GPLL4, 3 }, ++ { P_GPLL2, 4 }, ++}; ++ ++static const char * const gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = { ++ "xo", ++ "gephy_gcc_rx", ++ "gephy_gcc_tx", ++ "ubi32_pll", ++ "gpll0", ++}; ++ ++static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_GEPHY_RX, 1 }, ++ { P_GEPHY_TX, 2 }, ++ { P_UBI32_PLL, 3 }, ++ { P_GPLL0, 4 }, ++}; ++ ++static const char * const gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = { ++ "xo", ++ "gephy_gcc_tx", ++ "gephy_gcc_rx", ++ "ubi32_pll", ++ "gpll0", ++}; ++ ++static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_GEPHY_TX, 1 }, ++ { P_GEPHY_RX, 2 }, ++ { P_UBI32_PLL, 3 }, ++ { P_GPLL0, 4 }, ++}; ++ ++static const char * const gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = { ++ "xo", ++ "uniphy_gcc_rx", ++ "uniphy_gcc_tx", ++ "ubi32_pll", ++ "gpll0", ++}; ++ ++static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_UNIPHY_RX, 1 }, ++ { P_UNIPHY_TX, 2 }, ++ { P_UBI32_PLL, 3 }, ++ { P_GPLL0, 4 }, ++}; ++ ++static const char * const gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = { ++ "xo", ++ "uniphy_gcc_tx", ++ "uniphy_gcc_rx", ++ "ubi32_pll", ++ "gpll0", ++}; ++ ++static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = { ++ { P_XO, 0 }, ++ { P_UNIPHY_TX, 1 }, ++ { P_UNIPHY_RX, 2 }, ++ { P_UBI32_PLL, 3 }, ++ { P_GPLL0, 4 }, ++}; ++ ++static const char * const gcc_pcie20_phy0_pipe_clk_xo[] = { ++ "pcie20_phy0_pipe_clk", ++ "xo", ++}; ++ ++static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = { ++ { P_PCIE20_PHY0_PIPE, 0 }, ++ { P_XO, 2 }, ++}; ++ ++static const char * const gcc_pcie20_phy1_pipe_clk_xo[] = { ++ "pcie20_phy1_pipe_clk", ++ "xo", ++}; ++ ++static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = { ++ { P_PCIE20_PHY1_PIPE, 0 }, ++ { P_XO, 2 }, ++}; ++ ++static const char * const gcc_usb3phy_0_cc_pipe_clk_xo[] = { ++ "usb3phy_0_cc_pipe_clk", ++ "xo", ++}; ++ ++static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = { ++ { P_USB3PHY_0_PIPE, 0 }, ++ { P_XO, 2 }, ++}; ++ ++static struct clk_alpha_pll gpll0_main = { ++ .offset = 0x21000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .clkr = { ++ .enable_reg = 0x0b000, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gpll0_main", ++ .parent_names = (const char *[]){ ++ "xo" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_stromer_ops, ++ .flags = CLK_IS_CRITICAL, ++ }, ++ }, ++}; ++ ++static struct clk_fixed_factor gpll0_out_main_div2 = { ++ .mult = 1, ++ .div = 2, ++ .hw.init = &(struct clk_init_data){ ++ .name = "gpll0_out_main_div2", ++ .parent_names = (const char *[]){ ++ "gpll0_main" ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv gpll0 = { ++ .offset = 0x21000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .width = 4, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gpll0", ++ .parent_names = (const char *[]){ ++ "gpll0_main" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_alpha_pll gpll2_main = { ++ .offset = 0x4a000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .clkr = { ++ .enable_reg = 0x0b000, ++ .enable_mask = BIT(2), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gpll2_main", ++ .parent_names = (const char *[]){ ++ "xo" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_stromer_ops, ++ .flags = CLK_IS_CRITICAL, ++ }, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv gpll2 = { ++ .offset = 0x4a000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .width = 4, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gpll2", ++ .parent_names = (const char *[]){ ++ "gpll2_main" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_alpha_pll gpll4_main = { ++ .offset = 0x24000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .clkr = { ++ .enable_reg = 0x0b000, ++ .enable_mask = BIT(5), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gpll4_main", ++ .parent_names = (const char *[]){ ++ "xo" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_stromer_ops, ++ .flags = CLK_IS_CRITICAL, ++ }, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv gpll4 = { ++ .offset = 0x24000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .width = 4, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gpll4", ++ .parent_names = (const char *[]){ ++ "gpll4_main" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_alpha_pll ubi32_pll_main = { ++ .offset = 0x25000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .clkr = { ++ .enable_reg = 0x0b000, ++ .enable_mask = BIT(6), ++ .hw.init = &(struct clk_init_data){ ++ .name = "ubi32_pll_main", ++ .parent_names = (const char *[]){ ++ "xo" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_stromer_ops, ++ }, ++ }, ++}; ++ ++static struct clk_alpha_pll_postdiv ubi32_pll = { ++ .offset = 0x25000, ++ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], ++ .width = 4, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "ubi32_pll", ++ .parent_names = (const char *[]){ ++ "ubi32_pll_main" ++ }, ++ .num_parents = 1, ++ .ops = &clk_alpha_pll_postdiv_ro_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { ++ F(100000000, P_GPLL0, 8, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 apss_ahb_clk_src = { ++ .cmd_rcgr = 0x46000, ++ .mnd_width = 0, ++ .hid_width = 5, ++ .freq_tbl = ftbl_apss_ahb_clk_src, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "apss_ahb_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_IS_CRITICAL | CLK_IGNORE_UNUSED, ++ }, ++}; ++ ++static struct clk_regmap_div apss_ahb_postdiv_clk_src = { ++ .reg = 0x46018, ++ .shift = 4, ++ .width = 4, ++ .clkr = { ++ .hw.init = &(struct clk_init_data){ ++ .name = "apss_ahb_postdiv_clk_src", ++ .parent_names = (const char *[]){ ++ "apss_ahb_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_regmap_div_ops, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_apss_axi_clk_src[] = { ++ F(400000000, P_GPLL0, 2, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 apss_axi_clk_src = { ++ .cmd_rcgr = 0x38048, ++ .freq_tbl = ftbl_apss_axi_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "apss_axi_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll4, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = { ++ F(50000000, P_GPLL0, 16, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { ++ .cmd_rcgr = 0x0200c, ++ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "blsp1_qup1_i2c_apps_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { ++ .cmd_rcgr = 0x03000, ++ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "blsp1_qup2_i2c_apps_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { ++ .cmd_rcgr = 0x04000, ++ .freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "blsp1_qup3_i2c_apps_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = { ++ F(960000, P_XO, 10, 2, 5), ++ F(4800000, P_XO, 5, 0, 0), ++ F(9600000, P_XO, 2, 4, 5), ++ F(16000000, P_GPLL0, 10, 1, 5), ++ F(24000000, P_XO, 1, 0, 0), ++ F(50000000, P_GPLL0, 16, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { ++ .cmd_rcgr = 0x02024, ++ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "blsp1_qup1_spi_apps_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { ++ .cmd_rcgr = 0x03014, ++ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "blsp1_qup2_spi_apps_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { ++ .cmd_rcgr = 0x04014, ++ .freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "blsp1_qup3_spi_apps_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = { ++ F(3686400, P_GPLL0_DIV2, 1, 144, 15625), ++ F(7372800, P_GPLL0_DIV2, 1, 288, 15625), ++ F(14745600, P_GPLL0_DIV2, 1, 576, 15625), ++ F(24000000, P_XO, 1, 0, 0), ++ F(25000000, P_GPLL0, 16, 1, 2), ++ F(40000000, P_GPLL0, 1, 1, 20), ++ F(46400000, P_GPLL0, 1, 29, 500), ++ F(48000000, P_GPLL0, 1, 3, 50), ++ F(51200000, P_GPLL0, 1, 8, 125), ++ F(56000000, P_GPLL0, 1, 7, 100), ++ F(58982400, P_GPLL0, 1, 1152, 15625), ++ F(60000000, P_GPLL0, 1, 3, 40), ++ F(64000000, P_GPLL0, 10, 4, 5), ++ { } ++}; ++ ++static struct clk_rcg2 blsp1_uart1_apps_clk_src = { ++ .cmd_rcgr = 0x02044, ++ .freq_tbl = ftbl_blsp1_uart_apps_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "blsp1_uart1_apps_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 blsp1_uart2_apps_clk_src = { ++ .cmd_rcgr = 0x03034, ++ .freq_tbl = ftbl_blsp1_uart_apps_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "blsp1_uart2_apps_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_crypto_clk_src[] = { ++ F(160000000, P_GPLL0, 5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 crypto_clk_src = { ++ .cmd_rcgr = 0x16004, ++ .freq_tbl = ftbl_crypto_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "crypto_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = { ++ F(2500000, P_GEPHY_TX, 5, 0, 0), ++ F(24000000, P_XO, 1, 0, 0), ++ F(25000000, P_GEPHY_TX, 5, 0, 0), ++ F(125000000, P_GEPHY_TX, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 gmac0_rx_clk_src = { ++ .cmd_rcgr = 0x68020, ++ .parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map, ++ .hid_width = 5, ++ .freq_tbl = ftbl_gmac0_tx_clk_src, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gmac0_rx_clk_src", ++ .parent_names = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0, ++ .num_parents = 5, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_regmap_div gmac0_rx_div_clk_src = { ++ .reg = 0x68420, ++ .shift = 0, ++ .width = 4, ++ .clkr = { ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac0_rx_div_clk_src", ++ .parent_names = (const char *[]){ ++ "gmac0_rx_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_regmap_div_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_rcg2 gmac0_tx_clk_src = { ++ .cmd_rcgr = 0x68028, ++ .parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map, ++ .hid_width = 5, ++ .freq_tbl = ftbl_gmac0_tx_clk_src, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gmac0_tx_clk_src", ++ .parent_names = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0, ++ .num_parents = 5, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_regmap_div gmac0_tx_div_clk_src = { ++ .reg = 0x68424, ++ .shift = 0, ++ .width = 4, ++ .clkr = { ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac0_tx_div_clk_src", ++ .parent_names = (const char *[]){ ++ "gmac0_tx_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_regmap_div_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = { ++ F(2500000, P_UNIPHY_RX, 12.5, 0, 0), ++ F(24000000, P_XO, 1, 0, 0), ++ F(25000000, P_UNIPHY_RX, 2.5, 0, 0), ++ F(125000000, P_UNIPHY_RX, 2.5, 0, 0), ++ F(125000000, P_UNIPHY_RX, 1, 0, 0), ++ F(312500000, P_UNIPHY_RX, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 gmac1_rx_clk_src = { ++ .cmd_rcgr = 0x68030, ++ .parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map, ++ .hid_width = 5, ++ .freq_tbl = ftbl_gmac1_rx_clk_src, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gmac1_rx_clk_src", ++ .parent_names = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0, ++ .num_parents = 5, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_regmap_div gmac1_rx_div_clk_src = { ++ .reg = 0x68430, ++ .shift = 0, ++ .width = 4, ++ .clkr = { ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac1_rx_div_clk_src", ++ .parent_names = (const char *[]){ ++ "gmac1_rx_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_regmap_div_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = { ++ F(2500000, P_UNIPHY_TX, 12.5, 0, 0), ++ F(24000000, P_XO, 1, 0, 0), ++ F(25000000, P_UNIPHY_TX, 2.5, 0, 0), ++ F(125000000, P_UNIPHY_TX, 2.5, 0, 0), ++ F(125000000, P_UNIPHY_TX, 1, 0, 0), ++ F(312500000, P_UNIPHY_TX, 1, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 gmac1_tx_clk_src = { ++ .cmd_rcgr = 0x68038, ++ .parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map, ++ .hid_width = 5, ++ .freq_tbl = ftbl_gmac1_tx_clk_src, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gmac1_tx_clk_src", ++ .parent_names = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0, ++ .num_parents = 5, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_regmap_div gmac1_tx_div_clk_src = { ++ .reg = 0x68434, ++ .shift = 0, ++ .width = 4, ++ .clkr = { ++ .hw.init = &(struct clk_init_data){ ++ .name = "gmac1_tx_div_clk_src", ++ .parent_names = (const char *[]){ ++ "gmac1_tx_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_regmap_div_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_gmac_clk_src[] = { ++ F(240000000, P_GPLL4, 5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 gmac_clk_src = { ++ .cmd_rcgr = 0x68080, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .hid_width = 5, ++ .freq_tbl = ftbl_gmac_clk_src, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gmac_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll4, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_gp_clk_src[] = { ++ F(200000000, P_GPLL0, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 gp1_clk_src = { ++ .cmd_rcgr = 0x08004, ++ .freq_tbl = ftbl_gp_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gp1_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 gp2_clk_src = { ++ .cmd_rcgr = 0x09004, ++ .freq_tbl = ftbl_gp_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gp2_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 gp3_clk_src = { ++ .cmd_rcgr = 0x0a004, ++ .freq_tbl = ftbl_gp_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "gp3_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_lpass_axim_clk_src[] = { ++ F(133333334, P_GPLL0, 6, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 lpass_axim_clk_src = { ++ .cmd_rcgr = 0x2E028, ++ .freq_tbl = ftbl_lpass_axim_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "lpass_axim_clk_src", ++ .parent_names = gcc_xo_gpll0, ++ .num_parents = 2, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_lpass_sway_clk_src[] = { ++ F(66666667, P_GPLL0, 12, 0, 0), ++ { } ++}; ++ ++struct clk_rcg2 lpass_sway_clk_src = { ++ .cmd_rcgr = 0x2E040, ++ .freq_tbl = ftbl_lpass_sway_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "lpass_sway_clk_src", ++ .parent_names = gcc_xo_gpll0, ++ .num_parents = 2, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = { ++ F(2000000, P_XO, 12, 0, 0), ++}; ++ ++static struct clk_rcg2 pcie0_aux_clk_src = { ++ .cmd_rcgr = 0x75020, ++ .freq_tbl = ftbl_pcie0_aux_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "pcie0_aux_clk_src", ++ .parent_names = gcc_xo_gpll0_core_pi_sleep_clk, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = { ++ F(240000000, P_GPLL4, 5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 pcie0_axi_clk_src = { ++ .cmd_rcgr = 0x75050, ++ .freq_tbl = ftbl_pcie0_axi_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "pcie0_axi_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll4, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 pcie1_aux_clk_src = { ++ .cmd_rcgr = 0x76020, ++ .freq_tbl = ftbl_pcie0_aux_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "pcie1_aux_clk_src", ++ .parent_names = gcc_xo_gpll0_core_pi_sleep_clk, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++}; ++ ++static struct clk_rcg2 pcie1_axi_clk_src = { ++ .cmd_rcgr = 0x76050, ++ .freq_tbl = ftbl_gp_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "pcie1_axi_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_regmap_mux pcie0_pipe_clk_src = { ++ .reg = 0x7501c, ++ .shift = 8, ++ .width = 2, ++ .parent_map = gcc_pcie20_phy0_pipe_clk_xo_map, ++ .clkr = { ++ .hw.init = &(struct clk_init_data){ ++ .name = "pcie0_pipe_clk_src", ++ .parent_names = gcc_pcie20_phy0_pipe_clk_xo, ++ .num_parents = 2, ++ .ops = &clk_regmap_mux_closest_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_regmap_mux pcie1_pipe_clk_src = { ++ .reg = 0x7601c, ++ .shift = 8, ++ .width = 2, ++ .parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, ++ .clkr = { ++ .hw.init = &(struct clk_init_data){ ++ .name = "pcie1_pipe_clk_src", ++ .parent_names = gcc_pcie20_phy1_pipe_clk_xo, ++ .num_parents = 2, ++ .ops = &clk_regmap_mux_closest_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = { ++ F(100000000, P_GPLL0, 8, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 pcnoc_bfdcd_clk_src = { ++ .cmd_rcgr = 0x27000, ++ .freq_tbl = ftbl_pcnoc_bfdcd_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "pcnoc_bfdcd_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_IS_CRITICAL, ++ }, ++}; ++ ++static struct clk_fixed_factor pcnoc_clk_src = { ++ .mult = 1, ++ .div = 1, ++ .hw.init = &(struct clk_init_data){ ++ .name = "pcnoc_clk_src", ++ .parent_names = (const char *[]){ ++ "pcnoc_bfdcd_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qdss_at_clk_src[] = { ++ F(240000000, P_GPLL4, 5, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 qdss_at_clk_src = { ++ .cmd_rcgr = 0x2900c, ++ .freq_tbl = ftbl_qdss_at_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "qdss_at_clk_src", ++ .parent_names = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qdss_stm_clk_src[] = { ++ F(200000000, P_GPLL0, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 qdss_stm_clk_src = { ++ .cmd_rcgr = 0x2902C, ++ .freq_tbl = ftbl_qdss_stm_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "qdss_stm_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll0_out_main_div2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = { ++ F(266666667, P_GPLL0, 3, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 qdss_traceclkin_clk_src = { ++ .cmd_rcgr = 0x29048, ++ .freq_tbl = ftbl_qdss_traceclkin_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "qdss_traceclkin_clk_src", ++ .parent_names = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = { ++ F(600000000, P_GPLL4, 2, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 qdss_tsctr_clk_src = { ++ .cmd_rcgr = 0x29064, ++ .freq_tbl = ftbl_qdss_tsctr_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "qdss_tsctr_clk_src", ++ .parent_names = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_fixed_factor qdss_tsctr_div2_clk_src = { ++ .mult = 1, ++ .div = 2, ++ .hw.init = &(struct clk_init_data){ ++ .name = "qdss_tsctr_div2_clk_src", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_fixed_factor qdss_dap_sync_clk_src = { ++ .mult = 1, ++ .div = 4, ++ .hw.init = &(struct clk_init_data){ ++ .name = "qdss_dap_sync_clk_src", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ }, ++}; ++ ++static struct clk_fixed_factor eud_at_clk_src = { ++ .mult = 1, ++ .div = 6, ++ .hw.init = &(struct clk_init_data){ ++ .name = "eud_at_clk_src", ++ .parent_names = (const char *[]){ ++ "qdss_at_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = { ++ F(24000000, P_XO, 1, 0, 0), ++ F(100000000, P_GPLL0, 8, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), ++ F(320000000, P_GPLL0, 2.5, 0, 0), ++}; ++ ++static struct clk_rcg2 qpic_io_macro_clk_src = { ++ .cmd_rcgr = 0x57010, ++ .freq_tbl = ftbl_qpic_io_macro_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "qpic_io_macro_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = { ++ F(143713, P_XO, 1, 1, 167), ++ F(400000, P_XO, 1, 1, 60), ++ F(24000000, P_XO, 1, 0, 0), ++ F(48000000, P_GPLL2, 12, 1, 2), ++ F(96000000, P_GPLL2, 12, 0, 0), ++ F(177777778, P_GPLL0, 1, 2, 9), ++ F(192000000, P_GPLL2, 6, 0, 0), ++ F(200000000, P_GPLL0, 4, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 sdcc1_apps_clk_src = { ++ .cmd_rcgr = 0x42004, ++ .freq_tbl = ftbl_sdcc1_apps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "sdcc1_apps_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = { ++ F(266666667, P_GPLL0, 3, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 system_noc_bfdcd_clk_src = { ++ .cmd_rcgr = 0x26004, ++ .freq_tbl = ftbl_system_noc_bfdcd_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "system_noc_bfdcd_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll2_gpll0_out_main_div2, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_IS_CRITICAL, ++ }, ++}; ++ ++static struct clk_fixed_factor system_noc_clk_src = { ++ .mult = 1, ++ .div = 1, ++ .hw.init = &(struct clk_init_data){ ++ .name = "system_noc_clk_src", ++ .parent_names = (const char *[]){ ++ "system_noc_bfdcd_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_fixed_factor_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_rcg2 ubi0_axi_clk_src = { ++ .cmd_rcgr = 0x68088, ++ .freq_tbl = ftbl_apss_axi_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll2_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "ubi0_axi_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll2, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_ubi0_core_clk_src[] = { ++ F(850000000, P_UBI32_PLL, 1, 0, 0), ++ F(1000000000, P_UBI32_PLL, 1, 0, 0), ++}; ++ ++static struct clk_rcg2 ubi0_core_clk_src = { ++ .cmd_rcgr = 0x68100, ++ .freq_tbl = ftbl_ubi0_core_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_ubi32_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "ubi0_core_clk_src", ++ .parent_names = gcc_xo_ubi32_gpll0, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ }, ++}; ++ ++static struct clk_rcg2 usb0_aux_clk_src = { ++ .cmd_rcgr = 0x3e05c, ++ .freq_tbl = ftbl_pcie0_aux_clk_src, ++ .mnd_width = 16, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "usb0_aux_clk_src", ++ .parent_names = gcc_xo_gpll0_core_pi_sleep_clk, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = { ++ F(25000000, P_GPLL0, 16, 1, 2), ++ { } ++}; ++ ++static struct clk_rcg2 usb0_lfps_clk_src = { ++ .cmd_rcgr = 0x3e090, ++ .freq_tbl = ftbl_usb0_lfps_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "usb0_lfps_clk_src", ++ .parent_names = gcc_xo_gpll0, ++ .num_parents = 2, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_rcg2 usb0_master_clk_src = { ++ .cmd_rcgr = 0x3e00c, ++ .freq_tbl = ftbl_gp_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "usb0_master_clk_src", ++ .parent_names = gcc_xo_gpll0_out_main_div2_gpll0, ++ .num_parents = 3, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = { ++ F(60000000, P_GPLL4, 10, 1, 2), ++ { } ++}; ++ ++static struct clk_rcg2 usb0_mock_utmi_clk_src = { ++ .cmd_rcgr = 0x3e020, ++ .freq_tbl = ftbl_usb0_mock_utmi_clk_src, ++ .mnd_width = 8, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "usb0_mock_utmi_clk_src", ++ .parent_names = gcc_xo_gpll4_gpll0_gpll0_out_main_div2, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_regmap_mux usb0_pipe_clk_src = { ++ .reg = 0x3e048, ++ .shift = 8, ++ .width = 2, ++ .parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map, ++ .clkr = { ++ .hw.init = &(struct clk_init_data){ ++ .name = "usb0_pipe_clk_src", ++ .parent_names = gcc_usb3phy_0_cc_pipe_clk_xo, ++ .num_parents = 2, ++ .ops = &clk_regmap_mux_closest_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_q6_axi_clk_src[] = { ++ F(400000000, P_GPLL0, 2, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 q6_axi_clk_src = { ++ .cmd_rcgr = 0x59120, ++ .freq_tbl = ftbl_q6_axi_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_gpll2_gpll4_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "q6_axi_clk_src", ++ .parent_names = gcc_xo_gpll0_gpll2_gpll4, ++ .num_parents = 4, ++ .ops = &clk_rcg2_ops, ++ .flags = CLK_IGNORE_UNUSED, ++ }, ++}; ++ ++static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = { ++ F(133333333, P_GPLL0, 6, 0, 0), ++ { } ++}; ++ ++static struct clk_rcg2 wcss_ahb_clk_src = { ++ .cmd_rcgr = 0x59020, ++ .freq_tbl = ftbl_wcss_ahb_clk_src, ++ .hid_width = 5, ++ .parent_map = gcc_xo_gpll0_map, ++ .clkr.hw.init = &(struct clk_init_data){ ++ .name = "wcss_ahb_clk_src", ++ .parent_names = gcc_xo_gpll0, ++ .num_parents = 2, ++ .ops = &clk_rcg2_ops, ++ }, ++}; ++ ++static struct clk_branch gcc_sleep_clk_src = { ++ .halt_reg = 0x30000, ++ .clkr = { ++ .enable_reg = 0x30000, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_sleep_clk_src", ++ .parent_names = (const char *[]){ ++ "sleep_clk" ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch2_ops, ++ .flags = CLK_IS_CRITICAL, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_xo_clk_src = { ++ .halt_reg = 0x30018, ++ .clkr = { ++ .enable_reg = 0x30018, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_xo_clk_src", ++ .parent_names = (const char *[]){ ++ "xo" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_xo_clk = { ++ .halt_reg = 0x30030, ++ .clkr = { ++ .enable_reg = 0x30030, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_xo_clk", ++ .parent_names = (const char *[]){ ++ "gcc_xo_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_apss_ahb_clk = { ++ .halt_reg = 0x4601c, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(14), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_apss_ahb_clk", ++ .parent_names = (const char *[]){ ++ "apss_ahb_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_apss_axi_clk = { ++ .halt_reg = 0x46020, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(13), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_apss_axi_clk", ++ .parent_names = (const char *[]){ ++ "apss_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_ahb_clk = { ++ .halt_reg = 0x01008, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(10), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { ++ .halt_reg = 0x02008, ++ .clkr = { ++ .enable_reg = 0x02008, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_qup1_i2c_apps_clk", ++ .parent_names = (const char *[]){ ++ "blsp1_qup1_i2c_apps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { ++ .halt_reg = 0x02004, ++ .clkr = { ++ .enable_reg = 0x02004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_qup1_spi_apps_clk", ++ .parent_names = (const char *[]){ ++ "blsp1_qup1_spi_apps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { ++ .halt_reg = 0x03010, ++ .clkr = { ++ .enable_reg = 0x03010, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_qup2_i2c_apps_clk", ++ .parent_names = (const char *[]){ ++ "blsp1_qup2_i2c_apps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { ++ .halt_reg = 0x0300c, ++ .clkr = { ++ .enable_reg = 0x0300c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_qup2_spi_apps_clk", ++ .parent_names = (const char *[]){ ++ "blsp1_qup2_spi_apps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { ++ .halt_reg = 0x04010, ++ .clkr = { ++ .enable_reg = 0x04010, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_qup3_i2c_apps_clk", ++ .parent_names = (const char *[]){ ++ "blsp1_qup3_i2c_apps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { ++ .halt_reg = 0x0400c, ++ .clkr = { ++ .enable_reg = 0x0400c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_qup3_spi_apps_clk", ++ .parent_names = (const char *[]){ ++ "blsp1_qup3_spi_apps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_uart1_apps_clk = { ++ .halt_reg = 0x0203c, ++ .clkr = { ++ .enable_reg = 0x0203c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_uart1_apps_clk", ++ .parent_names = (const char *[]){ ++ "blsp1_uart1_apps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_blsp1_uart2_apps_clk = { ++ .halt_reg = 0x0302c, ++ .clkr = { ++ .enable_reg = 0x0302c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_blsp1_uart2_apps_clk", ++ .parent_names = (const char *[]){ ++ "blsp1_uart2_apps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_btss_lpo_clk = { ++ .halt_reg = 0x1c004, ++ .clkr = { ++ .enable_reg = 0x1c004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_btss_lpo_clk", ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_cmn_blk_ahb_clk = { ++ .halt_reg = 0x56308, ++ .clkr = { ++ .enable_reg = 0x56308, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_cmn_blk_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_cmn_blk_sys_clk = { ++ .halt_reg = 0x5630c, ++ .clkr = { ++ .enable_reg = 0x5630c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_cmn_blk_sys_clk", ++ .parent_names = (const char *[]){ ++ "gcc_xo_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_crypto_ahb_clk = { ++ .halt_reg = 0x16024, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_crypto_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_crypto_axi_clk = { ++ .halt_reg = 0x16020, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(1), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_crypto_axi_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_crypto_clk = { ++ .halt_reg = 0x1601c, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(2), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_crypto_clk", ++ .parent_names = (const char *[]){ ++ "crypto_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_dcc_clk = { ++ .halt_reg = 0x77004, ++ .clkr = { ++ .enable_reg = 0x77004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_dcc_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gephy_rx_clk = { ++ .halt_reg = 0x56010, ++ .clkr = { ++ .enable_reg = 0x56010, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gephy_rx_clk", ++ .parent_names = (const char *[]){ ++ "gmac0_rx_div_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gephy_tx_clk = { ++ .halt_reg = 0x56014, ++ .clkr = { ++ .enable_reg = 0x56014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gephy_tx_clk", ++ .parent_names = (const char *[]){ ++ "gmac0_tx_div_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac0_cfg_clk = { ++ .halt_reg = 0x68304, ++ .clkr = { ++ .enable_reg = 0x68304, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac0_cfg_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac0_ptp_clk = { ++ .halt_reg = 0x68300, ++ .clkr = { ++ .enable_reg = 0x68300, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac0_ptp_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac0_rx_clk = { ++ .halt_reg = 0x68240, ++ .clkr = { ++ .enable_reg = 0x68240, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac0_rx_clk", ++ .parent_names = (const char *[]){ ++ "gmac0_rx_div_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac0_sys_clk = { ++ .halt_reg = 0x68190, ++ .halt_check = BRANCH_HALT_DELAY, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x683190, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac0_sys_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac0_tx_clk = { ++ .halt_reg = 0x68244, ++ .clkr = { ++ .enable_reg = 0x68244, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac0_tx_clk", ++ .parent_names = (const char *[]){ ++ "gmac0_tx_div_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac1_cfg_clk = { ++ .halt_reg = 0x68324, ++ .clkr = { ++ .enable_reg = 0x68324, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac1_cfg_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac1_ptp_clk = { ++ .halt_reg = 0x68320, ++ .clkr = { ++ .enable_reg = 0x68320, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac1_ptp_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac1_rx_clk = { ++ .halt_reg = 0x68248, ++ .clkr = { ++ .enable_reg = 0x68248, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac1_rx_clk", ++ .parent_names = (const char *[]){ ++ "gmac1_rx_div_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac1_sys_clk = { ++ .halt_reg = 0x68310, ++ .clkr = { ++ .enable_reg = 0x68310, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac1_sys_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gmac1_tx_clk = { ++ .halt_reg = 0x6824c, ++ .clkr = { ++ .enable_reg = 0x6824c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gmac1_tx_clk", ++ .parent_names = (const char *[]){ ++ "gmac1_tx_div_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gp1_clk = { ++ .halt_reg = 0x08000, ++ .clkr = { ++ .enable_reg = 0x08000, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gp1_clk", ++ .parent_names = (const char *[]){ ++ "gp1_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gp2_clk = { ++ .halt_reg = 0x09000, ++ .clkr = { ++ .enable_reg = 0x09000, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gp2_clk", ++ .parent_names = (const char *[]){ ++ "gp2_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_gp3_clk = { ++ .halt_reg = 0x0a000, ++ .clkr = { ++ .enable_reg = 0x0a000, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_gp3_clk", ++ .parent_names = (const char *[]){ ++ "gp3_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_lpass_core_axim_clk = { ++ .halt_reg = 0x2E048, ++ .halt_check = BRANCH_VOTED, ++ .clkr = { ++ .enable_reg = 0x2E048, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_lpass_core_axim_clk", ++ .parent_names = (const char *[]){ ++ "lpass_axim_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_lpass_sway_clk = { ++ .halt_reg = 0x2E04C, ++ .clkr = { ++ .enable_reg = 0x2E04C, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_lpass_sway_clk", ++ .parent_names = (const char *[]){ ++ "lpass_sway_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_mdio0_ahb_clk = { ++ .halt_reg = 0x58004, ++ .clkr = { ++ .enable_reg = 0x58004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_mdioi0_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_mdio1_ahb_clk = { ++ .halt_reg = 0x58014, ++ .clkr = { ++ .enable_reg = 0x58014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_mdio1_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_ahb_clk = { ++ .halt_reg = 0x75010, ++ .clkr = { ++ .enable_reg = 0x75010, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie0_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_aux_clk = { ++ .halt_reg = 0x75014, ++ .clkr = { ++ .enable_reg = 0x75014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie0_aux_clk", ++ .parent_names = (const char *[]){ ++ "pcie0_aux_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_axi_m_clk = { ++ .halt_reg = 0x75008, ++ .clkr = { ++ .enable_reg = 0x75008, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie0_axi_m_clk", ++ .parent_names = (const char *[]){ ++ "pcie0_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_axi_s_bridge_clk = { ++ .halt_reg = 0x75048, ++ .clkr = { ++ .enable_reg = 0x75048, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie0_axi_s_bridge_clk", ++ .parent_names = (const char *[]){ ++ "pcie0_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_axi_s_clk = { ++ .halt_reg = 0x7500c, ++ .clkr = { ++ .enable_reg = 0x7500c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie0_axi_s_clk", ++ .parent_names = (const char *[]){ ++ "pcie0_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie0_pipe_clk = { ++ .halt_reg = 0x75018, ++ .halt_check = BRANCH_HALT_DELAY, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x75018, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie0_pipe_clk", ++ .parent_names = (const char *[]){ ++ "pcie0_pipe_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_ahb_clk = { ++ .halt_reg = 0x76010, ++ .clkr = { ++ .enable_reg = 0x76010, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie1_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_aux_clk = { ++ .halt_reg = 0x76014, ++ .clkr = { ++ .enable_reg = 0x76014, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie1_aux_clk", ++ .parent_names = (const char *[]){ ++ "pcie1_aux_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_axi_m_clk = { ++ .halt_reg = 0x76008, ++ .clkr = { ++ .enable_reg = 0x76008, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie1_axi_m_clk", ++ .parent_names = (const char *[]){ ++ "pcie1_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_axi_s_bridge_clk = { ++ .halt_reg = 0x76048, ++ .clkr = { ++ .enable_reg = 0x76048, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie1_axi_s_bridge_clk", ++ .parent_names = (const char *[]){ ++ "pcie1_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_axi_s_clk = { ++ .halt_reg = 0x7600c, ++ .clkr = { ++ .enable_reg = 0x7600c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie1_axi_s_clk", ++ .parent_names = (const char *[]){ ++ "pcie1_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_pcie1_pipe_clk = { ++ .halt_reg = 0x76018, ++ .halt_check = BRANCH_HALT_DELAY, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x76018, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_pcie1_pipe_clk", ++ .parent_names = (const char *[]){ ++ "pcie1_pipe_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_prng_ahb_clk = { ++ .halt_reg = 0x13004, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x0b004, ++ .enable_mask = BIT(8), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_prng_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_ahb_clk = { ++ .halt_reg = 0x59138, ++ .clkr = { ++ .enable_reg = 0x59138, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_q6_ahb_clk", ++ .parent_names = (const char *[]){ ++ "wcss_ahb_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_ahb_s_clk = { ++ .halt_reg = 0x5914C, ++ .clkr = { ++ .enable_reg = 0x5914C, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_q6_ahb_s_clk", ++ .parent_names = (const char *[]){ ++ "wcss_ahb_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_axim_clk = { ++ .halt_reg = 0x5913C, ++ .clkr = { ++ .enable_reg = 0x5913C, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_q6_axim_clk", ++ .parent_names = (const char *[]){ ++ "q6_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_axim2_clk = { ++ .halt_reg = 0x59150, ++ .clkr = { ++ .enable_reg = 0x59150, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_q6_axim2_clk", ++ .parent_names = (const char *[]){ ++ "q6_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_axis_clk = { ++ .halt_reg = 0x59154, ++ .clkr = { ++ .enable_reg = 0x59154, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_q6_axis_clk", ++ .parent_names = (const char *[]){ ++ "system_noc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6_tsctr_1to2_clk = { ++ .halt_reg = 0x59148, ++ .clkr = { ++ .enable_reg = 0x59148, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_q6_tsctr_1to2_clk", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_div2_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6ss_atbm_clk = { ++ .halt_reg = 0x59144, ++ .clkr = { ++ .enable_reg = 0x59144, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_q6ss_atbm_clk", ++ .parent_names = (const char *[]){ ++ "qdss_at_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6ss_pclkdbg_clk = { ++ .halt_reg = 0x59140, ++ .clkr = { ++ .enable_reg = 0x59140, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_q6ss_pclkdbg_clk", ++ .parent_names = (const char *[]){ ++ "qdss_dap_sync_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_q6ss_trig_clk = { ++ .halt_reg = 0x59128, ++ .clkr = { ++ .enable_reg = 0x59128, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_q6ss_trig_clk", ++ .parent_names = (const char *[]){ ++ "qdss_dap_sync_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_at_clk = { ++ .halt_reg = 0x29024, ++ .clkr = { ++ .enable_reg = 0x29024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_at_clk", ++ .parent_names = (const char *[]){ ++ "qdss_at_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_dap_clk = { ++ .halt_reg = 0x29084, ++ .clkr = { ++ .enable_reg = 0x29084, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_dap_clk", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_cfg_ahb_clk = { ++ .halt_reg = 0x29008, ++ .clkr = { ++ .enable_reg = 0x29008, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_cfg_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_dap_ahb_clk = { ++ .halt_reg = 0x29004, ++ .clkr = { ++ .enable_reg = 0x29004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_dap_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_etr_usb_clk = { ++ .halt_reg = 0x29028, ++ .clkr = { ++ .enable_reg = 0x29028, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_etr_usb_clk", ++ .parent_names = (const char *[]){ ++ "system_noc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_eud_at_clk = { ++ .halt_reg = 0x29020, ++ .clkr = { ++ .enable_reg = 0x29020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_eud_at_clk", ++ .parent_names = (const char *[]){ ++ "eud_at_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_stm_clk = { ++ .halt_reg = 0x29044, ++ .clkr = { ++ .enable_reg = 0x29044, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_stm_clk", ++ .parent_names = (const char *[]){ ++ "qdss_stm_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_traceclkin_clk = { ++ .halt_reg = 0x29060, ++ .clkr = { ++ .enable_reg = 0x29060, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_traceclkin_clk", ++ .parent_names = (const char *[]){ ++ "qdss_traceclkin_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qdss_tsctr_div8_clk = { ++ .halt_reg = 0x2908c, ++ .clkr = { ++ .enable_reg = 0x2908c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qdss_tsctr_div8_clk", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qpic_ahb_clk = { ++ .halt_reg = 0x57024, ++ .clkr = { ++ .enable_reg = 0x57024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qpic_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qpic_clk = { ++ .halt_reg = 0x57020, ++ .clkr = { ++ .enable_reg = 0x57020, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qpic_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_qpic_io_macro_clk = { ++ .halt_reg = 0x5701c, ++ .clkr = { ++ .enable_reg = 0x5701c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_qpic_io_macro_clk", ++ .parent_names = (const char *[]){ ++ "qpic_io_macro_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sdcc1_ahb_clk = { ++ .halt_reg = 0x4201c, ++ .clkr = { ++ .enable_reg = 0x4201c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_sdcc1_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sdcc1_apps_clk = { ++ .halt_reg = 0x42018, ++ .clkr = { ++ .enable_reg = 0x42018, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_sdcc1_apps_clk", ++ .parent_names = (const char *[]){ ++ "sdcc1_apps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_gmac0_ahb_clk = { ++ .halt_reg = 0x260a0, ++ .clkr = { ++ .enable_reg = 0x260a0, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_gmac0_ahb_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src", ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_gmac0_axi_clk = { ++ .halt_reg = 0x26084, ++ .clkr = { ++ .enable_reg = 0x26084, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_gmac0_axi_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src", ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_gmac1_ahb_clk = { ++ .halt_reg = 0x260a4, ++ .clkr = { ++ .enable_reg = 0x260a4, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_gmac1_ahb_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src", ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_gmac1_axi_clk = { ++ .halt_reg = 0x26088, ++ .clkr = { ++ .enable_reg = 0x26088, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_gmac1_axi_clk", ++ .parent_names = (const char *[]){ ++ "gmac_clk_src", ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_lpass_axim_clk = { ++ .halt_reg = 0x26074, ++ .clkr = { ++ .enable_reg = 0x26074, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_lpass_axim_clk", ++ .parent_names = (const char *[]){ ++ "lpass_axim_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_lpass_sway_clk = { ++ .halt_reg = 0x26078, ++ .clkr = { ++ .enable_reg = 0x26078, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_lpass_sway_clk", ++ .parent_names = (const char *[]){ ++ "lpass_sway_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_snoc_ubi0_axi_clk = { ++ .halt_reg = 0x26094, ++ .clkr = { ++ .enable_reg = 0x26094, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_snoc_ubi0_axi_clk", ++ .parent_names = (const char *[]){ ++ "ubi0_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sys_noc_pcie0_axi_clk = { ++ .halt_reg = 0x26048, ++ .clkr = { ++ .enable_reg = 0x26048, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_sys_noc_pcie0_axi_clk", ++ .parent_names = (const char *[]){ ++ "pcie0_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sys_noc_pcie1_axi_clk = { ++ .halt_reg = 0x2604c, ++ .clkr = { ++ .enable_reg = 0x2604c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_sys_noc_pcie1_axi_clk", ++ .parent_names = (const char *[]){ ++ "pcie1_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = { ++ .halt_reg = 0x26024, ++ .clkr = { ++ .enable_reg = 0x26024, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_sys_noc_qdss_stm_axi_clk", ++ .parent_names = (const char *[]){ ++ "qdss_stm_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sys_noc_usb0_axi_clk = { ++ .halt_reg = 0x26040, ++ .clkr = { ++ .enable_reg = 0x26040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_sys_noc_usb0_axi_clk", ++ .parent_names = (const char *[]){ ++ "usb0_master_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_sys_noc_wcss_ahb_clk = { ++ .halt_reg = 0x26034, ++ .clkr = { ++ .enable_reg = 0x26034, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_sys_noc_wcss_ahb_clk", ++ .parent_names = (const char *[]){ ++ "wcss_ahb_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_ubi0_axi_clk = { ++ .halt_reg = 0x68200, ++ .halt_check = BRANCH_HALT_DELAY, ++ .clkr = { ++ .enable_reg = 0x68200, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_ubi0_axi_clk", ++ .parent_names = (const char *[]){ ++ "ubi0_axi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_ubi0_cfg_clk = { ++ .halt_reg = 0x68160, ++ .halt_check = BRANCH_HALT_DELAY, ++ .clkr = { ++ .enable_reg = 0x68160, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_ubi0_cfg_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_ubi0_dbg_clk = { ++ .halt_reg = 0x68214, ++ .halt_check = BRANCH_HALT_DELAY, ++ .clkr = { ++ .enable_reg = 0x68214, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_ubi0_dbg_clk", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_ubi0_core_clk = { ++ .halt_reg = 0x68210, ++ .halt_check = BRANCH_HALT_DELAY, ++ .clkr = { ++ .enable_reg = 0x68210, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_ubi0_core_clk", ++ .parent_names = (const char *[]){ ++ "ubi0_core_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_ubi0_nc_axi_clk = { ++ .halt_reg = 0x68204, ++ .halt_check = BRANCH_HALT_DELAY, ++ .clkr = { ++ .enable_reg = 0x68204, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_ubi0_nc_axi_clk", ++ .parent_names = (const char *[]){ ++ "system_noc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_ubi0_utcm_clk = { ++ .halt_reg = 0x68208, ++ .halt_check = BRANCH_HALT_DELAY, ++ .clkr = { ++ .enable_reg = 0x68208, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_ubi0_utcm_clk", ++ .parent_names = (const char *[]){ ++ "system_noc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy_ahb_clk = { ++ .halt_reg = 0x56108, ++ .clkr = { ++ .enable_reg = 0x56108, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_uniphy_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy_rx_clk = { ++ .halt_reg = 0x56110, ++ .clkr = { ++ .enable_reg = 0x56110, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_uniphy_rx_clk", ++ .parent_names = (const char *[]){ ++ "gmac1_rx_div_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy_tx_clk = { ++ .halt_reg = 0x56114, ++ .clkr = { ++ .enable_reg = 0x56114, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_uniphy_tx_clk", ++ .parent_names = (const char *[]){ ++ "gmac1_tx_div_clk_src" ++ }, ++ .num_parents = 1, ++ .ops = &clk_branch2_ops, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_uniphy_sys_clk = { ++ .halt_reg = 0x5610C, ++ .clkr = { ++ .enable_reg = 0x5610C, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_uniphy_sys_clk", ++ .parent_names = (const char *[]){ ++ "gcc_xo_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_aux_clk = { ++ .halt_reg = 0x3e044, ++ .clkr = { ++ .enable_reg = 0x3e044, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_usb0_aux_clk", ++ .parent_names = (const char *[]){ ++ "usb0_aux_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_eud_at_clk = { ++ .halt_reg = 0x3e04c, ++ .halt_check = BRANCH_HALT_VOTED, ++ .clkr = { ++ .enable_reg = 0x3e04c, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_usb0_eud_at_clk", ++ .parent_names = (const char *[]){ ++ "eud_at_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_lfps_clk = { ++ .halt_reg = 0x3e050, ++ .clkr = { ++ .enable_reg = 0x3e050, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_usb0_lfps_clk", ++ .parent_names = (const char *[]){ ++ "usb0_lfps_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_master_clk = { ++ .halt_reg = 0x3e000, ++ .clkr = { ++ .enable_reg = 0x3e000, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_usb0_master_clk", ++ .parent_names = (const char *[]){ ++ "usb0_master_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_mock_utmi_clk = { ++ .halt_reg = 0x3e008, ++ .clkr = { ++ .enable_reg = 0x3e008, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_usb0_mock_utmi_clk", ++ .parent_names = (const char *[]){ ++ "usb0_mock_utmi_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = { ++ .halt_reg = 0x3e080, ++ .clkr = { ++ .enable_reg = 0x3e080, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_usb0_phy_cfg_ahb_clk", ++ .parent_names = (const char *[]){ ++ "pcnoc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_sleep_clk = { ++ .halt_reg = 0x3e004, ++ .clkr = { ++ .enable_reg = 0x3e004, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_usb0_sleep_clk", ++ .parent_names = (const char *[]){ ++ "gcc_sleep_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_usb0_pipe_clk = { ++ .halt_reg = 0x3e040, ++ .halt_check = BRANCH_HALT_DELAY, ++ .clkr = { ++ .enable_reg = 0x3e040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_usb0_pipe_clk", ++ .parent_names = (const char *[]){ ++ "usb0_pipe_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_acmt_clk = { ++ .halt_reg = 0x59064, ++ .clkr = { ++ .enable_reg = 0x59064, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_acmt_clk", ++ .parent_names = (const char *[]){ ++ "wcss_ahb_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_ahb_s_clk = { ++ .halt_reg = 0x59034, ++ .clkr = { ++ .enable_reg = 0x59034, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_ahb_s_clk", ++ .parent_names = (const char *[]){ ++ "wcss_ahb_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_axi_m_clk = { ++ .halt_reg = 0x5903C, ++ .clkr = { ++ .enable_reg = 0x5903C, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_axi_m_clk", ++ .parent_names = (const char *[]){ ++ "system_noc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_axi_s_clk = { ++ .halt_reg = 0x59068, ++ .clkr = { ++ .enable_reg = 0x59068, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_axi_s_clk", ++ .parent_names = (const char *[]){ ++ "system_noc_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = { ++ .halt_reg = 0x59050, ++ .clkr = { ++ .enable_reg = 0x59050, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_dbg_ifc_apb_bdg_clk", ++ .parent_names = (const char *[]){ ++ "qdss_dap_sync_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = { ++ .halt_reg = 0x59040, ++ .clkr = { ++ .enable_reg = 0x59040, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_dbg_ifc_apb_clk", ++ .parent_names = (const char *[]){ ++ "qdss_dap_sync_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = { ++ .halt_reg = 0x59054, ++ .clkr = { ++ .enable_reg = 0x59054, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_dbg_ifc_atb_bdg_clk", ++ .parent_names = (const char *[]){ ++ "qdss_at_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = { ++ .halt_reg = 0x59044, ++ .clkr = { ++ .enable_reg = 0x59044, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_dbg_ifc_atb_clk", ++ .parent_names = (const char *[]){ ++ "qdss_at_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = { ++ .halt_reg = 0x59060, ++ .clkr = { ++ .enable_reg = 0x59060, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_dbg_ifc_dapbus_bdg_clk", ++ .parent_names = (const char *[]){ ++ "qdss_dap_sync_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = { ++ .halt_reg = 0x5905C, ++ .clkr = { ++ .enable_reg = 0x5905C, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_dbg_ifc_dapbus_clk", ++ .parent_names = (const char *[]){ ++ "qdss_dap_sync_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = { ++ .halt_reg = 0x59058, ++ .clkr = { ++ .enable_reg = 0x59058, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_dbg_ifc_nts_bdg_clk", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_div2_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = { ++ .halt_reg = 0x59048, ++ .clkr = { ++ .enable_reg = 0x59048, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_dbg_ifc_nts_clk", ++ .parent_names = (const char *[]){ ++ "qdss_tsctr_div2_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_branch gcc_wcss_ecahb_clk = { ++ .halt_reg = 0x59038, ++ .clkr = { ++ .enable_reg = 0x59038, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_wcss_ecahb_clk", ++ .parent_names = (const char *[]){ ++ "wcss_ahb_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ ++static struct clk_hw *gcc_ipq5018_hws[] = { ++ &gpll0_out_main_div2.hw, ++ &pcnoc_clk_src.hw, ++ &system_noc_clk_src.hw, ++ &qdss_dap_sync_clk_src.hw, ++ &qdss_tsctr_div2_clk_src.hw, ++ &eud_at_clk_src.hw, ++}; ++ ++static const struct alpha_pll_config ubi32_pll_config = { ++ .l = 0x29, ++ .alpha = 0xAAAAAAAA, ++ .alpha_hi = 0xAA, ++ .config_ctl_val = 0x4001075b, ++ .main_output_mask = BIT(0), ++ .aux_output_mask = BIT(1), ++ .alpha_en_mask = BIT(24), ++ .vco_val = 0x1, ++ .vco_mask = GENMASK(21, 20), ++ .test_ctl_val = 0x0, ++ .test_ctl_hi_val = 0x0, ++}; ++ ++static struct clk_regmap *gcc_ipq5018_clks[] = { ++ [GPLL0_MAIN] = &gpll0_main.clkr, ++ [GPLL0] = &gpll0.clkr, ++ [GPLL2_MAIN] = &gpll2_main.clkr, ++ [GPLL2] = &gpll2.clkr, ++ [GPLL4_MAIN] = &gpll4_main.clkr, ++ [GPLL4] = &gpll4.clkr, ++ [UBI32_PLL_MAIN] = &ubi32_pll_main.clkr, ++ [UBI32_PLL] = &ubi32_pll.clkr, ++ [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, ++ [APSS_AHB_POSTDIV_CLK_SRC] = &apss_ahb_postdiv_clk_src.clkr, ++ [APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr, ++ [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, ++ [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, ++ [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, ++ [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, ++ [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, ++ [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, ++ [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, ++ [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, ++ [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, ++ [GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr, ++ [GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr, ++ [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, ++ [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, ++ [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, ++ [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, ++ [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, ++ [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, ++ [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, ++ [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, ++ [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, ++ [GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr, ++ [GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr, ++ [GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr, ++ [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, ++ [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, ++ [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, ++ [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, ++ [GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr, ++ [GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr, ++ [GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr, ++ [GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr, ++ [GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr, ++ [GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr, ++ [GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr, ++ [GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr, ++ [GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr, ++ [GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr, ++ [GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr, ++ [GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr, ++ [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, ++ [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, ++ [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, ++ [GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr, ++ [GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr, ++ [GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr, ++ [GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr, ++ [GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr, ++ [GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr, ++ [GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr, ++ [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, ++ [GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr, ++ [GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr, ++ [GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr, ++ [GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr, ++ [GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr, ++ [GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr, ++ [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, ++ [GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr, ++ [GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr, ++ [GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr, ++ [GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr, ++ [GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr, ++ [GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr, ++ [GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr, ++ [GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr, ++ [GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr, ++ [GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr, ++ [GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr, ++ [GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr, ++ [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, ++ [GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr, ++ [GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr, ++ [GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr, ++ [GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr, ++ [GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr, ++ [GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr, ++ [GCC_QPIC_CLK] = &gcc_qpic_clk.clkr, ++ [GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr, ++ [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, ++ [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, ++ [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, ++ [GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr, ++ [GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr, ++ [GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr, ++ [GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr, ++ [GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr, ++ [GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr, ++ [GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr, ++ [GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr, ++ [GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr, ++ [GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr, ++ [GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr, ++ [GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr, ++ [GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr, ++ [GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr, ++ [GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr, ++ [GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr, ++ [GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr, ++ [GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr, ++ [GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr, ++ [GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr, ++ [GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr, ++ [GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr, ++ [GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr, ++ [GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr, ++ [GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr, ++ [GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr, ++ [GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr, ++ [GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr, ++ [GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr, ++ [GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr, ++ [GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr, ++ [GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr, ++ [GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr, ++ [GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr, ++ [GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr, ++ [GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr, ++ [GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr, ++ [GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr, ++ [GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr, ++ [GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr, ++ [GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr, ++ [GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr, ++ [GCC_XO_CLK] = &gcc_xo_clk.clkr, ++ [GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr, ++ [GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr, ++ [GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr, ++ [GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr, ++ [GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr, ++ [GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr, ++ [GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr, ++ [GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr, ++ [GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr, ++ [GMAC_CLK_SRC] = &gmac_clk_src.clkr, ++ [GP1_CLK_SRC] = &gp1_clk_src.clkr, ++ [GP2_CLK_SRC] = &gp2_clk_src.clkr, ++ [GP3_CLK_SRC] = &gp3_clk_src.clkr, ++ [LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr, ++ [LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr, ++ [PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr, ++ [PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr, ++ [PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr, ++ [PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr, ++ [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, ++ [Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr, ++ [QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr, ++ [QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr, ++ [QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr, ++ [QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr, ++ [QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr, ++ [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, ++ [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, ++ [UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr, ++ [UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr, ++ [USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr, ++ [USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr, ++ [USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr, ++ [USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr, ++ [WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr, ++ [PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr, ++ [PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr, ++ [GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr, ++ [GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr, ++ [USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr, ++ [GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr, ++}; ++ ++static const struct qcom_reset_map gcc_ipq5018_resets[] = { ++ [GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 }, ++ [GCC_BLSP1_BCR] = { 0x01000, 0 }, ++ [GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 }, ++ [GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 }, ++ [GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 }, ++ [GCC_BLSP1_UART1_BCR] = { 0x02038, 0 }, ++ [GCC_BLSP1_UART2_BCR] = { 0x03028, 0 }, ++ [GCC_BOOT_ROM_BCR] = { 0x13008, 0 }, ++ [GCC_BTSS_BCR] = { 0x1c000, 0 }, ++ [GCC_CMN_BLK_BCR] = { 0x56300, 0 }, ++ [GCC_CMN_LDO_BCR] = { 0x33000, 0 }, ++ [GCC_CE_BCR] = { 0x33014, 0 }, ++ [GCC_CRYPTO_BCR] = { 0x16000, 0 }, ++ [GCC_DCC_BCR] = { 0x77000, 0 }, ++ [GCC_DCD_BCR] = { 0x2a000, 0 }, ++ [GCC_DDRSS_BCR] = { 0x1e000, 0 }, ++ [GCC_EDPD_BCR] = { 0x3a000, 0 }, ++ [GCC_GEPHY_BCR] = { 0x56000, 0 }, ++ [GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 }, ++ [GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 }, ++ [GCC_GEPHY_RX_ARES] = { 0x56004, 2 }, ++ [GCC_GEPHY_TX_ARES] = { 0x56004, 3 }, ++ [GCC_GMAC0_BCR] = { 0x19000, 0 }, ++ [GCC_GMAC0_CFG_ARES] = { 0x68428, 0 }, ++ [GCC_GMAC0_SYS_ARES] = { 0x68428, 1 }, ++ [GCC_GMAC1_BCR] = { 0x19100, 0 }, ++ [GCC_GMAC1_CFG_ARES] = { 0x68438, 0 }, ++ [GCC_GMAC1_SYS_ARES] = { 0x68438, 1 }, ++ [GCC_IMEM_BCR] = { 0x0e000, 0 }, ++ [GCC_LPASS_BCR] = { 0x2e000, 0 }, ++ [GCC_MDIO0_BCR] = { 0x58000, 0 }, ++ [GCC_MDIO1_BCR] = { 0x58010, 0 }, ++ [GCC_MPM_BCR] = { 0x2c000, 0 }, ++ [GCC_PCIE0_BCR] = { 0x75004, 0 }, ++ [GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 }, ++ [GCC_PCIE0_PHY_BCR] = { 0x75038, 0 }, ++ [GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 }, ++ [GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 }, ++ [GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 }, ++ [GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 }, ++ [GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 }, ++ [GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 }, ++ [GCC_PCIE0_AHB_ARES] = { 0x75040, 5 }, ++ [GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 }, ++ [GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 }, ++ [GCC_PCIE1_BCR] = { 0x76004, 0 }, ++ [GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 }, ++ [GCC_PCIE1_PHY_BCR] = { 0x76038, 0 }, ++ [GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 }, ++ [GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 }, ++ [GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 }, ++ [GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 }, ++ [GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 }, ++ [GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 }, ++ [GCC_PCIE1_AHB_ARES] = { 0x76040, 5 }, ++ [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, ++ [GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 }, ++ [GCC_PCNOC_BCR] = { 0x27018, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 }, ++ [GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 }, ++ [GCC_PRNG_BCR] = { 0x13000, 0 }, ++ [GCC_Q6SS_DBG_ARES] = { 0x59110, 0 }, ++ [GCC_Q6_AHB_S_ARES] = { 0x59110, 1 }, ++ [GCC_Q6_AHB_ARES] = { 0x59110, 2 }, ++ [GCC_Q6_AXIM2_ARES] = { 0x59110, 3 }, ++ [GCC_Q6_AXIM_ARES] = { 0x59110, 4 }, ++ [GCC_Q6_AXIS_ARES] = { 0x59158, 0 }, ++ [GCC_QDSS_BCR] = { 0x29000, 0 }, ++ [GCC_QPIC_BCR] = { 0x57018, 0 }, ++ [GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 }, ++ [GCC_SDCC1_BCR] = { 0x42000, 0 }, ++ [GCC_SEC_CTRL_BCR] = { 0x1a000, 0 }, ++ [GCC_SPDM_BCR] = { 0x2f000, 0 }, ++ [GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 }, ++ [GCC_TCSR_BCR] = { 0x28000, 0 }, ++ [GCC_TLMM_BCR] = { 0x34000, 0 }, ++ [GCC_UBI0_AXI_ARES] = { 0x68010, 0 }, ++ [GCC_UBI0_AHB_ARES] = { 0x68010, 1 }, ++ [GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 }, ++ [GCC_UBI0_DBG_ARES] = { 0x68010, 3 }, ++ [GCC_UBI0_UTCM_ARES] = { 0x68010, 6 }, ++ [GCC_UBI0_CORE_ARES] = { 0x68010, 7 }, ++ [GCC_UBI32_BCR] = { 0x19064, 0 }, ++ [GCC_UNIPHY_BCR] = { 0x56100, 0 }, ++ [GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 }, ++ [GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 }, ++ [GCC_UNIPHY_RX_ARES] = { 0x56104, 4 }, ++ [GCC_UNIPHY_TX_ARES] = { 0x56104, 5 }, ++ [GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 }, ++ [GCC_USB0_BCR] = { 0x3e070, 0 }, ++ [GCC_USB0_PHY_BCR] = { 0x3e034, 0 }, ++ [GCC_WCSS_BCR] = { 0x18000, 0 }, ++ [GCC_WCSS_DBG_ARES] = { 0x59008, 0 }, ++ [GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 }, ++ [GCC_WCSS_ACMT_ARES] = { 0x59008, 2 }, ++ [GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 }, ++ [GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 }, ++ [GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 }, ++ [GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 }, ++ [GCC_WCSS_Q6_BCR] = { 0x18004, 0 }, ++ [GCC_WCSSAON_RESET] = { 0x59010, 0}, ++ [GCC_GEPHY_MISC_ARES] = { 0x56004, 0 }, ++}; ++ ++static const struct of_device_id gcc_ipq5018_match_table[] = { ++ { .compatible = "qcom,gcc-ipq5018" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table); ++ ++static const struct regmap_config gcc_ipq5018_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x7fffc, ++ .fast_io = true, ++}; ++ ++static const struct qcom_cc_desc gcc_ipq5018_desc = { ++ .config = &gcc_ipq5018_regmap_config, ++ .clks = gcc_ipq5018_clks, ++ .num_clks = ARRAY_SIZE(gcc_ipq5018_clks), ++ .resets = gcc_ipq5018_resets, ++ .num_resets = ARRAY_SIZE(gcc_ipq5018_resets), ++}; ++ ++static int gcc_ipq5018_probe(struct platform_device *pdev) ++{ ++ int i, ret; ++ struct regmap *regmap; ++ struct clk *clk; ++ struct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc; ++ ++ regmap = qcom_cc_map(pdev, &ipq5018_desc); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ for (i = 0; i < ARRAY_SIZE(gcc_ipq5018_hws); i++) { ++ clk = devm_clk_register(&pdev->dev, gcc_ipq5018_hws[i]); ++ if (IS_ERR(clk)) ++ return PTR_ERR(clk); ++ } ++ /*Gen2 PHY*/ ++ clk_register_fixed_rate(&pdev->dev, "pcie20_phy0_pipe_clk", NULL, ++ CLK_IS_ROOT, 125000000); ++ clk_register_fixed_rate(&pdev->dev, "pcie20_phy1_pipe_clk", NULL, ++ CLK_IS_ROOT, 125000000); ++ ++ clk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config); ++ ++ ret = qcom_cc_really_probe(pdev, &ipq5018_desc, regmap); ++ if (ret) { ++ dev_err(&pdev->dev, "Failed to register ipq5018 GCC clocks\n"); ++ return ret; ++ } ++ ++ dev_info(&pdev->dev, "Registered ipq5018 GCC clocks provider"); ++ ++ return ret; ++} ++ ++static int gcc_ipq5018_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++static struct platform_driver gcc_ipq5018_driver = { ++ .probe = gcc_ipq5018_probe, ++ .remove = gcc_ipq5018_remove, ++ .driver = { ++ .name = "qcom,gcc-ipq5018", ++ .owner = THIS_MODULE, ++ .of_match_table = gcc_ipq5018_match_table, ++ }, ++}; ++ ++static int __init gcc_ipq5018_init(void) ++{ ++ return platform_driver_register(&gcc_ipq5018_driver); ++} ++core_initcall(gcc_ipq5018_init); ++ ++static void __exit gcc_ipq5018_exit(void) ++{ ++ platform_driver_unregister(&gcc_ipq5018_driver); ++} ++module_exit(gcc_ipq5018_exit); ++ ++MODULE_DESCRIPTION("Qualcomm Technologies, Inc. GCC IPQ5018 Driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:gcc-ipq5018"); +diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h +index 2fdfe8061363..f456fa4268b9 100644 +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -20,8 +20,8 @@ + #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ + #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ + #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ +- /* unused */ +- /* unused */ ++#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ ++#define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ + #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ + #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */ + #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */ +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/304-dt-bindings-pinctrl-qcom-Add-ipq5018-pinctrl-binding.patch b/target/linux/ipq50xx/patches/304-dt-bindings-pinctrl-qcom-Add-ipq5018-pinctrl-binding.patch new file mode 100644 index 0000000000..8bf550a97b --- /dev/null +++ b/target/linux/ipq50xx/patches/304-dt-bindings-pinctrl-qcom-Add-ipq5018-pinctrl-binding.patch @@ -0,0 +1,172 @@ +From f73d46914ae5bd46f7fcbec12a680dbb62c383d6 Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Mon, 28 Sep 2020 10:45:37 +0530 +Subject: [PATCH 4/7] dt-bindings: pinctrl: qcom: Add ipq5018 pinctrl bindings + +Add device tree binding Documentation details for ipq5018 +pinctrl driver. + +Signed-off-by: Varadarajan Narayanan + +Pick from <1601270140-4306-5-git-send-email-varada@codeaurora.org> + +Fix gpio-ranges + +Signed-off-by: hzy +--- + .../pinctrl/qcom,ipq5018-pinctrl.yaml | 143 ++++++++++++++++++ + 1 file changed, 143 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml + +diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml +new file mode 100644 +index 000000000000..237ef50a9562 +--- /dev/null ++++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml +@@ -0,0 +1,143 @@ ++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-pinctrl.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Qualcomm Technologies, Inc. IPQ5018 TLMM block ++ ++maintainers: ++ - Nitheesh Sekar ++ ++description: | ++ This binding describes the Top Level Mode Multiplexer block found in the ++ IPQ5018 platform. ++ ++properties: ++ compatible: ++ const: qcom,ipq5018-pinctrl ++ ++ reg: ++ maxItems: 1 ++ ++ interrupts: ++ description: Specifies the TLMM summary IRQ ++ maxItems: 1 ++ ++ interrupt-controller: true ++ ++ '#interrupt-cells': ++ description: ++ Specifies the PIN numbers and Flags, as defined in defined in ++ include/dt-bindings/interrupt-controller/irq.h ++ const: 2 ++ ++ gpio-controller: true ++ ++ '#gpio-cells': ++ description: Specifying the pin number and flags, as defined in ++ include/dt-bindings/gpio/gpio.h ++ const: 2 ++ ++ gpio-ranges: ++ maxItems: 1 ++ ++#PIN CONFIGURATION NODES ++patternProperties: ++ '-pinmux$': ++ type: object ++ description: ++ Pinctrl node's client devices use subnodes for desired pin configuration. ++ Client device subnodes use below standard properties. ++ $ref: "/schemas/pinctrl/pincfg-node.yaml" ++ ++ properties: ++ pins: ++ description: ++ List of gpio pins affected by the properties specified in this ++ subnode. ++ items: ++ oneOf: ++ - pattern: "^gpio([1-9]|[1-7][0-9]|80)$" ++ minItems: 1 ++ maxItems: 4 ++ ++ function: ++ description: ++ Specify the alternative function to be configured for the specified ++ pins. ++ enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3, ++ audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd, audio_rxfsync, ++ audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync, audio_txmclk, ++ blsp0_i2c, blsp0_spi, blsp0_uart0, blsp0_uart1, blsp1_i2c0, ++ blsp1_i2c1, blsp1_spi0, blsp1_spi1, blsp1_uart0, blsp1_uart1, ++ blsp1_uart2, blsp2_i2c0, blsp2_i2c1, blsp2_spi, blsp2_spi0, ++ blsp2_spi1, btss0, btss1, btss10, btss11, btss12, btss13, btss2, ++ btss3, btss4, btss5, btss6, btss7, btss8, btss9, burn0, burn1, ++ cri_trng, cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio, ++ gcc_plltest, gcc_tlmm, gpio, mac0, mac1, mdc, mdio, pcie0_clk, ++ pcie0_wake, pcie1_clk, pcie1_wake, pll_test, prng_rosc, pwm0, pwm1, ++ pwm2, pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, ++ qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, ++ qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, ++ qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b, ++ qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs, qspi0, qspi1, ++ qspi2, qspi3, reset_out, sdc1_clk, sdc1_cmd, sdc10, sdc11, sdc12, ++ sdc13, wci0, wci1, wci2, wci3, wci4, wci5, wci6, wci7, wsa_swrm, ++ wsi_clk3, wsi_data3, wsis_reset, xfem0, xfem1, xfem2, xfem3, xfem4, ++ xfem5, xfem6, xfem7 ] ++ ++ drive-strength: ++ enum: [2, 4, 6, 8, 10, 12, 14, 16] ++ default: 2 ++ description: ++ Selects the drive strength for the specified pins, in mA. ++ ++ bias-pull-down: true ++ ++ bias-pull-up: true ++ ++ bias-disable: true ++ ++ output-high: true ++ ++ output-low: true ++ ++ required: ++ - pins ++ - function ++ ++ additionalProperties: false ++ ++required: ++ - compatible ++ - reg ++ - interrupts ++ - interrupt-controller ++ - '#interrupt-cells' ++ - gpio-controller ++ - '#gpio-cells' ++ - gpio-ranges ++ ++additionalProperties: false ++ ++examples: ++ - | ++ #include ++ tlmm: pinctrl@1000000 { ++ compatible = "qcom,ipq5018-pinctrl"; ++ reg = <0x01000000 0x300000>; ++ interrupts = ; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&tlmm 0 0 80>; ++ ++ serial3-pinmux { ++ pins = "gpio44", "gpio45"; ++ function = "blsp2_uart"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/305-pinctrl-qcom-Add-IPQ5018-pinctrl-driver.patch b/target/linux/ipq50xx/patches/305-pinctrl-qcom-Add-IPQ5018-pinctrl-driver.patch new file mode 100644 index 0000000000..5b337c07b1 --- /dev/null +++ b/target/linux/ipq50xx/patches/305-pinctrl-qcom-Add-IPQ5018-pinctrl-driver.patch @@ -0,0 +1,964 @@ +From 0031239077dbc526fea08039641c605508680098 Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Mon, 28 Sep 2020 10:45:38 +0530 +Subject: [PATCH 5/7] pinctrl: qcom: Add IPQ5018 pinctrl driver + +This adds the pinctrl definitions for the TLMM of IPQ5018. + +Signed-off-by: Varadarajan Narayanan + +Pick from <1601270140-4306-6-git-send-email-varada@codeaurora.org> + +Signed-off-by: hzy +--- + drivers/pinctrl/qcom/Kconfig | 10 + + drivers/pinctrl/qcom/Makefile | 1 + + drivers/pinctrl/qcom/pinctrl-ipq5018.c | 903 +++++++++++++++++++++++++ + 3 files changed, 914 insertions(+) + create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c + +diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig +index 32fc2458b8eb..480a562ba96e 100644 +--- a/drivers/pinctrl/qcom/Kconfig ++++ b/drivers/pinctrl/qcom/Kconfig +@@ -32,6 +32,16 @@ config PINCTRL_IPQ4019 + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm TLMM block found in the Qualcomm IPQ4019 platform. + ++config PINCTRL_IPQ5018 ++ tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver" ++ depends on GPIOLIB && OF ++ select PINCTRL_MSM ++ help ++ This is the pinctrl, pinmux, pinconf and gpiolib driver for ++ the Qualcomm Technologies Inc. TLMM block found on the ++ Qualcomm Technologies Inc. IPQ5018 platform. Select this for ++ IPQ5018. ++ + config PINCTRL_IPQ8064 + tristate "Qualcomm IPQ8064 pin controller driver" + depends on GPIOLIB && OF +diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile +index f8bb0c265381..3b14cb92d443 100644 +--- a/drivers/pinctrl/qcom/Makefile ++++ b/drivers/pinctrl/qcom/Makefile +@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o + obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o + obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o + obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o ++obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o + obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o + obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o + obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o +diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c +new file mode 100644 +index 000000000000..92b38c4297e0 +--- /dev/null ++++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c +@@ -0,0 +1,903 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include "pinctrl-msm.h" ++ ++#define FUNCTION(fname) \ ++ [msm_mux_##fname] = { \ ++ .name = #fname, \ ++ .groups = fname##_groups, \ ++ .ngroups = ARRAY_SIZE(fname##_groups), \ ++ } ++ ++#define REG_SIZE 0x1000 ++#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \ ++ { \ ++ .name = "gpio" #id, \ ++ .pins = gpio##id##_pins, \ ++ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \ ++ .funcs = (int[]){ \ ++ msm_mux_gpio, /* gpio mode */ \ ++ msm_mux_##f1, \ ++ msm_mux_##f2, \ ++ msm_mux_##f3, \ ++ msm_mux_##f4, \ ++ msm_mux_##f5, \ ++ msm_mux_##f6, \ ++ msm_mux_##f7, \ ++ msm_mux_##f8, \ ++ msm_mux_##f9 \ ++ }, \ ++ .nfuncs = 10, \ ++ .ctl_reg = REG_SIZE * id, \ ++ .io_reg = 0x4 + REG_SIZE * id, \ ++ .intr_cfg_reg = 0x8 + REG_SIZE * id, \ ++ .intr_status_reg = 0xc + REG_SIZE * id, \ ++ .intr_target_reg = 0x8 + REG_SIZE * id, \ ++ .mux_bit = 2, \ ++ .pull_bit = 0, \ ++ .drv_bit = 6, \ ++ .oe_bit = 9, \ ++ .in_bit = 0, \ ++ .out_bit = 1, \ ++ .intr_enable_bit = 0, \ ++ .intr_status_bit = 0, \ ++ .intr_target_bit = 5, \ ++ .intr_target_kpss_val = 3, \ ++ .intr_raw_status_bit = 4, \ ++ .intr_polarity_bit = 1, \ ++ .intr_detection_bit = 2, \ ++ .intr_detection_width = 2, \ ++ } ++ ++static const struct pinctrl_pin_desc ipq5018_pins[] = { ++ PINCTRL_PIN(0, "GPIO_0"), ++ PINCTRL_PIN(1, "GPIO_1"), ++ PINCTRL_PIN(2, "GPIO_2"), ++ PINCTRL_PIN(3, "GPIO_3"), ++ PINCTRL_PIN(4, "GPIO_4"), ++ PINCTRL_PIN(5, "GPIO_5"), ++ PINCTRL_PIN(6, "GPIO_6"), ++ PINCTRL_PIN(7, "GPIO_7"), ++ PINCTRL_PIN(8, "GPIO_8"), ++ PINCTRL_PIN(9, "GPIO_9"), ++ PINCTRL_PIN(10, "GPIO_10"), ++ PINCTRL_PIN(11, "GPIO_11"), ++ PINCTRL_PIN(12, "GPIO_12"), ++ PINCTRL_PIN(13, "GPIO_13"), ++ PINCTRL_PIN(14, "GPIO_14"), ++ PINCTRL_PIN(15, "GPIO_15"), ++ PINCTRL_PIN(16, "GPIO_16"), ++ PINCTRL_PIN(17, "GPIO_17"), ++ PINCTRL_PIN(18, "GPIO_18"), ++ PINCTRL_PIN(19, "GPIO_19"), ++ PINCTRL_PIN(20, "GPIO_20"), ++ PINCTRL_PIN(21, "GPIO_21"), ++ PINCTRL_PIN(22, "GPIO_22"), ++ PINCTRL_PIN(23, "GPIO_23"), ++ PINCTRL_PIN(24, "GPIO_24"), ++ PINCTRL_PIN(25, "GPIO_25"), ++ PINCTRL_PIN(26, "GPIO_26"), ++ PINCTRL_PIN(27, "GPIO_27"), ++ PINCTRL_PIN(28, "GPIO_28"), ++ PINCTRL_PIN(29, "GPIO_29"), ++ PINCTRL_PIN(30, "GPIO_30"), ++ PINCTRL_PIN(31, "GPIO_31"), ++ PINCTRL_PIN(32, "GPIO_32"), ++ PINCTRL_PIN(33, "GPIO_33"), ++ PINCTRL_PIN(34, "GPIO_34"), ++ PINCTRL_PIN(35, "GPIO_35"), ++ PINCTRL_PIN(36, "GPIO_36"), ++ PINCTRL_PIN(37, "GPIO_37"), ++ PINCTRL_PIN(38, "GPIO_38"), ++ PINCTRL_PIN(39, "GPIO_39"), ++ PINCTRL_PIN(40, "GPIO_40"), ++ PINCTRL_PIN(41, "GPIO_41"), ++ PINCTRL_PIN(42, "GPIO_42"), ++ PINCTRL_PIN(43, "GPIO_43"), ++ PINCTRL_PIN(44, "GPIO_44"), ++ PINCTRL_PIN(45, "GPIO_45"), ++ PINCTRL_PIN(46, "GPIO_46"), ++}; ++ ++#define DECLARE_MSM_GPIO_PINS(pin) \ ++ static const unsigned int gpio##pin##_pins[] = { pin } ++DECLARE_MSM_GPIO_PINS(0); ++DECLARE_MSM_GPIO_PINS(1); ++DECLARE_MSM_GPIO_PINS(2); ++DECLARE_MSM_GPIO_PINS(3); ++DECLARE_MSM_GPIO_PINS(4); ++DECLARE_MSM_GPIO_PINS(5); ++DECLARE_MSM_GPIO_PINS(6); ++DECLARE_MSM_GPIO_PINS(7); ++DECLARE_MSM_GPIO_PINS(8); ++DECLARE_MSM_GPIO_PINS(9); ++DECLARE_MSM_GPIO_PINS(10); ++DECLARE_MSM_GPIO_PINS(11); ++DECLARE_MSM_GPIO_PINS(12); ++DECLARE_MSM_GPIO_PINS(13); ++DECLARE_MSM_GPIO_PINS(14); ++DECLARE_MSM_GPIO_PINS(15); ++DECLARE_MSM_GPIO_PINS(16); ++DECLARE_MSM_GPIO_PINS(17); ++DECLARE_MSM_GPIO_PINS(18); ++DECLARE_MSM_GPIO_PINS(19); ++DECLARE_MSM_GPIO_PINS(20); ++DECLARE_MSM_GPIO_PINS(21); ++DECLARE_MSM_GPIO_PINS(22); ++DECLARE_MSM_GPIO_PINS(23); ++DECLARE_MSM_GPIO_PINS(24); ++DECLARE_MSM_GPIO_PINS(25); ++DECLARE_MSM_GPIO_PINS(26); ++DECLARE_MSM_GPIO_PINS(27); ++DECLARE_MSM_GPIO_PINS(28); ++DECLARE_MSM_GPIO_PINS(29); ++DECLARE_MSM_GPIO_PINS(30); ++DECLARE_MSM_GPIO_PINS(31); ++DECLARE_MSM_GPIO_PINS(32); ++DECLARE_MSM_GPIO_PINS(33); ++DECLARE_MSM_GPIO_PINS(34); ++DECLARE_MSM_GPIO_PINS(35); ++DECLARE_MSM_GPIO_PINS(36); ++DECLARE_MSM_GPIO_PINS(37); ++DECLARE_MSM_GPIO_PINS(38); ++DECLARE_MSM_GPIO_PINS(39); ++DECLARE_MSM_GPIO_PINS(40); ++DECLARE_MSM_GPIO_PINS(41); ++DECLARE_MSM_GPIO_PINS(42); ++DECLARE_MSM_GPIO_PINS(43); ++DECLARE_MSM_GPIO_PINS(44); ++DECLARE_MSM_GPIO_PINS(45); ++DECLARE_MSM_GPIO_PINS(46); ++ ++enum ipq5018_functions { ++ msm_mux_atest_char, ++ msm_mux_atest_char0, ++ msm_mux_atest_char1, ++ msm_mux_atest_char2, ++ msm_mux_atest_char3, ++ msm_mux_audio_pdm0, ++ msm_mux_audio_pdm1, ++ msm_mux_audio_rxbclk, ++ msm_mux_audio_rxd, ++ msm_mux_audio_rxfsync, ++ msm_mux_audio_rxmclk, ++ msm_mux_audio_txbclk, ++ msm_mux_audio_txd, ++ msm_mux_audio_txfsync, ++ msm_mux_audio_txmclk, ++ msm_mux_blsp0_i2c, ++ msm_mux_blsp0_spi, ++ msm_mux_blsp0_uart0, ++ msm_mux_blsp0_uart1, ++ msm_mux_blsp1_i2c0, ++ msm_mux_blsp1_i2c1, ++ msm_mux_blsp1_spi0, ++ msm_mux_blsp1_spi1, ++ msm_mux_blsp1_uart0, ++ msm_mux_blsp1_uart1, ++ msm_mux_blsp1_uart2, ++ msm_mux_blsp2_i2c0, ++ msm_mux_blsp2_i2c1, ++ msm_mux_blsp2_spi, ++ msm_mux_blsp2_spi0, ++ msm_mux_blsp2_spi1, ++ msm_mux_btss0, ++ msm_mux_btss1, ++ msm_mux_btss10, ++ msm_mux_btss11, ++ msm_mux_btss12, ++ msm_mux_btss13, ++ msm_mux_btss2, ++ msm_mux_btss3, ++ msm_mux_btss4, ++ msm_mux_btss5, ++ msm_mux_btss6, ++ msm_mux_btss7, ++ msm_mux_btss8, ++ msm_mux_btss9, ++ msm_mux_burn0, ++ msm_mux_burn1, ++ msm_mux_cri_trng, ++ msm_mux_cri_trng0, ++ msm_mux_cri_trng1, ++ msm_mux_cxc_clk, ++ msm_mux_cxc_data, ++ msm_mux_dbg_out, ++ msm_mux_eud_gpio, ++ msm_mux_gcc_plltest, ++ msm_mux_gcc_tlmm, ++ msm_mux_gpio, ++ msm_mux_mac0, ++ msm_mux_mac1, ++ msm_mux_mdc, ++ msm_mux_mdio, ++ msm_mux_pcie0_clk, ++ msm_mux_pcie0_wake, ++ msm_mux_pcie1_clk, ++ msm_mux_pcie1_wake, ++ msm_mux_pll_test, ++ msm_mux_prng_rosc, ++ msm_mux_pwm0, ++ msm_mux_pwm1, ++ msm_mux_pwm2, ++ msm_mux_pwm3, ++ msm_mux_qdss_cti_trig_in_a0, ++ msm_mux_qdss_cti_trig_in_a1, ++ msm_mux_qdss_cti_trig_in_b0, ++ msm_mux_qdss_cti_trig_in_b1, ++ msm_mux_qdss_cti_trig_out_a0, ++ msm_mux_qdss_cti_trig_out_a1, ++ msm_mux_qdss_cti_trig_out_b0, ++ msm_mux_qdss_cti_trig_out_b1, ++ msm_mux_qdss_traceclk_a, ++ msm_mux_qdss_traceclk_b, ++ msm_mux_qdss_tracectl_a, ++ msm_mux_qdss_tracectl_b, ++ msm_mux_qdss_tracedata_a, ++ msm_mux_qdss_tracedata_b, ++ msm_mux_qspi_clk, ++ msm_mux_qspi_cs, ++ msm_mux_qspi0, ++ msm_mux_qspi1, ++ msm_mux_qspi2, ++ msm_mux_qspi3, ++ msm_mux_reset_out, ++ msm_mux_sdc1_clk, ++ msm_mux_sdc1_cmd, ++ msm_mux_sdc10, ++ msm_mux_sdc11, ++ msm_mux_sdc12, ++ msm_mux_sdc13, ++ msm_mux_wci0, ++ msm_mux_wci1, ++ msm_mux_wci2, ++ msm_mux_wci3, ++ msm_mux_wci4, ++ msm_mux_wci5, ++ msm_mux_wci6, ++ msm_mux_wci7, ++ msm_mux_wsa_swrm, ++ msm_mux_wsi_clk3, ++ msm_mux_wsi_data3, ++ msm_mux_wsis_reset, ++ msm_mux_xfem0, ++ msm_mux_xfem1, ++ msm_mux_xfem2, ++ msm_mux_xfem3, ++ msm_mux_xfem4, ++ msm_mux_xfem5, ++ msm_mux_xfem6, ++ msm_mux_xfem7, ++ msm_mux__, ++}; ++ ++static const char * const atest_char0_groups[] = { ++ "gpio0", ++}; ++static const char * const _groups[] = { ++ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", ++ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", ++ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", ++ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", ++ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", ++ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", "gpio46", ++}; ++static const char * const wci0_groups[] = { ++ "gpio0", "gpio0", ++}; ++static const char * const qdss_cti_trig_out_a0_groups[] = { ++ "gpio0", ++}; ++static const char * const xfem0_groups[] = { ++ "gpio0", ++}; ++static const char * const atest_char1_groups[] = { ++ "gpio1", ++}; ++static const char * const qdss_cti_trig_in_a0_groups[] = { ++ "gpio1", ++}; ++static const char * const wci1_groups[] = { ++ "gpio1", "gpio1", ++}; ++static const char * const xfem1_groups[] = { ++ "gpio1", ++}; ++static const char * const atest_char2_groups[] = { ++ "gpio2", ++}; ++static const char * const qdss_cti_trig_out_a1_groups[] = { ++ "gpio2", ++}; ++static const char * const wci2_groups[] = { ++ "gpio2", "gpio2", ++}; ++static const char * const xfem2_groups[] = { ++ "gpio2", ++}; ++static const char * const atest_char3_groups[] = { ++ "gpio3", ++}; ++static const char * const qdss_cti_trig_in_a1_groups[] = { ++ "gpio3", ++}; ++static const char * const wci3_groups[] = { ++ "gpio3", "gpio3", ++}; ++static const char * const xfem3_groups[] = { ++ "gpio3", ++}; ++static const char * const sdc13_groups[] = { ++ "gpio4", ++}; ++static const char * const qspi3_groups[] = { ++ "gpio4", ++}; ++static const char * const blsp1_spi1_groups[] = { ++ "gpio4", "gpio5", "gpio6", "gpio7", ++}; ++static const char * const btss0_groups[] = { ++ "gpio4", ++}; ++static const char * const dbg_out_groups[] = { ++ "gpio4", ++}; ++static const char * const qdss_traceclk_a_groups[] = { ++ "gpio4", ++}; ++static const char * const burn0_groups[] = { ++ "gpio4", ++}; ++static const char * const sdc12_groups[] = { ++ "gpio5", ++}; ++static const char * const qspi2_groups[] = { ++ "gpio5", ++}; ++static const char * const cxc_clk_groups[] = { ++ "gpio5", ++}; ++static const char * const blsp1_i2c1_groups[] = { ++ "gpio5", "gpio6", ++}; ++static const char * const btss1_groups[] = { ++ "gpio5", ++}; ++static const char * const qdss_tracectl_a_groups[] = { ++ "gpio5", ++}; ++static const char * const burn1_groups[] = { ++ "gpio5", ++}; ++static const char * const sdc11_groups[] = { ++ "gpio6", ++}; ++static const char * const qspi1_groups[] = { ++ "gpio6", ++}; ++static const char * const cxc_data_groups[] = { ++ "gpio6", ++}; ++static const char * const btss2_groups[] = { ++ "gpio6", ++}; ++static const char * const qdss_tracedata_a_groups[] = { ++ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", ++ "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", ++ "gpio20", "gpio21", ++}; ++static const char * const sdc10_groups[] = { ++ "gpio7", ++}; ++static const char * const qspi0_groups[] = { ++ "gpio7", ++}; ++static const char * const mac0_groups[] = { ++ "gpio7", ++}; ++static const char * const btss3_groups[] = { ++ "gpio7", ++}; ++static const char * const sdc1_cmd_groups[] = { ++ "gpio8", ++}; ++static const char * const qspi_cs_groups[] = { ++ "gpio8", ++}; ++static const char * const mac1_groups[] = { ++ "gpio8", ++}; ++static const char * const btss4_groups[] = { ++ "gpio8", ++}; ++static const char * const sdc1_clk_groups[] = { ++ "gpio9", ++}; ++static const char * const qspi_clk_groups[] = { ++ "gpio9", ++}; ++static const char * const blsp0_spi_groups[] = { ++ "gpio10", "gpio11", "gpio12", "gpio13", ++}; ++static const char * const blsp1_uart0_groups[] = { ++ "gpio10", "gpio11", "gpio12", "gpio13", ++}; ++static const char * const gcc_plltest_groups[] = { ++ "gpio10", "gpio12", ++}; ++static const char * const gcc_tlmm_groups[] = { ++ "gpio11", ++}; ++static const char * const blsp0_i2c_groups[] = { ++ "gpio12", "gpio13", ++}; ++static const char * const pcie0_clk_groups[] = { ++ "gpio14", ++}; ++static const char * const cri_trng0_groups[] = { ++ "gpio14", ++}; ++static const char * const cri_trng1_groups[] = { ++ "gpio15", ++}; ++static const char * const pcie0_wake_groups[] = { ++ "gpio16", ++}; ++static const char * const cri_trng_groups[] = { ++ "gpio16", ++}; ++static const char * const pcie1_clk_groups[] = { ++ "gpio17", ++}; ++static const char * const btss5_groups[] = { ++ "gpio17", ++}; ++static const char * const prng_rosc_groups[] = { ++ "gpio17", ++}; ++static const char * const blsp1_spi0_groups[] = { ++ "gpio18", "gpio19", "gpio20", "gpio21", ++}; ++static const char * const btss6_groups[] = { ++ "gpio18", ++}; ++static const char * const pcie1_wake_groups[] = { ++ "gpio19", ++}; ++static const char * const blsp1_i2c0_groups[] = { ++ "gpio19", "gpio20", ++}; ++static const char * const btss7_groups[] = { ++ "gpio19", ++}; ++static const char * const blsp0_uart0_groups[] = { ++ "gpio20", "gpio21", ++}; ++static const char * const pll_test_groups[] = { ++ "gpio22", ++}; ++static const char * const eud_gpio_groups[] = { ++ "gpio22", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", ++}; ++static const char * const audio_rxmclk_groups[] = { ++ "gpio23", "gpio23", ++}; ++static const char * const audio_pdm0_groups[] = { ++ "gpio23", "gpio24", ++}; ++static const char * const blsp2_spi1_groups[] = { ++ "gpio23", "gpio24", "gpio25", "gpio26", ++}; ++static const char * const blsp1_uart2_groups[] = { ++ "gpio23", "gpio24", "gpio25", "gpio26", ++}; ++static const char * const btss8_groups[] = { ++ "gpio23", ++}; ++static const char * const qdss_tracedata_b_groups[] = { ++ "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", ++ "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", ++ "gpio37", "gpio38", ++}; ++static const char * const audio_rxbclk_groups[] = { ++ "gpio24", ++}; ++static const char * const btss9_groups[] = { ++ "gpio24", ++}; ++static const char * const audio_rxfsync_groups[] = { ++ "gpio25", ++}; ++static const char * const audio_pdm1_groups[] = { ++ "gpio25", "gpio26", ++}; ++static const char * const blsp2_i2c1_groups[] = { ++ "gpio25", "gpio26", ++}; ++static const char * const btss10_groups[] = { ++ "gpio25", ++}; ++static const char * const audio_rxd_groups[] = { ++ "gpio26", ++}; ++static const char * const btss11_groups[] = { ++ "gpio26", ++}; ++static const char * const audio_txmclk_groups[] = { ++ "gpio27", "gpio27", ++}; ++static const char * const wsa_swrm_groups[] = { ++ "gpio27", "gpio28", ++}; ++static const char * const blsp2_spi_groups[] = { ++ "gpio27", ++}; ++static const char * const btss12_groups[] = { ++ "gpio27", ++}; ++static const char * const audio_txbclk_groups[] = { ++ "gpio28", ++}; ++static const char * const blsp0_uart1_groups[] = { ++ "gpio28", "gpio29", ++}; ++static const char * const btss13_groups[] = { ++ "gpio28", ++}; ++static const char * const audio_txfsync_groups[] = { ++ "gpio29", ++}; ++static const char * const audio_txd_groups[] = { ++ "gpio30", ++}; ++static const char * const wsis_reset_groups[] = { ++ "gpio30", ++}; ++static const char * const blsp2_spi0_groups[] = { ++ "gpio31", "gpio32", "gpio33", "gpio34", ++}; ++static const char * const blsp1_uart1_groups[] = { ++ "gpio31", "gpio32", "gpio33", "gpio34", ++}; ++static const char * const blsp2_i2c0_groups[] = { ++ "gpio33", "gpio34", ++}; ++static const char * const mdc_groups[] = { ++ "gpio36", ++}; ++static const char * const wsi_clk3_groups[] = { ++ "gpio36", ++}; ++static const char * const mdio_groups[] = { ++ "gpio37", ++}; ++static const char * const atest_char_groups[] = { ++ "gpio37", ++}; ++static const char * const wsi_data3_groups[] = { ++ "gpio37", ++}; ++static const char * const qdss_traceclk_b_groups[] = { ++ "gpio39", ++}; ++static const char * const reset_out_groups[] = { ++ "gpio40", ++}; ++static const char * const qdss_tracectl_b_groups[] = { ++ "gpio40", ++}; ++static const char * const pwm0_groups[] = { ++ "gpio42", ++}; ++static const char * const qdss_cti_trig_out_b0_groups[] = { ++ "gpio42", ++}; ++static const char * const wci4_groups[] = { ++ "gpio42", "gpio42", ++}; ++static const char * const xfem4_groups[] = { ++ "gpio42", ++}; ++static const char * const pwm1_groups[] = { ++ "gpio43", ++}; ++static const char * const qdss_cti_trig_in_b0_groups[] = { ++ "gpio43", ++}; ++static const char * const wci5_groups[] = { ++ "gpio43", "gpio43", ++}; ++static const char * const xfem5_groups[] = { ++ "gpio43", ++}; ++static const char * const pwm2_groups[] = { ++ "gpio44", ++}; ++static const char * const qdss_cti_trig_out_b1_groups[] = { ++ "gpio44", ++}; ++static const char * const wci6_groups[] = { ++ "gpio44", "gpio44", ++}; ++static const char * const xfem6_groups[] = { ++ "gpio44", ++}; ++static const char * const pwm3_groups[] = { ++ "gpio45", ++}; ++static const char * const qdss_cti_trig_in_b1_groups[] = { ++ "gpio45", ++}; ++static const char * const wci7_groups[] = { ++ "gpio45", "gpio45", ++}; ++static const char * const xfem7_groups[] = { ++ "gpio45", ++}; ++ ++static const char * const gpio_groups[] = { ++ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", ++ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", ++ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", ++ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", ++ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", ++ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", ++ "gpio43", "gpio44", "gpio45", "gpio46", ++}; ++ ++static const struct msm_function ipq5018_functions[] = { ++ FUNCTION(atest_char), ++ FUNCTION(atest_char0), ++ FUNCTION(atest_char1), ++ FUNCTION(atest_char2), ++ FUNCTION(atest_char3), ++ FUNCTION(audio_pdm0), ++ FUNCTION(audio_pdm1), ++ FUNCTION(audio_rxbclk), ++ FUNCTION(audio_rxd), ++ FUNCTION(audio_rxfsync), ++ FUNCTION(audio_rxmclk), ++ FUNCTION(audio_txbclk), ++ FUNCTION(audio_txd), ++ FUNCTION(audio_txfsync), ++ FUNCTION(audio_txmclk), ++ FUNCTION(blsp0_i2c), ++ FUNCTION(blsp0_spi), ++ FUNCTION(blsp0_uart0), ++ FUNCTION(blsp0_uart1), ++ FUNCTION(blsp1_i2c0), ++ FUNCTION(blsp1_i2c1), ++ FUNCTION(blsp1_spi0), ++ FUNCTION(blsp1_spi1), ++ FUNCTION(blsp1_uart0), ++ FUNCTION(blsp1_uart1), ++ FUNCTION(blsp1_uart2), ++ FUNCTION(blsp2_i2c0), ++ FUNCTION(blsp2_i2c1), ++ FUNCTION(blsp2_spi), ++ FUNCTION(blsp2_spi0), ++ FUNCTION(blsp2_spi1), ++ FUNCTION(btss0), ++ FUNCTION(btss1), ++ FUNCTION(btss10), ++ FUNCTION(btss11), ++ FUNCTION(btss12), ++ FUNCTION(btss13), ++ FUNCTION(btss2), ++ FUNCTION(btss3), ++ FUNCTION(btss4), ++ FUNCTION(btss5), ++ FUNCTION(btss6), ++ FUNCTION(btss7), ++ FUNCTION(btss8), ++ FUNCTION(btss9), ++ FUNCTION(burn0), ++ FUNCTION(burn1), ++ FUNCTION(cri_trng), ++ FUNCTION(cri_trng0), ++ FUNCTION(cri_trng1), ++ FUNCTION(cxc_clk), ++ FUNCTION(cxc_data), ++ FUNCTION(dbg_out), ++ FUNCTION(eud_gpio), ++ FUNCTION(gcc_plltest), ++ FUNCTION(gcc_tlmm), ++ FUNCTION(gpio), ++ FUNCTION(mac0), ++ FUNCTION(mac1), ++ FUNCTION(mdc), ++ FUNCTION(mdio), ++ FUNCTION(pcie0_clk), ++ FUNCTION(pcie0_wake), ++ FUNCTION(pcie1_clk), ++ FUNCTION(pcie1_wake), ++ FUNCTION(pll_test), ++ FUNCTION(prng_rosc), ++ FUNCTION(pwm0), ++ FUNCTION(pwm1), ++ FUNCTION(pwm2), ++ FUNCTION(pwm3), ++ FUNCTION(qdss_cti_trig_in_a0), ++ FUNCTION(qdss_cti_trig_in_a1), ++ FUNCTION(qdss_cti_trig_in_b0), ++ FUNCTION(qdss_cti_trig_in_b1), ++ FUNCTION(qdss_cti_trig_out_a0), ++ FUNCTION(qdss_cti_trig_out_a1), ++ FUNCTION(qdss_cti_trig_out_b0), ++ FUNCTION(qdss_cti_trig_out_b1), ++ FUNCTION(qdss_traceclk_a), ++ FUNCTION(qdss_traceclk_b), ++ FUNCTION(qdss_tracectl_a), ++ FUNCTION(qdss_tracectl_b), ++ FUNCTION(qdss_tracedata_a), ++ FUNCTION(qdss_tracedata_b), ++ FUNCTION(qspi_clk), ++ FUNCTION(qspi_cs), ++ FUNCTION(qspi0), ++ FUNCTION(qspi1), ++ FUNCTION(qspi2), ++ FUNCTION(qspi3), ++ FUNCTION(reset_out), ++ FUNCTION(sdc1_clk), ++ FUNCTION(sdc1_cmd), ++ FUNCTION(sdc10), ++ FUNCTION(sdc11), ++ FUNCTION(sdc12), ++ FUNCTION(sdc13), ++ FUNCTION(wci0), ++ FUNCTION(wci1), ++ FUNCTION(wci2), ++ FUNCTION(wci3), ++ FUNCTION(wci4), ++ FUNCTION(wci5), ++ FUNCTION(wci6), ++ FUNCTION(wci7), ++ FUNCTION(wsa_swrm), ++ FUNCTION(wsi_clk3), ++ FUNCTION(wsi_data3), ++ FUNCTION(wsis_reset), ++ FUNCTION(xfem0), ++ FUNCTION(xfem1), ++ FUNCTION(xfem2), ++ FUNCTION(xfem3), ++ FUNCTION(xfem4), ++ FUNCTION(xfem5), ++ FUNCTION(xfem6), ++ FUNCTION(xfem7), ++}; ++static const struct msm_pingroup ipq5018_groups[] = { ++ PINGROUP(0, atest_char0, _, qdss_cti_trig_out_a0, wci0, wci0, xfem0, ++ _, _, _), ++ PINGROUP(1, atest_char1, _, qdss_cti_trig_in_a0, wci1, wci1, xfem1, ++ _, _, _), ++ PINGROUP(2, atest_char2, _, qdss_cti_trig_out_a1, wci2, wci2, xfem2, ++ _, _, _), ++ PINGROUP(3, atest_char3, _, qdss_cti_trig_in_a1, wci3, wci3, xfem3, ++ _, _, _), ++ PINGROUP(4, sdc13, qspi3, blsp1_spi1, btss0, dbg_out, qdss_traceclk_a, ++ _, burn0, _), ++ PINGROUP(5, sdc12, qspi2, cxc_clk, blsp1_spi1, blsp1_i2c1, btss1, _, ++ qdss_tracectl_a, _), ++ PINGROUP(6, sdc11, qspi1, cxc_data, blsp1_spi1, blsp1_i2c1, btss2, _, ++ qdss_tracedata_a, _), ++ PINGROUP(7, sdc10, qspi0, mac0, blsp1_spi1, btss3, _, ++ qdss_tracedata_a, _, _), ++ PINGROUP(8, sdc1_cmd, qspi_cs, mac1, btss4, _, qdss_tracedata_a, _, ++ _, _), ++ PINGROUP(9, sdc1_clk, qspi_clk, _, qdss_tracedata_a, _, _, _, _, ++ _), ++ PINGROUP(10, blsp0_spi, blsp1_uart0, _, gcc_plltest, qdss_tracedata_a, ++ _, _, _, _), ++ PINGROUP(11, blsp0_spi, blsp1_uart0, _, gcc_tlmm, qdss_tracedata_a, ++ _, _, _, _), ++ PINGROUP(12, blsp0_spi, blsp0_i2c, blsp1_uart0, _, gcc_plltest, ++ qdss_tracedata_a, _, _, _), ++ PINGROUP(13, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, ++ _, _, _, _), ++ PINGROUP(14, pcie0_clk, _, _, cri_trng0, qdss_tracedata_a, _, _, _, _), ++ PINGROUP(15, _, _, cri_trng1, qdss_tracedata_a, _, _, _, _, _), ++ PINGROUP(16, pcie0_wake, _, _, cri_trng, qdss_tracedata_a, _, _, _, _), ++ PINGROUP(17, pcie1_clk, btss5, _, prng_rosc, qdss_tracedata_a, _, _, ++ _, _), ++ PINGROUP(18, blsp1_spi0, btss6, _, qdss_tracedata_a, _, _, _, _, _), ++ PINGROUP(19, pcie1_wake, blsp1_spi0, blsp1_i2c0, btss7, _, ++ qdss_tracedata_a, _, _, _), ++ PINGROUP(20, blsp0_uart0, blsp1_spi0, blsp1_i2c0, _, qdss_tracedata_a, ++ _, _, _, _), ++ PINGROUP(21, blsp0_uart0, blsp1_spi0, _, qdss_tracedata_a, _, _, _, ++ _, _), ++ PINGROUP(22, _, pll_test, eud_gpio, _, _, _, _, _, _), ++ PINGROUP(23, audio_rxmclk, audio_pdm0, audio_rxmclk, blsp2_spi1, ++ blsp1_uart2, btss8, _, qdss_tracedata_b, _), ++ PINGROUP(24, audio_rxbclk, audio_pdm0, blsp2_spi1, blsp1_uart2, btss9, ++ _, qdss_tracedata_b, _, _), ++ PINGROUP(25, audio_rxfsync, audio_pdm1, blsp2_i2c1, blsp2_spi1, ++ blsp1_uart2, btss10, _, qdss_tracedata_b, _), ++ PINGROUP(26, audio_rxd, audio_pdm1, blsp2_i2c1, blsp2_spi1, ++ blsp1_uart2, btss11, _, qdss_tracedata_b, _), ++ PINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss12, ++ _, qdss_tracedata_b, _, _), ++ PINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss13, ++ qdss_tracedata_b, _, _, _, _), ++ PINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _, ++ _, _, _), ++ PINGROUP(30, audio_txd, qdss_tracedata_b, _, wsis_reset, _, _, _, ++ _, _), ++ PINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, ++ _, _, _, _), ++ PINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, ++ _, _, _, _), ++ PINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, ++ eud_gpio, _, _, _), ++ PINGROUP(34, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, ++ eud_gpio, _, _, _), ++ PINGROUP(35, _, qdss_tracedata_b, eud_gpio, _, _, _, _, _, _), ++ PINGROUP(36, mdc, qdss_tracedata_b, _, wsi_clk3, _, _, _, _, _), ++ PINGROUP(37, mdio, atest_char, qdss_tracedata_b, _, wsi_data3, _, _, ++ _, _), ++ PINGROUP(38, qdss_tracedata_b, _, _, _, _, _, _, _, _), ++ PINGROUP(39, qdss_traceclk_b, _, _, _, _, _, _, _, _), ++ PINGROUP(40, reset_out, qdss_tracectl_b, _, _, _, _, _, _, _), ++ PINGROUP(41, _, _, _, _, _, _, _, _, _), ++ PINGROUP(42, pwm0, qdss_cti_trig_out_b0, wci4, wci4, xfem4, _, _, _, ++ _), ++ PINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci5, wci5, xfem5, _, _, _, _), ++ PINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci6, wci6, xfem6, _, _, _, ++ _), ++ PINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci7, wci7, xfem7, _, _, _, _), ++ PINGROUP(46, _, _, _, _, _, _, _, _, _), ++}; ++ ++static const struct msm_pinctrl_soc_data ipq5018_pinctrl = { ++ .pins = ipq5018_pins, ++ .npins = ARRAY_SIZE(ipq5018_pins), ++ .functions = ipq5018_functions, ++ .nfunctions = ARRAY_SIZE(ipq5018_functions), ++ .groups = ipq5018_groups, ++ .ngroups = ARRAY_SIZE(ipq5018_groups), ++ .ngpios = 47, ++}; ++ ++static int ipq5018_pinctrl_probe(struct platform_device *pdev) ++{ ++ return msm_pinctrl_probe(pdev, &ipq5018_pinctrl); ++} ++ ++static const struct of_device_id ipq5018_pinctrl_of_match[] = { ++ { .compatible = "qcom,ipq5018-pinctrl", }, ++ { }, ++}; ++ ++static struct platform_driver ipq5018_pinctrl_driver = { ++ .driver = { ++ .name = "ipq5018-pinctrl", ++ .of_match_table = ipq5018_pinctrl_of_match, ++ }, ++ .probe = ipq5018_pinctrl_probe, ++ .remove = msm_pinctrl_remove, ++}; ++ ++static int __init ipq5018_pinctrl_init(void) ++{ ++ return platform_driver_register(&ipq5018_pinctrl_driver); ++} ++arch_initcall(ipq5018_pinctrl_init); ++ ++static void __exit ipq5018_pinctrl_exit(void) ++{ ++ platform_driver_unregister(&ipq5018_pinctrl_driver); ++} ++module_exit(ipq5018_pinctrl_exit); ++ ++MODULE_DESCRIPTION("Qualcomm Technologies Inc ipq5018 pinctrl driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_DEVICE_TABLE(of, ipq5018_pinctrl_of_match); +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/306-arm64-dts-Add-ipq5018-SoC-and-MP03-board-support.patch b/target/linux/ipq50xx/patches/306-arm64-dts-Add-ipq5018-SoC-and-MP03-board-support.patch new file mode 100644 index 0000000000..2e094fc5b5 --- /dev/null +++ b/target/linux/ipq50xx/patches/306-arm64-dts-Add-ipq5018-SoC-and-MP03-board-support.patch @@ -0,0 +1,314 @@ +From 9bb7293b6c0c097df32d778347fe523cfa6c0bc6 Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Mon, 28 Sep 2020 10:45:39 +0530 +Subject: [PATCH 6/7] arm64: dts: Add ipq5018 SoC and MP03 board support + +Add initial device tree support for the Qualcomm IPQ5018 SoC and +MP03.1-C2 board. + +Signed-off-by: Varadarajan Narayanan + +Pick from <1601270140-4306-7-git-send-email-varada@codeaurora.org> + +Fix gpio-ranges + +Signed-off-by: hzy +--- + .../devicetree/bindings/arm/qcom.yaml | 7 + + arch/arm64/boot/dts/qcom/Makefile | 1 + + .../arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 30 +++ + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 201 ++++++++++++++++++ + 4 files changed, 239 insertions(+) + create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts + create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi + +diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml +index 3de6182cde97..515eb93879a6 100644 +--- a/Documentation/devicetree/bindings/arm/qcom.yaml ++++ b/Documentation/devicetree/bindings/arm/qcom.yaml +@@ -28,6 +28,7 @@ description: | + apq8074 + apq8084 + apq8096 ++ ipq5018 + ipq6018 + ipq8074 + mdm9615 +@@ -59,6 +60,7 @@ description: | + hk10-c2 + idp + liquid ++ mp03 + mtp + qrd + sbc +@@ -134,6 +136,11 @@ properties: + - qcom,ipq4019-dk04.1-c1 + - const: qcom,ipq4019 + ++ - items: ++ - enum: ++ - qcom,ipq5018-mp03 ++ - const: qcom,ipq5018 ++ + - items: + - enum: + - qcom,ipq8064-ap148 +diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile +index 6498a1ec893f..0d8b516362bc 100644 +--- a/arch/arm64/boot/dts/qcom/Makefile ++++ b/arch/arm64/boot/dts/qcom/Makefile +@@ -1,6 +1,7 @@ + dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb + dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb + dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb ++dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.1-c2.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb + dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb +diff --git a/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts +new file mode 100644 +index 000000000000..41bb3b3acb49 +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts +@@ -0,0 +1,30 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ5018 CP01 board device tree source ++ * ++ * Copyright (c) 2019, The Linux Foundation. All rights reserved. ++ */ ++ ++/dts-v1/; ++ ++#include "ipq5018.dtsi" ++ ++/ { ++ model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03-C2"; ++ compatible = "qcom,ipq5018-mp03", "qcom,ipq5018"; ++ ++ aliases { ++ serial0 = &blsp1_uart1; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ bootargs-append = " swiotlb=1"; ++ }; ++}; ++ ++&blsp1_uart1 { ++ pinctrl-0 = <&serial_1_pins>; ++ pinctrl-names = "default"; ++ status = "ok"; ++}; +diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +new file mode 100644 +index 000000000000..487cc15da457 +--- /dev/null ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -0,0 +1,201 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) ++/* ++ * IPQ5018 SoC device tree source ++ * ++ * Copyright (c) 2019, The Linux Foundation. All rights reserved. ++ */ ++ ++#include ++#include ++#include ++ ++/ { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ interrupt-parent = <&intc>; ++ ++ clocks { ++ sleep_clk: sleep-clk { ++ compatible = "fixed-clock"; ++ clock-frequency = <32000>; ++ #clock-cells = <0>; ++ }; ++ ++ xo: xo { ++ compatible = "fixed-clock"; ++ clock-frequency = <24000000>; ++ #clock-cells = <0>; ++ }; ++ }; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ CPU0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0>; ++ enable-method = "psci"; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ CPU1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ enable-method = "psci"; ++ reg = <0x1>; ++ next-level-cache = <&L2_0>; ++ }; ++ ++ L2_0: l2-cache { ++ compatible = "cache"; ++ cache-level = <0x2>; ++ }; ++ }; ++ ++ pmuv8: pmu { ++ compatible = "arm,cortex-a53-pmu"; ++ interrupts = ; ++ }; ++ ++ psci: psci { ++ compatible = "arm,psci-1.0"; ++ method = "smc"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ tz: tz@4ac00000 { ++ reg = <0x0 0x4ac00000 0x0 0x00400000>; ++ no-map; ++ }; ++ }; ++ ++ soc: soc { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0 0 0xffffffff>; ++ dma-ranges; ++ compatible = "simple-bus"; ++ ++ tlmm: pinctrl@1000000 { ++ compatible = "qcom,ipq5018-pinctrl"; ++ reg = <0x01000000 0x300000>; ++ interrupts = ; ++ gpio-controller; ++ #gpio-cells = <2>; ++ gpio-ranges = <&tlmm 0 0 80>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ ++ serial_1_pins: serial1-pinmux { ++ pins = "gpio31", "gpio32", "gpio33", "gpio34"; ++ function = "blsp1_uart1"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ gcc: gcc@1800000 { ++ compatible = "qcom,gcc-ipq5018"; ++ reg = <0x01800000 0x80000>; ++ clocks = <&xo>, <&sleep_clk>; ++ clock-names = "xo", "sleep_clk"; ++ #clock-cells = <1>; ++ #reset-cells = <1>; ++ }; ++ ++ blsp1_uart1: serial@78af000 { ++ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; ++ reg = <0x078af000 0x200>; ++ interrupts = ; ++ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, ++ <&gcc GCC_BLSP1_AHB_CLK>; ++ clock-names = "core", "iface"; ++ status = "disabled"; ++ }; ++ ++ intc: interrupt-controller@b000000 { ++ compatible = "qcom,msm-qgic2"; ++ interrupt-controller; ++ #interrupt-cells = <0x3>; ++ reg = <0x0b000000 0x1000>, /*GICD*/ ++ <0x0b002000 0x1000>, /*GICC*/ ++ <0x0b001000 0x1000>, /*GICH*/ ++ <0x0b004000 0x1000>; /*GICV*/ ++ interrupts = ; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = , ++ , ++ , ++ ; ++ }; ++ ++ timer@b120000 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ compatible = "arm,armv7-timer-mem"; ++ reg = <0x0b120000 0x1000>; ++ clock-frequency = <19200000>; ++ ++ frame@b120000 { ++ frame-number = <0>; ++ interrupts = , ++ ; ++ reg = <0x0b121000 0x1000>, ++ <0x0b122000 0x1000>; ++ }; ++ ++ frame@b123000 { ++ frame-number = <1>; ++ interrupts = ; ++ reg = <0xb123000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b124000 { ++ frame-number = <2>; ++ interrupts = ; ++ reg = <0x0b124000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b125000 { ++ frame-number = <3>; ++ interrupts = ; ++ reg = <0x0b125000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b126000 { ++ frame-number = <4>; ++ interrupts = ; ++ reg = <0x0b126000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b127000 { ++ frame-number = <5>; ++ interrupts = ; ++ reg = <0x0b127000 0x1000>; ++ status = "disabled"; ++ }; ++ ++ frame@b128000 { ++ frame-number = <6>; ++ interrupts = ; ++ reg = <0x0b128000 0x1000>; ++ status = "disabled"; ++ }; ++ }; ++ }; ++}; +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/307-arm64-defconfig-Enable-IPQ5018-SoC-base-configs.patch b/target/linux/ipq50xx/patches/307-arm64-defconfig-Enable-IPQ5018-SoC-base-configs.patch new file mode 100644 index 0000000000..447beeaa91 --- /dev/null +++ b/target/linux/ipq50xx/patches/307-arm64-defconfig-Enable-IPQ5018-SoC-base-configs.patch @@ -0,0 +1,39 @@ +From 0bb78c90f9a682277e73301e8325953d47ca6990 Mon Sep 17 00:00:00 2001 +From: Varadarajan Narayanan +Date: Mon, 28 Sep 2020 10:45:40 +0530 +Subject: [PATCH 7/7] arm64: defconfig: Enable IPQ5018 SoC base configs + +Enables clk & pinctrl related configs + +Signed-off-by: Varadarajan Narayanan + +Pick from <1601270140-4306-8-git-send-email-varada@codeaurora.org> + +Signed-off-by: hzy +--- + arch/arm64/configs/defconfig | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig +index c9a867ac32d4..dd04f9414c4d 100644 +--- a/arch/arm64/configs/defconfig ++++ b/arch/arm64/configs/defconfig +@@ -401,6 +401,7 @@ CONFIG_PINCTRL_IMX8MM=y + CONFIG_PINCTRL_IMX8QXP=y + CONFIG_PINCTRL_IMX8DXL=y + CONFIG_PINCTRL_MSM=y ++CONFIG_PINCTRL_IPQ5018=y + CONFIG_PINCTRL_IPQ8074=y + CONFIG_PINCTRL_IPQ6018=y + CONFIG_PINCTRL_MSM8916=y +@@ -702,6 +703,7 @@ CONFIG_QCOM_A53PLL=y + CONFIG_QCOM_CLK_APCS_MSM8916=y + CONFIG_QCOM_CLK_SMD_RPM=y + CONFIG_QCOM_CLK_RPMH=y ++CONFIG_IPQ_GCC_5018=y + CONFIG_IPQ_GCC_8074=y + CONFIG_IPQ_GCC_6018=y + CONFIG_MSM_GCC_8916=y +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/311-arm64-dts-qcom-ipq5018-Add-scm-node.patch b/target/linux/ipq50xx/patches/311-arm64-dts-qcom-ipq5018-Add-scm-node.patch new file mode 100644 index 0000000000..cc62a72815 --- /dev/null +++ b/target/linux/ipq50xx/patches/311-arm64-dts-qcom-ipq5018-Add-scm-node.patch @@ -0,0 +1,30 @@ +From 7c7f17c89b150040be98b754c201221294378f8d Mon Sep 17 00:00:00 2001 +From: hzy +Date: Tue, 7 Mar 2023 07:32:05 +0000 +Subject: [PATCH 1/2] arm64: dts: qcom: ipq5018: Add scm node + +Signed-off-by: hzy +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +index 487cc15da457..fdfa0f25c52b 100644 +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -65,6 +65,12 @@ + method = "smc"; + }; + ++ firmware { ++ scm { ++ compatible = "qcom,scm"; ++ }; ++ }; ++ + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/312-arm64-Kconfig-enable-qcom-scm.patch b/target/linux/ipq50xx/patches/312-arm64-Kconfig-enable-qcom-scm.patch new file mode 100644 index 0000000000..cafd019399 --- /dev/null +++ b/target/linux/ipq50xx/patches/312-arm64-Kconfig-enable-qcom-scm.patch @@ -0,0 +1,25 @@ +From 6f376e7ce60d9043579f78e4e7fd820651bbe144 Mon Sep 17 00:00:00 2001 +From: hzy +Date: Tue, 7 Mar 2023 07:36:50 +0000 +Subject: [PATCH 2/2] arm64: Kconfig: enable qcom scm + +Signed-off-by: hzy +--- + arch/arm64/Kconfig.platforms | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms +index 90202e5608d1..c1d672bb8c83 100644 +--- a/arch/arm64/Kconfig.platforms ++++ b/arch/arm64/Kconfig.platforms +@@ -184,6 +184,7 @@ config ARCH_QCOM + bool "Qualcomm Platforms" + select GPIOLIB + select PINCTRL ++ select QCOM_SCM + help + This enables support for the ARMv8 based Qualcomm chipsets. + +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/321-firmware-qcom_scm-Disable-SDI.patch b/target/linux/ipq50xx/patches/321-firmware-qcom_scm-Disable-SDI.patch new file mode 100644 index 0000000000..202aa5e96b --- /dev/null +++ b/target/linux/ipq50xx/patches/321-firmware-qcom_scm-Disable-SDI.patch @@ -0,0 +1,60 @@ +From 83a1c64c1234193aacea56c5857afa6adf5507a7 Mon Sep 17 00:00:00 2001 +From: hzy +Date: Tue, 7 Mar 2023 09:24:22 +0000 +Subject: [PATCH 1/2] firmware: qcom_scm: Disable SDI + +Signed-off-by: hzy +--- + drivers/firmware/qcom_scm.c | 16 ++++++++++++++++ + drivers/firmware/qcom_scm.h | 1 + + 2 files changed, 17 insertions(+) + +diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c +index 70fe261c0cd8..a85466cfda58 100644 +--- a/drivers/firmware/qcom_scm.c ++++ b/drivers/firmware/qcom_scm.c +@@ -360,6 +360,20 @@ void qcom_scm_cpu_power_down(u32 flags) + } + EXPORT_SYMBOL(qcom_scm_cpu_power_down); + ++static int qcom_scm_disable_sdi(void) ++{ ++ struct qcom_scm_desc desc = { ++ .svc = QCOM_SCM_SVC_BOOT, ++ .cmd = QCOM_SCM_BOOT_DISABLE_SDI, ++ .arginfo = QCOM_SCM_ARGS(2), ++ .args[0] = 1, /* Disable wdog debug */ ++ .args[1] = 0, /* SDI Enable */ ++ .owner = ARM_SMCCC_OWNER_SIP, ++ }; ++ ++ return qcom_scm_call(__scm->dev, &desc, NULL); ++} ++ + int qcom_scm_set_remote_state(u32 state, u32 id) + { + struct qcom_scm_desc desc = { +@@ -1322,6 +1322,8 @@ static int qcom_scm_probe(struct platform_device *pdev) + + __get_convention(); + ++ qcom_scm_disable_sdi(); ++ + /* + * If requested enable "download mode", from this point on warmboot + * will cause the the boot stages to enter download mode, unless +diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h +index 428da03635f0..343ba3a470b5 100644 +--- a/drivers/firmware/qcom_scm.h ++++ b/drivers/firmware/qcom_scm.h +@@ -74,6 +74,7 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, + #define QCOM_SCM_SVC_BOOT 0x01 + #define QCOM_SCM_BOOT_SET_ADDR 0x01 + #define QCOM_SCM_BOOT_TERMINATE_PC 0x02 ++#define QCOM_SCM_BOOT_DISABLE_SDI 0x09 + #define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10 + #define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a + #define QCOM_SCM_FLUSH_FLAG_MASK 0x3 +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/322-arm64-dts-qcom-ipq5018-set-download-mode.patch b/target/linux/ipq50xx/patches/322-arm64-dts-qcom-ipq5018-set-download-mode.patch new file mode 100644 index 0000000000..f2ad00a2b4 --- /dev/null +++ b/target/linux/ipq50xx/patches/322-arm64-dts-qcom-ipq5018-set-download-mode.patch @@ -0,0 +1,37 @@ +From 3e4c7ccd6acfe21232df62d3fb663e7f8b5a8b02 Mon Sep 17 00:00:00 2001 +From: hzy +Date: Tue, 7 Mar 2023 07:34:31 +0000 +Subject: [PATCH 2/2] arm64: dts: qcom: ipq5018: set download mode + +Signed-off-by: hzy +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +index fdfa0f25c52b..668a931c892e 100644 +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -68,6 +68,7 @@ + firmware { + scm { + compatible = "qcom,scm"; ++ qcom,dload-mode = <&tcsr_boot_misc 0>; + }; + }; + +@@ -116,6 +117,11 @@ + #reset-cells = <1>; + }; + ++ tcsr_boot_misc: syscon@193d100 { ++ compatible = "syscon"; ++ reg = <0x0193d100 0x4>; ++ }; ++ + blsp1_uart1: serial@78af000 { + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; + reg = <0x078af000 0x200>; +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/331-ARM-mach-qcom-Add-support-for-IPQ50xx.patch b/target/linux/ipq50xx/patches/331-ARM-mach-qcom-Add-support-for-IPQ50xx.patch new file mode 100644 index 0000000000..24a35ff146 --- /dev/null +++ b/target/linux/ipq50xx/patches/331-ARM-mach-qcom-Add-support-for-IPQ50xx.patch @@ -0,0 +1,42 @@ +From dd355a413cad48f795a6187a79b10f37ad1e59bd Mon Sep 17 00:00:00 2001 +From: hzy +Date: Thu, 2 Mar 2023 17:04:24 +0000 +Subject: [PATCH 1/2] ARM: mach-qcom: Add support for IPQ50xx + +Signed-off-by: hzy +--- + arch/arm/Makefile | 1 + + arch/arm/mach-qcom/Kconfig | 5 +++++ + 2 files changed, 6 insertions(+) + +diff --git a/arch/arm/Makefile b/arch/arm/Makefile +index 4f098edfbf20..23aff930c2de 100644 +--- a/arch/arm/Makefile ++++ b/arch/arm/Makefile +@@ -152,6 +152,7 @@ textofs-$(CONFIG_PM_H1940) := 0x00108000 + textofs-$(CONFIG_SA1111) := 0x00208000 + endif + textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000 ++textofs-$(CONFIG_ARCH_IPQ50XX) := 0x00208000 + textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 + textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 + textofs-$(CONFIG_ARCH_MESON) := 0x00208000 +diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig +index ecbf3c4eb878..9870d1b1f604 100644 +--- a/arch/arm/mach-qcom/Kconfig ++++ b/arch/arm/mach-qcom/Kconfig +@@ -12,6 +12,11 @@ menuconfig ARCH_QCOM + select CLKSRC_QCOM + select HAVE_ARM_ARCH_TIMER + ++config ARCH_IPQ50XX ++ bool "Enable support for IPQ50XX" ++ select CLKSRC_QCOM ++ select HAVE_ARM_ARCH_TIMER ++ + config ARCH_MSM8X60 + bool "Enable support for MSM8X60" + select CLKSRC_QCOM +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/332-arm-dts-qcom-Add-ipq5018-support.patch b/target/linux/ipq50xx/patches/332-arm-dts-qcom-Add-ipq5018-support.patch new file mode 100644 index 0000000000..45665e2477 --- /dev/null +++ b/target/linux/ipq50xx/patches/332-arm-dts-qcom-Add-ipq5018-support.patch @@ -0,0 +1,52 @@ +From 206c1e12a3836ce6863b259bd3273863af195586 Mon Sep 17 00:00:00 2001 +From: hzy +Date: Thu, 2 Mar 2023 17:04:24 +0000 +Subject: [PATCH 2/2] arm: dts: qcom: Add ipq5018 support + +Signed-off-by: hzy +--- + arch/arm/boot/dts/Makefile | 1 + + arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts | 4 ++++ + arch/arm/boot/dts/qcom-ipq5018.dtsi | 7 +++++++ + 3 files changed, 12 insertions(+) + create mode 100644 arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts + create mode 100644 arch/arm/boot/dts/qcom-ipq5018.dtsi + +diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile +index b21b3a64641a..6f88cb1c5d84 100644 +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -842,6 +842,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ + qcom-ipq4019-ap.dk04.1-c3.dtb \ + qcom-ipq4019-ap.dk07.1-c1.dtb \ + qcom-ipq4019-ap.dk07.1-c2.dtb \ ++ qcom-ipq5018-mp03.1-c2.dtb \ + qcom-ipq8064-ap148.dtb \ + qcom-ipq8064-rb3011.dtb \ + qcom-msm8226-samsung-s3ve3g.dtb \ +diff --git a/arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts b/arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts +new file mode 100644 +index 000000000000..361695870ed6 +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts +@@ -0,0 +1,4 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++ ++#include "../../../arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts" ++#include "qcom-ipq5018.dtsi" +diff --git a/arch/arm/boot/dts/qcom-ipq5018.dtsi b/arch/arm/boot/dts/qcom-ipq5018.dtsi +new file mode 100644 +index 000000000000..b14bd7558d3b +--- /dev/null ++++ b/arch/arm/boot/dts/qcom-ipq5018.dtsi +@@ -0,0 +1,7 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++/ { ++ pmu { ++ compatible = "arm,cortex-a7-pmu"; ++ }; ++}; +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/401-mtd-nand-qcom-use-the-ecc-strength-from-device-param.patch b/target/linux/ipq50xx/patches/401-mtd-nand-qcom-use-the-ecc-strength-from-device-param.patch new file mode 100644 index 0000000000..13839eb929 --- /dev/null +++ b/target/linux/ipq50xx/patches/401-mtd-nand-qcom-use-the-ecc-strength-from-device-param.patch @@ -0,0 +1,51 @@ +From 8f98c5c71e78abddd533d5e65a9bbb20365b30e7 Mon Sep 17 00:00:00 2001 +From: Rajkumar Ayyasamy +Date: Thu, 12 Mar 2020 14:19:16 +0530 +Subject: [PATCH 1/7] mtd: nand: qcom: use the ecc strength from device + parameter +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Currently the driver uses the ECC strength specified in +device tree. The ONFI or JEDEC device parameter page +contains the ‘ECC correctability’ field which indicates the +number of bits that the host should be able to correct per +512 bytes of data. The NAND base layer reads this parameter +during device scan time. Since QPIC NAND controller supports +8 bit ECC and same board can have different ECC strength +devices, so device ECC strength can be used. + +Change-Id: I4924ed4a3a0db56a217aabd0b7e7699078b4e7d5 +Signed-off-by: Abhishek Sahu +(cherry picked from commit f9b2c1442788f6cb9652c79557c9795faefe3513) +Signed-off-by: Rajkumar Ayyasamy + +Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/43a13a5bf504b9d09ac703d67c1b85934ef758e1 + +Signed-off-by: hzy +--- + drivers/mtd/nand/raw/qcom_nandc.c | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c +index 5af3bef6c230..673468d35d28 100644 +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -2477,6 +2477,13 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) + wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false; + cwperpage = mtd->writesize / NANDC_STEP_SIZE; + ++ /* ++ * Read the required ecc strength from NAND device and overwrite the ++ * device tree ecc strength ++ */ ++ if (chip->base.ecc.requirements.strength >= 8) ++ ecc->strength = 8; ++ + /* + * Each CW has 4 available OOB bytes which will be protected with ECC + * so remaining bytes can be used for ECC. +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/402-mtd-nand-ipq-add-compatible-used-in-linux-older-vers.patch b/target/linux/ipq50xx/patches/402-mtd-nand-ipq-add-compatible-used-in-linux-older-vers.patch new file mode 100644 index 0000000000..18445e8bd9 --- /dev/null +++ b/target/linux/ipq50xx/patches/402-mtd-nand-ipq-add-compatible-used-in-linux-older-vers.patch @@ -0,0 +1,37 @@ +From da56d8fc20c95ece57600126c8e7bc14d7a5e8c2 Mon Sep 17 00:00:00 2001 +From: Rajkumar Ayyasamy +Date: Thu, 28 May 2020 11:24:49 +0530 +Subject: [PATCH 2/7] mtd: nand: ipq: add compatible used in linux older + version + +Added compatible string which was used in the NAND driver of linux +older version. So that u-boot can work with linux-5.4 without any changes. + +Signed-off-by: Rajkumar Ayyasamy +Change-Id: I2437cc37de9646fbf61864b6a328c914a6f677a7 + +Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/cd490bba1bbab70c69e7e8b6e8a5e026a7bd18bf + +Signed-off-by: hzy +--- + drivers/mtd/nand/raw/qcom_nandc.c | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c +index 673468d35d28..375ae6a2d799 100644 +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -3042,6 +3042,10 @@ static const struct of_device_id qcom_nandc_of_match[] = { + .compatible = "qcom,ipq8074-nand", + .data = &ipq8074_nandc_props, + }, ++ { ++ .compatible = "qcom,ebi2-nandc-bam-v1.5.0", ++ .data = &ipq8074_nandc_props, ++ }, + {} + }; + MODULE_DEVICE_TABLE(of, qcom_nandc_of_match); +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/403-mtd-rawnand-qcom-Add-initial-support-for-qspi-nand.patch b/target/linux/ipq50xx/patches/403-mtd-rawnand-qcom-Add-initial-support-for-qspi-nand.patch new file mode 100644 index 0000000000..8528a211cc --- /dev/null +++ b/target/linux/ipq50xx/patches/403-mtd-rawnand-qcom-Add-initial-support-for-qspi-nand.patch @@ -0,0 +1,397 @@ +From 64cb8eaaa6b3f987d5e8126278f6f829d252d4e8 Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Wed, 8 Jul 2020 10:40:59 +0530 +Subject: [PATCH 3/7] mtd: rawnand: qcom: Add initial support for qspi nand + +This change will add initial support for qspi (serial nand). + +QPIC Version v.2.0 onwards supports serial nand as well so this +change will initialize all required register to enable qspi (serial +nand). + +This change is supporting very basic functionality of qspi nand flash. + +1. Reset device (Reset QSPI NAND device). + +2. Device detection (Read id QSPI NAND device). + +Signed-off-by: Md Sadre Alam +Change-Id: I5f29df80bcb8e58a1938eced1a8d88c237aceb1d + +Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/dbd01aa96d9d5bf5978e3c6ef2a4118ce7cc0bba + +Signed-off-by: hzy +--- + drivers/mtd/nand/raw/nand_ids.c | 13 +++ + drivers/mtd/nand/raw/qcom_nandc.c | 168 ++++++++++++++++++++++++++++-- + 2 files changed, 171 insertions(+), 10 deletions(-) + +diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c +index ba27902fc54b..03e472055d9e 100644 +--- a/drivers/mtd/nand/raw/nand_ids.c ++++ b/drivers/mtd/nand/raw/nand_ids.c +@@ -53,6 +53,19 @@ struct nand_flash_dev nand_flash_ids[] = { + SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640, + NAND_ECC_INFO(40, SZ_1K), 4 }, + ++ {"GD5F1GQ4RE9IG SPI NAND 1G 1.8V 4-bit", ++ { .id = {0xc8, 0xc1} }, ++ SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) }, ++ {"GD5F1GQ4RE9IH SPI NAND 1G 1.8V 4-bit", ++ { .id = {0xc8, 0xc9} }, ++ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) }, ++ {"GD5F2GQ5REYIH SPI NAND 2G 4-bit", ++ { .id = {0xc8, 0x22} }, ++ SZ_2K, SZ_256, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) }, ++ {"MT29F1G01ABBFDWB-IT SPI NAND 1G 1.8V 4-bit", ++ { .id = {0x2c, 0x15} }, ++ SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) }, ++ + LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS), +diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c +index 375ae6a2d799..361ee116422f 100644 +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -35,22 +35,33 @@ + #define NAND_DEV_CMD1 0xa4 + #define NAND_DEV_CMD2 0xa8 + #define NAND_DEV_CMD_VLD 0xac ++#define NAND_DEV_CMD7 0xb0 ++#define NAND_DEV_CMD8 0xb4 ++#define NAND_DEV_CMD9 0xb8 ++#define NAND_FLASH_SPI_CFG 0xc0 ++#define NAND_SPI_NUM_ADDR_CYCLES 0xc4 ++#define NAND_SPI_BUSY_CHECK_WAIT_CNT 0xc8 ++#define NAND_DEV_CMD3 0xd0 ++#define NAND_DEV_CMD4 0xd4 ++#define NAND_DEV_CMD5 0xd8 ++#define NAND_DEV_CMD6 0xdc + #define SFLASHC_BURST_CFG 0xe0 + #define NAND_ERASED_CW_DETECT_CFG 0xe8 + #define NAND_ERASED_CW_DETECT_STATUS 0xec + #define NAND_EBI2_ECC_BUF_CFG 0xf0 + #define FLASH_BUF_ACC 0x100 +- + #define NAND_CTRL 0xf00 + #define NAND_VERSION 0xf08 + #define NAND_READ_LOCATION_0 0xf20 + #define NAND_READ_LOCATION_1 0xf24 + #define NAND_READ_LOCATION_2 0xf28 + #define NAND_READ_LOCATION_3 0xf2c + #define NAND_READ_LOCATION_LAST_CW_0 0xf40 + #define NAND_READ_LOCATION_LAST_CW_1 0xf44 + #define NAND_READ_LOCATION_LAST_CW_2 0xf48 + #define NAND_READ_LOCATION_LAST_CW_3 0xf4c ++#define NAND_QSPI_MSTR_CONFIG 0xf60 ++ + + /* dummy register offsets, used by write_reg_dma */ + #define NAND_DEV_CMD1_RESTORE 0xdead +@@ -179,6 +194,28 @@ + #define ECC_BCH_4BIT BIT(2) + #define ECC_BCH_8BIT BIT(3) + ++/* QSPI NAND config reg bits */ ++#define LOAD_CLK_CNTR_INIT_EN (1 << 28) ++#define CLK_CNTR_INIT_VAL_VEC 0x924 ++#define FEA_STATUS_DEV_ADDR 0xc0 ++#define SPI_CFG (1 << 0) ++ ++/* CMD register value for qspi nand */ ++#define CMD0_VAL 0x1080D8D8 ++#define CMD1_VAL 0xF00F3000 ++#define CMD2_VAL 0xF0FF709F ++#define CMD3_VAL 0x3F310015 ++#define CMD7_VAL 0x04061F0F ++#define CMD_VLD_VAL 0xd ++#define SPI_NUM_ADDR 0xDA4DB ++#define WAIT_CNT 0x10 ++ ++/* QSPI NAND CMD reg bits value */ ++#define SPI_WP (1 << 28) ++#define SPI_HOLD (1 << 27) ++#define SPI_TRANSFER_MODE_x1 (1 << 29) ++#define SPI_TRANSFER_MODE_x4 (3 << 29) ++ + #define nandc_set_read_loc_first(chip, reg, cw_offset, read_size, is_last_read_loc) \ + nandc_set_reg(chip, reg, \ + ((cw_offset) << READ_LOCATION_OFFSET) | \ +@@ -314,6 +351,9 @@ struct nandc_regs { + __le32 read_location_last1; + __le32 read_location_last2; + __le32 read_location_last3; ++ __le32 spi_cfg; ++ __le32 num_addr_cycle; ++ __le32 busy_wait_cnt; + + __le32 erased_cw_detect_cfg_clr; + __le32 erased_cw_detect_cfg_set; +@@ -367,6 +407,7 @@ struct qcom_nand_controller { + + struct clk *core_clk; + struct clk *aon_clk; ++ struct clk *iomacro_clk; + + union { + /* will be used only by QPIC for BAM DMA */ +@@ -460,13 +501,15 @@ struct qcom_nand_host { + * @is_qpic - whether NAND CTRL is part of qpic IP + * @qpic_v2 - flag to indicate QPIC IP version 2 + * @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset ++ * @is_serial_nand - QSPI nand flag, whether QPIC support serial nand or not + */ + struct qcom_nandc_props { + u32 ecc_modes; + bool is_bam; + bool is_qpic; + bool qpic_v2; + u32 dev_cmd_reg_start; ++ bool is_serial_nand; + }; + + /* Frees the BAM transaction memory */ +@@ -640,6 +683,12 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset) + return ®s->read_location_last2; + case NAND_READ_LOCATION_LAST_CW_3: + return ®s->read_location_last3; ++ case NAND_FLASH_SPI_CFG: ++ return ®s->spi_cfg; ++ case NAND_SPI_NUM_ADDR_CYCLES: ++ return ®s->num_addr_cycle; ++ case NAND_SPI_BUSY_CHECK_WAIT_CNT: ++ return ®s->busy_wait_cnt; + default: + return NULL; + } +@@ -1244,11 +1293,23 @@ static int read_id(struct qcom_nand_host *host, int column) + { + struct nand_chip *chip = &host->chip; + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); ++ u32 cmd = OP_FETCH_ID; + + if (column == -1) + return 0; + +- nandc_set_reg(chip, NAND_FLASH_CMD, OP_FETCH_ID); ++ if (nandc->props->is_serial_nand) { ++ cmd |= (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1); ++ /* For spi nand read 2-bytes id only ++ * else if nandc->buf_count == 4; then the id value ++ * will repeat and the SLC device will be detect as MLC. ++ * by nand base layer ++ * so overwrite the nandc->buf_count == 2; ++ */ ++ nandc->buf_count = 2; ++ } ++ ++ nandc_set_reg(chip, NAND_FLASH_CMD, cmd); + nandc_set_reg(chip, NAND_ADDR0, column); + nandc_set_reg(chip, NAND_ADDR1, 0); + nandc_set_reg(chip, NAND_FLASH_CHIP_SELECT, +@@ -1268,8 +1329,13 @@ static int reset(struct qcom_nand_host *host) + { + struct nand_chip *chip = &host->chip; + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); ++ int cmd_rst; ++ ++ cmd_rst = OP_RESET_DEVICE; ++ if (nandc->props->is_serial_nand) ++ cmd_rst |= (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1); + +- nandc_set_reg(chip, NAND_FLASH_CMD, OP_RESET_DEVICE); ++ nandc_set_reg(chip, NAND_FLASH_CMD, cmd_rst); + nandc_set_reg(chip, NAND_EXEC_CMD, 1); + + write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); +@@ -2471,6 +2537,8 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) + int cwperpage, bad_block_byte, ret; + bool wide_bus; + int ecc_mode = 1; ++ int num_addr_cycle = 5, dsbl_sts_aftr_write = 0; ++ int wr_rd_bsy_gap = 2, recovery_cycle = 7; + + /* controller only supports 512 bytes data steps */ + ecc->size = NANDC_STEP_SIZE; +@@ -2579,33 +2647,43 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) + host->cw_size = host->cw_data + ecc->bytes; + bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1; + ++ /* For QSPI serial nand QPIC config register value got changed ++ * so configure the new value for qspi serial nand ++ */ ++ if (nandc->props->is_serial_nand) { ++ num_addr_cycle = 3; ++ dsbl_sts_aftr_write = 1; ++ wr_rd_bsy_gap = 20; ++ recovery_cycle = 0; ++ } ++ + host->cfg0 = (cwperpage - 1) << CW_PER_PAGE + | host->cw_data << UD_SIZE_BYTES +- | 0 << DISABLE_STATUS_AFTER_WRITE +- | 5 << NUM_ADDR_CYCLES ++ | dsbl_sts_aftr_write << DISABLE_STATUS_AFTER_WRITE ++ | num_addr_cycle << NUM_ADDR_CYCLES + | host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS + | 0 << STATUS_BFR_READ + | 1 << SET_RD_MODE_AFTER_STATUS + | host->spare_bytes << SPARE_SIZE_BYTES; + +- host->cfg1 = 7 << NAND_RECOVERY_CYCLES ++ host->cfg1 = recovery_cycle << NAND_RECOVERY_CYCLES + | 0 << CS_ACTIVE_BSY + | bad_block_byte << BAD_BLOCK_BYTE_NUM + | 0 << BAD_BLOCK_IN_SPARE_AREA +- | 2 << WR_RD_BSY_GAP ++ | wr_rd_bsy_gap << WR_RD_BSY_GAP + | wide_bus << WIDE_FLASH + | host->bch_enabled << ENABLE_BCH_ECC; + + host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE + | host->cw_size << UD_SIZE_BYTES +- | 5 << NUM_ADDR_CYCLES ++ | num_addr_cycle << NUM_ADDR_CYCLES + | 0 << SPARE_SIZE_BYTES; + +- host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES ++ host->cfg1_raw = recovery_cycle << NAND_RECOVERY_CYCLES + | 0 << CS_ACTIVE_BSY + | 17 << BAD_BLOCK_BYTE_NUM + | 1 << BAD_BLOCK_IN_SPARE_AREA +- | 2 << WR_RD_BSY_GAP ++ | wr_rd_bsy_gap << WR_RD_BSY_GAP + | wide_bus << WIDE_FLASH + | 1 << DEV0_CFG1_ECC_DISABLE; + +@@ -2781,6 +2859,47 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) + return 0; + } + ++static void qspi_write_reg_bam(struct qcom_nand_controller *nandc, ++ unsigned int val, unsigned int reg) ++{ ++ int ret; ++ ++ clear_bam_transaction(nandc); ++ nandc_set_reg(chip, reg, val); ++ write_reg_dma(nandc, reg, 1, NAND_BAM_NEXT_SGL); ++ ++ ret = submit_descs(nandc); ++ if (ret) ++ dev_err(nandc->dev, "Error in submitting descriptor to write config reg\n"); ++ free_descs(nandc); ++} ++ ++static void qspi_nand_init(struct qcom_nand_controller *nandc) ++{ ++ u32 spi_cfg_val = 0x0; ++ u32 reg = 0x0; ++ ++ spi_cfg_val |= (LOAD_CLK_CNTR_INIT_EN | CLK_CNTR_INIT_VAL_VEC ++ | FEA_STATUS_DEV_ADDR | SPI_CFG); ++ ++ qspi_write_reg_bam(nandc, 0x0, NAND_FLASH_SPI_CFG); ++ qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG); ++ spi_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN; ++ qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG); ++ ++ reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD0); ++ nandc_write(nandc, reg, CMD0_VAL); ++ nandc_write(nandc, reg + 4, CMD1_VAL); ++ nandc_write(nandc, reg + 8, CMD2_VAL); ++ nandc_write(nandc, reg + 12, CMD_VLD_VAL); ++ nandc_write(nandc, reg + 16, CMD7_VAL); ++ reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD3); ++ nandc_write(nandc, reg, CMD3_VAL); ++ ++ qspi_write_reg_bam(nandc, SPI_NUM_ADDR, NAND_SPI_NUM_ADDR_CYCLES); ++ qspi_write_reg_bam(nandc, WAIT_CNT, NAND_SPI_BUSY_CHECK_WAIT_CNT); ++} ++ + static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, + struct qcom_nand_host *host, + struct device_node *dn) +@@ -2830,6 +2949,9 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, + /* set up initial status value */ + host->status = NAND_STATUS_READY | NAND_STATUS_WP; + ++ if (nandc->props->is_serial_nand) ++ qspi_nand_init(nandc); ++ + ret = nand_scan(chip, 1); + if (ret) + return ret; +@@ -2934,6 +3056,12 @@ static int qcom_nandc_probe(struct platform_device *pdev) + if (IS_ERR(nandc->aon_clk)) + return PTR_ERR(nandc->aon_clk); + ++ if (nandc->props->is_serial_nand) { ++ nandc->iomacro_clk = devm_clk_get(dev, "io_macro"); ++ if (IS_ERR(nandc->iomacro_clk)) ++ return PTR_ERR(nandc->iomacro_clk); ++ } ++ + ret = qcom_nandc_parse_dt(pdev); + if (ret) + return ret; +@@ -2962,6 +3090,12 @@ static int qcom_nandc_probe(struct platform_device *pdev) + if (ret) + goto err_nandc_alloc; + ++ if (nandc->props->is_serial_nand) { ++ ret = clk_prepare_enable(nandc->iomacro_clk); ++ if (ret) ++ goto err_setup; ++ } ++ + ret = qcom_nandc_setup(nandc); + if (ret) + goto err_setup; +@@ -3009,6 +3143,7 @@ static const struct qcom_nandc_props ipq806x_nandc_props = { + .ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT), + .is_bam = false, + .dev_cmd_reg_start = 0x0, ++ .is_serial_nand = false, + }; + + static const struct qcom_nandc_props ipq4019_nandc_props = { +@@ -3016,6 +3151,7 @@ static const struct qcom_nandc_props ipq4019_nandc_props = { + .is_bam = true, + .is_qpic = true, + .dev_cmd_reg_start = 0x0, ++ .is_serial_nand = false, + }; + + static const struct qcom_nandc_props ipq8074_nandc_props = { +@@ -3023,6 +3159,15 @@ static const struct qcom_nandc_props ipq8074_nandc_props = { + .is_bam = true, + .is_qpic = true, + .dev_cmd_reg_start = 0x7000, ++ .is_serial_nand = false, ++}; ++ ++static const struct qcom_nandc_props ipq5018_nandc_props = { ++ .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT), ++ .is_bam = true, ++ .qpic_v2 = true, ++ .dev_cmd_reg_start = 0x7000, ++ .is_serial_nand = true, + }; + + /* +@@ -3046,6 +3190,10 @@ static const struct of_device_id qcom_nandc_of_match[] = { + .compatible = "qcom,ebi2-nandc-bam-v1.5.0", + .data = &ipq8074_nandc_props, + }, ++ { ++ .compatible = "qcom,ebi2-nandc-bam-v2.1.1", ++ .data = &ipq5018_nandc_props, ++ }, + {} + }; + MODULE_DEVICE_TABLE(of, qcom_nandc_of_match); +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/404-mtd-rawnand-qcom-Read-QPIC-version.patch b/target/linux/ipq50xx/patches/404-mtd-rawnand-qcom-Read-QPIC-version.patch new file mode 100644 index 0000000000..de8bad61c3 --- /dev/null +++ b/target/linux/ipq50xx/patches/404-mtd-rawnand-qcom-Read-QPIC-version.patch @@ -0,0 +1,60 @@ +From 13bae86b4d3ed01f885e111eda4224a2985ed9a4 Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Tue, 21 Jul 2020 21:19:58 +0530 +Subject: [PATCH 4/7] mtd: rawnand: qcom: Read QPIC version + +This change will add support to read QPIC version. +QPIC version V2.0 onwards some new register introduced +in QPIC. So based on hw_version we will update those +register. + +Signed-off-by: Md Sadre Alam +Change-Id: Iadc95a12145e03b8edf0deb6537b819ad4baec22 + +Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/bfd90c9e9e90c0fa9150d25d2b2e6d4d321610f0 + +Signed-off-by: hzy +--- + drivers/mtd/nand/raw/qcom_nandc.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c +index 361ee116422f..e19074062348 100644 +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -442,6 +442,7 @@ struct qcom_nand_controller { + + u32 cmd1, vld; + const struct qcom_nandc_props *props; ++ u32 hw_version; + }; + + /* +@@ -2539,6 +2540,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) + int ecc_mode = 1; + int num_addr_cycle = 5, dsbl_sts_aftr_write = 0; + int wr_rd_bsy_gap = 2, recovery_cycle = 7; ++ u32 version_reg; + + /* controller only supports 512 bytes data steps */ + ecc->size = NANDC_STEP_SIZE; +@@ -2552,6 +2554,16 @@ static int qcom_nand_attach_chip(struct nand_chip *chip) + if (chip->base.eccreq.strength >= 8) + ecc->strength = 8; + ++ /* Read QPIC version register */ ++ version_reg = (NAND_VERSION + 0x4000); ++ nandc->hw_version = nandc_read(nandc, version_reg); ++ pr_info("QPIC controller hw version Major:%d, Minor:%d\n", ++ ((nandc->hw_version & NAND_VERSION_MAJOR_MASK) ++ >> NAND_VERSION_MAJOR_SHIFT), ++ ((nandc->hw_version & NAND_VERSION_MINOR_MASK) ++ >> NAND_VERSION_MINOR_SHIFT)); ++ nandc->hw_version = ((nandc->hw_version & NAND_VERSION_MAJOR_MASK) ++ >> NAND_VERSION_MAJOR_SHIFT); + /* + * Each CW has 4 available OOB bytes which will be protected with ECC + * so remaining bytes can be used for ECC. +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/405-mtd-rawnand-qcom-Enable-support-for-erase-read-write.patch b/target/linux/ipq50xx/patches/405-mtd-rawnand-qcom-Enable-support-for-erase-read-write.patch new file mode 100644 index 0000000000..57308a6885 --- /dev/null +++ b/target/linux/ipq50xx/patches/405-mtd-rawnand-qcom-Enable-support-for-erase-read-write.patch @@ -0,0 +1,66 @@ +From a5ba59a246e3842ee997e4f2d1ac8cecc8be464c Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Tue, 1 Sep 2020 11:28:09 +0530 +Subject: [PATCH 5/7] mtd: rawnand: qcom: Enable support for erase,read & write + for serial nand. + +This change will enable support for erase, read & write support for +QSPI serial nand. In QPIC V2.0 onwards, to read last code word new +regiater is introduced. So to read for first three code word we have to +use LOCATION_n register and for last code word we ahve to use LAST_CW_n. + +Signed-off-by: Md Sadre Alam +Change-Id: Iafe34e238754dfc006363dd400a48cf9fc8d92d9 + +Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/17e85de9e7933a94461f76fe40a5b88334dfdad6 + +Signed-off-by: hzy +--- + drivers/mtd/nand/raw/qcom_nandc.c | 97 ++++++++++++++++++++++++++----- + 1 file changed, 83 insertions(+), 14 deletions(-) + +diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c +index e19074062348..0a6b67ddcda2 100644 +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -733,13 +752,18 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read) + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); + u32 cmd, cfg0, cfg1, ecc_bch_cfg; + ++ cmd = (PAGE_ACC | LAST_PAGE); ++ ++ if (nandc->props->is_serial_nand) ++ cmd |= (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD); ++ + if (read) { + if (host->use_ecc) +- cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE; ++ cmd |= OP_PAGE_READ_WITH_ECC; + else +- cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE; ++ cmd |= OP_PAGE_READ; + } else { +- cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE; ++ cmd |= OP_PROGRAM_PAGE; + } + + if (host->use_ecc) { +@@ -1265,9 +1298,13 @@ static int erase_block(struct qcom_nand_host *host, int page_addr) + { + struct nand_chip *chip = &host->chip; + struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip); ++ u32 ers_cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE; + +- nandc_set_reg(chip, NAND_FLASH_CMD, +- OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE); ++ if (nandc->props->is_serial_nand) { ++ ers_cmd |= (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1); ++ page_addr <<= 16; ++ } ++ nandc_set_reg(chip, NAND_FLASH_CMD, ers_cmd); + nandc_set_reg(chip, NAND_ADDR0, page_addr); + nandc_set_reg(chip, NAND_ADDR1, 0); + nandc_set_reg(chip, NAND_DEV0_CFG0, +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/406-mtd-rawnand-qcom-Update-bits-of-QPIC_NAND_FLASH_SPI_.patch b/target/linux/ipq50xx/patches/406-mtd-rawnand-qcom-Update-bits-of-QPIC_NAND_FLASH_SPI_.patch new file mode 100644 index 0000000000..6ac9632ed1 --- /dev/null +++ b/target/linux/ipq50xx/patches/406-mtd-rawnand-qcom-Update-bits-of-QPIC_NAND_FLASH_SPI_.patch @@ -0,0 +1,88 @@ +From 47e22e1fc494cd7f11043f80819665d7203effa7 Mon Sep 17 00:00:00 2001 +From: Md Sadre Alam +Date: Wed, 30 Dec 2020 02:23:30 +0530 +Subject: [PATCH 6/7] mtd: rawnand: qcom: Update bits of + QPIC_NAND_FLASH_SPI_CFG reg + +This change will update bits of QPIC_NAND_FLASH_SPI_CFG register +to select serial nand functionality in QPIC controller. + +Signed-off-by: Md Sadre Alam +Change-Id: I643bb47b37cc326783d57d6c0f13618f8e216a37 + +Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/468d4aa56157d9e742a9eb90fe29b1eeb0151b60 + +Signed-off-by: hzy +--- + drivers/mtd/nand/raw/qcom_nandc.c | 17 +++++++++-------- + 1 file changed, 9 insertions(+), 8 deletions(-) + +diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c +index 0a6b67ddcda2..dc723a7ffa0e 100644 +--- a/drivers/mtd/nand/raw/qcom_nandc.c ++++ b/drivers/mtd/nand/raw/qcom_nandc.c +@@ -62,7 +62,6 @@ + #define NAND_READ_LOCATION_LAST_CW_3 0xf4c + #define NAND_QSPI_MSTR_CONFIG 0xf60 + +- + /* dummy register offsets, used by write_reg_dma */ + #define NAND_DEV_CMD1_RESTORE 0xdead + #define NAND_DEV_CMD_VLD_RESTORE 0xbeef +@@ -2781,21 +2859,6 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc) + return 0; + } + +-static void qspi_write_reg_bam(struct qcom_nand_controller *nandc, +- unsigned int val, unsigned int reg) +-{ +- int ret; +- +- clear_bam_transaction(nandc); +- nandc_set_reg(chip, reg, val); +- write_reg_dma(nandc, reg, 1, NAND_BAM_NEXT_SGL); +- +- ret = submit_descs(nandc); +- if (ret) +- dev_err(nandc->dev, "Error in submitting descriptor to write config reg\n"); +- free_descs(nandc); +-} +- + static void qspi_nand_init(struct qcom_nand_controller *nandc) + { + u32 spi_cfg_val = 0x0; +@@ -2960,13 +2959,14 @@ static void qspi_nand_init(struct qcom_nand_controller *nandc) + u32 spi_cfg_val = 0x0; + u32 reg = 0x0; + +- spi_cfg_val |= (LOAD_CLK_CNTR_INIT_EN | CLK_CNTR_INIT_VAL_VEC +- | FEA_STATUS_DEV_ADDR | SPI_CFG); ++ spi_cfg_val |= (LOAD_CLK_CNTR_INIT_EN | (CLK_CNTR_INIT_VAL_VEC << 16) ++ | (FEA_STATUS_DEV_ADDR << 8) | SPI_CFG); + +- qspi_write_reg_bam(nandc, 0x0, NAND_FLASH_SPI_CFG); +- qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG); ++ reg = dev_cmd_reg_addr(nandc, NAND_FLASH_SPI_CFG); ++ nandc_write(nandc, reg, 0); ++ nandc_write(nandc, reg, spi_cfg_val); + spi_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN; +- qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG); ++ nandc_write(nandc, reg, spi_cfg_val); + + reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD0); + nandc_write(nandc, reg, CMD0_VAL); +@@ -2977,8 +2977,9 @@ static void qspi_nand_init(struct qcom_nand_controller *nandc) + reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD3); + nandc_write(nandc, reg, CMD3_VAL); + +- qspi_write_reg_bam(nandc, SPI_NUM_ADDR, NAND_SPI_NUM_ADDR_CYCLES); +- qspi_write_reg_bam(nandc, WAIT_CNT, NAND_SPI_BUSY_CHECK_WAIT_CNT); ++ reg = dev_cmd_reg_addr(nandc, NAND_SPI_NUM_ADDR_CYCLES); ++ nandc_write(nandc, reg, SPI_NUM_ADDR); ++ nandc_write(nandc, reg + 4, WAIT_CNT); + } + + static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/407-drivers-mtd-nand-add-SPI-NAND-devices.patch b/target/linux/ipq50xx/patches/407-drivers-mtd-nand-add-SPI-NAND-devices.patch new file mode 100644 index 0000000000..cdd4f6e0cb --- /dev/null +++ b/target/linux/ipq50xx/patches/407-drivers-mtd-nand-add-SPI-NAND-devices.patch @@ -0,0 +1,75 @@ +From 8963f2d66180d5002209b93cfdc1dca4b9c521e1 Mon Sep 17 00:00:00 2001 +From: Vandhiadevan Karunamoorthy +Date: Tue, 2 Nov 2021 17:30:11 +0530 +Subject: [PATCH 7/7] drivers: mtd: nand: add SPI NAND devices + +This changes add the below given list of SPI NAND +1. W25N01JW +2. GD5F1GQ5REYIG +3. F50D1G41LB +4. GD5F4GQ6REYIHR +5. W25N02JWZEIF +6. MX35UF1GE4AC +7. F50D2G41KA-83YIG2V +8. DS35M1GA +9. GD5F2GQ5REYIG + +Change-Id: Ib8f669b86e8cb8a30462a868fb4bbc5606142bba +Signed-off-by: Vandhiadevan Karunamoorthy + +Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/d9b8a8fcc227d9da867dca22f9c6e9a1e690650d + +Signed-off-by: hzy +--- + drivers/mtd/nand/raw/nand_ids.c | 35 +++++++++++++++++++++++++++++++++ + 1 file changed, 35 insertions(+) + +diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c +index 03e472055d9e..b91ef498c9e3 100644 +--- a/drivers/mtd/nand/raw/nand_ids.c ++++ b/drivers/mtd/nand/raw/nand_ids.c +@@ -66,6 +66,41 @@ struct nand_flash_dev nand_flash_ids[] = { + { .id = {0x2c, 0x15} }, + SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) }, + ++ {"MX35UF4GE4AD-Z4I SPI NAND 1G 1.8V", ++ { .id = {0xc2, 0xb7} }, ++ SZ_4K, SZ_512, SZ_256K, 0, 2, 256, NAND_ECC_INFO(8, SZ_512) }, ++ {"GD5F1GQ5REYIH SPI NAND 1G 1.8V", ++ { .id = {0xc8, 0x21} }, ++ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) }, ++ {"W25N01JW SPI NAND 1.8V 1G-BIT", ++ { .id = {0xef, 0xbc} }, ++ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) }, ++ {"GD5F1GQ5REYIG SPI NAND 1G", ++ { .id = {0xc8, 0x41} }, ++ SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) }, ++ {"F50D1G41LB(2M) SPI NAND 1G 1.8V", ++ { .id = {0xc8, 0x11} }, ++ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) }, ++ {"GD5F4GQ6REYIHR SPI NAND 4G 1.8V", ++ { .id = {0xc8, 0x25} }, ++ SZ_2K, SZ_512, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) }, ++ {"W25N02JWZEIF SPI NAND 2G 1.8V", ++ { .id = {0xef, 0xbf} }, ++ SZ_2K, SZ_256, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) }, ++ {"MX35UF1GE4AC SPI NAND 1G 1.8V", ++ { .id = {0xc2, 0x92} }, ++ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) }, ++ {"F50D2G41KA-83YIG2V SPI NAND 2G 1.8V", ++ { .id = {0xc8, 0x51} }, ++ SZ_2K, SZ_256, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) }, ++ {"DS35M1GA SPI NAND 1G 1.8V", ++ { .id = {0xe5, 0x21} }, ++ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) }, ++ {"GD5F2GQ5REYIG SPI NAND 2G", ++ { .id = {0xc8, 0x42} }, ++ SZ_2K, SZ_256, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) }, ++ ++ + LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS), +-- +2.25.1 + diff --git a/target/linux/ipq50xx/patches/411-arm64-dts-qcom-ipq5018-Add-nand-node.patch b/target/linux/ipq50xx/patches/411-arm64-dts-qcom-ipq5018-Add-nand-node.patch new file mode 100644 index 0000000000..d3d054084a --- /dev/null +++ b/target/linux/ipq50xx/patches/411-arm64-dts-qcom-ipq5018-Add-nand-node.patch @@ -0,0 +1,65 @@ +From 84f2d1697645ce75c61b4888ee397f272d3dd6b2 Mon Sep 17 00:00:00 2001 +From: hzy +Date: Fri, 10 Mar 2023 16:34:30 +0000 +Subject: [PATCH 1/1] arm64: dts: qcom: ipq5018: Add nand node + +Signed-off-by: hzy +--- + arch/arm64/boot/dts/qcom/ipq5018.dtsi | 42 +++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) + +diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +index 668a931c892e..c214ac5580eb 100644 +--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi +@@ -209,5 +209,47 @@ + status = "disabled"; + }; + }; ++ ++ qpic_bam: dma@7984000 { ++ compatible = "qcom,bam-v1.7.0"; ++ reg = <0x7984000 0x1c000>; ++ interrupts = ; ++ clocks = <&gcc GCC_QPIC_AHB_CLK>; ++ clock-names = "bam_clk"; ++ #dma-cells = <1>; ++ qcom,ee = <0>; ++ status = "disabled"; ++ }; ++ ++ nand: qpic-nand@79b0000 { ++ compatible = "qcom,ebi2-nandc-bam-v2.1.1"; ++ reg = <0x79b0000 0x10000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&gcc GCC_QPIC_CLK>, ++ <&gcc GCC_QPIC_AHB_CLK>, ++ <&gcc GCC_QPIC_IO_MACRO_CLK>; ++ clock-names = "core", "aon", "io_macro"; ++ ++ dmas = <&qpic_bam 0>, ++ <&qpic_bam 1>, ++ <&qpic_bam 2>, ++ <&qpic_bam 3>; ++ dma-names = "tx", "rx", "cmd", "status"; ++ ++ qpic,io_macro_clk_rates = <24000000 100000000 200000000 320000000>; ++ status = "disabled"; ++ ++ nandcs@0 { ++ compatible = "qcom,nandcs"; ++ reg = <0>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ nand-ecc-strength = <4>; ++ nand-ecc-step-size = <512>; ++ nand-bus-width = <8>; ++ }; ++ }; + }; + }; +-- +2.25.1 +