mirror of
https://github.com/hzyitc/openwrt-redmi-ax3000.git
synced 2025-12-16 16:31:57 +00:00
99 lines
2.9 KiB
Diff
99 lines
2.9 KiB
Diff
From f85c726162496b3d1cba80867b8d780c142b77eb Mon Sep 17 00:00:00 2001
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From: hzy <hzyitc@outlook.com>
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Date: Mon, 20 Mar 2023 20:27:17 +0000
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Subject: [PATCH 3/3] arm64: dts: qcom: ipq5018: Add ess node
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 75 +++++++++++++++++++++++++++
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1 file changed, 75 insertions(+)
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diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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index 71da4ba4f6bb..0bc0f271b251 100644
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -271,5 +271,80 @@
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clocks-name = "gcc_mdio_ahb_clk";
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status = "disabled";
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};
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+
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+ nss-dp-common {
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+ compatible = "qcom,nss-dp-common";
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+ qcom,tcsr-base = <0x01937000>;
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+ };
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+
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+ ess-uniphy@98000 {
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+ compatible = "qcom,ess-uniphy";
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+ reg = <0x98000 0x800>;
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+ uniphy_access_mode = "local bus";
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+ };
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+
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+ ess-instance {
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+ ess-switch@0x39c00000 {
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+ compatible = "qcom,ess-switch-ipq50xx";
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+ reg = <0x39c00000 0x200000>;
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+ switch_access_mode = "local bus";
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+ clocks = <&gcc GCC_CMN_BLK_AHB_CLK>,
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+ <&gcc GCC_CMN_BLK_SYS_CLK>,
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+ <&gcc GCC_UNIPHY_AHB_CLK>,
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+ <&gcc GCC_UNIPHY_SYS_CLK>,
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+ <&gcc GCC_MDIO0_AHB_CLK>,
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+ <&gcc GCC_MDIO1_AHB_CLK>,
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+ <&gcc GCC_GMAC0_CFG_CLK>,
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+ <&gcc GCC_GMAC0_SYS_CLK>,
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+ <&gcc GCC_GMAC1_CFG_CLK>,
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+ <&gcc GCC_GMAC1_SYS_CLK>,
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+ <&gcc GCC_GEPHY_RX_CLK>,
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+ <&gcc GCC_GEPHY_TX_CLK>,
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+ <&gcc GCC_UNIPHY_RX_CLK>,
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+ <&gcc GCC_UNIPHY_TX_CLK>,
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+ <&gcc GCC_GMAC0_RX_CLK>,
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+ <&gcc GCC_GMAC0_TX_CLK>,
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+ <&gcc GCC_GMAC1_RX_CLK>,
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+ <&gcc GCC_GMAC1_TX_CLK>,
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+ <&gcc GCC_SNOC_GMAC0_AHB_CLK>,
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+ <&gcc GCC_SNOC_GMAC1_AHB_CLK>,
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+ <&gcc GCC_GMAC0_PTP_CLK>,
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+ <&gcc GCC_GMAC1_PTP_CLK>;
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+ clock-names = "cmn_ahb_clk",
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+ "cmn_sys_clk",
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+ "uniphy_ahb_clk",
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+ "uniphy_sys_clk",
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+ "gcc_mdio0_ahb_clk",
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+ "gcc_mdio1_ahb_clk",
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+ "gcc_gmac0_cfg_clk",
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+ "gcc_gmac0_sys_clk",
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+ "gcc_gmac1_cfg_clk",
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+ "gcc_gmac1_sys_clk",
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+ "uniphy0_port1_rx_clk",
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+ "uniphy0_port1_tx_clk",
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+ "uniphy1_port5_rx_clk",
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+ "uniphy1_port5_tx_clk",
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+ "nss_port1_rx_clk",
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+ "nss_port1_tx_clk",
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+ "nss_port2_rx_clk",
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+ "nss_port2_tx_clk",
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+ "gcc_snoc_gmac0_ahb_clk",
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+ "gcc_snoc_gmac1_ahb_clk",
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+ "gcc_gmac0_ptp_clk",
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+ "gcc_gmac1_ptp_clk";
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+ resets = <&gcc GCC_GEPHY_BCR>,
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+ <&gcc GCC_UNIPHY_BCR>,
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+ <&gcc GCC_GMAC0_BCR>,
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+ <&gcc GCC_GMAC1_BCR>,
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+ <&gcc GCC_UNIPHY_SOFT_RESET>,
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+ <&gcc GCC_GEPHY_MISC_ARES>;
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+ reset-names = "gephy_bcr_rst",
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+ "uniphy_bcr_rst",
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+ "gmac0_bcr_rst",
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+ "gmac1_bcr_rst",
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+ "uniphy1_soft_rst",
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+ "gephy_misc_rst";
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+ };
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+ };
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};
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};
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--
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2.25.1
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