mirror of
https://github.com/hzyitc/openwrt-redmi-ax3000.git
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110 lines
2.7 KiB
Diff
110 lines
2.7 KiB
Diff
From c22fb5533f31593bbc8ffa603c69ec002338ca5a Mon Sep 17 00:00:00 2001
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From: hzy <hzyitc@outlook.com>
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Date: Tue, 14 Mar 2023 17:25:13 +0000
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Subject: [PATCH 4/4] arm64: dts: qcom: ipq5018: Add APSS mailbox and clock
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node
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 54 +++++++++++++++++++++++++++
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1 file changed, 54 insertions(+)
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diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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index 668a931c892e..1114a1134202 100644
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -8,6 +8,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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+#include <dt-bindings/clock/qcom,apss-ipq.h>
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/ {
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#address-cells = <2>;
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@@ -37,7 +38,11 @@
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compatible = "arm,cortex-a53";
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reg = <0x0>;
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enable-method = "psci";
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+ qcom,acc = <&acc0>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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CPU1: cpu@1 {
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@@ -45,7 +50,11 @@
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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+ qcom,acc = <&acc1>;
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next-level-cache = <&L2_0>;
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+ clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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+ clock-names = "cpu";
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+ operating-points-v2 = <&cpu_opp_table>;
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};
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L2_0: l2-cache {
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@@ -54,6 +63,23 @@
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};
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};
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+ cpu_opp_table: opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-800000000 {
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+ opp-hz = /bits/ 64 <800000000>;
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+ opp-microvolt = <1100>;
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+ clock-latency-ns = <200000>;
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+ };
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+
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+ opp-1008000000 {
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+ opp-hz = /bits/ 64 <1008000000>;
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+ opp-microvolt = <1100>;
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+ clock-latency-ns = <200000>;
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+ };
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+ };
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+
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pmuv8: pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
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@@ -143,6 +169,34 @@
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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+ apcs_glb: mailbox@b111000 {
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+ compatible = "qcom,ipq5018-apcs-apps-global";
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+ reg = <0x0b111000 0x1000>;
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+ clocks = <&xo>, <&a53pll>;
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+ clock-names = "xo", "pll";
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+
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+ #clock-cells = <1>;
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+ #mbox-cells = <1>;
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+ };
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+
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+ a53pll: clock@b116000 {
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+ compatible = "qcom,ipq5018-a53pll";
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+ reg = <0x0b116000 0x40>;
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+ #clock-cells = <0>;
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+ clocks = <&xo>;
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+ clock-names = "xo";
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+ };
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+
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+ acc0:clock-controller@b188000 {
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+ compatible = "qcom,arm-cortex-acc";
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+ reg = <0x0b188000 0x1000>;
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+ };
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+
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+ acc1:clock-controller@b198000 {
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+ compatible = "qcom,arm-cortex-acc";
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+ reg = <0x0b198000 0x1000>;
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+ };
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+
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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--
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2.25.1
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