diff --git a/feeds/wifi-ax/ath11k-wifi/Makefile b/feeds/wifi-ax/ath11k-wifi/Makefile index a4f0bcc82..4b76a1857 100644 --- a/feeds/wifi-ax/ath11k-wifi/Makefile +++ b/feeds/wifi-ax/ath11k-wifi/Makefile @@ -27,7 +27,8 @@ ALLWIFIBOARDS:= \ cig-wf188 \ cig-wf188n \ cig-wf194c \ - sercomm-wallaby + sercomm-wallaby \ + edgecore-eap102 ALLWIFIPACKAGES:=$(foreach BOARD,$(ALLWIFIBOARDS),ath11k-wifi-$(BOARD)) @@ -106,6 +107,7 @@ $(eval $(call generate-ath11k-wifi-package,cig-wf188,Cigtech WF188)) $(eval $(call generate-ath11k-wifi-package,cig-wf188n,Cigtech WF188n)) $(eval $(call generate-ath11k-wifi-package,cig-wf194c,Cigtech WF194c)) $(eval $(call generate-ath11k-wifi-package,sercomm-wallaby,Sercomm Kiwi)) +$(eval $(call generate-ath11k-wifi-package,edgecore-eap102,Edgecore EAP102)) $(foreach PACKAGE,$(ALLWIFIPACKAGES),$(eval $(call BuildPackage,$(PACKAGE)))) $(eval $(call BuildPackage,ath11k-wifi-qcom-ipq8074)) diff --git a/feeds/wifi-ax/ath11k-wifi/board-edgecore-eap102.IPQ8074 b/feeds/wifi-ax/ath11k-wifi/board-edgecore-eap102.IPQ8074 new file mode 100644 index 000000000..88fce866b Binary files /dev/null and b/feeds/wifi-ax/ath11k-wifi/board-edgecore-eap102.IPQ8074 differ diff --git a/feeds/wifi-ax/mac80211/Makefile b/feeds/wifi-ax/mac80211/Makefile index aa65707d5..128d5e312 100644 --- a/feeds/wifi-ax/mac80211/Makefile +++ b/feeds/wifi-ax/mac80211/Makefile @@ -43,6 +43,7 @@ config-y:= \ MAC80211_RC_MINSTREL_HT \ MAC80211_RC_MINSTREL_VHT \ MAC80211_RC_DEFAULT_MINSTREL \ + MAC80211_LEDS \ WLAN_VENDOR_ADMTEK \ WLAN_VENDOR_ATH \ WLAN_VENDOR_ATMEL \ diff --git a/patches/0035-ipq807x-add-edgecore-EAP-102-support.patch b/patches/0035-ipq807x-add-edgecore-EAP-102-support.patch new file mode 100644 index 000000000..d61ffef0f --- /dev/null +++ b/patches/0035-ipq807x-add-edgecore-EAP-102-support.patch @@ -0,0 +1,1027 @@ +From 34f431b13c858b63d9361f1291734fb53900e73b Mon Sep 17 00:00:00 2001 +From: John Crispin +Date: Fri, 16 Oct 2020 04:27:42 +0200 +Subject: [PATCH] ipq807x: add edgecore EAP-102 support + +Signed-off-by: John Crispin +--- + .../ipq807x/base-files/etc/board.d/01_leds | 4 + + .../ipq807x/base-files/etc/board.d/02_network | 4 + + .../etc/hotplug.d/firmware/10-ath11k-caldata | 1 + + .../base-files/lib/upgrade/platform.sh | 2 + + .../boot/dts/qcom/qcom-ipq807x-eap102.dts | 922 ++++++++++++++++++ + target/linux/ipq807x/image/ipq807x.mk | 10 + + 6 files changed, 943 insertions(+) + create mode 100755 target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts + +diff --git a/target/linux/ipq807x/base-files/etc/board.d/01_leds b/target/linux/ipq807x/base-files/etc/board.d/01_leds +index 5196da447b..3ed1227a3d 100755 +--- a/target/linux/ipq807x/base-files/etc/board.d/01_leds ++++ b/target/linux/ipq807x/base-files/etc/board.d/01_leds +@@ -15,6 +15,10 @@ cig,wf194c) + ucidef_set_led_netdev "wan" "WAN" "wf194c:green:wan" "br-wan" "tx rx link" + ucidef_set_led_netdev "lan" "LAN" "wf194c:green:lan" "br-lan" "tx rx link" + ;; ++edgecore,eap102) ++ ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy0tx" ++ ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wifi2" "phy1tx" ++ ;; + esac + + board_config_flush +diff --git a/target/linux/ipq807x/base-files/etc/board.d/02_network b/target/linux/ipq807x/base-files/etc/board.d/02_network +index aadf9d4ff2..0ae29613d9 100755 +--- a/target/linux/ipq807x/base-files/etc/board.d/02_network ++++ b/target/linux/ipq807x/base-files/etc/board.d/02_network +@@ -26,6 +26,10 @@ qcom_setup_interfaces() + ucidef_set_interface_lan "eth0" + ucidef_set_interface_wan "eth1" + ;; ++ edgecore,eap102) ++ ucidef_set_interface_lan "eth1" ++ ucidef_set_interface_wan "eth0" ++ ;; + esac + } + +diff --git a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata +index 30292c2505..faade0972f 100755 +--- a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata ++++ b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata +@@ -29,6 +29,7 @@ case "$FIRMWARE" in + "IPQ8074/caldata.bin") + case "$board" in + cig,wf194c|\ ++ edgecore,eap102 |\ + qcom,ipq807x-hk01|\ + qcom,ipq807x-hk14|\ + sercomm,wallaby) +diff --git a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh +index 0073b94bbb..43ee219412 100755 +--- a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh ++++ b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh +@@ -23,6 +23,7 @@ platform_check_image() { + cig,wf188|\ + cig,wf188n|\ + cig,wf194c|\ ++ edgecore,eap102|\ + qcom,ipq6018-cp01|\ + qcom,ipq807x-hk01|\ + sercomm,wallaby) +@@ -44,6 +45,7 @@ platform_do_upgrade() { + ;; + cig,wf188n|\ + cig,wf194c|\ ++ edgecore,eap102|\ + qcom,ipq6018-cp01|\ + qcom,ipq807x-hk01|\ + sercomm,wallaby) +diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts +new file mode 100755 +index 0000000000..f81cf2d4af +--- /dev/null ++++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts +@@ -0,0 +1,922 @@ ++/dts-v1/; ++/* ++ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++#include "qcom-ipq807x-soc.dtsi" ++#include "qcom-ipq807x-ac-cpu.dtsi" ++ ++/ { ++ #address-cells = <0x2>; ++ #size-cells = <0x2>; ++ model = "Edgecore EAP102"; ++ compatible = "edgecore,eap102", "qcom,ipq807x-ac02", "qcom,ipq807x"; ++ qcom,msm-id = <0x178 0x0>; ++ interrupt-parent = <&intc>; ++ qcom,board-id = <0x8 0x0>; ++ qcom,pmic-id = <0x0 0x0 0x0 0x0>; ++ ++ aliases { ++ /* ++ * Aliases as required by u-boot ++ * to patch MAC addresses ++ */ ++ ethernet0 = "/soc/dp1"; ++ ethernet1 = "/soc/dp2"; ++ ethernet2 = "/soc/dp3"; ++ ethernet3 = "/soc/dp4"; ++ ethernet4 = "/soc/dp5"; ++ ethernet5 = "/soc/dp6"; ++ ++ led-boot = &led_power; ++ led-failsafe = &led_power; ++ led-running = &led_power; ++ led-upgrade = &led_power; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw \ ++ init=/init"; ++ #ifdef __IPQ_MEM_PROFILE_256_MB__ ++ bootargs-append = " swiotlb=1"; ++ #else ++ bootargs-append = " swiotlb=1 coherent_pool=2M"; ++ #endif ++ }; ++}; ++ ++&tlmm { ++ pinctrl-0 = <&btcoex_pins>; ++ pinctrl-names = "default"; ++ ++ btcoex_pins: btcoex_pins { ++ mux_0 { ++ pins = "gpio64"; ++ function = "pta1_1"; ++ drive-strength = <6>; ++ bias-pull-down; ++ }; ++ mux_1 { ++ pins = "gpio65"; ++ function = "pta1_2"; ++ drive-strength = <6>; ++ bias-pull-down; ++ }; ++ }; ++ ++ mdio_pins: mdio_pinmux { ++ mux_0 { ++ pins = "gpio68"; ++ function = "mdc"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ mux_1 { ++ pins = "gpio69"; ++ function = "mdio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ mux_2 { ++ pins = "gpio33"; ++ function = "gpio"; ++ bias-pull-up; ++ }; ++ mux_3 { ++ pins = "gpio44"; ++ function = "gpio"; ++ bias-pull-up; ++ }; ++ }; ++ ++ uart_pins: uart_pins { ++ mux { ++ pins = "gpio23", "gpio24"; ++ function = "blsp4_uart1"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ spi_0_pins: spi_0_pins { ++ mux { ++ pins = "gpio38", "gpio39", "gpio40", "gpio41"; ++ function = "blsp0_spi"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ qpic_pins: qpic_pins { ++ data_0 { ++ pins = "gpio15"; ++ function = "qpic_pad0"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ data_1 { ++ pins = "gpio12"; ++ function = "qpic_pad1"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ data_2 { ++ pins = "gpio13"; ++ function = "qpic_pad2"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ data_3 { ++ pins = "gpio14"; ++ function = "qpic_pad3"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ data_4 { ++ pins = "gpio5"; ++ function = "qpic_pad4"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ data_5 { ++ pins = "gpio6"; ++ function = "qpic_pad5"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ data_6 { ++ pins = "gpio7"; ++ function = "qpic_pad6"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ data_7 { ++ pins = "gpio8"; ++ function = "qpic_pad7"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ qpic_pad { ++ pins = "gpio1", "gpio3", "gpio4", ++ "gpio10", "gpio11", "gpio17"; ++ function = "qpic_pad"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ hsuart_pins: hsuart_pins { ++ mux { ++ pins = "gpio49"; ++ function = "blsp2_uart"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ button_pins: button_pins { ++ ++ reset_button { ++ pins = "gpio66"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ }; ++ ++ led_pins: led_pins { ++ led_pwr { ++ pins = "gpio46"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ ++ led_2g { ++ pins = "gpio47"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ ++ led_5g { ++ pins = "gpio48"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ ++ led_bt { ++ pins = "gpio50"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ usb_mux_sel_pins: usb_mux_pins { ++ mux { ++ pins = "gpio27"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ pcie0_pins: pcie_pins { ++ pcie0_rst { ++ pins = "gpio58"; ++ function = "pcie0_rst"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ pcie0_wake { ++ pins = "gpio59"; ++ function = "pcie0_wake"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++}; ++ ++&soc { ++ gpio_keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&button_pins>; ++ pinctrl-names = "default"; ++ ++ button@1 { ++ label = "reset_button"; ++ linux,code = ; ++ gpios = <&tlmm 66 GPIO_ACTIVE_LOW>; ++ linux,input-type = <1>; ++ debounce-interval = <60>; ++ }; ++ }; ++ ++ mdio: mdio@90000 { ++ pinctrl-0 = <&mdio_pins>; ++ pinctrl-names = "default"; ++ phy-reset-gpio = <&tlmm 37 0 &tlmm 25 1 &tlmm 44 1>; ++ compatible = "qcom,ipq40xx-mdio", "qcom,qca-mdio"; ++ phy0: ethernet-phy@0 { ++ reg = <0>; ++ }; ++ phy1: ethernet-phy@1 { ++ reg = <1>; ++ }; ++ phy2: ethernet-phy@2 { ++ reg = <2>; ++ }; ++ phy3: ethernet-phy@3 { ++ reg = <3>; ++ }; ++ phy4: ethernet-phy@4 { ++ reg = <24>; ++ }; ++ phy5: ethernet-phy@5 { ++ reg = <28>; ++ }; ++ }; ++ ++ ess-switch@3a000000 { ++ switch_cpu_bmp = <0x1>; /* cpu port bitmap */ ++ switch_lan_bmp = <0x3e>; /* lan port bitmap */ ++ switch_wan_bmp = <0x40>; /* wan port bitmap */ ++ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ ++ switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/ ++ switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/ ++ bm_tick_mode = <0>; /* bm tick mode */ ++ tm_tick_mode = <0>; /* tm tick mode */ ++ qcom,port_phyinfo { ++ port@0 { ++ port_id = <1>; ++ phy_address = <0>; ++ }; ++ port@1 { ++ port_id = <2>; ++ phy_address = <1>; ++ }; ++ port@2 { ++ port_id = <3>; ++ phy_address = <2>; ++ }; ++ port@3 { ++ port_id = <4>; ++ phy_address = <3>; ++ }; ++ port@4 { ++ port_id = <5>; ++ phy_address = <24>; ++ port_mac_sel = "QGMAC_PORT"; ++ }; ++ port@5 { ++ port_id = <6>; ++ phy_address = <28>; ++ port_mac_sel = "QGMAC_PORT"; ++ }; ++ }; ++ port_scheduler_resource { ++ port@0 { ++ port_id = <0>; ++ ucast_queue = <0 143>; ++ mcast_queue = <256 271>; ++ l0sp = <0 35>; ++ l0cdrr = <0 47>; ++ l0edrr = <0 47>; ++ l1cdrr = <0 7>; ++ l1edrr = <0 7>; ++ }; ++ port@1 { ++ port_id = <1>; ++ ucast_queue = <144 159>; ++ mcast_queue = <272 275>; ++ l0sp = <36 39>; ++ l0cdrr = <48 63>; ++ l0edrr = <48 63>; ++ l1cdrr = <8 11>; ++ l1edrr = <8 11>; ++ }; ++ port@2 { ++ port_id = <2>; ++ ucast_queue = <160 175>; ++ mcast_queue = <276 279>; ++ l0sp = <40 43>; ++ l0cdrr = <64 79>; ++ l0edrr = <64 79>; ++ l1cdrr = <12 15>; ++ l1edrr = <12 15>; ++ }; ++ port@3 { ++ port_id = <3>; ++ ucast_queue = <176 191>; ++ mcast_queue = <280 283>; ++ l0sp = <44 47>; ++ l0cdrr = <80 95>; ++ l0edrr = <80 95>; ++ l1cdrr = <16 19>; ++ l1edrr = <16 19>; ++ }; ++ port@4 { ++ port_id = <4>; ++ ucast_queue = <192 207>; ++ mcast_queue = <284 287>; ++ l0sp = <48 51>; ++ l0cdrr = <96 111>; ++ l0edrr = <96 111>; ++ l1cdrr = <20 23>; ++ l1edrr = <20 23>; ++ }; ++ port@5 { ++ port_id = <5>; ++ ucast_queue = <208 223>; ++ mcast_queue = <288 291>; ++ l0sp = <52 55>; ++ l0cdrr = <112 127>; ++ l0edrr = <112 127>; ++ l1cdrr = <24 27>; ++ l1edrr = <24 27>; ++ }; ++ port@6 { ++ port_id = <6>; ++ ucast_queue = <224 239>; ++ mcast_queue = <292 295>; ++ l0sp = <56 59>; ++ l0cdrr = <128 143>; ++ l0edrr = <128 143>; ++ l1cdrr = <28 31>; ++ l1edrr = <28 31>; ++ }; ++ port@7 { ++ port_id = <7>; ++ ucast_queue = <240 255>; ++ mcast_queue = <296 299>; ++ l0sp = <60 63>; ++ l0cdrr = <144 159>; ++ l0edrr = <144 159>; ++ l1cdrr = <32 35>; ++ l1edrr = <32 35>; ++ }; ++ }; ++ port_scheduler_config { ++ port@0 { ++ port_id = <0>; ++ l1scheduler { ++ group@0 { ++ sp = <0 1>; /*L0 SPs*/ ++ /*cpri cdrr epri edrr*/ ++ cfg = <0 0 0 0>; ++ }; ++ }; ++ l0scheduler { ++ group@0 { ++ /*unicast queues*/ ++ ucast_queue = <0 4 8>; ++ /*multicast queues*/ ++ mcast_queue = <256 260>; ++ /*sp cpri cdrr epri edrr*/ ++ cfg = <0 0 0 0 0>; ++ }; ++ group@1 { ++ ucast_queue = <1 5 9>; ++ mcast_queue = <257 261>; ++ cfg = <0 1 1 1 1>; ++ }; ++ group@2 { ++ ucast_queue = <2 6 10>; ++ mcast_queue = <258 262>; ++ cfg = <0 2 2 2 2>; ++ }; ++ group@3 { ++ ucast_queue = <3 7 11>; ++ mcast_queue = <259 263>; ++ cfg = <0 3 3 3 3>; ++ }; ++ }; ++ }; ++ port@1 { ++ port_id = <1>; ++ l1scheduler { ++ group@0 { ++ sp = <36>; ++ cfg = <0 8 0 8>; ++ }; ++ group@1 { ++ sp = <37>; ++ cfg = <1 9 1 9>; ++ }; ++ }; ++ l0scheduler { ++ group@0 { ++ ucast_queue = <144>; ++ ucast_loop_pri = <16>; ++ mcast_queue = <272>; ++ mcast_loop_pri = <4>; ++ cfg = <36 0 48 0 48>; ++ }; ++ }; ++ }; ++ port@2 { ++ port_id = <2>; ++ l1scheduler { ++ group@0 { ++ sp = <40>; ++ cfg = <0 12 0 12>; ++ }; ++ group@1 { ++ sp = <41>; ++ cfg = <1 13 1 13>; ++ }; ++ }; ++ l0scheduler { ++ group@0 { ++ ucast_queue = <160>; ++ ucast_loop_pri = <16>; ++ mcast_queue = <276>; ++ mcast_loop_pri = <4>; ++ cfg = <40 0 64 0 64>; ++ }; ++ }; ++ }; ++ port@3 { ++ port_id = <3>; ++ l1scheduler { ++ group@0 { ++ sp = <44>; ++ cfg = <0 16 0 16>; ++ }; ++ group@1 { ++ sp = <45>; ++ cfg = <1 17 1 17>; ++ }; ++ }; ++ l0scheduler { ++ group@0 { ++ ucast_queue = <176>; ++ ucast_loop_pri = <16>; ++ mcast_queue = <280>; ++ mcast_loop_pri = <4>; ++ cfg = <44 0 80 0 80>; ++ }; ++ }; ++ }; ++ port@4 { ++ port_id = <4>; ++ l1scheduler { ++ group@0 { ++ sp = <48>; ++ cfg = <0 20 0 20>; ++ }; ++ group@1 { ++ sp = <49>; ++ cfg = <1 21 1 21>; ++ }; ++ }; ++ l0scheduler { ++ group@0 { ++ ucast_queue = <192>; ++ ucast_loop_pri = <16>; ++ mcast_queue = <284>; ++ mcast_loop_pri = <4>; ++ cfg = <48 0 96 0 96>; ++ }; ++ }; ++ }; ++ port@5 { ++ port_id = <5>; ++ l1scheduler { ++ group@0 { ++ sp = <52>; ++ cfg = <0 24 0 24>; ++ }; ++ group@1 { ++ sp = <53>; ++ cfg = <1 25 1 25>; ++ }; ++ }; ++ l0scheduler { ++ group@0 { ++ ucast_queue = <208>; ++ ucast_loop_pri = <16>; ++ mcast_queue = <288>; ++ mcast_loop_pri = <4>; ++ cfg = <52 0 112 0 112>; ++ }; ++ }; ++ }; ++ port@6 { ++ port_id = <6>; ++ l1scheduler { ++ group@0 { ++ sp = <56>; ++ cfg = <0 28 0 28>; ++ }; ++ group@1 { ++ sp = <57>; ++ cfg = <1 29 1 29>; ++ }; ++ }; ++ l0scheduler { ++ group@0 { ++ ucast_queue = <224>; ++ ucast_loop_pri = <16>; ++ mcast_queue = <292>; ++ mcast_loop_pri = <4>; ++ cfg = <56 0 128 0 128>; ++ }; ++ }; ++ }; ++ port@7 { ++ port_id = <7>; ++ l1scheduler { ++ group@0 { ++ sp = <60>; ++ cfg = <0 32 0 32>; ++ }; ++ }; ++ l0scheduler { ++ group@0 { ++ ucast_queue = <240>; ++ mcast_queue = <296>; ++ cfg = <60 0 144 0 144>; ++ }; ++ }; ++ }; ++ }; ++ }; ++ ++ dp1 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <1>; ++ reg = <0x3a001000 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <0>; ++ phy-mode = "sgmii"; ++ }; ++ ++ dp2 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <2>; ++ reg = <0x3a001200 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <1>; ++ phy-mode = "sgmii"; ++ }; ++ ++ dp3 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <3>; ++ reg = <0x3a001400 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <2>; ++ phy-mode = "sgmii"; ++ }; ++ ++ dp4 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <4>; ++ reg = <0x3a001600 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <3>; ++ phy-mode = "sgmii"; ++ }; ++ ++ dp5 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <5>; ++ reg = <0x3a001800 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <24>; ++ phy-mode = "sgmii"; ++ }; ++ ++ dp6 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <6>; ++ reg = <0x3a001a00 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <28>; ++ phy-mode = "sgmii"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&led_pins>; ++ pinctrl-names = "default"; ++ ++ led_power: led_pwr { ++ label = "green:power"; ++ gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ linux,default-trigger = "led_pwr"; ++ }; ++ ++ led_2g { ++ label = "green:wifi2"; ++ gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ led_5g { ++ label = "green:wifi5"; ++ gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ led_bt { ++ gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>; ++ label = "green:bt"; ++ default-state = "off"; ++ linux,default-trigger = "led_bt"; ++ }; ++ }; ++ nss-macsec0 { ++ compatible = "qcom,nss-macsec"; ++ phy_addr = <0x18>; ++ phy_access_mode = <0>; ++ mdiobus = <&mdio>; ++ }; ++ nss-macsec1 { ++ compatible = "qcom,nss-macsec"; ++ phy_addr = <0x1c>; ++ phy_access_mode = <0>; ++ mdiobus = <&mdio>; ++ }; ++}; ++ ++&serial_blsp4 { ++ pinctrl-0 = <&uart_pins>; ++ pinctrl-names = "default"; ++ status = "ok"; ++}; ++ ++&spi_0 { /* BLSP1 QUP1 */ ++ pinctrl-0 = <&spi_0_pins>; ++ pinctrl-names = "default"; ++ cs-select = <0>; ++ status = "ok"; ++ ++ m25p80@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0>; ++ compatible = "n25q128a11"; ++ linux,modalias = "m25p80", "n25q128a11"; ++ spi-max-frequency = <50000000>; ++ use-default-sizes; ++ }; ++}; ++ ++&serial_blsp2 { ++ pinctrl-0 = <&hsuart_pins>; ++ pinctrl-names = "default"; ++ status = "ok"; ++}; ++ ++&nss0 { ++ qcom,low-frequency = <187200000>; ++ qcom,mid-frequency = <748800000>; ++ qcom,max-frequency = <1497600000>; ++}; ++ ++&msm_imem { ++ status = "disabled"; ++}; ++ ++&ssphy_0 { ++ status = "ok"; ++}; ++ ++&qusb_phy_0 { ++ status = "ok"; ++}; ++ ++&ssphy_1 { ++ status = "ok"; ++}; ++ ++&qusb_phy_1 { ++ status = "ok"; ++}; ++ ++&usb3_0 { ++ status = "ok"; ++}; ++ ++&usb3_1 { ++ status = "ok"; ++}; ++ ++&cryptobam { ++ status = "ok"; ++}; ++ ++&crypto { ++ status = "ok"; ++}; ++ ++&i2c_0 { ++ status = "disabled"; ++}; ++ ++&i2c_1 { ++ status = "disabled"; ++}; ++ ++&qpic_bam { ++ status = "ok"; ++}; ++ ++&nand { ++ pinctrl-0 = <&qpic_pins>; ++ pinctrl-names = "default"; ++ status = "ok"; ++}; ++ ++&qpic_lcd { ++ status = "disabled"; ++}; ++ ++&qpic_lcd_panel { ++ status = "disabled"; ++}; ++ ++&ledc { ++ status = "disabled"; ++}; ++ ++&pcie0 { ++ status = "ok"; ++}; ++ ++&pcie1 { ++ status = "disabled"; ++}; ++ ++&glink_rpm { ++ status = "disabled"; ++}; ++ ++&apc_cpr { ++ /* Same CPR configuration as OAK */ ++ compatible = "qcom,cpr4-ipq817x-apss-regulator"; ++ ++ thread@0 { ++ apc_vreg: regulator { ++ regulator-min-microvolt = <1>; ++ regulator-max-microvolt = <2>; ++ qcom,cpr-fuse-corners = <2>; ++ qcom,cpr-corners = <3>; ++ qcom,cpr-speed-bin-corners = <3>; ++ qcom,cpr-corner-fmax-map = <1 3>; ++ ++ qcom,cpr-voltage-ceiling = ++ <840000 904000 944000>; ++ qcom,cpr-voltage-floor = ++ <592000 648000 712000>; ++ qcom,corner-frequencies = ++ <1017600000 1382400000 1382400000>; ++ ++ qcom,cpr-open-loop-voltage-fuse-adjustment-0 = ++ /* Speed bin 0; CPR rev 0..7 */ ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>; ++ ++ qcom,cpr-open-loop-voltage-fuse-adjustment-1 = ++ /* Speed bin 0; CPR rev 0..7 */ ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 20000 26000>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>; ++ ++ qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0 = ++ /* Speed bin 0; CPR rev 0..7 */ ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>; ++ ++ qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1 = ++ /* Speed bin 0; CPR rev 0..7 */ ++ < 0 0>, ++ < 0 7000>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>, ++ < 0 0>; ++ ++ qcom,cpr-floor-to-ceiling-max-range = ++ < 40000 40000 40000>, ++ < 40000 40000 40000>, ++ < 40000 40000 40000>, ++ < 40000 40000 40000>, ++ < 40000 40000 40000>, ++ < 40000 40000 40000>, ++ < 40000 40000 40000>, ++ < 40000 40000 40000>; ++ }; ++ }; ++}; ++ ++&npu_cpr { ++ status = "disabled"; ++}; ++ ++&nss0 { ++ npu-supply = <&dummy_reg>; ++ mx-supply = <&dummy_reg>; ++}; ++ ++&wifi0 { ++ qcom,board_id = <0x92>; ++}; ++ ++&wifi1 { ++ qcom,board_id = <0x292>; ++}; +diff --git a/target/linux/ipq807x/image/ipq807x.mk b/target/linux/ipq807x/image/ipq807x.mk +index 9a8cbd8581..d0c02cd803 100644 +--- a/target/linux/ipq807x/image/ipq807x.mk ++++ b/target/linux/ipq807x/image/ipq807x.mk +@@ -39,3 +39,13 @@ define Device/cig_wf194 + DEVICE_PACKAGES := ath11k-wifi-cig-wf194c aq-fw-download uboot-envtools + endef + TARGET_DEVICES += cig_wf194 ++ ++define Device/edgecore_eap102 ++ DEVICE_TITLE := Edgecore EAP102 ++ DEVICE_DTS := qcom-ipq807x-eap102 ++ DEVICE_DTS_DIR := $(DTS_DIR)/qcom ++ DEVICE_DTS_CONFIG=config@ac02 ++ SUPPORTED_DEVICES := edgecore,eap102 ++ DEVICE_PACKAGES := ath11k-wifi-edgecore-eap102 kmod-usb3 kmod-usb2 ++endef ++TARGET_DEVICES += edgecore_eap102 +-- +2.25.1 + diff --git a/profiles/eap102.yml b/profiles/eap102.yml new file mode 100644 index 000000000..c0882d66c --- /dev/null +++ b/profiles/eap102.yml @@ -0,0 +1,10 @@ +--- +profile: edgecore_eap102 +target: ipq807x +subtarget: ipq807x +description: Build image for the Edgecore EAP102 +feeds: + - name: ipq807x + path: ../../feeds/ipq807x + +