--- a/drivers/net/wireless/ath/ath11k/core.c +++ b/drivers/net/wireless/ath/ath11k/core.c @@ -1091,22 +1091,22 @@ int ath11k_core_pre_init(struct ath11k_b return ret; } - switch (ab->hw_rev) { - case ATH11K_HW_IPQ8074: - case ATH11K_HW_IPQ6018: - ab->regs = &ipa8074_regs; - break; - case ATH11K_HW_QCA6290: - case ATH11K_HW_QCA6390: - break; + switch (ab->hw_rev) { + case ATH11K_HW_IPQ8074: + case ATH11K_HW_IPQ6018: + ab->srng_regs = &ipq8074_srng_regs; + break; + case ATH11K_HW_QCA6290: + case ATH11K_HW_QCA6390: + break; case ATH11K_HW_QCN90XX: - ab->regs = &qcn9000_regs; + ab->srng_regs = &qcn9000_srng_regs; break; - default: - ath11k_err(ab, "unsupported core hardware revision %d\n", - ab->hw_rev); - return -ENOTSUPP; - } + default: + ath11k_err(ab, "unsupported core hardware revision %d\n", + ab->hw_rev); + return -ENOTSUPP; + } ret = ath11k_ce_attr_attach(ab); --- a/drivers/net/wireless/ath/ath11k/core.h +++ b/drivers/net/wireless/ath/ath11k/core.h @@ -832,6 +832,7 @@ struct ath11k_base { const struct ath11k_hw_regs *regs; bool is_poll; struct ath11k_poll poll; + const struct hal_srng_regs *srng_regs; /* must be last */ u8 drv_priv[0] __aligned(sizeof(void *)); --- a/drivers/net/wireless/ath/ath11k/hal.c +++ b/drivers/net/wireless/ath/ath11k/hal.c @@ -189,6 +189,338 @@ static struct hal_srng_config hw_srng_co }, }; +const struct hal_srng_reo_configs reo_config = { + .reo1_ring_msi1_base_lsb_offset = + (HAL_REO1_RING_MSI1_BASE_LSB - HAL_REO1_RING_BASE_LSB), + .reo1_ring_msi1_base_msb_offset = + (HAL_REO1_RING_MSI1_BASE_MSB - HAL_REO1_RING_BASE_LSB), + .reo1_ring_msi1_data_offset = + (HAL_REO1_RING_MSI1_DATA - HAL_REO1_RING_BASE_LSB), + .reo1_ring_base_msb_offset = + (HAL_REO1_RING_BASE_MSB - HAL_REO1_RING_BASE_LSB), + .reo1_ring_id_offset = + (HAL_REO1_RING_ID - HAL_REO1_RING_BASE_LSB), + .reo1_ring_producer_int_setup_offset = + (HAL_REO1_RING_PRODUCER_INT_SETUP - HAL_REO1_RING_BASE_LSB), + .reo1_ring_hp_addr_lsb_offset = + (HAL_REO1_RING_HP_ADDR_LSB - HAL_REO1_RING_BASE_LSB), + .reo1_ring_hp_addr_msb_offset = + (HAL_REO1_RING_HP_ADDR_MSB - HAL_REO1_RING_BASE_LSB), + .reo1_ring_misc_offset = + (HAL_REO1_RING_MISC - HAL_REO1_RING_BASE_LSB), +}; + +static const struct hal_srng_reg_grps ipq8074_srng_reg_grps[HAL_MAX_RING_TYPES] = { + { /* REO_DST */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP, + }, + .reg_size = { + HAL_REO2_RING_BASE_LSB - HAL_REO1_RING_BASE_LSB, + HAL_REO2_RING_HP - HAL_REO1_RING_HP, + }, + }, + { /* REO_EXCEPTION */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP, + }, + }, + { /* REO_REINJECT */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP, + }, + }, + { /* REO_CMD */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP, + }, + }, + { /* REO_STATUS */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + + HAL_REO_STATUS_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP, + }, + }, + { /* TCL_DATA */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_IPQ8074_TCL1_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP, + }, + .reg_size = { + HAL_IPQ8074_TCL2_RING_BASE_LSB - HAL_IPQ8074_TCL1_RING_BASE_LSB, + HAL_TCL2_RING_HP - HAL_TCL1_RING_HP, + }, + }, + { /* TCL_CMD */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_IPQ8074_TCL_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP, + }, + }, + { /* TCL_STATUS */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_TCL_REG + + HAL_IPQ8074_TCL_STATUS_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP, + }, + }, + { /* CE_SRC */ + .reg_start = { + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_SRC_REG + + HAL_CE_DST_RING_BASE_LSB), + HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP, + }, + .reg_size = { + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE1_SRC_REG - + HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_SRC_REG), + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE1_SRC_REG - + HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_SRC_REG), + }, + }, + { /* CE_DST */ + .reg_start = { + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_DST_REG + + HAL_CE_DST_RING_BASE_LSB), + HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_HP, + }, + .reg_size = { + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE1_DST_REG - + HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_DST_REG), + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE1_DST_REG - + HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_DST_REG), + }, + }, + { /* CE_DST_STATUS */ + .reg_start = { + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_DST_REG + + HAL_CE_DST_STATUS_RING_BASE_LSB), + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_DST_REG + + HAL_CE_DST_STATUS_RING_HP), + }, + .reg_size = { + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE1_DST_REG - + HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_DST_REG), + (HAL_IPQ8074_SEQ_WCSS_UMAC_CE1_DST_REG - + HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_DST_REG), + }, + }, + { /* WBM_IDLE_LINK */ + .reg_start = { + (HAL_SEQ_WCSS_UMAC_WBM_REG + + HAL_IPQ8074_WBM_IDLE_LINK_RING_BASE_LSB), + (HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP), + }, + }, + { /* SW2WBM_RELEASE */ + .reg_start = { + (HAL_SEQ_WCSS_UMAC_WBM_REG + + HAL_IPQ8074_WBM_RELEASE_RING_BASE_LSB), + (HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP), + }, + }, + { /* WBM2SW_RELEASE */ + .reg_start = { + (HAL_SEQ_WCSS_UMAC_WBM_REG + + HAL_IPQ8074_WBM0_RELEASE_RING_BASE_LSB), + (HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP), + }, + .reg_size = { + (HAL_IPQ8074_WBM1_RELEASE_RING_BASE_LSB - + HAL_IPQ8074_WBM0_RELEASE_RING_BASE_LSB), + (HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP), + }, + }, +}; + +const struct hal_srng_regs ipq8074_srng_regs = { + .srng_reg_grps = ipq8074_srng_reg_grps, + .srng_reo_config = &reo_config, + .tcl1_ring_msi1_base_lsb_offset = + (HAL_IPQ8074_TCL1_RING_MSI1_BASE_LSB - HAL_IPQ8074_TCL1_RING_BASE_LSB), + .tcl1_ring_msi1_base_msb_offset = + (HAL_IPQ8074_TCL1_RING_MSI1_BASE_MSB - HAL_IPQ8074_TCL1_RING_BASE_LSB), + .tcl1_ring_msi1_data_offset = + (HAL_IPQ8074_TCL1_RING_MSI1_DATA - HAL_IPQ8074_TCL1_RING_BASE_LSB), + .tcl1_ring_base_msb_offset = + (HAL_IPQ8074_TCL1_RING_BASE_MSB - HAL_IPQ8074_TCL1_RING_BASE_LSB), + .tcl1_ring_id_offset = + (HAL_IPQ8074_TCL1_RING_ID - HAL_IPQ8074_TCL1_RING_BASE_LSB), + .tcl1_ring_consr_int_setup_IX0_offset = + (HAL_IPQ8074_TCL1_RING_CONSUMER_INT_SETUP_IX0 - + HAL_IPQ8074_TCL1_RING_BASE_LSB), + .tcl1_ring_consr_int_setup_IX1_offset = + (HAL_IPQ8074_TCL1_RING_CONSUMER_INT_SETUP_IX1 - + HAL_IPQ8074_TCL1_RING_BASE_LSB), + .tcl1_ring_tp_addr_lsb_offset = + (HAL_IPQ8074_TCL1_RING_TP_ADDR_LSB - HAL_IPQ8074_TCL1_RING_BASE_LSB), + .tcl1_ring_tp_addr_msb_offset = + (HAL_IPQ8074_TCL1_RING_TP_ADDR_MSB - HAL_IPQ8074_TCL1_RING_BASE_LSB), + .tcl1_ring_misc_offset = + (HAL_IPQ8074_TCL1_RING_MISC - HAL_IPQ8074_TCL1_RING_BASE_LSB), + .wbm_idle_link_ring_misc = 0x00000870, +}; + +static const struct hal_srng_reg_grps qcn9000_srng_reg_grps[HAL_MAX_RING_TYPES] = { + { /* REO_DST */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP, + }, + .reg_size = { + HAL_REO2_RING_BASE_LSB - HAL_REO1_RING_BASE_LSB, + HAL_REO2_RING_HP - HAL_REO1_RING_HP, + }, + }, + { /* REO_EXCEPTION */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP, + }, + }, + { /* REO_REINJECT */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP, + }, + }, + { /* REO_CMD */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP, + }, + }, + { /* REO_STATUS */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_REO_REG + + HAL_REO_STATUS_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP, + }, + }, + { /* TCL_DATA */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_QCN9000_TCL1_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP, + }, + .reg_size = { + HAL_QCN9000_TCL2_RING_BASE_LSB - HAL_QCN9000_TCL1_RING_BASE_LSB, + HAL_TCL2_RING_HP - HAL_TCL1_RING_HP, + }, + }, + { /* TCL_CMD */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_QCN9000_TCL_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP, + }, + }, + { /* TCL_STATUS */ + .reg_start = { + HAL_SEQ_WCSS_UMAC_TCL_REG + + HAL_QCN9000_TCL_STATUS_RING_BASE_LSB, + HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP, + }, + }, + { /* CE_SRC */ + .reg_start = { + (HAL_QCN9000_SEQ_WCSS_UMAC_CE0_SRC_REG + + HAL_CE_DST_RING_BASE_LSB), + HAL_QCN9000_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP, + }, + .reg_size = { + (HAL_QCN9000_SEQ_WCSS_UMAC_CE1_SRC_REG - + HAL_QCN9000_SEQ_WCSS_UMAC_CE0_SRC_REG), + (HAL_QCN9000_SEQ_WCSS_UMAC_CE1_SRC_REG - + HAL_QCN9000_SEQ_WCSS_UMAC_CE0_SRC_REG), + }, + }, + { /* CE_DST */ + .reg_start = { + (HAL_QCN9000_SEQ_WCSS_UMAC_CE0_DST_REG + + HAL_CE_DST_RING_BASE_LSB), + HAL_QCN9000_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_HP, + }, + .reg_size = { + (HAL_QCN9000_SEQ_WCSS_UMAC_CE1_DST_REG - + HAL_QCN9000_SEQ_WCSS_UMAC_CE0_DST_REG), + (HAL_QCN9000_SEQ_WCSS_UMAC_CE1_DST_REG - + HAL_QCN9000_SEQ_WCSS_UMAC_CE0_DST_REG), + }, + }, + { /* CE_DST_STATUS */ + .reg_start = { + (HAL_QCN9000_SEQ_WCSS_UMAC_CE0_DST_REG + + HAL_CE_DST_STATUS_RING_BASE_LSB), + (HAL_QCN9000_SEQ_WCSS_UMAC_CE0_DST_REG + + HAL_CE_DST_STATUS_RING_HP), + }, + .reg_size = { + (HAL_QCN9000_SEQ_WCSS_UMAC_CE1_DST_REG - + HAL_QCN9000_SEQ_WCSS_UMAC_CE0_DST_REG), + (HAL_QCN9000_SEQ_WCSS_UMAC_CE1_DST_REG - + HAL_QCN9000_SEQ_WCSS_UMAC_CE0_DST_REG), + }, + }, + { /* WBM_IDLE_LINK */ + .reg_start = { + (HAL_SEQ_WCSS_UMAC_WBM_REG + + HAL_QCN9000_WBM_IDLE_LINK_RING_BASE_LSB), + (HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP), + }, + }, + { /* SW2WBM_RELEASE */ + .reg_start = { + (HAL_SEQ_WCSS_UMAC_WBM_REG + + HAL_QCN9000_WBM_RELEASE_RING_BASE_LSB), + (HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP), + }, + }, + { /* WBM2SW_RELEASE */ + .reg_start = { + (HAL_SEQ_WCSS_UMAC_WBM_REG + + HAL_QCN9000_WBM0_RELEASE_RING_BASE_LSB), + (HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP), + }, + .reg_size = { + (HAL_QCN9000_WBM1_RELEASE_RING_BASE_LSB - + HAL_QCN9000_WBM0_RELEASE_RING_BASE_LSB), + (HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP), + }, + }, +}; + +const struct hal_srng_regs qcn9000_srng_regs = { + .srng_reg_grps = qcn9000_srng_reg_grps, + .srng_reo_config = &reo_config, + .tcl1_ring_msi1_base_lsb_offset = + (HAL_QCN9000_TCL1_RING_MSI1_BASE_LSB - HAL_QCN9000_TCL1_RING_BASE_LSB), + .tcl1_ring_msi1_base_msb_offset = + (HAL_QCN9000_TCL1_RING_MSI1_BASE_MSB - HAL_QCN9000_TCL1_RING_BASE_LSB), + .tcl1_ring_msi1_data_offset = + (HAL_QCN9000_TCL1_RING_MSI1_DATA - HAL_QCN9000_TCL1_RING_BASE_LSB), + .tcl1_ring_base_msb_offset = + (HAL_QCN9000_TCL1_RING_BASE_MSB - HAL_QCN9000_TCL1_RING_BASE_LSB), + .tcl1_ring_id_offset = + (HAL_QCN9000_TCL1_RING_ID - HAL_QCN9000_TCL1_RING_BASE_LSB), + .tcl1_ring_consr_int_setup_IX0_offset = + (HAL_QCN9000_TCL1_RING_CONSUMER_INT_SETUP_IX0 - + HAL_QCN9000_TCL1_RING_BASE_LSB), + .tcl1_ring_consr_int_setup_IX1_offset = + (HAL_QCN9000_TCL1_RING_CONSUMER_INT_SETUP_IX1 - + HAL_QCN9000_TCL1_RING_BASE_LSB), + .tcl1_ring_tp_addr_lsb_offset = + (HAL_QCN9000_TCL1_RING_TP_ADDR_LSB - HAL_QCN9000_TCL1_RING_BASE_LSB), + .tcl1_ring_tp_addr_msb_offset = + (HAL_QCN9000_TCL1_RING_TP_ADDR_MSB - HAL_QCN9000_TCL1_RING_BASE_LSB), + .tcl1_ring_misc_offset = + (HAL_QCN9000_TCL1_RING_MISC - HAL_QCN9000_TCL1_RING_BASE_LSB), + .wbm_idle_link_ring_misc = 0x00000884, +}; + + static int ath11k_hal_alloc_cont_rdp(struct ath11k_base *ab) { struct ath11k_hal *hal = &ab->hal; @@ -248,7 +580,7 @@ static void ath11k_hal_free_cont_wrp(str static void ath11k_hal_ce_dst_setup(struct ath11k_base *ab, struct hal_srng *srng, int ring_num) { - struct hal_srng_config *srng_config = &hw_srng_config[HAL_CE_DST]; + struct hal_srng_config *srng_config = &ab->hal.srng_config[HAL_CE_DST]; u32 addr; u32 val; @@ -267,6 +599,7 @@ static void ath11k_hal_srng_dst_hw_init( struct hal_srng *srng) { struct ath11k_hal *hal = &ab->hal; + const struct hal_srng_reo_configs *reo_config = ab->srng_regs->srng_reo_config; u32 val; u64 hp_addr; u32 reg_base; @@ -275,7 +608,7 @@ static void ath11k_hal_srng_dst_hw_init( if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { ath11k_hif_write32(ab, reg_base + - HAL_REO1_RING_MSI1_BASE_LSB_OFFSET, + reo_config->reo1_ring_msi1_base_lsb_offset, (u32)srng->msi_addr); val = FIELD_PREP(HAL_REO1_RING_MSI1_BASE_MSB_ADDR, @@ -283,10 +616,10 @@ static void ath11k_hal_srng_dst_hw_init( HAL_ADDR_MSB_REG_SHIFT)) | HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE; ath11k_hif_write32(ab, reg_base + - HAL_REO1_RING_MSI1_BASE_MSB_OFFSET, val); + reo_config->reo1_ring_msi1_base_msb_offset, val); ath11k_hif_write32(ab, - reg_base + HAL_REO1_RING_MSI1_DATA_OFFSET, + reg_base + reo_config->reo1_ring_msi1_data_offset, srng->msi_data); } @@ -297,11 +630,11 @@ static void ath11k_hal_srng_dst_hw_init( HAL_ADDR_MSB_REG_SHIFT)) | FIELD_PREP(HAL_REO1_RING_BASE_MSB_RING_SIZE, (srng->entry_size * srng->num_entries)); - ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_BASE_MSB_OFFSET, val); + ath11k_hif_write32(ab, reg_base + reo_config->reo1_ring_base_msb_offset, val); val = FIELD_PREP(HAL_REO1_RING_ID_RING_ID, srng->ring_id) | FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size); - ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_ID_OFFSET, val); + ath11k_hif_write32(ab, reg_base + reo_config->reo1_ring_id_offset, val); /* interrupt setup */ val = FIELD_PREP(HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD, @@ -312,15 +645,15 @@ static void ath11k_hal_srng_dst_hw_init( srng->entry_size)); ath11k_hif_write32(ab, - reg_base + HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET, + reg_base + reo_config->reo1_ring_producer_int_setup_offset, val); hp_addr = hal->rdp.paddr + ((unsigned long)srng->u.dst_ring.hp_addr - (unsigned long)hal->rdp.vaddr); - ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_LSB_OFFSET, + ath11k_hif_write32(ab, reg_base + reo_config->reo1_ring_hp_addr_lsb_offset, hp_addr & HAL_ADDR_LSB_REG_MASK); - ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_HP_ADDR_MSB_OFFSET, + ath11k_hif_write32(ab, reg_base + reo_config->reo1_ring_hp_addr_msb_offset, hp_addr >> HAL_ADDR_MSB_REG_SHIFT); /* Initialize head and tail pointers to indicate ring is empty */ @@ -339,13 +672,14 @@ static void ath11k_hal_srng_dst_hw_init( val |= HAL_REO1_RING_MISC_MSI_SWAP; val |= HAL_REO1_RING_MISC_SRNG_ENABLE; - ath11k_hif_write32(ab, reg_base + HAL_REO1_RING_MISC_OFFSET, val); + ath11k_hif_write32(ab, reg_base + reo_config->reo1_ring_misc_offset, val); } static void ath11k_hal_srng_src_hw_init(struct ath11k_base *ab, struct hal_srng *srng) { struct ath11k_hal *hal = &ab->hal; + const struct hal_srng_regs *srng_regs = ab->srng_regs; u32 val; u64 tp_addr; u32 reg_base; @@ -354,7 +688,7 @@ static void ath11k_hal_srng_src_hw_init( if (srng->flags & HAL_SRNG_FLAGS_MSI_INTR) { ath11k_hif_write32(ab, reg_base + - HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET, + srng_regs->tcl1_ring_msi1_base_lsb_offset, (u32)srng->msi_addr); val = FIELD_PREP(HAL_TCL1_RING_MSI1_BASE_MSB_ADDR, @@ -362,11 +696,11 @@ static void ath11k_hal_srng_src_hw_init( HAL_ADDR_MSB_REG_SHIFT)) | HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE; ath11k_hif_write32(ab, reg_base + - HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET, + srng_regs->tcl1_ring_msi1_base_msb_offset, val); ath11k_hif_write32(ab, reg_base + - HAL_TCL1_RING_MSI1_DATA_OFFSET, + srng_regs->tcl1_ring_msi1_data_offset, srng->msi_data); } @@ -377,10 +711,10 @@ static void ath11k_hal_srng_src_hw_init( HAL_ADDR_MSB_REG_SHIFT)) | FIELD_PREP(HAL_TCL1_RING_BASE_MSB_RING_SIZE, (srng->entry_size * srng->num_entries)); - ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_BASE_MSB_OFFSET, val); + ath11k_hif_write32(ab, reg_base + srng_regs->tcl1_ring_base_msb_offset, val); val = FIELD_PREP(HAL_REO1_RING_ID_ENTRY_SIZE, srng->entry_size); - ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_ID_OFFSET, val); + ath11k_hif_write32(ab, reg_base + srng_regs->tcl1_ring_id_offset, val); /* interrupt setup */ /* NOTE: IPQ8074 v2 requires the interrupt timer threshold in the @@ -394,7 +728,7 @@ static void ath11k_hal_srng_src_hw_init( srng->entry_size)); ath11k_hif_write32(ab, - reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET, + reg_base + srng_regs->tcl1_ring_consr_int_setup_IX0_offset, val); val = 0; @@ -403,7 +737,7 @@ static void ath11k_hal_srng_src_hw_init( srng->u.src_ring.low_threshold); } ath11k_hif_write32(ab, - reg_base + HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET, + reg_base + srng_regs->tcl1_ring_consr_int_setup_IX1_offset, val); if (srng->ring_id != HAL_SRNG_RING_ID_WBM_IDLE_LINK) { @@ -411,10 +745,10 @@ static void ath11k_hal_srng_src_hw_init( ((unsigned long)srng->u.src_ring.tp_addr - (unsigned long)hal->rdp.vaddr); ath11k_hif_write32(ab, - reg_base + HAL_TCL1_RING_TP_ADDR_LSB_OFFSET, + reg_base + srng_regs->tcl1_ring_tp_addr_lsb_offset, tp_addr & HAL_ADDR_LSB_REG_MASK); ath11k_hif_write32(ab, - reg_base + HAL_TCL1_RING_TP_ADDR_MSB_OFFSET, + reg_base + srng_regs->tcl1_ring_tp_addr_msb_offset, tp_addr >> HAL_ADDR_MSB_REG_SHIFT); } @@ -438,7 +772,7 @@ static void ath11k_hal_srng_src_hw_init( val |= HAL_TCL1_RING_MISC_SRNG_ENABLE; - ath11k_hif_write32(ab, reg_base + HAL_TCL1_RING_MISC_OFFSET, val); + ath11k_hif_write32(ab, reg_base + srng_regs->tcl1_ring_misc_offset, val); } static void ath11k_hal_srng_hw_init(struct ath11k_base *ab, @@ -454,7 +788,7 @@ static int ath11k_hal_srng_get_ring_id(s enum hal_ring_type type, int ring_num, int mac_id) { - struct hal_srng_config *srng_config = &hw_srng_config[type]; + struct hal_srng_config *srng_config = &ab->hal.srng_config[type]; int ring_id; if (ring_num >= srng_config->max_rings) { @@ -899,7 +1233,7 @@ void ath11k_hal_setup_link_idle_list(str /* Enable the SRNG */ ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_WBM_REG + - HAL_WBM_IDLE_LINK_RING_MISC_ADDR, 0x40); + ab->srng_regs->wbm_idle_link_ring_misc, 0x40); } int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, @@ -907,7 +1241,7 @@ int ath11k_hal_srng_setup(struct ath11k_ struct hal_srng_params *params) { struct ath11k_hal *hal = &ab->hal; - struct hal_srng_config *srng_config = &hw_srng_config[type]; + struct hal_srng_config *srng_config = &ab->hal.srng_config[type]; struct hal_srng *srng; int ring_id; u32 lmac_idx; @@ -1013,100 +1347,16 @@ int ath11k_hal_srng_setup(struct ath11k_ static void ath11k_hal_srng_init_config(struct ath11k_base *ab) { struct ath11k_hal *hal = &ab->hal; + const struct hal_srng_reg_grps *srng_reg_grps; + struct hal_srng_config *srng_config; + u16 i; - hal->srng_config[HAL_REO_DST].reg_start[0] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_BASE_LSB; - hal->srng_config[HAL_REO_DST].reg_start[1] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_RING_HP; - hal->srng_config[HAL_REO_DST].reg_size[0] = - HAL_REO2_RING_BASE_LSB - HAL_REO1_RING_BASE_LSB; - hal->srng_config[HAL_REO_DST].reg_size[1] = - HAL_REO2_RING_HP - HAL_REO1_RING_HP; - - hal->srng_config[HAL_REO_EXCEPTION].reg_start[0] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_BASE_LSB; - hal->srng_config[HAL_REO_EXCEPTION].reg_start[1] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_TCL_RING_HP; - - hal->srng_config[HAL_REO_REINJECT].reg_start[0] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_BASE_LSB; - hal->srng_config[HAL_REO_REINJECT].reg_start[1] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_SW2REO_RING_HP; - - hal->srng_config[HAL_REO_CMD].reg_start[0] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_RING_BASE_LSB; - hal->srng_config[HAL_REO_CMD].reg_start[1] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_CMD_HP; - - hal->srng_config[HAL_REO_STATUS].reg_start[0] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_RING_BASE_LSB; - hal->srng_config[HAL_REO_STATUS].reg_start[1] = - HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO_STATUS_HP; - - hal->srng_config[HAL_TCL_DATA].reg_start[0] = - HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_BASE_LSB; - hal->srng_config[HAL_TCL_DATA].reg_start[1] = - HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_HP; - hal->srng_config[HAL_TCL_DATA].reg_size[0] = - HAL_TCL2_RING_BASE_LSB - HAL_TCL1_RING_BASE_LSB; - hal->srng_config[HAL_TCL_DATA].reg_size[1] = - HAL_TCL2_RING_HP - HAL_TCL1_RING_HP; - - hal->srng_config[HAL_TCL_CMD].reg_start[0] = - HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_BASE_LSB; - hal->srng_config[HAL_TCL_CMD].reg_start[1] = - HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_RING_HP; - - hal->srng_config[HAL_TCL_STATUS].reg_start[0] = - HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_BASE_LSB; - hal->srng_config[HAL_TCL_STATUS].reg_start[1] = - HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL_STATUS_RING_HP; - - hal->srng_config[HAL_CE_SRC].reg_start[0] = - HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_BASE_LSB; - hal->srng_config[HAL_CE_SRC].reg_start[1] = - HAL_SEQ_WCSS_UMAC_CE0_SRC_REG + HAL_CE_DST_RING_HP; - hal->srng_config[HAL_CE_SRC].reg_size[0] = - HAL_SEQ_WCSS_UMAC_CE1_SRC_REG - HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; - hal->srng_config[HAL_CE_SRC].reg_size[1] = - HAL_SEQ_WCSS_UMAC_CE1_SRC_REG - HAL_SEQ_WCSS_UMAC_CE0_SRC_REG; - - hal->srng_config[HAL_CE_DST].reg_start[0] = - HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_BASE_LSB; - hal->srng_config[HAL_CE_DST].reg_start[1] = - HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_RING_HP; - hal->srng_config[HAL_CE_DST].reg_size[0] = - HAL_SEQ_WCSS_UMAC_CE1_DST_REG - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; - hal->srng_config[HAL_CE_DST].reg_size[1] = - HAL_SEQ_WCSS_UMAC_CE1_DST_REG - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; - - hal->srng_config[HAL_CE_DST_STATUS].reg_start[0] = - HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_STATUS_RING_BASE_LSB; - hal->srng_config[HAL_CE_DST_STATUS].reg_start[1] = - HAL_SEQ_WCSS_UMAC_CE0_DST_REG + HAL_CE_DST_STATUS_RING_HP; - hal->srng_config[HAL_CE_DST_STATUS].reg_size[0] = - HAL_SEQ_WCSS_UMAC_CE1_DST_REG - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; - hal->srng_config[HAL_CE_DST_STATUS].reg_size[1] = - HAL_SEQ_WCSS_UMAC_CE1_DST_REG - HAL_SEQ_WCSS_UMAC_CE0_DST_REG; - - hal->srng_config[HAL_WBM_IDLE_LINK].reg_start[0] = - HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_BASE_LSB; - hal->srng_config[HAL_WBM_IDLE_LINK].reg_start[1] = - HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_IDLE_LINK_RING_HP; - - hal->srng_config[HAL_SW2WBM_RELEASE].reg_start[0] = - HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_BASE_LSB; - hal->srng_config[HAL_SW2WBM_RELEASE].reg_start[1] = - HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM_RELEASE_RING_HP; - - hal->srng_config[HAL_WBM2SW_RELEASE].reg_start[0] = - HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_BASE_LSB; - hal->srng_config[HAL_WBM2SW_RELEASE].reg_start[1] = - HAL_SEQ_WCSS_UMAC_WBM_REG + HAL_WBM0_RELEASE_RING_HP; - hal->srng_config[HAL_WBM2SW_RELEASE].reg_size[0] = - HAL_WBM1_RELEASE_RING_BASE_LSB - HAL_WBM0_RELEASE_RING_BASE_LSB; - hal->srng_config[HAL_WBM2SW_RELEASE].reg_size[1] = - HAL_WBM1_RELEASE_RING_HP - HAL_WBM0_RELEASE_RING_HP; + for (i = 0; i < HAL_MAX_RING_TYPES; i++) { + srng_config = &hal->srng_config[i]; + srng_reg_grps = &ab->srng_regs->srng_reg_grps[i]; + srng_config->reg_start = srng_reg_grps->reg_start; + srng_config->reg_size = srng_reg_grps->reg_size; + } } int ath11k_hal_srng_init(struct ath11k_base *ab) @@ -1116,7 +1366,10 @@ int ath11k_hal_srng_init(struct ath11k_b memset(hal, 0, sizeof(*hal)); - hal->srng_config = hw_srng_config; + hal->srng_config = kmemdup(hw_srng_config, sizeof(hw_srng_config), GFP_KERNEL); + if (hal->srng_config == NULL) + return -ENOMEM; + ath11k_hal_srng_init_config(ab); ret = ath11k_hal_alloc_cont_rdp(ab); @@ -1141,6 +1394,9 @@ void ath11k_hal_srng_deinit(struct ath11 { ath11k_hal_free_cont_rdp(ab); ath11k_hal_free_cont_wrp(ab); + kfree(ab->hal.srng_config); + ab->hal.srng_config = NULL; + } void ath11k_hal_dump_srng_stats(struct ath11k_base *ab) --- a/drivers/net/wireless/ath/ath11k/hal.h +++ b/drivers/net/wireless/ath/ath11k/hal.h @@ -38,10 +38,19 @@ struct ath11k_base; #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 -#define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG ab->regs->hal_seq_wcss_umac_ce0_src_reg -#define HAL_SEQ_WCSS_UMAC_CE0_DST_REG ab->regs->hal_seq_wcss_umac_ce0_dst_reg -#define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG ab->regs->hal_seq_wcss_umac_ce1_src_reg -#define HAL_SEQ_WCSS_UMAC_CE1_DST_REG ab->regs->hal_seq_wcss_umac_ce1_dst_reg + +/* IPQ8074 umac ce registers */ +#define HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_SRC_REG 0x00a00000 +#define HAL_IPQ8074_SEQ_WCSS_UMAC_CE0_DST_REG 0x00a01000 +#define HAL_IPQ8074_SEQ_WCSS_UMAC_CE1_SRC_REG 0x00a02000 +#define HAL_IPQ8074_SEQ_WCSS_UMAC_CE1_DST_REG 0x00a03000 + +/* QCN9000 umac ce registers */ +#define HAL_QCN9000_SEQ_WCSS_UMAC_CE0_SRC_REG 0x01b80000 +#define HAL_QCN9000_SEQ_WCSS_UMAC_CE0_DST_REG 0x01b81000 +#define HAL_QCN9000_SEQ_WCSS_UMAC_CE1_SRC_REG 0x01b82000 +#define HAL_QCN9000_SEQ_WCSS_UMAC_CE1_DST_REG 0x01b83000 + #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000 @@ -49,40 +58,36 @@ struct ath11k_base; /* SW2TCL(x) R0 ring configuration address */ #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c -#define HAL_TCL1_RING_BASE_LSB ab->regs->hal_tcl1_ring_base_lsb -#define HAL_TCL1_RING_BASE_MSB ab->regs->hal_tcl1_ring_base_msb -#define HAL_TCL1_RING_ID ab->regs->hal_tcl1_ring_id -#define HAL_TCL1_RING_MISC ab->regs->hal_tcl1_ring_misc -#define HAL_TCL1_RING_TP_ADDR_LSB ab->regs->hal_tcl1_ring_tp_addr_lsb -#define HAL_TCL1_RING_TP_ADDR_MSB ab->regs->hal_tcl1_ring_tp_addr_msb -#define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0 ab->regs->hal_tcl1_ring_consumer_int_setup_ix0 -#define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1 ab->regs->hal_tcl1_ring_consumer_int_setup_ix1 -#define HAL_TCL1_RING_MSI1_BASE_LSB ab->regs->hal_tcl1_ring_msi1_base_lsb -#define HAL_TCL1_RING_MSI1_BASE_MSB ab->regs->hal_tcl1_ring_msi1_base_msb -#define HAL_TCL1_RING_MSI1_DATA ab->regs->hal_tcl1_ring_msi1_data -#define HAL_TCL2_RING_BASE_LSB ab->regs->hal_tcl2_ring_base_lsb -#define HAL_TCL_RING_BASE_LSB ab->regs->hal_tcl_ring_base_lsb - -#define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET \ - (HAL_TCL1_RING_MSI1_BASE_LSB - HAL_TCL1_RING_BASE_LSB) -#define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET \ - (HAL_TCL1_RING_MSI1_BASE_MSB - HAL_TCL1_RING_BASE_LSB) -#define HAL_TCL1_RING_MSI1_DATA_OFFSET \ - (HAL_TCL1_RING_MSI1_DATA - HAL_TCL1_RING_BASE_LSB) -#define HAL_TCL1_RING_BASE_MSB_OFFSET \ - (HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB) -#define HAL_TCL1_RING_ID_OFFSET \ - (HAL_TCL1_RING_ID - HAL_TCL1_RING_BASE_LSB) -#define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET \ - (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0 - HAL_TCL1_RING_BASE_LSB) -#define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET \ - (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1 - HAL_TCL1_RING_BASE_LSB) -#define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET \ - (HAL_TCL1_RING_TP_ADDR_LSB - HAL_TCL1_RING_BASE_LSB) -#define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET \ - (HAL_TCL1_RING_TP_ADDR_MSB - HAL_TCL1_RING_BASE_LSB) -#define HAL_TCL1_RING_MISC_OFFSET \ - (HAL_TCL1_RING_MISC - HAL_TCL1_RING_BASE_LSB) + +/* IPQ8074 SW2TCL(x) R0 ring configuration address */ +#define HAL_IPQ8074_TCL1_RING_BASE_LSB 0x00000510 +#define HAL_IPQ8074_TCL1_RING_BASE_MSB 0x00000514 +#define HAL_IPQ8074_TCL1_RING_ID 0x00000518 +#define HAL_IPQ8074_TCL1_RING_MISC 0x00000520 +#define HAL_IPQ8074_TCL1_RING_TP_ADDR_LSB 0x0000052c +#define HAL_IPQ8074_TCL1_RING_TP_ADDR_MSB 0x00000530 +#define HAL_IPQ8074_TCL1_RING_CONSUMER_INT_SETUP_IX0 0x00000540 +#define HAL_IPQ8074_TCL1_RING_CONSUMER_INT_SETUP_IX1 0x00000544 +#define HAL_IPQ8074_TCL1_RING_MSI1_BASE_LSB 0x00000558 +#define HAL_IPQ8074_TCL1_RING_MSI1_BASE_MSB 0x0000055c +#define HAL_IPQ8074_TCL1_RING_MSI1_DATA 0x00000560 +#define HAL_IPQ8074_TCL2_RING_BASE_LSB 0x00000568 +#define HAL_IPQ8074_TCL_RING_BASE_LSB 0x00000618 + +/* QCN9000 SW2TCL(x) R0 ring configuration address */ +#define HAL_QCN9000_TCL1_RING_BASE_LSB 0x000004f0 +#define HAL_QCN9000_TCL1_RING_BASE_MSB 0x000004f4 +#define HAL_QCN9000_TCL1_RING_ID 0x000004f8 +#define HAL_QCN9000_TCL1_RING_MISC 0x00000500 +#define HAL_QCN9000_TCL1_RING_TP_ADDR_LSB 0x0000050c +#define HAL_QCN9000_TCL1_RING_TP_ADDR_MSB 0x00000510 +#define HAL_QCN9000_TCL1_RING_CONSUMER_INT_SETUP_IX0 0x00000520 +#define HAL_QCN9000_TCL1_RING_CONSUMER_INT_SETUP_IX1 0x00000524 +#define HAL_QCN9000_TCL1_RING_MSI1_BASE_LSB 0x00000538 +#define HAL_QCN9000_TCL1_RING_MSI1_BASE_MSB 0x0000053c +#define HAL_QCN9000_TCL1_RING_MSI1_DATA 0x00000540 +#define HAL_QCN9000_TCL2_RING_BASE_LSB 0x00000548 +#define HAL_QCN9000_TCL_RING_BASE_LSB 0x000005f8 /* SW2TCL(x) R2 ring pointers (head/tail) address */ #define HAL_TCL1_RING_HP 0x00002000 @@ -94,7 +99,11 @@ struct ath11k_base; (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) /* TCL STATUS ring address */ -#define HAL_TCL_STATUS_RING_BASE_LSB ab->regs->hal_tcl_status_ring_base_lsb +/* IPQ8074 TCL STATUS ring address */ +#define HAL_IPQ8074_TCL_STATUS_RING_BASE_LSB 0x00000720 + +/* IPQ8074 TCL STATUS ring address */ +#define HAL_QCN9000_TCL_STATUS_RING_BASE_LSB 0x00000700 #define HAL_TCL_STATUS_RING_HP 0x00002030 /* REO2SW(x) R0 ring configuration address */ @@ -103,51 +112,35 @@ struct ath11k_base; #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 -#define HAL_REO1_RING_BASE_LSB ab->regs->hal_reo1_ring_base_lsb -#define HAL_REO1_RING_BASE_MSB ab->regs->hal_reo1_ring_base_msb -#define HAL_REO1_RING_ID ab->regs->hal_reo1_ring_id -#define HAL_REO1_RING_MISC ab->regs->hal_reo1_ring_misc -#define HAL_REO1_RING_HP_ADDR_LSB ab->regs->hal_reo1_ring_hp_addr_lsb -#define HAL_REO1_RING_HP_ADDR_MSB ab->regs->hal_reo1_ring_hp_addr_msb -#define HAL_REO1_RING_PRODUCER_INT_SETUP ab->regs->hal_reo1_ring_producer_int_setup -#define HAL_REO1_RING_MSI1_BASE_LSB ab->regs->hal_reo1_ring_msi1_base_lsb -#define HAL_REO1_RING_MSI1_BASE_MSB ab->regs->hal_reo1_ring_msi1_base_msb -#define HAL_REO1_RING_MSI1_DATA ab->regs->hal_reo1_ring_msi1_data -#define HAL_REO2_RING_BASE_LSB ab->regs->hal_reo2_ring_base_lsb -#define HAL_REO1_AGING_THRESH_IX_0 ab->regs->hal_reo1_aging_thresh_ix_0 -#define HAL_REO1_AGING_THRESH_IX_1 ab->regs->hal_reo1_aging_thresh_ix_1 -#define HAL_REO1_AGING_THRESH_IX_2 ab->regs->hal_reo1_aging_thresh_ix_2 -#define HAL_REO1_AGING_THRESH_IX_3 ab->regs->hal_reo1_aging_thresh_ix_3 - -#define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET \ - (HAL_REO1_RING_MSI1_BASE_LSB - HAL_REO1_RING_BASE_LSB) -#define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET \ - (HAL_REO1_RING_MSI1_BASE_MSB - HAL_REO1_RING_BASE_LSB) -#define HAL_REO1_RING_MSI1_DATA_OFFSET \ - (HAL_REO1_RING_MSI1_DATA - HAL_REO1_RING_BASE_LSB) -#define HAL_REO1_RING_BASE_MSB_OFFSET \ - (HAL_REO1_RING_BASE_MSB - HAL_REO1_RING_BASE_LSB) -#define HAL_REO1_RING_ID_OFFSET (HAL_REO1_RING_ID - HAL_REO1_RING_BASE_LSB) -#define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET \ - (HAL_REO1_RING_PRODUCER_INT_SETUP - HAL_REO1_RING_BASE_LSB) -#define HAL_REO1_RING_HP_ADDR_LSB_OFFSET \ - (HAL_REO1_RING_HP_ADDR_LSB - HAL_REO1_RING_BASE_LSB) -#define HAL_REO1_RING_HP_ADDR_MSB_OFFSET \ - (HAL_REO1_RING_HP_ADDR_MSB - HAL_REO1_RING_BASE_LSB) -#define HAL_REO1_RING_MISC_OFFSET (HAL_REO1_RING_MISC - HAL_REO1_RING_BASE_LSB) + +#define HAL_REO1_RING_BASE_LSB 0x0000029c +#define HAL_REO1_RING_BASE_MSB 0x000002a0 +#define HAL_REO1_RING_ID 0x000002a4 +#define HAL_REO1_RING_MISC 0x000002ac +#define HAL_REO1_RING_HP_ADDR_LSB 0x000002b0 +#define HAL_REO1_RING_HP_ADDR_MSB 0x000002b4 +#define HAL_REO1_RING_PRODUCER_INT_SETUP 0x000002c0 +#define HAL_REO1_RING_MSI1_BASE_LSB 0x000002e4 +#define HAL_REO1_RING_MSI1_BASE_MSB 0x000002e8 +#define HAL_REO1_RING_MSI1_DATA 0x000002ec +#define HAL_REO2_RING_BASE_LSB 0x000002f4 +#define HAL_REO1_AGING_THRESH_IX_0 0x00000564 +#define HAL_REO1_AGING_THRESH_IX_1 0x00000568 +#define HAL_REO1_AGING_THRESH_IX_2 0x0000056c +#define HAL_REO1_AGING_THRESH_IX_3 0x00000570 /* REO2SW(x) R2 ring pointers (head/tail) address */ -#define HAL_REO1_RING_HP ab->regs->hal_reo1_ring_hp -#define HAL_REO1_RING_TP ab->regs->hal_reo1_ring_tp -#define HAL_REO2_RING_HP ab->regs->hal_reo2_ring_hp +#define HAL_REO1_RING_HP 0x00003038 +#define HAL_REO1_RING_TP 0x0000303c +#define HAL_REO2_RING_HP 0x00003040 #define HAL_REO1_RING_TP_OFFSET (HAL_REO1_RING_TP - HAL_REO1_RING_HP) /* REO2TCL R0 ring configuration address */ -#define HAL_REO_TCL_RING_BASE_LSB ab->regs->hal_reo_tcl_ring_base_lsb +#define HAL_REO_TCL_RING_BASE_LSB 0x000003fc /* REO2TCL R2 ring pointer (head/tail) address */ -#define HAL_REO_TCL_RING_HP ab->regs->hal_reo_tcl_ring_hp +#define HAL_REO_TCL_RING_HP 0x00003058 /* REO CMD R0 address */ #define HAL_REO_CMD_RING_BASE_LSB 0x00000194 @@ -171,12 +164,16 @@ struct ath11k_base; #define HAL_CE_DST_STATUS_RING_HP 0x00000408 /* REO status address */ -#define HAL_REO_STATUS_RING_BASE_LSB ab->regs->hal_reo_status_ring_base_lsb -#define HAL_REO_STATUS_HP ab->regs->hal_reo_status_hp +#define HAL_REO_STATUS_RING_BASE_LSB 0x00000504 +#define HAL_REO_STATUS_HP 0x00003070 + +/* IPQ8074 WBM Idle R0 address */ +#define HAL_IPQ8074_WBM_IDLE_LINK_RING_BASE_LSB 0x00000860 +#define HAL_IPQ8074_WBM_IDLE_LINK_RING_MISC_ADDR 0x00000870 + +#define HAL_QCN9000_WBM_IDLE_LINK_RING_BASE_LSB 0x00000874 +#define HAL_QCN9000_WBM_IDLE_LINK_RING_MISC_ADDR 0x00000884 -/* WBM Idle R0 address */ -#define HAL_WBM_IDLE_LINK_RING_BASE_LSB ab->regs->hal_wbm_idle_link_ring_base_lsb -#define HAL_WBM_IDLE_LINK_RING_MISC_ADDR ab->regs->hal_wbm_idle_link_ring_misc #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058 @@ -190,15 +187,22 @@ struct ath11k_base; /* WBM Idle R2 address */ #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0 -/* SW2WBM R0 release address */ -#define HAL_WBM_RELEASE_RING_BASE_LSB ab->regs->hal_wbm_release_ring_base_lsb +/* IPQ8074 SW2WBM R0 release address */ +#define HAL_IPQ8074_WBM_RELEASE_RING_BASE_LSB 0x000001d8 + +/* QCN9000 SW2WBM R0 release address */ +#define HAL_QCN9000_WBM_RELEASE_RING_BASE_LSB 0x000001ec /* SW2WBM R2 release address */ #define HAL_WBM_RELEASE_RING_HP 0x00003018 -/* WBM2SW R0 release address */ -#define HAL_WBM0_RELEASE_RING_BASE_LSB ab->regs->hal_wbm0_release_ring_base_lsb -#define HAL_WBM1_RELEASE_RING_BASE_LSB ab->regs->hal_wbm1_release_ring_base_lsb +/* IPQ8074 WBM2SW R0 release address */ +#define HAL_IPQ8074_WBM0_RELEASE_RING_BASE_LSB 0x00000910 +#define HAL_IPQ8074_WBM1_RELEASE_RING_BASE_LSB 0x00000968 + +/* QCN9000 WBM2SW R0 release address */ +#define HAL_QCN9000_WBM0_RELEASE_RING_BASE_LSB 0x00000924 +#define HAL_QCN9000_WBM1_RELEASE_RING_BASE_LSB 0x0000097c /* WBM2SW R2 release address */ #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 @@ -380,7 +384,7 @@ enum hal_srng_ring_id { HAL_SRNG_NUM_LMAC_RINGS) enum hal_ring_type { - HAL_REO_DST, + HAL_REO_DST = 0, HAL_REO_EXCEPTION, HAL_REO_REINJECT, HAL_REO_CMD, @@ -609,13 +613,50 @@ struct hal_srng_config { int start_ring_id; u16 max_rings; u16 entry_size; - u32 reg_start[HAL_SRNG_NUM_REG_GRP]; - u16 reg_size[HAL_SRNG_NUM_REG_GRP]; + const u32 *reg_start; + const u16 *reg_size; u8 lmac_ring; enum hal_srng_dir ring_dir; u32 max_size; }; +/* HW SRNG reg groups */ +struct hal_srng_reg_grps { + u32 reg_start[HAL_SRNG_NUM_REG_GRP]; + u16 reg_size[HAL_SRNG_NUM_REG_GRP]; +}; + +struct hal_srng_reo_configs { + u32 reo1_ring_msi1_base_lsb_offset; + u32 reo1_ring_msi1_base_msb_offset; + u32 reo1_ring_msi1_data_offset; + u32 reo1_ring_base_msb_offset; + u32 reo1_ring_id_offset; + u32 reo1_ring_producer_int_setup_offset; + u32 reo1_ring_hp_addr_lsb_offset; + u32 reo1_ring_hp_addr_msb_offset; + u32 reo1_ring_misc_offset; +}; + +struct hal_srng_regs { + const struct hal_srng_reg_grps *srng_reg_grps; + const struct hal_srng_reo_configs *srng_reo_config; + u32 tcl1_ring_msi1_base_lsb_offset; + u32 tcl1_ring_msi1_base_msb_offset; + u32 tcl1_ring_msi1_data_offset; + u32 tcl1_ring_base_msb_offset; + u32 tcl1_ring_id_offset; + u32 tcl1_ring_consr_int_setup_IX0_offset; + u32 tcl1_ring_consr_int_setup_IX1_offset; + u32 tcl1_ring_tp_addr_lsb_offset; + u32 tcl1_ring_tp_addr_msb_offset; + u32 tcl1_ring_misc_offset; + u32 wbm_idle_link_ring_misc; +}; + +extern const struct hal_srng_regs ipq8074_srng_regs; +extern const struct hal_srng_regs qcn9000_srng_regs; + /** * enum hal_rx_buf_return_buf_manager * --- a/drivers/net/wireless/ath/ath11k/hw.c +++ b/drivers/net/wireless/ath/ath11k/hw.c @@ -9,140 +9,6 @@ #include "core.h" #include "debug.h" -const struct ath11k_hw_regs ipa8074_regs = { - /* SW2TCL(x) R0 ring configuration address */ - .hal_tcl1_ring_base_lsb = 0x00000510, - .hal_tcl1_ring_base_msb = 0x00000514, - .hal_tcl1_ring_id = 0x00000518, - .hal_tcl1_ring_misc= 0x00000520, - .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, - .hal_tcl1_ring_tp_addr_msb = 0x00000530, - .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, - .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, - .hal_tcl1_ring_msi1_base_lsb = 0x00000558, - .hal_tcl1_ring_msi1_base_msb = 0x0000055c, - .hal_tcl1_ring_msi1_data = 0x00000560, - .hal_tcl2_ring_base_lsb = 0x00000568, - .hal_tcl_ring_base_lsb = 0x00000618, - - /* TCL STATUS ring address */ - .hal_tcl_status_ring_base_lsb = 0x00000720, - - /* REO2SW(x) R0 ring configuration address */ - .hal_reo1_ring_base_lsb = 0x0000029c, - .hal_reo1_ring_base_msb = 0x000002a0, - .hal_reo1_ring_id = 0x000002a4, - .hal_reo1_ring_misc = 0x000002ac, - .hal_reo1_ring_hp_addr_lsb = 0x000002b0, - .hal_reo1_ring_hp_addr_msb = 0x000002b4, - .hal_reo1_ring_producer_int_setup = 0x000002c0, - .hal_reo1_ring_msi1_base_lsb = 0x000002e4, - .hal_reo1_ring_msi1_base_msb = 0x000002e8, - .hal_reo1_ring_msi1_data = 0x000002ec, - .hal_reo2_ring_base_lsb = 0x000002f4, - .hal_reo1_aging_thresh_ix_0 = 0x00000564, - .hal_reo1_aging_thresh_ix_1 = 0x00000568, - .hal_reo1_aging_thresh_ix_2 = 0x0000056c, - .hal_reo1_aging_thresh_ix_3 = 0x00000570, - - /* REO2SW(x) R2 ring pointers (head/tail) address */ - .hal_reo1_ring_hp = 0x00003038, - .hal_reo1_ring_tp = 0x0000303c, - .hal_reo2_ring_hp = 0x00003040, - - /* REO2TCL R0 ring configuration address */ - .hal_reo_tcl_ring_base_lsb = 0x000003fc, - .hal_reo_tcl_ring_hp = 0x00003058, - - /* REO status address */ - .hal_reo_status_ring_base_lsb = 0x00000504, - .hal_reo_status_hp = 0x00003070, - - /* WCSS relative address */ - .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, - .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, - .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, - .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, - - /* WBM Idle address */ - .hal_wbm_idle_link_ring_base_lsb = 0x00000860, - .hal_wbm_idle_link_ring_misc = 0x00000870, - - /* SW2WBM release address */ - .hal_wbm_release_ring_base_lsb = 0x000001d8, - - /* WBM2SW release address */ - .hal_wbm0_release_ring_base_lsb = 0x00000910, - .hal_wbm1_release_ring_base_lsb = 0x00000968, -}; - -const struct ath11k_hw_regs qcn9000_regs = { - /* SW2TCL(x) R0 ring configuration address */ - .hal_tcl1_ring_base_lsb = 0x000004f0, - .hal_tcl1_ring_base_msb = 0x000004f4, - .hal_tcl1_ring_id = 0x000004f8, - .hal_tcl1_ring_misc = 0x00000500, - .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, - .hal_tcl1_ring_tp_addr_msb = 0x00000510, - .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, - .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, - .hal_tcl1_ring_msi1_base_lsb = 0x00000538, - .hal_tcl1_ring_msi1_base_msb = 0x0000053c, - .hal_tcl1_ring_msi1_data = 0x00000540, - .hal_tcl2_ring_base_lsb = 0x00000548, - .hal_tcl_ring_base_lsb = 0x000005f8, - - /* TCL STATUS ring address */ - .hal_tcl_status_ring_base_lsb = 0x00000700, - - /* REO2SW(x) R0 ring configuration address */ - .hal_reo1_ring_base_lsb = 0x0000029c, - .hal_reo1_ring_base_msb = 0x000002a0, - .hal_reo1_ring_id = 0x000002a4, - .hal_reo1_ring_misc = 0x000002ac, - .hal_reo1_ring_hp_addr_lsb = 0x000002b0, - .hal_reo1_ring_hp_addr_msb = 0x000002b4, - .hal_reo1_ring_producer_int_setup = 0x000002c0, - .hal_reo1_ring_msi1_base_lsb = 0x000002e4, - .hal_reo1_ring_msi1_base_msb = 0x000002e8, - .hal_reo1_ring_msi1_data = 0x000002ec, - .hal_reo2_ring_base_lsb = 0x000002f4, - .hal_reo1_aging_thresh_ix_0 = 0x00000564, - .hal_reo1_aging_thresh_ix_1 = 0x00000568, - .hal_reo1_aging_thresh_ix_2 = 0x0000056c, - .hal_reo1_aging_thresh_ix_3 = 0x00000570, - - /* REO2SW(x) R2 ring pointers (head/tail) address */ - .hal_reo1_ring_hp = 0x00003038, - .hal_reo1_ring_tp = 0x0000303c, - .hal_reo2_ring_hp = 0x00003040, - - /* REO2TCL R0 ring configuration address */ - .hal_reo_tcl_ring_base_lsb = 0x000003fc, - .hal_reo_tcl_ring_hp = 0x00003058, - - /* REO status address */ - .hal_reo_status_ring_base_lsb = 0x00000504, - .hal_reo_status_hp = 0x00003070, - - /* WCSS relative address */ - .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, - .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, - .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, - .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, - - /* WBM Idle address */ - .hal_wbm_idle_link_ring_base_lsb = 0x00000874, - .hal_wbm_idle_link_ring_misc = 0x00000884, - - /* SW2WBM release address */ - .hal_wbm_release_ring_base_lsb = 0x000001ec, - - /* WBM2SW release address */ - .hal_wbm0_release_ring_base_lsb = 0x00000924, - .hal_wbm1_release_ring_base_lsb = 0x0000097c, -}; - /* Map from pdev index to hw mac index */ static u8 ath11k_qca8074_hw_mac_from_pdev_id(struct ath11k_base *ab, int pdev_idx)