From 02d197d190a9fa405e5fd9164bcfc5fb201d9295 Mon Sep 17 00:00:00 2001 From: John Crispin Date: Sat, 24 Oct 2020 12:26:51 +0200 Subject: [PATCH] ipq807x: add edgecore eap101 support Signed-off-by: John Crispin --- target/linux/ipq807x/Makefile | 1 + .../ipq807x/base-files/etc/board.d/01_leds | 1 + .../ipq807x/base-files/etc/board.d/02_network | 4 + .../etc/hotplug.d/firmware/10-ath11k-caldata | 1 + .../ipq807x/base-files/etc/init.d/bootcount | 11 + .../base-files/lib/upgrade/platform.sh | 5 + target/linux/ipq807x/image/ipq60xx.mk | 10 + target/linux/ipq807x/patches/106-eap101.patch | 975 ++++++++++++++++++ 8 files changed, 1008 insertions(+) create mode 100755 target/linux/ipq807x/base-files/etc/init.d/bootcount create mode 100644 target/linux/ipq807x/patches/106-eap101.patch diff --git a/target/linux/ipq807x/Makefile b/target/linux/ipq807x/Makefile index e132546f2c..d1d6e0e6fc 100644 --- a/target/linux/ipq807x/Makefile +++ b/target/linux/ipq807x/Makefile @@ -16,6 +16,7 @@ DEFAULT_PACKAGES += kmod-qca-nss-dp kmod-qca-ssdk swconfig \ kmod-qca-nss-drv \ kmod-usb-phy-ipq807x kmod-usb-dwc3-of-simple \ kmod-ath11k-ahb kmod-qrtr_mproc wpad \ + kmod-gpio-button-hotplug \ qca-thermald-10.4 qca-ssdk-shell $(eval $(call BuildTarget)) diff --git a/target/linux/ipq807x/base-files/etc/board.d/01_leds b/target/linux/ipq807x/base-files/etc/board.d/01_leds index 3ed1227a3d..12492bf3d1 100755 --- a/target/linux/ipq807x/base-files/etc/board.d/01_leds +++ b/target/linux/ipq807x/base-files/etc/board.d/01_leds @@ -15,6 +15,7 @@ cig,wf194c) ucidef_set_led_netdev "wan" "WAN" "wf194c:green:wan" "br-wan" "tx rx link" ucidef_set_led_netdev "lan" "LAN" "wf194c:green:lan" "br-lan" "tx rx link" ;; +edgecore,eap101\ edgecore,eap102) ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy0tx" ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wifi2" "phy1tx" diff --git a/target/linux/ipq807x/base-files/etc/board.d/02_network b/target/linux/ipq807x/base-files/etc/board.d/02_network index 0ae29613d9..c1f4f1829f 100755 --- a/target/linux/ipq807x/base-files/etc/board.d/02_network +++ b/target/linux/ipq807x/base-files/etc/board.d/02_network @@ -26,6 +26,10 @@ qcom_setup_interfaces() ucidef_set_interface_lan "eth0" ucidef_set_interface_wan "eth1" ;; + edgecore,eap101) + ucidef_set_interface_lan "eth1 eth2" + ucidef_set_interface_wan "eth0" + ;; edgecore,eap102) ucidef_set_interface_lan "eth1" ucidef_set_interface_wan "eth0" diff --git a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata index faade0972f..6004e8b88d 100755 --- a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata +++ b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata @@ -41,6 +41,7 @@ case "$FIRMWARE" in case "$board" in cig,wf188|\ cig,wf188n|\ + edgecore,eap101|\ qcom,ipq6018-cp01) caldata_extract "0:ART" 0x1000 0x20000 ;; diff --git a/target/linux/ipq807x/base-files/etc/init.d/bootcount b/target/linux/ipq807x/base-files/etc/init.d/bootcount new file mode 100755 index 0000000000..ac345d6d4a --- /dev/null +++ b/target/linux/ipq807x/base-files/etc/init.d/bootcount @@ -0,0 +1,11 @@ +#!/bin/sh /etc/rc.common + +START=99 + +boot() { + case "$(board_name)" in + edgecore,eap101) + fw_setenv bootcount 0 + ;; + esac +} diff --git a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh index 43ee219412..5be62f59a9 100755 --- a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh +++ b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh @@ -23,6 +23,7 @@ platform_check_image() { cig,wf188|\ cig,wf188n|\ cig,wf194c|\ + edgecore,eap101|\ edgecore,eap102|\ qcom,ipq6018-cp01|\ qcom,ipq807x-hk01|\ @@ -51,5 +52,9 @@ platform_do_upgrade() { sercomm,wallaby) nand_upgrade_tar "$1" ;; + edgecore,eap101) + CI_UBIPART="rootfs1" + nand_upgrade_tar "$1" + ;; esac } diff --git a/target/linux/ipq807x/image/ipq60xx.mk b/target/linux/ipq807x/image/ipq60xx.mk index 6a2d30bbb6..fd66acab58 100644 --- a/target/linux/ipq807x/image/ipq60xx.mk +++ b/target/linux/ipq807x/image/ipq60xx.mk @@ -22,6 +22,16 @@ define Device/cig_wf188n endef TARGET_DEVICES += cig_wf188n +define Device/edgecore_eap101 + DEVICE_TITLE := EdgeCore EAP101 + DEVICE_DTS := qcom-ipq6018-edgecore-eap101 + DEVICE_DTS_DIR := $(DTS_DIR)/qcom + DEVICE_DTS_CONFIG := config@cp01-c1 + SUPPORTED_DEVICES := edgecore,eap101 + DEVICE_PACKAGES := ath11k-wifi-edgecore-eap101 uboot-env +endef +TARGET_DEVICES += edgecore_eap101 + define Device/qcom_cp01_c1 DEVICE_TITLE := Qualcomm Cypress C1 DEVICE_DTS := qcom-ipq6018-cp01-c1 diff --git a/target/linux/ipq807x/patches/106-eap101.patch b/target/linux/ipq807x/patches/106-eap101.patch new file mode 100644 index 0000000000..6b0eb2f831 --- /dev/null +++ b/target/linux/ipq807x/patches/106-eap101.patch @@ -0,0 +1,975 @@ +Index: linux-4.4.60-qsdk-ad8f8efb2edcd35cdb130466cfc1923c37ef7ec1/arch/arm64/boot/dts/qcom/qcom-ipq6018-cp01-edgecore.dtsi +=================================================================== +--- /dev/null ++++ linux-4.4.60-qsdk-ad8f8efb2edcd35cdb130466cfc1923c37ef7ec1/arch/arm64/boot/dts/qcom/qcom-ipq6018-cp01-edgecore.dtsi +@@ -0,0 +1,542 @@ ++/* ++ * Copyright (c) 2019, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#include "qcom-ipq6018.dtsi" ++#include ++#include ++ ++/ { ++ #address-cells = <0x2>; ++ #size-cells = <0x2>; ++ compatible = "qcom,ipq6018-cp01", "qcom,ipq6018"; ++ interrupt-parent = <&intc>; ++ qcom,msm-id = <0x192 0x0>, <0x193 0x0>; ++ ++ aliases { ++ serial0 = &blsp1_uart3; ++ serial1 = &blsp1_uart2; ++ sdhc2 = &sdhc_2; ++ /* ++ * Aliases as required by u-boot ++ * to patch MAC addresses ++ */ ++ ethernet0 = "/soc/dp1"; ++ ethernet1 = "/soc/dp2"; ++ ethernet2 = "/soc/dp3"; ++ ++ led-boot = &led_power; ++ led-failsafe = &led_power; ++ led-running = &led_power; ++ led-upgrade = &led_power; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyMSM0,115200,n8 rw init=/init"; ++#ifdef __IPQ_MEM_PROFILE_256_MB__ ++ bootargs-append = " swiotlb=1"; ++#else ++ bootargs-append = " swiotlb=1 coherent_pool=2M"; ++#endif ++ }; ++ ++}; ++ ++&tlmm { ++ pinctrl-0 = <&sd_ldo_pins>; ++ pinctrl-names = "default"; ++ ++ uart_pins: uart_pins { ++ mux { ++ pins = "gpio44", "gpio45"; ++ function = "blsp2_uart"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ sd_ldo_pins: sd_ldo_pins { ++ mux { ++ pins = "gpio66"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-disable; ++ output-low; ++ }; ++ }; ++ ++ spi_0_pins: spi_0_pins { ++ mux { ++ pins = "gpio38", "gpio39", "gpio40", "gpio41"; ++ function = "blsp0_spi"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ spi_1_pins: spi_1_pins { ++ mux { ++ pins = "gpio69", "gpio71", "gpio72"; ++ function = "blsp1_spi"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ spi_cs { ++ pins = "gpio70"; ++ function = "blsp1_spi"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ quartz_interrupt { ++ pins = "gpio78"; ++ function = "gpio"; ++ input; ++ bias-disable; ++ }; ++ quartz_reset { ++ pins = "gpio79"; ++ function = "gpio"; ++ output-low; ++ bias-disable; ++ }; ++ ++ }; ++ ++ qpic_pins: qpic_pins { ++ data_0 { ++ pins = "gpio15"; ++ function = "qpic_pad0"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_1 { ++ pins = "gpio12"; ++ function = "qpic_pad1"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_2 { ++ pins = "gpio13"; ++ function = "qpic_pad2"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_3 { ++ pins = "gpio14"; ++ function = "qpic_pad3"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_4 { ++ pins = "gpio5"; ++ function = "qpic_pad4"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_5 { ++ pins = "gpio6"; ++ function = "qpic_pad5"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_6 { ++ pins = "gpio7"; ++ function = "qpic_pad6"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_7 { ++ pins = "gpio8"; ++ function = "qpic_pad7"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ qpic_pad { ++ pins = "gpio1", "gpio3", "gpio4", ++ "gpio10", "gpio11", "gpio17"; ++ function = "qpic_pad"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ sd_pins: sd_pins { ++ mux { ++ pins = "gpio62"; ++ function = "sd_card"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ }; ++ ++ extcon_usb_pins: extcon_usb_pins { ++ mux { ++ pins = "gpio26"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-pull-down; ++ }; ++ }; ++ ++ button_pins: button_pins { ++ wps_button { ++ pins = "gpio9"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ reset_button { ++ pins = "gpio19"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ }; ++ ++ mdio_pins: mdio_pinmux { ++ mux_0 { ++ pins = "gpio64"; ++ function = "mdc"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ mux_1 { ++ pins = "gpio65"; ++ function = "mdio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ mux_2 { ++ pins = "gpio75"; ++ function = "gpio"; ++ bias-pull-up; ++ }; ++ mux_3 { ++ pins = "gpio77"; ++ function = "gpio"; ++ bias-pull-up; ++ }; ++ }; ++ ++ leds_pins: leds_pins { ++ led_pwr { ++ pins = "gpio74"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ led_5g { ++ pins = "gpio35"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ led_2g { ++ pins = "gpio37"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ led_wan { ++ pins = "gpio62"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ led_lan1 { ++ pins = "gpio61"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ led_lan2 { ++ pins = "gpio63"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ led_bt { ++ pins = "gpio73"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ hsuart_pins: hsuart_pins { ++ mux { ++ pins = "gpio71", "gpio72", "gpio69", "gpio70"; ++ function = "blsp1_uart"; ++ drive-strength = <8>; ++ bias-disable; ++ }; ++ }; ++ ++ btcoex_pins: btcoex_pins { ++ mux_0 { ++ pins = "gpio51"; ++ function = "pta1_1"; ++ drive-strength = <6>; ++ bias-pull-down; ++ }; ++ mux_1 { ++ pins = "gpio53"; ++ function = "pta1_0"; ++ drive-strength = <6>; ++ bias-pull-down; ++ }; ++ mux_2 { ++ pins = "gpio52"; ++ function = "pta1_2"; ++ drive-strength = <6>; ++ bias-pull-down; ++ }; ++ }; ++}; ++ ++&soc { ++ extcon_usb: extcon_usb { ++ pinctrl-0 = <&extcon_usb_pins>; ++ pinctrl-names = "default"; ++ id-gpio = <&tlmm 26 GPIO_ACTIVE_LOW>; ++ status = "ok"; ++ }; ++ ++ mdio: mdio@90000 { ++ pinctrl-0 = <&mdio_pins>; ++ pinctrl-names = "default"; ++ phy-reset-gpio = <&tlmm 75 0 &tlmm 77 1>; ++ status = "ok"; ++ phy0: ethernet-phy@0 { ++ reg = <0x1c>; ++ }; ++ phy1: ethernet-phy@1 { ++ reg = <3>; ++ }; ++ phy2: ethernet-phy@2 { ++ reg = <4>; ++ }; ++ }; ++ ++ dp1 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <5>; ++ reg = <0x3a001000 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <28>; ++ phy-mode = "sgmii"; ++ }; ++ ++ dp2 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <4>; ++ reg = <0x3a001200 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <3>; ++ phy-mode = "sgmii"; ++ }; ++ ++ dp3 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <3>; ++ reg = <0x3a001400 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <4>; ++ phy-mode = "sgmii"; ++ }; ++ ++ ++ nss-macsec0 { ++ compatible = "qcom,nss-macsec"; ++ phy_addr = <0x1c>; ++ phy_access_mode = <0>; ++ mdiobus = <&mdio>; ++ }; ++ ++ ess-switch@3a000000 { ++ switch_cpu_bmp = <0x1>; /* cpu port bitmap */ ++ switch_lan_bmp = <0x1e>; /* lan port bitmap */ ++ switch_wan_bmp = <0x20>; /* wan port bitmap */ ++ switch_inner_bmp = <0xc0>; /*inner port bitmap*/ ++ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ ++ switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/ ++ switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ ++ qcom,port_phyinfo { ++ port@2 { ++ port_id = <3>; ++ phy_address = <4>; ++ }; ++ port@1 { ++ port_id = <4>; ++ phy_address = <3>; ++ }; ++ port@0 { ++ port_id = <5>; ++ phy_address = <0x1c>; ++ port_mac_sel = "QGMAC_PORT"; ++ }; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&button_pins>; ++ pinctrl-names = "default"; ++ ++ /*wps { ++ label = "wps"; ++ linux,code = ; ++ gpios = <&tlmm 9 GPIO_ACTIVE_LOW>; ++ linux,input-type = <1>; ++ debounce-interval = <60>; ++ };*/ ++ reset { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; ++ linux,input-type = <1>; ++ debounce-interval = <60>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&leds_pins>; ++ pinctrl-names = "default"; ++ ++ led_power: led@74 { ++ label = "green:power"; ++ gpios = <&tlmm 74 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "led_pwr"; ++ default-state = "on"; ++ }; ++ led@35 { ++ label = "green:wifi5"; ++ gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "led_5g"; ++ default-state = "off"; ++ }; ++ led@37 { ++ label = "green:wifi2"; ++ gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "led_2g"; ++ default-state = "off"; ++ }; ++ }; ++}; ++ ++&blsp1_uart3 { ++ pinctrl-0 = <&uart_pins>; ++ pinctrl-names = "default"; ++ status = "ok"; ++}; ++ ++&spi_0 { ++ pinctrl-0 = <&spi_0_pins>; ++ pinctrl-names = "default"; ++ cs-select = <0>; ++ status = "ok"; ++ ++ m25p80@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0>; ++ compatible = "n25q128a11"; ++ linux,modalias = "m25p80", "n25q128a11"; ++ spi-max-frequency = <50000000>; ++ use-default-sizes; ++ }; ++}; ++ ++&blsp1_uart2 { ++ pinctrl-0 = <&hsuart_pins &btcoex_pins>; ++ pinctrl-names = "default"; ++ dmas = <&blsp_dma 2>, ++ <&blsp_dma 3>; ++ dma-names = "tx", "rx"; ++ status = "ok"; ++}; ++ ++&spi_1 { /* BLSP1 QUP1 */ ++ pinctrl-0 = <&spi_1_pins>; ++ pinctrl-names = "default"; ++ cs-select = <0>; ++ quartz-reset-gpio = <&tlmm 79 1>; ++ status = "disabled"; ++ spidev1: spi@1 { ++ compatible = "qca,spidev"; ++ reg = <0>; ++ spi-max-frequency = <24000000>; ++ }; ++}; ++ ++&qpic_bam { ++ status = "ok"; ++}; ++ ++&nand { ++ pinctrl-0 = <&qpic_pins>; ++ pinctrl-names = "default"; ++ status = "ok"; ++}; ++ ++&ssphy_0 { ++ status = "ok"; ++}; ++ ++&qusb_phy_0 { ++ status = "ok"; ++}; ++ ++&qusb_phy_1 { ++ status = "ok"; ++}; ++ ++&usb2 { ++ status = "ok"; ++}; ++ ++&usb3 { ++ status = "ok"; ++}; ++ ++&nss_crypto { ++ status = "ok"; ++}; ++ ++&pcie_phy { ++ status = "ok"; ++}; ++ ++&pcie0 { ++ status = "ok"; ++}; ++ ++&qpic_lcd { ++ status = "ok"; ++}; ++ ++&qpic_lcd_panel { ++ status = "ok"; ++}; +Index: linux-4.4.60-qsdk-ad8f8efb2edcd35cdb130466cfc1923c37ef7ec1/arch/arm64/boot/dts/qcom/qcom-ipq6018-edgecore-eap101.dts +=================================================================== +--- /dev/null ++++ linux-4.4.60-qsdk-ad8f8efb2edcd35cdb130466cfc1923c37ef7ec1/arch/arm64/boot/dts/qcom/qcom-ipq6018-edgecore-eap101.dts +@@ -0,0 +1,423 @@ ++/dts-v1/; ++/* ++ * Copyright (c) 2019, The Linux Foundation. All rights reserved. ++ * ++ * Permission to use, copy, modify, and/or distribute this software for any ++ * purpose with or without fee is hereby granted, provided that the above ++ * copyright notice and this permission notice appear in all copies. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES ++ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF ++ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ++ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES ++ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ++ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF ++ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. ++ */ ++ ++#include "qcom-ipq6018.dtsi" ++#include "qcom-ipq6018-rpm-regulator.dtsi" ++#include "qcom-ipq6018-cpr-regulator.dtsi" ++#include "qcom-ipq6018-cp-cpu.dtsi" ++#include ++#include ++ ++/ { ++ #address-cells = <0x2>; ++ #size-cells = <0x2>; ++ model = "EdgeCore EAP101"; ++ compatible = "edgecore,eap101", "qcom,ipq6018-cp01", "qcom,ipq6018"; ++ interrupt-parent = <&intc>; ++ ++ aliases { ++ serial0 = &blsp1_uart3; ++ serial1 = &blsp1_uart2; ++ ++ /* ++ * Aliases as required by u-boot ++ * to patch MAC addresses ++ */ ++ ethernet0 = "/soc/dp1"; ++ ethernet1 = "/soc/dp2"; ++ ++ led-boot = &led_power; ++ led-failsafe = &led_power; ++ led-running = &led_power; ++ led-upgrade = &led_power; ++ }; ++ ++ chosen { ++ bootargs = "console=ttyMSM0,115200,n8 rw init=/init"; ++ bootargs-append = " console=ttyMSM0,115200,n8 swiotlb=1 coherent_pool=2M"; ++ }; ++ ++ /* ++ * +=========+==============+========================+ ++ * | | | | ++ * | Region | Start Offset | Size | ++ * | | | | ++ * +--------+--------------+-------------------------+ ++ * | | | | ++ * | | | | ++ * | | | | ++ * | | | | ++ * | Linux | 0x41000000 | 139MB | ++ * | | | | ++ * | | | | ++ * | | | | ++ * +--------+--------------+-------------------------+ ++ * | TZ App | 0x49B00000 | 6MB | ++ * +--------+--------------+-------------------------+ ++ * ++ * From the available 145 MB for Linux in the first 256 MB, ++ * we are reserving 6 MB for TZAPP. ++ * ++ * Refer arch/arm64/boot/dts/qcom/qcom-ipq6018-memory.dtsi ++ * for memory layout. ++ */ ++ ++/* TZAPP is enabled only in default memory profile */ ++#if !defined(__IPQ_MEM_PROFILE_256_MB__) && !defined(__IPQ_MEM_PROFILE_512_MB__) ++ reserved-memory { ++ tzapp:tzapp@49B00000 { /* TZAPPS */ ++ no-map; ++ reg = <0x0 0x49B00000 0x0 0x00600000>; ++ }; ++ }; ++#endif ++}; ++ ++&tlmm { ++ uart_pins: uart_pins { ++ mux { ++ pins = "gpio44", "gpio45"; ++ function = "blsp2_uart"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ spi_0_pins: spi_0_pins { ++ mux { ++ pins = "gpio38", "gpio39", "gpio40", "gpio41"; ++ function = "blsp0_spi"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ qpic_pins: qpic_pins { ++ data_0 { ++ pins = "gpio15"; ++ function = "qpic_pad0"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_1 { ++ pins = "gpio12"; ++ function = "qpic_pad1"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_2 { ++ pins = "gpio13"; ++ function = "qpic_pad2"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_3 { ++ pins = "gpio14"; ++ function = "qpic_pad3"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_4 { ++ pins = "gpio5"; ++ function = "qpic_pad4"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_5 { ++ pins = "gpio6"; ++ function = "qpic_pad5"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_6 { ++ pins = "gpio7"; ++ function = "qpic_pad6"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ data_7 { ++ pins = "gpio8"; ++ function = "qpic_pad7"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ qpic_pad { ++ pins = "gpio1", "gpio3", "gpio4", ++ "gpio10", "gpio11", "gpio17"; ++ function = "qpic_pad"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ ++ extcon_usb_pins: extcon_usb_pins { ++ mux { ++ pins = "gpio26"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-pull-down; ++ }; ++ }; ++ ++ button_pins: button_pins { ++ wps_button { ++ pins = "gpio19"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ }; ++ ++ mdio_pins: mdio_pinmux { ++ mux_0 { ++ pins = "gpio64"; ++ function = "mdc"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ mux_1 { ++ pins = "gpio65"; ++ function = "mdio"; ++ drive-strength = <8>; ++ bias-pull-up; ++ }; ++ mux_2 { ++ pins = "gpio75"; ++ function = "gpio"; ++ bias-pull-up; ++ }; ++ }; ++ ++ leds_pins: leds_pins { ++ led_pwr { ++ pins = "gpio74"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ led_5g { ++ pins = "gpio35"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ led_2g { ++ pins = "gpio37"; ++ function = "gpio"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++ uart2_pins: uart2_pins { ++ mux { ++ pins = "gpio57", "gpio58"; ++ function = "blsp4_uart"; ++ drive-strength = <8>; ++ bias-pull-down; ++ }; ++ }; ++}; ++ ++&soc { ++ extcon_usb: extcon_usb { ++ pinctrl-0 = <&extcon_usb_pins>; ++ pinctrl-names = "default"; ++ id-gpio = <&tlmm 26 GPIO_ACTIVE_LOW>; ++ status = "ok"; ++ }; ++ ++ mdio: mdio@90000 { ++ pinctrl-0 = <&mdio_pins>; ++ pinctrl-names = "default"; ++ phy-reset-gpio = <&tlmm 75 0 &tlmm 77 1>; ++ status = "ok"; ++ phy0: ethernet-phy@0 { ++ reg = <0x1c>; ++ }; ++ phy1: ethernet-phy@1 { ++ reg = <3>; ++ }; ++ phy2: ethernet-phy@2 { ++ reg = <4>; ++ }; ++ }; ++ ++ dp1 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <5>; ++ reg = <0x3a001000 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <28>; ++ phy-mode = "sgmii"; ++ }; ++ ++ dp2 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <4>; ++ reg = <0x3a001200 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <3>; ++ phy-mode = "sgmii"; ++ }; ++ ++ dp3 { ++ device_type = "network"; ++ compatible = "qcom,nss-dp"; ++ qcom,id = <3>; ++ reg = <0x3a001400 0x200>; ++ qcom,mactype = <0>; ++ local-mac-address = [000000000000]; ++ qcom,link-poll = <1>; ++ qcom,phy-mdio-addr = <4>; ++ phy-mode = "sgmii"; ++ }; ++ ++ ess-switch@3a000000 { ++ switch_cpu_bmp = <0x1>; /* cpu port bitmap */ ++ switch_lan_bmp = <0x1e>; /* lan port bitmap */ ++ switch_wan_bmp = <0x20>; /* wan port bitmap */ ++ switch_inner_bmp = <0xc0>; /*inner port bitmap*/ ++ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/ ++ switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/ ++ switch_mac_mode2 = <0xff>; /* mac mode for uniphy instance2*/ ++ qcom,port_phyinfo { ++ port@2 { ++ port_id = <3>; ++ phy_address = <4>; ++ }; ++ port@1 { ++ port_id = <4>; ++ phy_address = <3>; ++ }; ++ port@0 { ++ port_id = <5>; ++ phy_address = <0x1c>; ++ port_mac_sel = "QGMAC_PORT"; ++ }; ++ }; ++ }; ++ ++ gpio_keys { ++ compatible = "gpio-keys"; ++ pinctrl-0 = <&button_pins>; ++ pinctrl-names = "default"; ++ ++ wps { ++ label = "reset"; ++ linux,code = ; ++ gpios = <&tlmm 19 GPIO_ACTIVE_LOW>; ++ linux,input-type = <1>; ++ debounce-interval = <60>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ pinctrl-0 = <&leds_pins>; ++ pinctrl-names = "default"; ++ ++ led@25 { ++ label = "wifi5g"; ++ gpios = <&tlmm 35 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "wf188:green:5g"; ++ default-state = "off"; ++ }; ++ led@24 { ++ label = "wifi2g"; ++ gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "wf188:green:2g"; ++ default-state = "off"; ++ }; ++ led_power: led@16 { ++ label = "led_pwr"; ++ gpios = <&tlmm 74 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "green:power"; ++ default-state = "off"; ++ }; ++ }; ++}; ++ ++&blsp1_uart3 { ++ pinctrl-0 = <&uart_pins>; ++ pinctrl-names = "default"; ++ status = "ok"; ++}; ++ ++&spi_0 { ++ pinctrl-0 = <&spi_0_pins>; ++ pinctrl-names = "default"; ++ cs-select = <0>; ++ status = "ok"; ++ ++ m25p80@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ reg = <0>; ++ compatible = "n25q128a11"; ++ linux,modalias = "m25p80", "n25q128a11"; ++ spi-max-frequency = <50000000>; ++ use-default-sizes; ++ }; ++}; ++ ++&blsp1_uart2 { ++ pinctrl-0 = <&uart2_pins>; ++ pinctrl-names = "default"; ++ dmas = <&blsp_dma 2>, ++ <&blsp_dma 3>; ++ dma-names = "tx", "rx"; ++ status = "ok"; ++}; ++&qpic_bam { ++ status = "ok"; ++}; ++ ++&nand { ++ pinctrl-0 = <&qpic_pins>; ++ pinctrl-names = "default"; ++ status = "ok"; ++}; ++ ++&ssphy_0 { ++ status = "ok"; ++}; ++ ++&qusb_phy_0 { ++ status = "ok"; ++}; ++ ++&qusb_phy_1 { ++ status = "ok"; ++}; ++ ++&usb2 { ++ status = "ok"; ++}; ++ ++&usb3 { ++ status = "ok"; ++}; ++ ++&nss_crypto { ++ status = "ok"; ++}; -- 2.25.1