From ade6581e16903e4372e3b253bd2334713c925a95 Mon Sep 17 00:00:00 2001 From: Kathiravan Thirumoorthy Date: Mon, 6 Nov 2023 13:41:35 +0530 Subject: [PATCH] PCI: qcom: update the rate adapter control settings for IPQ5332 x1 controller With the current value(0x3FF), throughput regression is seen. Based on the VI team recommendation, update the setting to new value 0x0, which is also the default value for the single lane controller. Change-Id: I43a3ab89caeedffb1798c326c80fbdeae70fd05d Fixes: f07b4ea7063e ("pcie: qcom: ipq5332: Add support to update system_noc rate adapter") Signed-off-by: Kathiravan Thirumoorthy --- drivers/pci/controller/dwc/pcie-qcom.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 454a2339765f..9c9b5aedbd3a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -118,9 +118,6 @@ /* RATEADAPT_VAL = 256 / ((342M / 240M) - 1) */ #define AGGR_NOC_PCIE_1LANE_RATEADAPT_VAL 0x200 -/* RATEADAPT_VAL = 256 / ((266M / 240M) - 1) = 2363 > Max Value 1023*/ -#define SYSTEM_NOC_PCIE_RATEADAPT_VAL_MAX 0x3FF - #define SYSTEM_NOC_PCIE_RATEADAPT_BYPASS 0x1 #define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 @@ -1523,9 +1520,7 @@ static int qcom_pcie_post_init_1_27_0(struct qcom_pcie *pcie) writel(AGGR_NOC_PCIE_1LANE_RATEADAPT_VAL, pcie->aggr_noc); if (pcie->system_noc != NULL && !IS_ERR(pcie->system_noc)) { - if (pcie->num_lanes == 1) - writel(SYSTEM_NOC_PCIE_RATEADAPT_VAL_MAX, pcie->system_noc); - else + if (pcie->num_lanes == 2) writel(SYSTEM_NOC_PCIE_RATEADAPT_BYPASS, pcie->system_noc); } -- 2.34.1