From 133398bb3eed3869ca2852e4107202ed5b4f5151 Mon Sep 17 00:00:00 2001 From: Sridharan S N Date: Wed, 22 Nov 2023 17:05:02 +0530 Subject: [PATCH] spi: qup: add chip select support This patch configures cs_select field of QUP0_SPI_IO_CONTROL register to select appropriate chip used in the hardware. Default chip select for QUP SPI is 0. Change-Id: I25f8c834ea3906087ce85bcb9323722dcb4b7144 Signed-off-by: Sridharan S N --- drivers/spi/spi-qup.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 205e54f157b4..cf9acc201a6c 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -999,7 +999,7 @@ static int spi_qup_probe(struct platform_device *pdev) struct resource *res; struct device *dev; void __iomem *base; - u32 max_freq, iomode, num_cs; + u32 max_freq, iomode, num_cs, cs_select; int ret, irq, size; dev = &pdev->dev; @@ -1029,6 +1029,14 @@ static int spi_qup_probe(struct platform_device *pdev) return -ENXIO; } + /* Use cs-select dt-property to configure QUP SPI chip select. + * Default chip select is 0. + */ + if (of_property_read_u32(pdev->dev.of_node, "cs-select", &cs_select)) { + dev_dbg(dev, "cs-select not found\n"); + cs_select = 0; + } + ret = clk_prepare_enable(cclk); if (ret) { dev_err(dev, "cannot enable core clock\n"); @@ -1141,7 +1149,8 @@ static int spi_qup_probe(struct platform_device *pdev) base + QUP_ERROR_FLAGS_EN); writel_relaxed(0, base + SPI_CONFIG); - writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL); + writel_relaxed(SPI_IO_C_NO_TRI_STATE | SPI_IO_C_CS_SELECT(cs_select), + base + SPI_IO_CONTROL); ret = devm_request_irq(dev, irq, spi_qup_qup_irq, IRQF_TRIGGER_HIGH, pdev->name, controller); -- 2.34.1