mirror of
https://github.com/Telecominfraproject/wlan-ap.git
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3affbc1cad
This series is based on * 2020-07-10 ipq6018-ilq-11-0_qca_oem-034672b0676c37b1f4519e5720e18e95fe6236ef Add support for * qsdk kernel/v4.4 * qsdk ethernet subsystem * v5.7 ath11k backport + QualComm staging patches (wlan_ap_1.0) * ath11k-firmware * hostapd/iw/... Feature support * full boot, system detection * sysupgrade to nand * HE support via latest hostapd * driver support for usb, crypto, hwmon, cpufreq, ... Missing * NSS/HW flow offloading - FW blob is not redistributable Using the qsdk v4.4 is an intermediate solution while the vanilla is being tested. Vanilla kernel is almost on feature par. Work has already started to upstream the ethernet and switch drivers. Once complete the target will be fully upstream. Signed-off-by: John Crispin <john@phrozen.org>
127 lines
3.8 KiB
Diff
127 lines
3.8 KiB
Diff
From 4ca0ac69e8861650b6068548435064edb1dfa236 Mon Sep 17 00:00:00 2001
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From: Anilkumar Kolli <akolli@codeaurora.org>
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Date: Mon, 23 Mar 2020 15:04:05 +0530
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Subject: [PATCH 161/164] ath11k: Add reg read/write/window select ops
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Add support for bus read/write/window selection ops
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for target access.
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Signed-off-by: Govind Singh <govinds@codeaurora.org>
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Signed-off-by: Anilkumar Kolli <akolli@codeaurora.org>
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---
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drivers/net/wireless/ath/ath11k/core.h | 1 +
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drivers/net/wireless/ath/ath11k/pci.c | 46 ++++++++++++++++++++++++++++++++++
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drivers/net/wireless/ath/ath11k/pci.h | 10 ++++++++
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3 files changed, 57 insertions(+)
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--- a/drivers/net/wireless/ath/ath11k/core.h
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+++ b/drivers/net/wireless/ath/ath11k/core.h
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@@ -796,6 +796,7 @@ struct ath11k_base {
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bool m3_fw_support;
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bool mhi_support;
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bool fixed_mem_region;
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+ bool use_register_windowing;
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/* must be last */
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u8 drv_priv[0] __aligned(sizeof(void *));
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};
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--- a/drivers/net/wireless/ath/ath11k/pci.c
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+++ b/drivers/net/wireless/ath/ath11k/pci.c
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@@ -214,11 +214,53 @@ static const struct service_to_pipe targ
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},
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};
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+static inline void ath11k_pci_select_window(struct ath11k_pci *ar_pci, u32 offset)
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+{
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+ u32 window = (offset >> WINDOW_SHIFT) & WINDOW_VALUE_MASK;
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+
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+ if (window != ar_pci->register_window) {
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+ iowrite32(WINDOW_ENABLE_BIT | window,
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+ ar_pci->mem + WINDOW_REG_ADDRESS);
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+ ar_pci->register_window = window;
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+ }
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+}
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+
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static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab)
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{
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return (struct ath11k_pci *)ab->drv_priv;
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}
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+static void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
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+{
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+ struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
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+
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+ if (ab->use_register_windowing) {
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+ spin_lock_bh(&ar_pci->window_lock);
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+ ath11k_pci_select_window(ar_pci, offset);
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+ iowrite32(value, ar_pci->mem + WINDOW_START + (offset & WINDOW_RANGE_MASK));
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+ spin_unlock_bh(&ar_pci->window_lock);
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+ } else {
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+ iowrite32(value, ar_pci->mem + offset);
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+ }
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+}
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+
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+static u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
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+{
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+ struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
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+ u32 val;
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+
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+ if (ab->use_register_windowing) {
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+ spin_lock_bh(&ar_pci->window_lock);
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+ ath11k_pci_select_window(ar_pci, offset);
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+ val = ioread32(ar_pci->mem + WINDOW_START + (offset & WINDOW_RANGE_MASK));
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+ spin_unlock_bh(&ar_pci->window_lock);
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+ } else {
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+ val = ioread32(ar_pci->mem + offset);
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+ }
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+
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+ return val;
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+}
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+
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int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector)
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{
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struct pci_dev *pci_dev = to_pci_dev(dev);
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@@ -560,6 +602,8 @@ static int ath11k_pci_start(struct ath11
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static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
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.start = ath11k_pci_start,
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.stop = ath11k_pci_stop,
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+ .read32 = ath11k_pci_read32,
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+ .write32 = ath11k_pci_write32,
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.power_down = ath11k_pci_power_down,
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.power_up = ath11k_pci_power_up,
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};
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@@ -607,6 +651,8 @@ static int ath11k_pci_probe(struct pci_d
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ab->m3_fw_support = true;
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ab->mhi_support = true;
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ab->fixed_mem_region = false;
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+ ab->use_register_windowing = true;
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+ spin_lock_init(&ar_pci->window_lock);
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ret = ath11k_pci_claim(ar_pci, pdev);
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if (ret) {
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--- a/drivers/net/wireless/ath/ath11k/pci.h
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+++ b/drivers/net/wireless/ath/ath11k/pci.h
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@@ -15,6 +15,14 @@
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#define PCI_DMA_MASK_64_BIT 64
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#define PCI_DMA_MASK_32_BIT 32
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+#define MAX_UNWINDOWED_ADDRESS 0x80000
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+#define WINDOW_ENABLE_BIT 0x40000000
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+#define WINDOW_REG_ADDRESS 0x310C
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+#define WINDOW_SHIFT 19
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+#define WINDOW_VALUE_MASK 0x3F
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+#define WINDOW_START MAX_UNWINDOWED_ADDRESS
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+#define WINDOW_RANGE_MASK 0x7FFFF
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+
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struct ath11k_msi_user {
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char *name;
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int num_vectors;
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@@ -39,6 +47,8 @@ struct ath11k_pci {
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u32 msi_ep_base_data;
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struct mhi_controller *mhi_ctrl;
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unsigned long mhi_state;
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+ u32 register_window;
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+ spinlock_t window_lock;
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};
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int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name,
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