mirror of
https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-12-20 10:51:27 +00:00
371 lines
11 KiB
C
371 lines
11 KiB
C
/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Xiufeng Li <Xiufeng.Li@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_MT7988_H
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#define _DT_BINDINGS_CLK_MT7988_H
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/* INFRACFG */
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#define CK_INFRA_CK_F26M 0
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#define CK_INFRA_PWM_O 1
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#define CK_INFRA_PCIE_OCC_P0 2
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#define CK_INFRA_PCIE_OCC_P1 3
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#define CK_INFRA_PCIE_OCC_P2 4
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#define CK_INFRA_PCIE_OCC_P3 5
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#define CK_INFRA_133M_HCK 6
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#define CK_INFRA_133M_PHCK 7
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#define CK_INFRA_66M_PHCK 8
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#define CK_INFRA_FAUD_L_O 9
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#define CK_INFRA_FAUD_AUD_O 10
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#define CK_INFRA_FAUD_EG2_O 11
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#define CK_INFRA_I2C_O 12
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#define CK_INFRA_UART_O0 13
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#define CK_INFRA_UART_O1 14
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#define CK_INFRA_UART_O2 15
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#define CK_INFRA_NFI_O 16
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#define CK_INFRA_SPINFI_O 17
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#define CK_INFRA_SPI0_O 18
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#define CK_INFRA_SPI1_O 19
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#define CK_INFRA_LB_MUX_FRTC 20
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#define CK_INFRA_FRTC 21
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#define CK_INFRA_FMSDC400_O 22
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#define CK_INFRA_FMSDC2_HCK_OCC 23
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#define CK_INFRA_PERI_133M 24
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#define CK_INFRA_USB_O 25
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#define CK_INFRA_USB_O_P1 26
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#define CK_INFRA_USB_FRMCNT_O 27
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#define CK_INFRA_USB_FRMCNT_O_P1 28
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#define CK_INFRA_USB_XHCI_O 29
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#define CK_INFRA_USB_XHCI_O_P1 30
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#define CK_INFRA_USB_PIPE_O 31
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#define CK_INFRA_USB_PIPE_O_P1 32
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#define CK_INFRA_USB_UTMI_O 33
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#define CK_INFRA_USB_UTMI_O_P1 34
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#define CK_INFRA_PCIE_PIPE_OCC_P0 35
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#define CK_INFRA_PCIE_PIPE_OCC_P1 36
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#define CK_INFRA_PCIE_PIPE_OCC_P2 37
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#define CK_INFRA_PCIE_PIPE_OCC_P3 38
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#define CK_INFRA_F26M_O0 39
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#define CK_INFRA_F26M_O1 40
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#define CK_INFRA_133M_MCK 41
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#define CK_INFRA_66M_MCK 42
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#define CK_INFRA_PERI_66M_O 43
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#define CK_INFRA_USB_SYS_O 44
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#define CK_INFRA_USB_SYS_O_P1 45
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#define CLK_INFRA_NR_CLK 46
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/* INFRACFG_AO */
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#define CK_INFRA_MUX_UART0_SEL 0
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#define CK_INFRA_MUX_UART1_SEL 1
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#define CK_INFRA_MUX_UART2_SEL 2
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#define CK_INFRA_MUX_SPI0_SEL 3
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#define CK_INFRA_MUX_SPI1_SEL 4
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#define CK_INFRA_MUX_SPI2_SEL 5
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#define CK_INFRA_PWM_SEL 6
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#define CK_INFRA_PWM_CK1_SEL 7
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#define CK_INFRA_PWM_CK2_SEL 8
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#define CK_INFRA_PWM_CK3_SEL 9
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#define CK_INFRA_PWM_CK4_SEL 10
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#define CK_INFRA_PWM_CK5_SEL 11
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#define CK_INFRA_PWM_CK6_SEL 12
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#define CK_INFRA_PWM_CK7_SEL 13
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#define CK_INFRA_PWM_CK8_SEL 14
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#define CK_INFRA_PCIE_GFMUX_TL_O_P0_SEL 15
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#define CK_INFRA_PCIE_GFMUX_TL_O_P1_SEL 16
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#define CK_INFRA_PCIE_GFMUX_TL_O_P2_SEL 17
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#define CK_INFRA_PCIE_GFMUX_TL_O_P3_SEL 18
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#define CK_INFRA_66M_GPT_BCK 19
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#define CK_INFRA_66M_PWM_HCK 20
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#define CK_INFRA_66M_PWM_BCK 21
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#define CK_INFRA_66M_PWM_CK1 22
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#define CK_INFRA_66M_PWM_CK2 23
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#define CK_INFRA_66M_PWM_CK3 24
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#define CK_INFRA_66M_PWM_CK4 25
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#define CK_INFRA_66M_PWM_CK5 26
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#define CK_INFRA_66M_PWM_CK6 27
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#define CK_INFRA_66M_PWM_CK7 28
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#define CK_INFRA_66M_PWM_CK8 29
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#define CK_INFRA_133M_CQDMA_BCK 30
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#define CK_INFRA_66M_AUD_SLV_BCK 31
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#define CK_INFRA_AUD_26M 32
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#define CK_INFRA_AUD_L 33
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#define CK_INFRA_AUD_AUD 34
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#define CK_INFRA_AUD_EG2 35
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#define CK_INFRA_DRAMC_F26M 36
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#define CK_INFRA_133M_DBG_ACKM 37
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#define CK_INFRA_66M_AP_DMA_BCK 38
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#define CK_INFRA_66M_SEJ_BCK 39
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#define CK_INFRA_PRE_CK_SEJ_F13M 40
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#define CK_INFRA_26M_THERM_SYSTEM 41
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#define CK_INFRA_I2C_BCK 42
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#define CK_INFRA_52M_UART0_CK 43
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#define CK_INFRA_52M_UART1_CK 44
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#define CK_INFRA_52M_UART2_CK 45
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#define CK_INFRA_NFI 46
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#define CK_INFRA_SPINFI 47
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#define CK_INFRA_66M_NFI_HCK 48
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#define CK_INFRA_104M_SPI0 49
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#define CK_INFRA_104M_SPI1 50
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#define CK_INFRA_104M_SPI2_BCK 51
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#define CK_INFRA_66M_SPI0_HCK 52
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#define CK_INFRA_66M_SPI1_HCK 53
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#define CK_INFRA_66M_SPI2_HCK 54
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#define CK_INFRA_66M_FLASHIF_AXI 55
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#define CK_INFRA_RTC 56
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#define CK_INFRA_26M_ADC_BCK 57
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#define CK_INFRA_RC_ADC 58
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#define CK_INFRA_MSDC400 59
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#define CK_INFRA_MSDC2_HCK 60
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#define CK_INFRA_133M_MSDC_0_HCK 61
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#define CK_INFRA_66M_MSDC_0_HCK 62
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#define CK_INFRA_133M_CPUM_BCK 63
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#define CK_INFRA_BIST2FPC 64
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#define CK_INFRA_I2C_X16W_MCK_CK_P1 65
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#define CK_INFRA_I2C_X16W_PCK_CK_P1 66
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#define CK_INFRA_133M_USB_HCK 67
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#define CK_INFRA_133M_USB_HCK_CK_P1 68
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#define CK_INFRA_66M_USB_HCK 69
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#define CK_INFRA_66M_USB_HCK_CK_P1 70
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#define CK_INFRA_USB_SYS 71
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#define CK_INFRA_USB_SYS_CK_P1 72
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#define CK_INFRA_USB_REF 73
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#define CK_INFRA_USB_CK_P1 74
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#define CK_INFRA_USB_FRMCNT 75
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#define CK_INFRA_USB_FRMCNT_CK_P1 76
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#define CK_INFRA_USB_PIPE 77
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#define CK_INFRA_USB_PIPE_CK_P1 78
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#define CK_INFRA_USB_UTMI 79
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#define CK_INFRA_USB_UTMI_CK_P1 80
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#define CK_INFRA_USB_XHCI 81
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#define CK_INFRA_USB_XHCI_CK_P1 82
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#define CK_INFRA_PCIE_GFMUX_TL_P0 83
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#define CK_INFRA_PCIE_GFMUX_TL_P1 84
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#define CK_INFRA_PCIE_GFMUX_TL_P2 85
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#define CK_INFRA_PCIE_GFMUX_TL_P3 86
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#define CK_INFRA_PCIE_PIPE_P0 87
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#define CK_INFRA_PCIE_PIPE_P1 88
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#define CK_INFRA_PCIE_PIPE_P2 89
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#define CK_INFRA_PCIE_PIPE_P3 90
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#define CK_INFRA_133M_PCIE_CK_P0 91
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#define CK_INFRA_133M_PCIE_CK_P1 92
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#define CK_INFRA_133M_PCIE_CK_P2 93
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#define CK_INFRA_133M_PCIE_CK_P3 94
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#define CK_INFRA_PCIE_PERI_26M_CK_P0 95
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#define CK_INFRA_PCIE_PERI_26M_CK_P1 96
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#define CK_INFRA_PCIE_PERI_26M_CK_P2 97
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#define CK_INFRA_PCIE_PERI_26M_CK_P3 98
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#define CLK_INFRA_AO_NR_CLK 99
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/* TOPCKGEN */
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#define CK_TOP_NETSYS_SEL 0
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#define CK_TOP_NETSYS_500M_SEL 1
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#define CK_TOP_NETSYS_2X_SEL 2
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#define CK_TOP_NETSYS_GSW_SEL 3
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#define CK_TOP_ETH_GMII_SEL 4
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#define CK_TOP_NETSYS_MCU_SEL 5
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#define CK_TOP_NETSYS_PAO_2X_SEL 6
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#define CK_TOP_EIP197_SEL 7
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#define CK_TOP_AXI_INFRA_SEL 8
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#define CK_TOP_UART_SEL 9
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#define CK_TOP_EMMC_250M_SEL 10
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#define CK_TOP_EMMC_400M_SEL 11
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#define CK_TOP_SPI_SEL 12
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#define CK_TOP_SPIM_MST_SEL 13
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#define CK_TOP_NFI1X_SEL 14
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#define CK_TOP_SPINFI_SEL 15
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#define CK_TOP_PWM_SEL 16
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#define CK_TOP_I2C_SEL 17
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#define CK_TOP_PCIE_MBIST_250M_SEL 18
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#define CK_TOP_PEXTP_TL_SEL 19
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#define CK_TOP_PEXTP_TL_P1_SEL 20
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#define CK_TOP_PEXTP_TL_P2_SEL 21
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#define CK_TOP_PEXTP_TL_P3_SEL 22
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#define CK_TOP_USB_SYS_SEL 23
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#define CK_TOP_USB_SYS_P1_SEL 24
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#define CK_TOP_USB_XHCI_SEL 25
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#define CK_TOP_USB_XHCI_P1_SEL 26
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#define CK_TOP_USB_FRMCNT_SEL 27
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#define CK_TOP_USB_FRMCNT_P1_SEL 28
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#define CK_TOP_AUD_SEL 29
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#define CK_TOP_A1SYS_SEL 30
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#define CK_TOP_AUD_L_SEL 31
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#define CK_TOP_A_TUNER_SEL 32
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#define CK_TOP_SSPXTP_SEL 33
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#define CK_TOP_USB_PHY_SEL 34
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#define CK_TOP_USXGMII_SBUS_0_SEL 35
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#define CK_TOP_USXGMII_SBUS_1_SEL 36
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#define CK_TOP_SGM_0_SEL 37
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#define CK_TOP_SGM_SBUS_0_SEL 38
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#define CK_TOP_SGM_1_SEL 39
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#define CK_TOP_SGM_SBUS_1_SEL 40
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#define CK_TOP_XFI_PHY_0_XTAL_SEL 41
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#define CK_TOP_XFI_PHY_1_XTAL_SEL 42
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#define CK_TOP_SYSAXI_SEL 43
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#define CK_TOP_SYSAPB_SEL 44
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#define CK_TOP_ETH_REFCK_50M_SEL 45
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#define CK_TOP_ETH_SYS_200M_SEL 46
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#define CK_TOP_ETH_SYS_SEL 47
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#define CK_TOP_ETH_XGMII_SEL 48
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#define CK_TOP_BUS_TOPS_SEL 49
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#define CK_TOP_NPU_TOPS_SEL 50
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#define CK_TOP_DRAMC_SEL 51
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#define CK_TOP_DRAMC_MD32_SEL 52
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#define CK_TOP_INFRA_F26M_SEL 53
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#define CK_TOP_PEXTP_P0_SEL 54
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#define CK_TOP_PEXTP_P1_SEL 55
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#define CK_TOP_PEXTP_P2_SEL 56
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#define CK_TOP_PEXTP_P3_SEL 57
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#define CK_TOP_DA_XTP_GLB_P0_SEL 58
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#define CK_TOP_DA_XTP_GLB_P1_SEL 59
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#define CK_TOP_DA_XTP_GLB_P2_SEL 60
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#define CK_TOP_DA_XTP_GLB_P3_SEL 61
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#define CK_TOP_CKM_SEL 62
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#define CK_TOP_DA_SELM_XTAL_SEL 63
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#define CK_TOP_PEXTP_SEL 64
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#define CK_TOP_TOPS_P2_26M_SEL 65
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#define CK_TOP_MCUSYS_BACKUP_625M_SEL 66
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#define CK_TOP_NETSYS_SYNC_250M_SEL 67
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#define CK_TOP_MACSEC_SEL 68
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#define CK_TOP_NETSYS_TOPS_400M_SEL 69
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#define CK_TOP_NETSYS_PPEFB_250M_SEL 70
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#define CK_TOP_NETSYS_WARP_SEL 71
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#define CK_TOP_ETH_MII_SEL 72
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#define CK_TOP_CK_NPU_SEL_CM_TOPS_SEL 73
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#define CK_TOP_CB_CKSQ_40M 74
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#define CK_TOP_CB_M_416M 75
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#define CK_TOP_CB_M_D2 76
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#define CK_TOP_M_D3_D2 77
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#define CK_TOP_CB_M_D4 78
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#define CK_TOP_CB_M_D8 79
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#define CK_TOP_M_D8_D2 80
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#define CK_TOP_CB_MM_720M 81
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#define CK_TOP_CB_MM_D2 82
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#define CK_TOP_CB_MM_D3_D5 83
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#define CK_TOP_CB_MM_D4 84
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#define CK_TOP_MM_D6_D2 85
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#define CK_TOP_CB_MM_D8 86
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#define CK_TOP_CB_APLL2_196M 87
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#define CK_TOP_CB_APLL2_D4 88
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#define CK_TOP_CB_NET1_D4 89
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#define CK_TOP_CB_NET1_D5 90
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#define CK_TOP_NET1_D5_D2 91
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#define CK_TOP_NET1_D5_D4 92
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#define CK_TOP_CB_NET1_D8 93
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#define CK_TOP_NET1_D8_D2 94
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#define CK_TOP_NET1_D8_D4 95
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#define CK_TOP_NET1_D8_D8 96
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#define CK_TOP_NET1_D8_D16 97
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#define CK_TOP_CB_NET2_800M 98
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#define CK_TOP_CB_NET2_D2 99
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#define CK_TOP_CB_NET2_D4 100
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#define CK_TOP_NET2_D4_D4 101
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#define CK_TOP_NET2_D4_D8 102
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#define CK_TOP_CB_NET2_D6 103
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#define CK_TOP_CB_NET2_D8 104
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#define CK_TOP_CB_WEDMCU_208M 105
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#define CK_TOP_CB_SGM_325M 106
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#define CK_TOP_CB_NETSYS_850M 107
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#define CK_TOP_CB_MSDC_400M 108
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#define CK_TOP_CKSQ_40M_D2 109
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#define CK_TOP_CB_RTC_32K 110
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#define CK_TOP_CB_RTC_32P7K 111
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#define CK_TOP_INFRA_F32K 112
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#define CK_TOP_CKSQ_SRC 113
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#define CK_TOP_NETSYS_2X 114
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#define CK_TOP_NETSYS_GSW 115
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#define CK_TOP_NETSYS_WED_MCU 116
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#define CK_TOP_EIP197 117
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#define CK_TOP_EMMC_250M 118
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#define CK_TOP_EMMC_400M 119
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#define CK_TOP_SPI 120
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#define CK_TOP_SPIM_MST 121
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#define CK_TOP_NFI1X 122
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#define CK_TOP_SPINFI_BCK 123
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#define CK_TOP_I2C_BCK 124
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#define CK_TOP_USB_SYS 125
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#define CK_TOP_USB_SYS_P1 126
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#define CK_TOP_USB_XHCI 127
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#define CK_TOP_USB_XHCI_P1 128
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#define CK_TOP_USB_FRMCNT 129
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#define CK_TOP_USB_FRMCNT_P1 130
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#define CK_TOP_AUD 131
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#define CK_TOP_A1SYS 132
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#define CK_TOP_AUD_L 133
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#define CK_TOP_A_TUNER 134
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#define CK_TOP_SYSAXI 135
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#define CK_TOP_INFRA_F26M 136
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#define CK_TOP_USB_REF 137
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#define CK_TOP_USB_CK_P1 138
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#define CK_TOP_AUD_I2S_M 139
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#define CLK_TOP_NR_CLK 140
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/* APMIXEDSYS */
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#define CK_APMIXED_NETSYSPLL 0
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#define CK_APMIXED_MPLL 1
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#define CK_APMIXED_MMPLL 2
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#define CK_APMIXED_APLL2 3
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#define CK_APMIXED_NET1PLL 4
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#define CK_APMIXED_NET2PLL 5
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#define CK_APMIXED_WEDMCUPLL 6
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#define CK_APMIXED_SGMPLL 7
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#define CK_APMIXED_ARM_B 8
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#define CK_APMIXED_CCIPLL2_B 9
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#define CK_APMIXED_USXGMIIPLL 10
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#define CK_APMIXED_MSDCPLL 11
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#define CLK_APMIXED_NR_CLK 12
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/* MCUSYS */
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#define CK_MCU_BUS_DIV_SEL 0
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#define CK_MCU_ARM_DIV_SEL 1
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#define CLK_MCU_NR_CLK 2
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/* ETHDMA */
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#define CK_ETHDMA_XGP1_EN 0
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#define CK_ETHDMA_XGP2_EN 1
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#define CK_ETHDMA_XGP3_EN 2
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#define CK_ETHDMA_FE_EN 3
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#define CK_ETHDMA_GP2_EN 4
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#define CK_ETHDMA_GP1_EN 5
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#define CK_ETHDMA_GP3_EN 6
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#define CK_ETHDMA_ESW_EN 7
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#define CK_ETHDMA_CRYPT0_EN 8
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#define CLK_ETHDMA_NR_CLK 9
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/* SGMIISYS_0 */
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#define CK_SGM0_TX_EN 0
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#define CK_SGM0_RX_EN 1
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#define CLK_SGMII0_NR_CLK 2
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/* SGMIISYS_1 */
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#define CK_SGM1_TX_EN 0
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#define CK_SGM1_RX_EN 1
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#define CLK_SGMII1_NR_CLK 2
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/* ETHWARP */
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#define CK_ETHWARP_WOCPU2_EN 0
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#define CK_ETHWARP_WOCPU1_EN 1
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#define CK_ETHWARP_WOCPU0_EN 2
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#define CLK_ETHWARP_NR_CLK 3
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#endif /* _DT_BINDINGS_CLK_MT7988_H */
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