mirror of
https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-12-17 17:31:27 +00:00
1028 lines
22 KiB
Diff
1028 lines
22 KiB
Diff
From 34f431b13c858b63d9361f1291734fb53900e73b Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Fri, 16 Oct 2020 04:27:42 +0200
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Subject: [PATCH] ipq807x: add edgecore EAP-102 support
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Signed-off-by: John Crispin <john@phrozen.org>
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---
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.../ipq807x/base-files/etc/board.d/01_leds | 4 +
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.../ipq807x/base-files/etc/board.d/02_network | 4 +
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.../etc/hotplug.d/firmware/10-ath11k-caldata | 1 +
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.../base-files/lib/upgrade/platform.sh | 2 +
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.../boot/dts/qcom/qcom-ipq807x-eap102.dts | 922 ++++++++++++++++++
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target/linux/ipq807x/image/ipq807x.mk | 10 +
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6 files changed, 943 insertions(+)
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create mode 100755 target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts
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diff --git a/target/linux/ipq807x/base-files/etc/board.d/01_leds b/target/linux/ipq807x/base-files/etc/board.d/01_leds
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index 5196da447b..3ed1227a3d 100755
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--- a/target/linux/ipq807x/base-files/etc/board.d/01_leds
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+++ b/target/linux/ipq807x/base-files/etc/board.d/01_leds
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@@ -15,6 +15,10 @@ cig,wf194c)
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ucidef_set_led_netdev "wan" "WAN" "wf194c:green:wan" "br-wan" "tx rx link"
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ucidef_set_led_netdev "lan" "LAN" "wf194c:green:lan" "br-lan" "tx rx link"
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;;
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+edgecore,eap102)
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+ ucidef_set_led_wlan "wlan5g" "WLAN5G" "green:wifi5" "phy0tx"
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+ ucidef_set_led_wlan "wlan2g" "WLAN2G" "green:wifi2" "phy1tx"
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+ ;;
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esac
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board_config_flush
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diff --git a/target/linux/ipq807x/base-files/etc/board.d/02_network b/target/linux/ipq807x/base-files/etc/board.d/02_network
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index aadf9d4ff2..0ae29613d9 100755
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--- a/target/linux/ipq807x/base-files/etc/board.d/02_network
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+++ b/target/linux/ipq807x/base-files/etc/board.d/02_network
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@@ -26,6 +26,10 @@ qcom_setup_interfaces()
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ucidef_set_interface_lan "eth0"
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ucidef_set_interface_wan "eth1"
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;;
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+ edgecore,eap102)
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+ ucidef_set_interface_lan "eth1"
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+ ucidef_set_interface_wan "eth0"
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+ ;;
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esac
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}
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diff --git a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata
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index 30292c2505..faade0972f 100755
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--- a/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata
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+++ b/target/linux/ipq807x/base-files/etc/hotplug.d/firmware/10-ath11k-caldata
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@@ -29,6 +29,7 @@ case "$FIRMWARE" in
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"IPQ8074/caldata.bin")
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case "$board" in
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cig,wf194c|\
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+ edgecore,eap102 |\
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qcom,ipq807x-hk01|\
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qcom,ipq807x-hk14|\
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sercomm,wallaby)
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diff --git a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh
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index 0073b94bbb..43ee219412 100755
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--- a/target/linux/ipq807x/base-files/lib/upgrade/platform.sh
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+++ b/target/linux/ipq807x/base-files/lib/upgrade/platform.sh
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@@ -23,6 +23,7 @@ platform_check_image() {
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cig,wf188|\
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cig,wf188n|\
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cig,wf194c|\
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+ edgecore,eap102|\
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qcom,ipq6018-cp01|\
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qcom,ipq807x-hk01|\
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sercomm,wallaby)
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@@ -44,6 +45,7 @@ platform_do_upgrade() {
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;;
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cig,wf188n|\
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cig,wf194c|\
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+ edgecore,eap102|\
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qcom,ipq6018-cp01|\
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qcom,ipq807x-hk01|\
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sercomm,wallaby)
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diff --git a/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts
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new file mode 100755
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index 0000000000..f81cf2d4af
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--- /dev/null
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+++ b/target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/qcom-ipq807x-eap102.dts
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@@ -0,0 +1,922 @@
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+/dts-v1/;
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+/*
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+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
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+ *
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+ * Permission to use, copy, modify, and/or distribute this software for any
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+ * purpose with or without fee is hereby granted, provided that the above
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+ * copyright notice and this permission notice appear in all copies.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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+ */
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+#include "qcom-ipq807x-soc.dtsi"
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+#include "qcom-ipq807x-ac-cpu.dtsi"
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+
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+/ {
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+ #address-cells = <0x2>;
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+ #size-cells = <0x2>;
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+ model = "Edgecore EAP102";
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+ compatible = "edgecore,eap102", "qcom,ipq807x-ac02", "qcom,ipq807x";
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+ qcom,msm-id = <0x178 0x0>;
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+ interrupt-parent = <&intc>;
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+ qcom,board-id = <0x8 0x0>;
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+ qcom,pmic-id = <0x0 0x0 0x0 0x0>;
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+
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+ aliases {
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+ /*
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+ * Aliases as required by u-boot
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+ * to patch MAC addresses
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+ */
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+ ethernet0 = "/soc/dp1";
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+ ethernet1 = "/soc/dp2";
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+ ethernet2 = "/soc/dp3";
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+ ethernet3 = "/soc/dp4";
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+ ethernet4 = "/soc/dp5";
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+ ethernet5 = "/soc/dp6";
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+
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+ led-boot = &led_power;
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+ led-failsafe = &led_power;
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+ led-running = &led_power;
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+ led-upgrade = &led_power;
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+ };
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+
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+ chosen {
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+ bootargs = "console=ttyMSM0,115200,n8 root=/dev/ram0 rw \
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+ init=/init";
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+ #ifdef __IPQ_MEM_PROFILE_256_MB__
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+ bootargs-append = " swiotlb=1";
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+ #else
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+ bootargs-append = " swiotlb=1 coherent_pool=2M";
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+ #endif
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+ };
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+};
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+
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+&tlmm {
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+ pinctrl-0 = <&btcoex_pins>;
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+ pinctrl-names = "default";
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+
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+ btcoex_pins: btcoex_pins {
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+ mux_0 {
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+ pins = "gpio64";
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+ function = "pta1_1";
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+ drive-strength = <6>;
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+ bias-pull-down;
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+ };
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+ mux_1 {
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+ pins = "gpio65";
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+ function = "pta1_2";
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+ drive-strength = <6>;
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+ bias-pull-down;
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+ };
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+ };
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+
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+ mdio_pins: mdio_pinmux {
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+ mux_0 {
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+ pins = "gpio68";
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+ function = "mdc";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+ mux_1 {
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+ pins = "gpio69";
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+ function = "mdio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+ mux_2 {
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+ pins = "gpio33";
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+ function = "gpio";
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+ bias-pull-up;
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+ };
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+ mux_3 {
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+ pins = "gpio44";
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+ function = "gpio";
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+ bias-pull-up;
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+ };
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+ };
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+
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+ uart_pins: uart_pins {
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+ mux {
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+ pins = "gpio23", "gpio24";
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+ function = "blsp4_uart1";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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+
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+ spi_0_pins: spi_0_pins {
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+ mux {
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+ pins = "gpio38", "gpio39", "gpio40", "gpio41";
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+ function = "blsp0_spi";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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+
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+ qpic_pins: qpic_pins {
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+ data_0 {
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+ pins = "gpio15";
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+ function = "qpic_pad0";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ data_1 {
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+ pins = "gpio12";
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+ function = "qpic_pad1";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ data_2 {
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+ pins = "gpio13";
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+ function = "qpic_pad2";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ data_3 {
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+ pins = "gpio14";
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+ function = "qpic_pad3";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ data_4 {
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+ pins = "gpio5";
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+ function = "qpic_pad4";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ data_5 {
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+ pins = "gpio6";
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+ function = "qpic_pad5";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ data_6 {
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+ pins = "gpio7";
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+ function = "qpic_pad6";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ data_7 {
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+ pins = "gpio8";
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+ function = "qpic_pad7";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ qpic_pad {
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+ pins = "gpio1", "gpio3", "gpio4",
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+ "gpio10", "gpio11", "gpio17";
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+ function = "qpic_pad";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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+
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+ hsuart_pins: hsuart_pins {
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+ mux {
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+ pins = "gpio49";
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+ function = "blsp2_uart";
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+ drive-strength = <8>;
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+ bias-disable;
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+ };
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+ };
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+
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+ button_pins: button_pins {
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+
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+ reset_button {
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+ pins = "gpio66";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-up;
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+ };
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+ };
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+
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+ led_pins: led_pins {
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+ led_pwr {
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+ pins = "gpio46";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+
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+ led_2g {
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+ pins = "gpio47";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+
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+ led_5g {
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+ pins = "gpio48";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+
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+ led_bt {
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+ pins = "gpio50";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+ };
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+
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+ usb_mux_sel_pins: usb_mux_pins {
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+ mux {
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+ pins = "gpio27";
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+ function = "gpio";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+ };
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+
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+ pcie0_pins: pcie_pins {
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+ pcie0_rst {
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+ pins = "gpio58";
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+ function = "pcie0_rst";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+ pcie0_wake {
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+ pins = "gpio59";
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+ function = "pcie0_wake";
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+ drive-strength = <8>;
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+ bias-pull-down;
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+ };
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+ };
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+
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+};
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+
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+&soc {
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+ gpio_keys {
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+ compatible = "gpio-keys";
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+ pinctrl-0 = <&button_pins>;
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+ pinctrl-names = "default";
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+
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+ button@1 {
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+ label = "reset_button";
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+ linux,code = <KEY_RESTART>;
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+ gpios = <&tlmm 66 GPIO_ACTIVE_LOW>;
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+ linux,input-type = <1>;
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+ debounce-interval = <60>;
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+ };
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+ };
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+
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+ mdio: mdio@90000 {
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+ pinctrl-0 = <&mdio_pins>;
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+ pinctrl-names = "default";
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+ phy-reset-gpio = <&tlmm 37 0 &tlmm 25 1 &tlmm 44 1>;
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+ compatible = "qcom,ipq40xx-mdio", "qcom,qca-mdio";
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+ phy0: ethernet-phy@0 {
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+ reg = <0>;
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+ };
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+ phy1: ethernet-phy@1 {
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+ reg = <1>;
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+ };
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+ phy2: ethernet-phy@2 {
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+ reg = <2>;
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+ };
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+ phy3: ethernet-phy@3 {
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+ reg = <3>;
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+ };
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+ phy4: ethernet-phy@4 {
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+ reg = <24>;
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+ };
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+ phy5: ethernet-phy@5 {
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+ reg = <28>;
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+ };
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+ };
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+
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+ ess-switch@3a000000 {
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+ switch_cpu_bmp = <0x1>; /* cpu port bitmap */
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+ switch_lan_bmp = <0x3e>; /* lan port bitmap */
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+ switch_wan_bmp = <0x40>; /* wan port bitmap */
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+ switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
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+ switch_mac_mode1 = <0xf>; /* mac mode for uniphy instance1*/
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+ switch_mac_mode2 = <0xf>; /* mac mode for uniphy instance2*/
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+ bm_tick_mode = <0>; /* bm tick mode */
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+ tm_tick_mode = <0>; /* tm tick mode */
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+ qcom,port_phyinfo {
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+ port@0 {
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+ port_id = <1>;
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+ phy_address = <0>;
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+ };
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+ port@1 {
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+ port_id = <2>;
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+ phy_address = <1>;
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+ };
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+ port@2 {
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+ port_id = <3>;
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+ phy_address = <2>;
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+ };
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+ port@3 {
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+ port_id = <4>;
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+ phy_address = <3>;
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+ };
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+ port@4 {
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+ port_id = <5>;
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+ phy_address = <24>;
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+ port_mac_sel = "QGMAC_PORT";
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+ };
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+ port@5 {
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+ port_id = <6>;
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+ phy_address = <28>;
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+ port_mac_sel = "QGMAC_PORT";
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+ };
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+ };
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+ port_scheduler_resource {
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+ port@0 {
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+ port_id = <0>;
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+ ucast_queue = <0 143>;
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+ mcast_queue = <256 271>;
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+ l0sp = <0 35>;
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+ l0cdrr = <0 47>;
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+ l0edrr = <0 47>;
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+ l1cdrr = <0 7>;
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+ l1edrr = <0 7>;
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+ };
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+ port@1 {
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+ port_id = <1>;
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+ ucast_queue = <144 159>;
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+ mcast_queue = <272 275>;
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+ l0sp = <36 39>;
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+ l0cdrr = <48 63>;
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+ l0edrr = <48 63>;
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+ l1cdrr = <8 11>;
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+ l1edrr = <8 11>;
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+ };
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+ port@2 {
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+ port_id = <2>;
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+ ucast_queue = <160 175>;
|
|
+ mcast_queue = <276 279>;
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+ l0sp = <40 43>;
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+ l0cdrr = <64 79>;
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+ l0edrr = <64 79>;
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+ l1cdrr = <12 15>;
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+ l1edrr = <12 15>;
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+ };
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+ port@3 {
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+ port_id = <3>;
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+ ucast_queue = <176 191>;
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+ mcast_queue = <280 283>;
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+ l0sp = <44 47>;
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+ l0cdrr = <80 95>;
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+ l0edrr = <80 95>;
|
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+ l1cdrr = <16 19>;
|
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+ l1edrr = <16 19>;
|
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+ };
|
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+ port@4 {
|
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+ port_id = <4>;
|
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+ ucast_queue = <192 207>;
|
|
+ mcast_queue = <284 287>;
|
|
+ l0sp = <48 51>;
|
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+ l0cdrr = <96 111>;
|
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+ l0edrr = <96 111>;
|
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+ l1cdrr = <20 23>;
|
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+ l1edrr = <20 23>;
|
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+ };
|
|
+ port@5 {
|
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+ port_id = <5>;
|
|
+ ucast_queue = <208 223>;
|
|
+ mcast_queue = <288 291>;
|
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+ l0sp = <52 55>;
|
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+ l0cdrr = <112 127>;
|
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+ l0edrr = <112 127>;
|
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+ l1cdrr = <24 27>;
|
|
+ l1edrr = <24 27>;
|
|
+ };
|
|
+ port@6 {
|
|
+ port_id = <6>;
|
|
+ ucast_queue = <224 239>;
|
|
+ mcast_queue = <292 295>;
|
|
+ l0sp = <56 59>;
|
|
+ l0cdrr = <128 143>;
|
|
+ l0edrr = <128 143>;
|
|
+ l1cdrr = <28 31>;
|
|
+ l1edrr = <28 31>;
|
|
+ };
|
|
+ port@7 {
|
|
+ port_id = <7>;
|
|
+ ucast_queue = <240 255>;
|
|
+ mcast_queue = <296 299>;
|
|
+ l0sp = <60 63>;
|
|
+ l0cdrr = <144 159>;
|
|
+ l0edrr = <144 159>;
|
|
+ l1cdrr = <32 35>;
|
|
+ l1edrr = <32 35>;
|
|
+ };
|
|
+ };
|
|
+ port_scheduler_config {
|
|
+ port@0 {
|
|
+ port_id = <0>;
|
|
+ l1scheduler {
|
|
+ group@0 {
|
|
+ sp = <0 1>; /*L0 SPs*/
|
|
+ /*cpri cdrr epri edrr*/
|
|
+ cfg = <0 0 0 0>;
|
|
+ };
|
|
+ };
|
|
+ l0scheduler {
|
|
+ group@0 {
|
|
+ /*unicast queues*/
|
|
+ ucast_queue = <0 4 8>;
|
|
+ /*multicast queues*/
|
|
+ mcast_queue = <256 260>;
|
|
+ /*sp cpri cdrr epri edrr*/
|
|
+ cfg = <0 0 0 0 0>;
|
|
+ };
|
|
+ group@1 {
|
|
+ ucast_queue = <1 5 9>;
|
|
+ mcast_queue = <257 261>;
|
|
+ cfg = <0 1 1 1 1>;
|
|
+ };
|
|
+ group@2 {
|
|
+ ucast_queue = <2 6 10>;
|
|
+ mcast_queue = <258 262>;
|
|
+ cfg = <0 2 2 2 2>;
|
|
+ };
|
|
+ group@3 {
|
|
+ ucast_queue = <3 7 11>;
|
|
+ mcast_queue = <259 263>;
|
|
+ cfg = <0 3 3 3 3>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ port@1 {
|
|
+ port_id = <1>;
|
|
+ l1scheduler {
|
|
+ group@0 {
|
|
+ sp = <36>;
|
|
+ cfg = <0 8 0 8>;
|
|
+ };
|
|
+ group@1 {
|
|
+ sp = <37>;
|
|
+ cfg = <1 9 1 9>;
|
|
+ };
|
|
+ };
|
|
+ l0scheduler {
|
|
+ group@0 {
|
|
+ ucast_queue = <144>;
|
|
+ ucast_loop_pri = <16>;
|
|
+ mcast_queue = <272>;
|
|
+ mcast_loop_pri = <4>;
|
|
+ cfg = <36 0 48 0 48>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ port@2 {
|
|
+ port_id = <2>;
|
|
+ l1scheduler {
|
|
+ group@0 {
|
|
+ sp = <40>;
|
|
+ cfg = <0 12 0 12>;
|
|
+ };
|
|
+ group@1 {
|
|
+ sp = <41>;
|
|
+ cfg = <1 13 1 13>;
|
|
+ };
|
|
+ };
|
|
+ l0scheduler {
|
|
+ group@0 {
|
|
+ ucast_queue = <160>;
|
|
+ ucast_loop_pri = <16>;
|
|
+ mcast_queue = <276>;
|
|
+ mcast_loop_pri = <4>;
|
|
+ cfg = <40 0 64 0 64>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ port@3 {
|
|
+ port_id = <3>;
|
|
+ l1scheduler {
|
|
+ group@0 {
|
|
+ sp = <44>;
|
|
+ cfg = <0 16 0 16>;
|
|
+ };
|
|
+ group@1 {
|
|
+ sp = <45>;
|
|
+ cfg = <1 17 1 17>;
|
|
+ };
|
|
+ };
|
|
+ l0scheduler {
|
|
+ group@0 {
|
|
+ ucast_queue = <176>;
|
|
+ ucast_loop_pri = <16>;
|
|
+ mcast_queue = <280>;
|
|
+ mcast_loop_pri = <4>;
|
|
+ cfg = <44 0 80 0 80>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ port@4 {
|
|
+ port_id = <4>;
|
|
+ l1scheduler {
|
|
+ group@0 {
|
|
+ sp = <48>;
|
|
+ cfg = <0 20 0 20>;
|
|
+ };
|
|
+ group@1 {
|
|
+ sp = <49>;
|
|
+ cfg = <1 21 1 21>;
|
|
+ };
|
|
+ };
|
|
+ l0scheduler {
|
|
+ group@0 {
|
|
+ ucast_queue = <192>;
|
|
+ ucast_loop_pri = <16>;
|
|
+ mcast_queue = <284>;
|
|
+ mcast_loop_pri = <4>;
|
|
+ cfg = <48 0 96 0 96>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ port@5 {
|
|
+ port_id = <5>;
|
|
+ l1scheduler {
|
|
+ group@0 {
|
|
+ sp = <52>;
|
|
+ cfg = <0 24 0 24>;
|
|
+ };
|
|
+ group@1 {
|
|
+ sp = <53>;
|
|
+ cfg = <1 25 1 25>;
|
|
+ };
|
|
+ };
|
|
+ l0scheduler {
|
|
+ group@0 {
|
|
+ ucast_queue = <208>;
|
|
+ ucast_loop_pri = <16>;
|
|
+ mcast_queue = <288>;
|
|
+ mcast_loop_pri = <4>;
|
|
+ cfg = <52 0 112 0 112>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ port@6 {
|
|
+ port_id = <6>;
|
|
+ l1scheduler {
|
|
+ group@0 {
|
|
+ sp = <56>;
|
|
+ cfg = <0 28 0 28>;
|
|
+ };
|
|
+ group@1 {
|
|
+ sp = <57>;
|
|
+ cfg = <1 29 1 29>;
|
|
+ };
|
|
+ };
|
|
+ l0scheduler {
|
|
+ group@0 {
|
|
+ ucast_queue = <224>;
|
|
+ ucast_loop_pri = <16>;
|
|
+ mcast_queue = <292>;
|
|
+ mcast_loop_pri = <4>;
|
|
+ cfg = <56 0 128 0 128>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ port@7 {
|
|
+ port_id = <7>;
|
|
+ l1scheduler {
|
|
+ group@0 {
|
|
+ sp = <60>;
|
|
+ cfg = <0 32 0 32>;
|
|
+ };
|
|
+ };
|
|
+ l0scheduler {
|
|
+ group@0 {
|
|
+ ucast_queue = <240>;
|
|
+ mcast_queue = <296>;
|
|
+ cfg = <60 0 144 0 144>;
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+ };
|
|
+
|
|
+ dp1 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,nss-dp";
|
|
+ qcom,id = <1>;
|
|
+ reg = <0x3a001000 0x200>;
|
|
+ qcom,mactype = <0>;
|
|
+ local-mac-address = [000000000000];
|
|
+ qcom,link-poll = <1>;
|
|
+ qcom,phy-mdio-addr = <0>;
|
|
+ phy-mode = "sgmii";
|
|
+ };
|
|
+
|
|
+ dp2 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,nss-dp";
|
|
+ qcom,id = <2>;
|
|
+ reg = <0x3a001200 0x200>;
|
|
+ qcom,mactype = <0>;
|
|
+ local-mac-address = [000000000000];
|
|
+ qcom,link-poll = <1>;
|
|
+ qcom,phy-mdio-addr = <1>;
|
|
+ phy-mode = "sgmii";
|
|
+ };
|
|
+
|
|
+ dp3 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,nss-dp";
|
|
+ qcom,id = <3>;
|
|
+ reg = <0x3a001400 0x200>;
|
|
+ qcom,mactype = <0>;
|
|
+ local-mac-address = [000000000000];
|
|
+ qcom,link-poll = <1>;
|
|
+ qcom,phy-mdio-addr = <2>;
|
|
+ phy-mode = "sgmii";
|
|
+ };
|
|
+
|
|
+ dp4 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,nss-dp";
|
|
+ qcom,id = <4>;
|
|
+ reg = <0x3a001600 0x200>;
|
|
+ qcom,mactype = <0>;
|
|
+ local-mac-address = [000000000000];
|
|
+ qcom,link-poll = <1>;
|
|
+ qcom,phy-mdio-addr = <3>;
|
|
+ phy-mode = "sgmii";
|
|
+ };
|
|
+
|
|
+ dp5 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,nss-dp";
|
|
+ qcom,id = <5>;
|
|
+ reg = <0x3a001800 0x200>;
|
|
+ qcom,mactype = <0>;
|
|
+ local-mac-address = [000000000000];
|
|
+ qcom,link-poll = <1>;
|
|
+ qcom,phy-mdio-addr = <24>;
|
|
+ phy-mode = "sgmii";
|
|
+ };
|
|
+
|
|
+ dp6 {
|
|
+ device_type = "network";
|
|
+ compatible = "qcom,nss-dp";
|
|
+ qcom,id = <6>;
|
|
+ reg = <0x3a001a00 0x200>;
|
|
+ qcom,mactype = <0>;
|
|
+ local-mac-address = [000000000000];
|
|
+ qcom,link-poll = <1>;
|
|
+ qcom,phy-mdio-addr = <28>;
|
|
+ phy-mode = "sgmii";
|
|
+ };
|
|
+
|
|
+ leds {
|
|
+ compatible = "gpio-leds";
|
|
+ pinctrl-0 = <&led_pins>;
|
|
+ pinctrl-names = "default";
|
|
+
|
|
+ led_power: led_pwr {
|
|
+ label = "green:power";
|
|
+ gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
|
|
+ default-state = "on";
|
|
+ linux,default-trigger = "led_pwr";
|
|
+ };
|
|
+
|
|
+ led_2g {
|
|
+ label = "green:wifi2";
|
|
+ gpio = <&tlmm 47 GPIO_ACTIVE_HIGH>;
|
|
+ default-state = "off";
|
|
+ };
|
|
+
|
|
+ led_5g {
|
|
+ label = "green:wifi5";
|
|
+ gpio = <&tlmm 48 GPIO_ACTIVE_HIGH>;
|
|
+ default-state = "off";
|
|
+ };
|
|
+
|
|
+ led_bt {
|
|
+ gpios = <&tlmm 50 GPIO_ACTIVE_HIGH>;
|
|
+ label = "green:bt";
|
|
+ default-state = "off";
|
|
+ linux,default-trigger = "led_bt";
|
|
+ };
|
|
+ };
|
|
+ nss-macsec0 {
|
|
+ compatible = "qcom,nss-macsec";
|
|
+ phy_addr = <0x18>;
|
|
+ phy_access_mode = <0>;
|
|
+ mdiobus = <&mdio>;
|
|
+ };
|
|
+ nss-macsec1 {
|
|
+ compatible = "qcom,nss-macsec";
|
|
+ phy_addr = <0x1c>;
|
|
+ phy_access_mode = <0>;
|
|
+ mdiobus = <&mdio>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&serial_blsp4 {
|
|
+ pinctrl-0 = <&uart_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&spi_0 { /* BLSP1 QUP1 */
|
|
+ pinctrl-0 = <&spi_0_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ cs-select = <0>;
|
|
+ status = "ok";
|
|
+
|
|
+ m25p80@0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ reg = <0>;
|
|
+ compatible = "n25q128a11";
|
|
+ linux,modalias = "m25p80", "n25q128a11";
|
|
+ spi-max-frequency = <50000000>;
|
|
+ use-default-sizes;
|
|
+ };
|
|
+};
|
|
+
|
|
+&serial_blsp2 {
|
|
+ pinctrl-0 = <&hsuart_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&nss0 {
|
|
+ qcom,low-frequency = <187200000>;
|
|
+ qcom,mid-frequency = <748800000>;
|
|
+ qcom,max-frequency = <1497600000>;
|
|
+};
|
|
+
|
|
+&msm_imem {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&ssphy_0 {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&qusb_phy_0 {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&ssphy_1 {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&qusb_phy_1 {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&usb3_0 {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&usb3_1 {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&cryptobam {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&crypto {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&i2c_0 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&i2c_1 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&qpic_bam {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&nand {
|
|
+ pinctrl-0 = <&qpic_pins>;
|
|
+ pinctrl-names = "default";
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&qpic_lcd {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&qpic_lcd_panel {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&ledc {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&pcie0 {
|
|
+ status = "ok";
|
|
+};
|
|
+
|
|
+&pcie1 {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&glink_rpm {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&apc_cpr {
|
|
+ /* Same CPR configuration as OAK */
|
|
+ compatible = "qcom,cpr4-ipq817x-apss-regulator";
|
|
+
|
|
+ thread@0 {
|
|
+ apc_vreg: regulator {
|
|
+ regulator-min-microvolt = <1>;
|
|
+ regulator-max-microvolt = <2>;
|
|
+ qcom,cpr-fuse-corners = <2>;
|
|
+ qcom,cpr-corners = <3>;
|
|
+ qcom,cpr-speed-bin-corners = <3>;
|
|
+ qcom,cpr-corner-fmax-map = <1 3>;
|
|
+
|
|
+ qcom,cpr-voltage-ceiling =
|
|
+ <840000 904000 944000>;
|
|
+ qcom,cpr-voltage-floor =
|
|
+ <592000 648000 712000>;
|
|
+ qcom,corner-frequencies =
|
|
+ <1017600000 1382400000 1382400000>;
|
|
+
|
|
+ qcom,cpr-open-loop-voltage-fuse-adjustment-0 =
|
|
+ /* Speed bin 0; CPR rev 0..7 */
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>;
|
|
+
|
|
+ qcom,cpr-open-loop-voltage-fuse-adjustment-1 =
|
|
+ /* Speed bin 0; CPR rev 0..7 */
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 20000 26000>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>;
|
|
+
|
|
+ qcom,cpr-open-loop-voltage-fuse-adjustment-v2-0 =
|
|
+ /* Speed bin 0; CPR rev 0..7 */
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>;
|
|
+
|
|
+ qcom,cpr-open-loop-voltage-fuse-adjustment-v2-1 =
|
|
+ /* Speed bin 0; CPR rev 0..7 */
|
|
+ < 0 0>,
|
|
+ < 0 7000>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>,
|
|
+ < 0 0>;
|
|
+
|
|
+ qcom,cpr-floor-to-ceiling-max-range =
|
|
+ < 40000 40000 40000>,
|
|
+ < 40000 40000 40000>,
|
|
+ < 40000 40000 40000>,
|
|
+ < 40000 40000 40000>,
|
|
+ < 40000 40000 40000>,
|
|
+ < 40000 40000 40000>,
|
|
+ < 40000 40000 40000>,
|
|
+ < 40000 40000 40000>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&npu_cpr {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&nss0 {
|
|
+ npu-supply = <&dummy_reg>;
|
|
+ mx-supply = <&dummy_reg>;
|
|
+};
|
|
+
|
|
+&wifi0 {
|
|
+ qcom,board_id = <0x92>;
|
|
+};
|
|
+
|
|
+&wifi1 {
|
|
+ qcom,board_id = <0x292>;
|
|
+};
|
|
diff --git a/target/linux/ipq807x/image/ipq807x.mk b/target/linux/ipq807x/image/ipq807x.mk
|
|
index 9a8cbd8581..d0c02cd803 100644
|
|
--- a/target/linux/ipq807x/image/ipq807x.mk
|
|
+++ b/target/linux/ipq807x/image/ipq807x.mk
|
|
@@ -39,3 +39,13 @@ define Device/cig_wf194
|
|
DEVICE_PACKAGES := ath11k-wifi-cig-wf194c aq-fw-download uboot-envtools
|
|
endef
|
|
TARGET_DEVICES += cig_wf194
|
|
+
|
|
+define Device/edgecore_eap102
|
|
+ DEVICE_TITLE := Edgecore EAP102
|
|
+ DEVICE_DTS := qcom-ipq807x-eap102
|
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+ DEVICE_DTS_DIR := $(DTS_DIR)/qcom
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+ DEVICE_DTS_CONFIG=config@ac02
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+ SUPPORTED_DEVICES := edgecore,eap102
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+ DEVICE_PACKAGES := ath11k-wifi-edgecore-eap102 kmod-usb3 kmod-usb2
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+endef
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+TARGET_DEVICES += edgecore_eap102
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--
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2.25.1
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