wlan-ap-Telecominfraproject/feeds/ipq95xx/mac80211/patches/qca/635-ath12k-fix-enabling-reoq-lut.patch
John Crispin b9b03a6e38 ipq95xx: add Qualcomm wifi-7 support
Signed-off-by: John Crispin <john@phrozen.org>
2023-04-10 14:25:48 +02:00

108 lines
3.9 KiB
Diff

From fd8608ad0b9c008e6b75b21fce979d7aef3a2748 Mon Sep 17 00:00:00 2001
From: Sriram R <quic_srirrama@quicinc.com>
Date: Fri, 13 May 2022 18:30:29 +0530
Subject: [PATCH] ath12k: fix enabling reoq lut
Enable REOQ LUT by setting host service flags and also
LUT feature enable in REO HW register.
Ensure to write the upper 32bits of lut addr in the registers
Signed-off-by: Sriram R <quic_srirrama@quicinc.com>
---
drivers/net/wireless/ath/ath12k/dp.c | 13 ++++++++++---
drivers/net/wireless/ath/ath12k/dp_rx.c | 3 +++
drivers/net/wireless/ath/ath12k/hal.h | 6 ++++++
drivers/net/wireless/ath/ath12k/wmi.c | 1 +
drivers/net/wireless/ath/ath12k/wmi.h | 1 +
5 files changed, 21 insertions(+), 3 deletions(-)
--- a/drivers/net/wireless/ath/ath12k/dp.c
+++ b/drivers/net/wireless/ath/ath12k/dp.c
@@ -1439,8 +1439,7 @@ free:
static int ath12k_dp_reoq_lut_setup(struct ath12k_base *ab)
{
struct ath12k_dp *dp = &ab->dp;
-
- return 0;
+ u32 val;
dp->reoq_lut.vaddr = dma_alloc_coherent(ab->dev,
DP_REOQ_LUT_SIZE,
@@ -1455,7 +1454,15 @@ static int ath12k_dp_reoq_lut_setup(stru
memset(dp->reoq_lut.vaddr, 0, DP_REOQ_LUT_SIZE);
ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_LUT_BASE0,
- dp->reoq_lut.paddr);
+ dp->reoq_lut.paddr >> 8);
+
+ val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR_READ);
+
+ ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_ADDR_READ,
+ val | HAL_REO_QDESC_ADDR_READ_LUT_ENABLE);
+
+ ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + HAL_REO1_QDESC_MAX_PEERID,
+ HAL_REO_QDESC_MAX_PEERID);
return 0;
}
--- a/drivers/net/wireless/ath/ath12k/dp_rx.c
+++ b/drivers/net/wireless/ath/ath12k/dp_rx.c
@@ -19,6 +19,7 @@
#include "dp_tx.h"
#include "peer.h"
#include "dp_mon.h"
+#include "hif.h"
#define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ)
--- a/drivers/net/wireless/ath/ath12k/hal.h
+++ b/drivers/net/wireless/ath/ath12k/hal.h
@@ -40,6 +40,8 @@ struct ath12k_base;
#define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x)))
+#define HAL_REO_QDESC_MAX_PEERID 8191
+
/* WCSS Relative address */
#define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
#define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
@@ -132,6 +134,9 @@ struct ath12k_base;
#define HAL_REO1_SW_COOKIE_CFG1 0x00000054
#define HAL_REO1_QDESC_LUT_BASE0 0x00000058
#define HAL_REO1_QDESC_LUT_BASE1 0x0000005c
+#define HAL_REO1_QDESC_ADDR_READ 0x00000060
+#define HAL_REO1_QDESC_MAX_PEERID 0x0000006c
+
#define HAL_REO1_RING_BASE_LSB 0x000004e4
#define HAL_REO1_RING_BASE_MSB 0x000004e8
#define HAL_REO1_RING_ID 0x000004ec
@@ -308,6 +313,7 @@ struct ath12k_base;
#define HAL_REO1_SW_COOKIE_CFG_ALIGN BIT(18)
#define HAL_REO1_SW_COOKIE_CFG_ENABLE BIT(19)
#define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE BIT(20)
+#define HAL_REO_QDESC_ADDR_READ_LUT_ENABLE BIT(7)
/* CE ring bit field mask and shift */
#define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
--- a/drivers/net/wireless/ath/ath12k/wmi.c
+++ b/drivers/net/wireless/ath/ath12k/wmi.c
@@ -3849,6 +3849,7 @@ ath12k_wmi_copy_resource_config(struct w
wmi_cfg->flags2 = WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_SET;
wmi_cfg->host_service_flags &= ~(1 << WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT);
wmi_cfg->host_service_flags |= 1 << WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT;
+ wmi_cfg->host_service_flags |= 1 << WMI_RSRC_CFG_HOST_SVC_FLAG_REO_QREF_SUPPORT_BIT;
wmi_cfg->ema_max_vap_cnt = tg_cfg->ema_max_vap_cnt;
wmi_cfg->ema_max_profile_period = tg_cfg->ema_max_profile_period;
}
--- a/drivers/net/wireless/ath/ath12k/wmi.h
+++ b/drivers/net/wireless/ath/ath12k/wmi.h
@@ -2395,6 +2395,7 @@ struct wmi_init_cmd {
} __packed;
#define WMI_RSRC_CFG_HOST_SVC_FLAG_REG_CC_EXT_SUPPORT_BIT 4
+#define WMI_RSRC_CFG_HOST_SVC_FLAG_REO_QREF_SUPPORT_BIT 12
#define WMI_RSRC_CFG_FLAGS2_CALC_NEXT_DTIM_COUNT_SET BIT(9)
struct wmi_resource_config {