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https://github.com/Telecominfraproject/wlan-ap.git
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49 lines
1.4 KiB
Diff
49 lines
1.4 KiB
Diff
From e9529ab46677d2b5a525bfea17b077d1737829d9 Mon Sep 17 00:00:00 2001
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From: Devi Priya <quic_devipriy@quicinc.com>
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Date: Mon, 20 Nov 2023 21:42:14 +0530
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Subject: [PATCH] clk: qcom: clk-rcg2: Fix clock rate overflow for high parent
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frequencies
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If the parent clock rate is greater than unsigned long max/2 then
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integer overflow happens when calculating the clock rate on 32-bit systems.
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As RCG2 uses half integer dividers, the clock rate is first being
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multiplied by 2 which will overflow the unsigned long max value.
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Hence, replace the common pattern of doing 64-bit multiplication
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and then a do_div() call with simpler mult_frac call.
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Change-Id: Ib14685ec025539e4e15b5485594ab75802945936
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Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
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---
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drivers/clk/qcom/clk-rcg2.c | 14 ++++----------
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1 file changed, 4 insertions(+), 10 deletions(-)
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diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
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index 8c340d3f87b1..27806ae151f8 100644
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--- a/drivers/clk/qcom/clk-rcg2.c
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+++ b/drivers/clk/qcom/clk-rcg2.c
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@@ -158,17 +158,11 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
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static unsigned long
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calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
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{
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- if (hid_div) {
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- rate *= 2;
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- rate /= hid_div + 1;
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- }
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+ if (hid_div)
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+ rate = mult_frac(rate, 2, hid_div + 1);
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- if (mode) {
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- u64 tmp = rate;
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- tmp *= m;
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- do_div(tmp, n);
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- rate = tmp;
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- }
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+ if (mode)
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+ rate = mult_frac(rate, m, n);
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return rate;
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}
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--
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2.34.1
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