mirror of
https://github.com/Telecominfraproject/wlan-ap.git
synced 2025-12-17 09:21:35 +00:00
132 lines
4.5 KiB
Diff
132 lines
4.5 KiB
Diff
From 4dce3ecf40589410905f76b73aa54cc7586c66a8 Mon Sep 17 00:00:00 2001
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From: Shradha Todi <shradha.t@samsung.com>
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Date: Wed, 22 Jun 2022 21:21:58 +0530
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Subject: [PATCH] PCI: dwc: Add support for vendor specific capability search
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and create debugfs files in DWC driver
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Add vendor specific extended configuration space capability search API
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using struct dw_pcie pointer for DW controllers.
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Add call to create_debugfs_files() from DWC driver to create the RASDES
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debugfs structure for each platform driver. Since it can be used for
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both DW HOST controller as well as DW EP controller, let's add it in the
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common setup function.
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Change-Id: I6c4e38e0efda4b21c20084b91e8754205859b988
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Signed-off-by: Shradha Todi <shradha.t@samsung.com>
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Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
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Signed-off-by: Omeshwari Wazekar <quic_owazekar@quicinc.com>
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---
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drivers/pci/controller/dwc/Kconfig | 8 ++++++++
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drivers/pci/controller/dwc/Makefile | 1 +
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drivers/pci/controller/dwc/pcie-designware.c | 20 ++++++++++++++++++++
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drivers/pci/controller/dwc/pcie-designware.h | 5 +++++
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4 files changed, 34 insertions(+)
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diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig
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index ae9d083c406f..a4905735eec3 100644
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--- a/drivers/pci/controller/dwc/Kconfig
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+++ b/drivers/pci/controller/dwc/Kconfig
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@@ -6,6 +6,14 @@ menu "DesignWare PCI Core Support"
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config PCIE_DW
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bool
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+config PCIE_DW_DEBUGFS
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+ bool "DWC PCIe debugfs entries"
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+ help
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+ Enables debugfs entries for the DWC PCIe Controller.
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+ These entries make use of the RAS DES features in the DW
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+ controller to help in debug, error injection and statistical
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+ counters
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+
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config PCIE_DW_HOST
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bool
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select PCIE_DW
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diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
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index 8ba7b67f5e50..0109ccf25d5a 100644
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--- a/drivers/pci/controller/dwc/Makefile
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+++ b/drivers/pci/controller/dwc/Makefile
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@@ -1,5 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PCIE_DW) += pcie-designware.o
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+obj-$(CONFIG_PCIE_DW_DEBUGFS) += pcie-designware-debugfs.o
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obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
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obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
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obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
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diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
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index 575834cae3b9..446057ad53a8 100644
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--- a/drivers/pci/controller/dwc/pcie-designware.c
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+++ b/drivers/pci/controller/dwc/pcie-designware.c
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@@ -18,6 +18,7 @@
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#include "../../pci.h"
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#include "pcie-designware.h"
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+#include "pcie-designware-debugfs.h"
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void dw_pcie_version_detect(struct dw_pcie *pci)
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{
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@@ -117,6 +118,22 @@ static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
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return 0;
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}
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+u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u8 vsec_cap)
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+{
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+ u16 vsec = 0;
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+ u32 header;
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+
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+ while ((vsec = dw_pcie_find_next_ext_capability(pci, vsec,
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+ PCI_EXT_CAP_ID_VNDR))) {
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+ header = dw_pcie_readl_dbi(pci, vsec + PCI_VNDR_HEADER);
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+ if (PCI_VNDR_HEADER_ID(header) == vsec_cap)
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+ return vsec;
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+ }
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+
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+ return 0;
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+}
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+EXPORT_SYMBOL_GPL(dw_pcie_find_vsec_capability);
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+
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u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
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{
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return dw_pcie_find_next_ext_capability(pci, 0, cap);
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@@ -703,4 +720,7 @@ void dw_pcie_setup(struct dw_pcie *pci)
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break;
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}
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dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
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+
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+ if (create_debugfs_files(pci))
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+ dev_err(pci->dev, "Couldn't create debugfs files\n");
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}
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diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
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index a871ae7eb59e..5e87785b5e07 100644
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--- a/drivers/pci/controller/dwc/pcie-designware.h
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+++ b/drivers/pci/controller/dwc/pcie-designware.h
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@@ -211,6 +211,9 @@
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#define MAX_IATU_IN 256
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#define MAX_IATU_OUT 256
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+/* Synopsys Vendor specific data */
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+#define DW_PCIE_RAS_CAP_ID 0x2
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+
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struct dw_pcie;
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struct dw_pcie_rp;
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struct dw_pcie_ep;
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@@ -321,6 +324,7 @@ struct dw_pcie {
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int link_gen;
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u8 n_fts[2];
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bool iatu_unroll_enabled: 1;
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+ u32 ras_cap_offset;
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};
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#define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp)
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@@ -332,6 +336,7 @@ void dw_pcie_version_detect(struct dw_pcie *pci);
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u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
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u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
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+u16 dw_pcie_find_vsec_capability(struct dw_pcie *pci, u8 vsec_cap);
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int dw_pcie_read(void __iomem *addr, int size, u32 *val);
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int dw_pcie_write(void __iomem *addr, int size, u32 val);
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--
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2.34.1
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