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Merge Official Source

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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2025-09-12 16:32:31 +08:00
commit f5945c9cb5
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GPG Key ID: 6850B6345C862176
95 changed files with 4710 additions and 681 deletions
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40
package/boot/arm-trusted-firmware-rockchip/Makefile
View File

@ -9,9 +9,9 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL:=https://github.com/rockchip-linux/rkbin.git
PKG_SOURCE_DATE:=2025-01-24
PKG_SOURCE_VERSION:=f43a462e7a1429a9d407ae52b4745033034a6cf9
PKG_MIRROR_HASH:=97f899f37f7996e62e8f9dd72e732ea74dd1d553796a863b1533a0d3d6f0c62b
PKG_SOURCE_DATE:=2025-06-13
PKG_SOURCE_VERSION:=74213af1e952c4683d2e35952507133b61394862
PKG_MIRROR_HASH:=4b801b1301ae297f660340617b5f398b23a3f0b43bc7f0ef42c21f0f43eb8990
PKG_MAINTAINER:=Tianling Shen <cnsztl@immortalwrt.org>
@ -30,10 +30,9 @@ define Trusted-Firmware-A/rk3308
TPL:=rk33/$(RK3308_TPL)
endef
define Trusted-Firmware-A/rk3308-rock-pi-s
define Trusted-Firmware-A/rk3308-tpl-rock-pi-s
NAME:=Radxa ROCK Pi S board
BUILD_SUBTARGET:=armv8
ATF:=rk33/$(RK3308_ATF)
TPL:=rk33/$(RK3308_TPL_ROCK_PI_S)
endef
@ -63,10 +62,9 @@ define Trusted-Firmware-A/rk3568
TPL:=rk35/$(RK3568_TPL)
endef
define Trusted-Firmware-A/rk3568-e25
define Trusted-Firmware-A/rk3568-tpl-e25
NAME:=Radxa E25 board
BUILD_SUBTARGET:=armv8
ATF:=rk35/$(RK3568_ATF)
TPL:=rk35/$(RK3568_TPL_E25)
endef
@ -78,41 +76,43 @@ endef
TFA_TARGETS:= \
rk3308 \
rk3308-rock-pi-s \
rk3308-tpl-rock-pi-s \
rk3328 \
rk3399 \
rk3566 \
rk3568 \
rk3568-e25 \
rk3568-tpl-e25 \
rk3588
ifeq ($(BUILD_VARIANT),rk3308-rock-pi-s)
ifeq ($(BUILD_VARIANT),rk3308-tpl-rock-pi-s)
define Download/rk3308-tpl-rock-pi-s
FILE:=$(RK3308_TPL_ROCK_PI_S)
URL:=https://github.com/radxa/rkbin/raw/5696fab20dcac57c1458f72dc7604ba60e553adf/bin/rk33/
HASH:=8a1a42df23cccb86a2dabc14a5c0e9227d64a51b9b83e9968ef5af3b30787f7d
FILE:=$(notdir $(TPL))
URL_FILE:=$(TPL)
URL:=https://github.com/radxa/rkbin/raw/2b54df9d062ef91a9fffbc85472b070c9220c4cf/bin/
HASH:=45af030ed2cb322cc5a91c32350130fc1f1ea9508794fa4b5d309eadf70e3d04
endef
define Build/Prepare
$(eval $(call Download,rk3308-tpl-rock-pi-s))
$(call Build/Prepare/Default)
$(CP) $(DL_DIR)/$(RK3308_TPL_ROCK_PI_S) $(PKG_BUILD_DIR)/bin/rk33/
$(CP) $(DL_DIR)/$(notdir $(TPL)) $(PKG_BUILD_DIR)/bin/$(TPL)
endef
endif
ifeq ($(BUILD_VARIANT),rk3568-e25)
ifeq ($(BUILD_VARIANT),rk3568-tpl-e25)
define Download/rk3568-tpl-e25
FILE:=$(RK3568_TPL_E25)
URL:=https://github.com/radxa/rkbin/raw/5696fab20dcac57c1458f72dc7604ba60e553adf/bin/rk35/
HASH:=1815f9649dc5661a3ef184b052da39286e51453a66f6ff53cc3e345d65dfabd4
FILE:=$(notdir $(TPL))
URL_FILE:=$(TPL)
URL:=https://github.com/radxa/rkbin/raw/2e77c53ab0279585b09ecdaa54fe3e2bf80f9475/bin/
HASH:=1bb9f92a6515a70b91c0f8bd3aa4dc31432afc4317b9408f82c43ca63cb10ab6
endef
define Build/Prepare
$(eval $(call Download,rk3568-tpl-e25))
$(call Build/Prepare/Default)
$(CP) $(DL_DIR)/$(RK3568_TPL_E25) $(PKG_BUILD_DIR)/bin/rk35/
$(CP) $(DL_DIR)/$(notdir $(TPL)) $(PKG_BUILD_DIR)/bin/$(TPL)
endef
endif
@ -135,7 +135,9 @@ endef
define Package/trusted-firmware-a/install
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
ifneq ($(ATF),)
$(CP) $(PKG_BUILD_DIR)/bin/$(ATF) $(STAGING_DIR_IMAGE)/
endif
ifneq ($(LOADER),)
$(CP) $(PKG_BUILD_DIR)/tools/loaderimage $(STAGING_DIR_IMAGE)/
$(CP) $(PKG_BUILD_DIR)/$(BUILD_VARIANT)-idbloader.bin $(STAGING_DIR_IMAGE)/

14
package/boot/arm-trusted-firmware-rockchip/atf-version.mk
View File

@ -1,6 +1,6 @@
RK3308_ATF:=rk3308_bl31_v2.26.elf
RK3308_ATF:=rk3308_bl31_v2.27.elf
RK3308_TPL:=rk3308_ddr_589MHz_uart2_m1_v2.10.bin
RK3308_TPL_ROCK_PI_S:=rk3308_ddr_589MHz_uart0_m0_v2.07.bin
RK3308_TPL_ROCK_PI_S:=rk3308_ddr_589MHz_uart0_m0_v2.10.bin
RK3328_ATF:=rk322xh_bl31_v1.49.elf
RK3328_TPL:=rk3328_ddr_333MHz_v1.21.bin
@ -10,12 +10,12 @@ RK3399_ATF:=rk3399_bl31_v1.36.elf
RK3399_TPL:=rk3399_ddr_800MHz_v1.30.bin
RK3399_LOADER:=rk3399_miniloader_v1.30.bin
RK3566_ATF:=rk3568_bl31_v1.44.elf
RK3566_ATF:=rk3568_bl31_v1.45.elf
RK3566_TPL:=rk3566_ddr_1056MHz_v1.23.bin
RK3568_ATF:=rk3568_bl31_v1.44.elf
RK3568_ATF:=rk3568_bl31_v1.45.elf
RK3568_TPL:=rk3568_ddr_1560MHz_v1.23.bin
RK3568_TPL_E25:=rk3568_ddr_1560MHz_uart2_m0_115200_v1.21.bin
RK3568_TPL_E25:=rk3568_ddr_1560MHz_uart2_m0_115200_v1.23.bin
RK3588_ATF:=rk3588_bl31_v1.48.elf
RK3588_TPL:=rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.18.bin
RK3588_ATF:=rk3588_bl31_v1.51.elf
RK3588_TPL:=rk3588_ddr_lp4_2112MHz_lp5_2400MHz_v1.19.bin

4
package/boot/uboot-rockchip/Makefile
View File

@ -36,7 +36,7 @@ endef
define U-Boot/rock-pi-s-rk3308
$(U-Boot/rk3308/Default)
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3308-rock-pi-s
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3308-tpl-rock-pi-s
TPL:=$(RK3308_TPL_ROCK_PI_S)
NAME:=ROCK Pi S
BUILD_DEVICES:= \
@ -287,7 +287,7 @@ endef
define U-Boot/radxa-e25-rk3568
$(U-Boot/rk3568/Default)
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568-e25
DEPENDS:=+PACKAGE_u-boot-$(1):trusted-firmware-a-rk3568-tpl-e25
TPL:=$(RK3568_TPL_E25)
NAME:=E25
BUILD_DEVICES:= \

124
package/boot/uboot-rockchip/patches/100-board-rockchip-add-Lunzn-FastRhino-R66S.patch Normal file
View File

@ -0,0 +1,124 @@
From 03610008ce31b7a780b7864a0a916d945b7234ba Mon Sep 17 00:00:00 2001
From: Tianling Shen <cnsztl@gmail.com>
Date: Mon, 8 Sep 2025 19:29:55 +0800
Subject: [PATCH] board: rockchip: add Lunzn FastRhino R66S
Lunzn Fastrhino R66S is a high-performance mini router.
Specification:
- Rockchip RK3568
- 1/2GB LPDDR4 RAM
- SD card slot
- 2x USB 3.0 Port
- 2x 2500 Base-T (PCIe, r8125b)
- 12v DC Jack
Signed-off-by: Tianling Shen <cnsztl@gmail.com>
---
.../arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi | 3 +
board/rockchip/evb_rk3568/MAINTAINERS | 7 ++
configs/fastrhino-r66s-rk3568_defconfig | 64 +++++++++++++++++++
doc/board/rockchip/rockchip.rst | 1 +
4 files changed, 75 insertions(+)
create mode 100644 arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
create mode 100644 configs/fastrhino-r66s-rk3568_defconfig
--- /dev/null
+++ b/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
@@ -0,0 +1,3 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include "rk356x-u-boot.dtsi"
--- a/board/rockchip/evb_rk3568/MAINTAINERS
+++ b/board/rockchip/evb_rk3568/MAINTAINERS
@@ -14,6 +14,13 @@ F: configs/evb-rk3568_defconfig
F: arch/arm/dts/rk3568-evb-u-boot.dtsi
F: arch/arm/dts/rk3568-evb.dts
+FASTRHINO-R66S-RK3568
+M: Tianling Shen <cnsztl@gmail.com>
+R: Jonas Karlman <jonas@kwiboo.se>
+S: Maintained
+F: configs/fastrhino-r66s-rk3568_defconfig
+F: arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
+
GENERIC-RK3568
M: Jonas Karlman <jonas@kwiboo.se>
S: Maintained
--- /dev/null
+++ b/configs/fastrhino-r66s-rk3568_defconfig
@@ -0,0 +1,64 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_SYS_HAS_NONCACHED_MEMORY=y
+CONFIG_COUNTER_FREQUENCY=24000000
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-fastrhino-r66s"
+CONFIG_ROCKCHIP_RK3568=y
+CONFIG_SPL_SERIAL=y
+CONFIG_SYS_LOAD_ADDR=0xc00800
+CONFIG_DEBUG_UART_BASE=0xFE660000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_PCI=y
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_FIT_SIGNATURE=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb"
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_MAX_SIZE=0x40000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_SPL_ATF=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_PMIC=y
+CONFIG_CMD_REGULATOR=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_CLK=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_MISC=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_RTL8169=y
+CONFIG_PCIE_DW_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_SPL_RAM=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYS_NS16550_MEM32=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_ERRNO_STR=y
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -128,6 +128,7 @@ List of mainline supported Rockchip boar
- FriendlyElec NanoPi R5S (nanopi-r5s-rk3568)
- Generic RK3566/RK3568 (generic-rk3568)
- Hardkernel ODROID-M1 (odroid-m1-rk3568)
+ - Lunzn FastRhino R66S (fastrhino-r66s-rk3568)
- QNAP TS-433 (qnap-ts433-rk3568)
- Radxa E25 Carrier Board (radxa-e25-rk3568)
- Radxa ROCK 3A (rock-3a-rk3568)

2
package/boot/uboot-rockchip/patches/111-rockchip-rk3588-generic-Enable-support-for-RK3582.patch
View File

@ -61,7 +61,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
CONFIG_SPL_MAX_SIZE=0x40000
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -145,7 +145,7 @@ List of mainline supported Rockchip boar
@@ -146,7 +146,7 @@ List of mainline supported Rockchip boar
- FriendlyElec NanoPC-T6 (nanopc-t6-rk3588)
- FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
- FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)

17
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r66s-u-boot.dtsi
View File

@ -1,17 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk356x-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdmmc0;
};
};
&pcie3x1 {
/delete-property/ vpcie3v3-supply;
};
&pcie3x2 {
/delete-property/ vpcie3v3-supply;
};

8
package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-fastrhino-r68s-u-boot.dtsi
View File

@ -1,12 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "rk3568-fastrhino-r66s-u-boot.dtsi"
/ {
chosen {
u-boot,spl-boot-order = "same-as-spl", &sdhci;
};
};
#include "rk356x-u-boot.dtsi"
&i2c0 {
bootph-pre-ram;

73
package/boot/uboot-rockchip/src/configs/fastrhino-r66s-rk3568_defconfig
View File

@ -1,73 +0,0 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_HAS_NONCACHED_MEMORY=y
CONFIG_COUNTER_FREQUENCY=24000000
CONFIG_ARCH_ROCKCHIP=y
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-fastrhino-r66s"
CONFIG_ROCKCHIP_RK3568=y
CONFIG_SPL_SERIAL=y
CONFIG_DEBUG_UART_BASE=0xFE660000
CONFIG_DEBUG_UART_CLOCK=24000000
CONFIG_SYS_LOAD_ADDR=0xc00800
CONFIG_PCI=y
CONFIG_DEBUG_UART=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-fastrhino-r66s.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_SPL_MAX_SIZE=0x40000
CONFIG_SPL_PAD_TO=0x7f8000
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
CONFIG_SPL_ATF=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_SPL_REGMAP=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_CLK=y
CONFIG_ROCKCHIP_GPIO=y
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_MISC=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_SDMA=y
CONFIG_MMC_SDHCI_ROCKCHIP=y
CONFIG_RTL8169=y
CONFIG_PCIE_DW_ROCKCHIP=y
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_RK8XX=y
CONFIG_REGULATOR_RK8XX=y
CONFIG_PWM_ROCKCHIP=y
CONFIG_SPL_RAM=y
CONFIG_BAUDRATE=1500000
CONFIG_DEBUG_UART_SHIFT=2
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SYSRESET=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_OHCI_GENERIC=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GENERIC=y
CONFIG_ERRNO_STR=y

3
package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic
View File

@ -138,8 +138,7 @@ ubnt,unifi-6-plus)
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x80000" "0x10000"
;;
teltonika,rutc50)
local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x0" "0x10000" "0x10000"
ubootenv_add_mtd "u-boot-env" "0x0" "0x10000" "0x10000"
;;
xiaomi,mi-router-ax3000t|\
xiaomi,mi-router-wr30u-stock|\

4
package/boot/uboot-tools/uboot-envtools/files/qualcommax_ipq50xx
View File

@ -26,9 +26,7 @@ xiaomi,ax6000)
ubootenv_add_sys_mtd "bdata" "0x0" "0x10000" "0x20000"
;;
yuncore,ax830)
idx="$(find_mtd_index 0:APPSBLENV)"
[ -n "$idx" ] && \
ubootenv_add_uci_config "/dev/mtd$idx" "0x0" "0x10000" "0x10000"
ubootenv_add_mtd "0:APPSBLENV" "0x0" "0x10000" "0x10000"
;;
esac

4
package/kernel/r8125/Makefile
View File

@ -1,12 +1,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=r8125
PKG_VERSION:=9.016.00
PKG_VERSION:=9.016.01
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://github.com/openwrt/rtl8125/releases/download/$(PKG_VERSION)
PKG_HASH:=cd1955dd07d2f5a6faaa210ffc4e8af992421295a32ab6ddcfa759bed9eba922
PKG_HASH:=5434b26500538a62541c55cd09eea099177f59bd9cc48d16969089a9bcdbbd41
PKG_BUILD_PARALLEL:=1
PKG_LICENSE:=GPLv2

4
package/kernel/r8125/patches/110-r8125-print-link-speed-and-duplex-mode.patch
View File

@ -38,7 +38,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
@@ -5045,6 +5046,38 @@ rtl8125_link_down_patch(struct net_devic
@@ -5051,6 +5052,38 @@ rtl8125_link_down_patch(struct net_devic
#endif
}
@ -77,7 +77,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
static void
_rtl8125_check_link_status(struct net_device *dev, unsigned int link_state)
{
@@ -5057,11 +5090,18 @@ _rtl8125_check_link_status(struct net_de
@@ -5063,11 +5096,18 @@ _rtl8125_check_link_status(struct net_de
if (link_state == R8125_LINK_STATE_ON) {
rtl8125_link_on_patch(dev);

4
package/kernel/r8125/patches/120-add-LED-configuration-from-OF.patch
View File

@ -8,7 +8,7 @@
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/interrupt.h>
@@ -14807,6 +14808,25 @@ rtl8125_restore_phy_fuse_dout(struct rtl
@@ -14800,6 +14801,25 @@ rtl8125_restore_phy_fuse_dout(struct rtl
return;
}
@ -34,7 +34,7 @@
static void
rtl8125_init_software_variable(struct net_device *dev)
{
@@ -15309,6 +15329,7 @@ rtl8125_init_software_variable(struct ne
@@ -15316,6 +15336,7 @@ rtl8125_init_software_variable(struct ne
else if (tp->InitRxDescType == RX_DESC_RING_TYPE_4)
tp->rtl8125_rx_config &= ~EnableRxDescV4_1;

4
package/kernel/r8125/patches/130-add-devname-configuration-from-OF.patch
View File

@ -1,6 +1,6 @@
--- a/src/r8125_n.c
+++ b/src/r8125_n.c
@@ -16360,6 +16360,7 @@ rtl8125_init_board(struct pci_dev *pdev,
@@ -16367,6 +16367,7 @@ rtl8125_init_board(struct pci_dev *pdev,
void __iomem *ioaddr;
struct net_device *dev;
struct rtl8125_private *tp;
@ -8,7 +8,7 @@
int rc = -ENOMEM, i, pm_cap;
assert(ioaddr_out != NULL);
@@ -16374,6 +16375,9 @@ rtl8125_init_board(struct pci_dev *pdev,
@@ -16381,6 +16382,9 @@ rtl8125_init_board(struct pci_dev *pdev,
goto err_out;
}

6
package/kernel/r8126/Makefile
View File

@ -1,12 +1,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=r8126
PKG_VERSION:=10.015.00
PKG_RELEASE:=3
PKG_VERSION:=10.016.00
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://github.com/openwrt/rtl8126/releases/download/$(PKG_VERSION)
PKG_HASH:=fac513aa925264a95b053e7532fcda56022d29db288f6625fafee2759a8a6124
PKG_HASH:=50c8d3d49592d2e8f372bd7ece8e7df9b50a71b055c077d42eacc42302914440
PKG_BUILD_PARALLEL:=1
PKG_LICENSE:=GPLv2

8
package/kernel/r8126/patches/110-r8126-print-link-speed-and-duplex-mode.patch
View File

@ -18,7 +18,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
--- a/src/r8126.h
+++ b/src/r8126.h
@@ -1756,6 +1756,10 @@ enum RTL8126_register_content {
@@ -1752,6 +1752,10 @@ enum RTL8126_register_content {
LinkStatus = 0x02,
FullDup = 0x01,
@ -39,8 +39,8 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
@@ -4661,6 +4662,40 @@ rtl8126_link_down_patch(struct net_devic
#endif
@@ -4410,6 +4411,40 @@ rtl8126_link_down_patch(struct net_devic
//rtl8126_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising);
}
+static unsigned int rtl8126_phy_duplex(u32 status)
@ -80,7 +80,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
static void
_rtl8126_check_link_status(struct net_device *dev, unsigned int link_state)
{
@@ -4673,11 +4708,18 @@ _rtl8126_check_link_status(struct net_de
@@ -4422,11 +4457,18 @@ _rtl8126_check_link_status(struct net_de
if (link_state == R8126_LINK_STATE_ON) {
rtl8126_link_on_patch(dev);

4
package/kernel/r8126/patches/120-add-LED-configuration-from-OF.patch
View File

@ -8,7 +8,7 @@
#include <linux/if_vlan.h>
#include <linux/crc32.h>
#include <linux/interrupt.h>
@@ -11910,6 +11911,25 @@ rtl8126_setup_mqs_reg(struct rtl8126_pri
@@ -11708,6 +11709,25 @@ rtl8126_setup_mqs_reg(struct rtl8126_pri
tp->imr_reg[i] = (u16)(IMR1_8125 + (i - 1) * 4);
}
@ -34,7 +34,7 @@
static void
rtl8126_init_software_variable(struct net_device *dev)
{
@@ -12188,6 +12208,8 @@ rtl8126_init_software_variable(struct ne
@@ -11938,6 +11958,8 @@ rtl8126_init_software_variable(struct ne
else if (tp->InitRxDescType == RX_DESC_RING_TYPE_4)
tp->rtl8126_rx_config &= ~EnableRxDescV4_1;

4
package/kernel/r8126/patches/130-add-devname-configuration-from-OF.patch
View File

@ -1,6 +1,6 @@
--- a/src/r8126_n.c
+++ b/src/r8126_n.c
@@ -13226,6 +13226,7 @@ rtl8126_init_board(struct pci_dev *pdev,
@@ -12937,6 +12937,7 @@ rtl8126_init_board(struct pci_dev *pdev,
void __iomem *ioaddr;
struct net_device *dev;
struct rtl8126_private *tp;
@ -8,7 +8,7 @@
int rc = -ENOMEM, i, pm_cap;
assert(ioaddr_out != NULL);
@@ -13240,6 +13241,9 @@ rtl8126_init_board(struct pci_dev *pdev,
@@ -12951,6 +12952,9 @@ rtl8126_init_board(struct pci_dev *pdev,
goto err_out;
}

6
package/kernel/r8127/Makefile
View File

@ -1,12 +1,12 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=r8127
PKG_VERSION:=11.014.00
PKG_RELEASE:=3
PKG_VERSION:=11.015.00
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://github.com/openwrt/rtl8127/releases/download/$(PKG_VERSION)
PKG_HASH:=f496bc16c32d2e8f9482c57d006604c70d9e8d55b4f1f999b88c602de9104094
PKG_HASH:=ab21bf69368fb9de7f591b2e81cf1a815988bbf086ecbf41af7de9787b10594b
PKG_BUILD_PARALLEL:=1
PKG_LICENSE:=GPLv2

6
package/kernel/r8127/patches/200-r8127-print-link-speed-and-duplex-mode.patch
View File

@ -18,7 +18,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
--- a/src/r8127.h
+++ b/src/r8127.h
@@ -1753,6 +1753,11 @@ enum RTL8127_register_content {
@@ -1770,6 +1770,11 @@ enum RTL8127_register_content {
LinkStatus = 0x02,
FullDup = 0x01,
@ -40,7 +40,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/delay.h>
@@ -4746,6 +4747,42 @@ rtl8127_link_down_patch(struct net_devic
@@ -4734,6 +4735,42 @@ rtl8127_link_down_patch(struct net_devic
#endif
}
@ -83,7 +83,7 @@ Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
static void
_rtl8127_check_link_status(struct net_device *dev, unsigned int link_state)
{
@@ -4758,11 +4795,18 @@ _rtl8127_check_link_status(struct net_de
@@ -4746,11 +4783,18 @@ _rtl8127_check_link_status(struct net_de
if (link_state == R8127_LINK_STATE_ON) {
rtl8127_link_on_patch(dev);

2
package/kernel/r8168/Makefile
View File

@ -2,7 +2,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=r8168
PKG_VERSION:=8.055.00
PKG_RELEASE:=3
PKG_RELEASE:=4
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:=https://github.com/openwrt/rtl8168/releases/download/$(PKG_VERSION)

4
package/libs/libxml2/Makefile
View File

@ -2,14 +2,14 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=libxml2
PKG_VERSION:=2.14.5
PKG_RELEASE:=1
PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@GNOME/libxml2/$(basename $(PKG_VERSION))
PKG_HASH:=03d006f3537616833c16c53addcdc32a0eb20e55443cba4038307e3fa7d8d44b
PKG_LICENSE:=MIT
PKG_LICENSE_FILES:=COPYING
PKG_LICENSE_FILES:=Copyright
PKG_CPE_ID:=cpe:/a:xmlsoft:libxml2
HOST_BUILD_DEPENDS := libiconv-full/host

4
package/libs/openssl/Makefile
View File

@ -9,7 +9,7 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=openssl
PKG_VERSION:=3.5.2
PKG_RELEASE:=1
PKG_RELEASE:=2
PKG_BUILD_FLAGS:=no-mips16 gc-sections no-lto
PKG_BUILD_PARALLEL:=1
@ -24,7 +24,7 @@ PKG_SOURCE_URL:= \
PKG_HASH:=c53a47e5e441c930c3928cf7bf6fb00e5d129b630e0aa873b08258656e7345ec
PKG_LICENSE:=Apache-2.0
PKG_LICENSE_FILES:=LICENSE
PKG_LICENSE_FILES:=LICENSE.txt
PKG_MAINTAINER:=Eneas U de Queiroz <cotequeiroz@gmail.com>
PKG_CPE_ID:=cpe:/a:openssl:openssl
PKG_CONFIG_DEPENDS:= \

4
package/network/utils/ethtool/Makefile
View File

@ -8,13 +8,13 @@
include $(TOPDIR)/rules.mk
PKG_NAME:=ethtool
PKG_VERSION:=6.14
PKG_VERSION:=6.15
PKG_RELEASE:=1
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@KERNEL/software/network/ethtool
PKG_HASH:=9338bb00e492878d3bbe3cd2894e60db35813634c208db0b20f5c7ee84da69b1
PKG_HASH:=9477c365114d910120aaec5336a1d16196c833d8486f7c6da67bedef57880ade
PKG_LICENSE:=GPL-2.0
PKG_LICENSE_FILES:=COPYING

6
package/network/utils/ethtool/patches/0001-ethtool-make-building-for-RSS-input-xfrm-optional.patch
View File

@ -37,7 +37,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
[Install the bash-completion script in this directory. @<:@default=yes@:>@]),
--- a/ethtool.c
+++ b/ethtool.c
@@ -4114,7 +4114,7 @@ static int do_grxfh(struct cmd_context *
@@ -4170,7 +4170,7 @@ static int do_grxfh(struct cmd_context *
}
if (rss->hfunc)
printf(" Unknown hash function: 0x%x\n", rss->hfunc);
@ -46,7 +46,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
printf("RSS input transformation:\n");
printf(" symmetric-xor: %s\n",
(rss->input_xfrm & RXH_XFRM_SYM_XOR) ? "on" : "off");
@@ -4123,6 +4123,7 @@ static int do_grxfh(struct cmd_context *
@@ -4182,6 +4182,7 @@ static int do_grxfh(struct cmd_context *
if (rss->input_xfrm)
printf(" Unknown bits in RSS input transformation: 0x%x\n",
rss->input_xfrm);
@ -54,7 +54,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
out:
free(hfuncs);
@@ -4442,7 +4443,15 @@ static int do_srxfh(struct cmd_context *
@@ -4503,7 +4504,15 @@ static int do_srxfh(struct cmd_context *
rss->cmd = ETHTOOL_SRSSH;
rss->rss_context = rss_context;
rss->hfunc = req_hfunc;

9
target/linux/ath79/dts/ar7240_netgear_wnr1000-v2.dts
View File

@ -190,6 +190,10 @@
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0x200>;
};
};
};
};
@ -214,9 +218,8 @@
ath9k: wifi@0,0 {
compatible = "pci168c,002b";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&macaddr_art_0 1>;
nvmem-cell-names = "mac-address";
qca,no-eeprom;
nvmem-cells = <&macaddr_art_0 1>, <&calibration_art_1000>;
nvmem-cell-names = "mac-address", "calibration";
#gpio-cells = <2>;
gpio-controller;
};

9
target/linux/ath79/dts/ar7240_netgear_wnr612-v2.dtsi
View File

@ -120,6 +120,10 @@
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0x200>;
};
};
};
};
@ -144,9 +148,8 @@
ath9k: wifi@0,0 {
compatible = "pci168c,002b";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&macaddr_art_0 1>;
nvmem-cell-names = "mac-address";
qca,no-eeprom;
nvmem-cells = <&macaddr_art_0 1>, <&calibration_art_1000>;
nvmem-cell-names = "mac-address", "calibration";
#gpio-cells = <2>;
gpio-controller;
};

2
target/linux/ath79/dts/ar7240_openmesh_om2p-v1.dts
View File

@ -145,7 +145,7 @@
};
calibration_art_1000: calibration@1000 {
reg = <0x1000 0x440>;
reg = <0x1000 0x200>;
};
};
};

14
target/linux/ath79/dts/ar7240_tplink.dtsi
View File

@ -103,6 +103,15 @@
reg = <0x3f0000 0x10000>;
label = "art";
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
calibration_art_1000: calibration@1000 {
};
};
};
};
};
@ -117,9 +126,8 @@
ath9k: wifi@0,0 {
reg = <0x0000 0 0 0 0>;
qca,no-eeprom;
nvmem-cells = <&macaddr_uboot_1fc00 0>;
nvmem-cell-names = "mac-address";
nvmem-cells = <&macaddr_uboot_1fc00 0>, <&calibration_art_1000>;
nvmem-cell-names = "mac-address", "calibration";
#gpio-cells = <2>;
gpio-controller;
};

4
target/linux/ath79/dts/ar7240_tplink_tl-wa.dtsi
View File

@ -20,7 +20,3 @@
nvmem-cells = <&macaddr_uboot_1fc00 0>;
nvmem-cell-names = "mac-address";
};
&ath9k {
compatible = "pci168c,002a";
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wa701nd-v1.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WA701ND v1";
compatible = "tplink,tl-wa701nd-v1", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002b";
};
&calibration_art_1000 {
reg = <0x1000 0x200>;
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wa730re-v1.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WA730RE v1";
compatible = "tplink,tl-wa730re-v1", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002b";
};
&calibration_art_1000 {
reg = <0x1000 0x200>;
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wa801nd-v1.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WA801ND v1";
compatible = "tplink,tl-wa801nd-v1", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002a";
};
&calibration_art_1000 {
reg = <0x1000 0xeb8>;
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wa830re-v1.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WA830RE v1";
compatible = "tplink,tl-wa830re-v1", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002a";
};
&calibration_art_1000 {
reg = <0x1000 0xeb8>;
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wa901nd-v1.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WA901ND v1";
compatible = "tplink,tl-wa901nd-v1", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002b";
};
&calibration_art_1000 {
reg = <0x1000 0x200>;
};

4
target/linux/ath79/dts/ar7240_tplink_tl-wr.dtsi
View File

@ -41,7 +41,3 @@
nvmem-cells = <&macaddr_uboot_1fc00 1>;
nvmem-cell-names = "mac-address";
};
&ath9k {
compatible = "pci168c,002b";
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wr740n-v1.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WR740N v1/v2";
compatible = "tplink,tl-wr740n-v1", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002b";
};
&calibration_art_1000 {
reg = <0x1000 0x200>;
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wr740n-v3.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WR740N v3";
compatible = "tplink,tl-wr740n-v3", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002b";
};
&calibration_art_1000 {
reg = <0x1000 0x200>;
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wr741-v1.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WR741N/ND v1/v2";
compatible = "tplink,tl-wr741-v1", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002b";
};
&calibration_art_1000 {
reg = <0x1000 0x200>;
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wr743nd-v1.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WR743ND v1";
compatible = "tplink,tl-wr743nd-v1", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002b";
};
&calibration_art_1000 {
reg = <0x1000 0x200>;
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wr841-v5.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WR841N/ND v5/v6";
compatible = "tplink,tl-wr841-v5", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002a";
};
&calibration_art_1000 {
reg = <0x1000 0xeb8>;
};

8
target/linux/ath79/dts/ar7240_tplink_tl-wr941-v4.dts
View File

@ -6,3 +6,11 @@
model = "TP-Link TL-WR941N/ND v4";
compatible = "tplink,tl-wr941-v4", "qca,ar7240";
};
&ath9k {
compatible = "pci168c,002a";
};
&calibration_art_1000 {
reg = <0x1000 0xeb8>;
};

16
target/linux/ath79/tiny/base-files/etc/hotplug.d/firmware/10-ath9k-eeprom
View File

@ -12,30 +12,16 @@ case "$FIRMWARE" in
buffalo,whr-g301n|\
engenius,eap350-v1|\
engenius,ecb350-v1|\
engenius,enh202-v1|\
tplink,tl-wa701nd-v1|\
tplink,tl-wa730re-v1|\
tplink,tl-wa801nd-v1|\
tplink,tl-wa830re-v1|\
tplink,tl-wa901nd-v1|\
tplink,tl-wr841-v5|\
tplink,tl-wr941-v4)
engenius,enh202-v1)
caldata_extract "art" 0x1000 0xeb8
;;
dlink,dir-615-e4)
caldata_extract "art" 0x1000 0x1000
ath9k_patch_mac_crc $(mtd_get_mac_ascii "nvram" "lan_mac") 0x10c
;;
netgear,wnr1000-v2|\
netgear,wnr2000-v3|\
netgear,wnr612-v2|\
on,n150r|\
tplink,tl-mr3220-v1|\
tplink,tl-mr3420-v1|\
tplink,tl-wr740n-v1|\
tplink,tl-wr740n-v3|\
tplink,tl-wr741-v1|\
tplink,tl-wr743nd-v1|\
tplink,tl-wr841-v7|\
ubnt,airrouter|\
ubnt,bullet-m-ar7240|\

22
target/linux/econet/Makefile Normal file
View File

@ -0,0 +1,22 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2009-2025 OpenWrt.org
include $(TOPDIR)/rules.mk
ARCH:=mips
BOARD:=econet
BOARDNAME:=EcoNet EN75xx MIPS
FEATURES:=dt source-only squashfs nand
SUBTARGETS:=en751221
KERNEL_PATCHVER:=6.12
define Target/Description
Build firmware image for EcoNet EN75xx MIPS based boards.
endef
# include the profiles
include $(INCLUDE_DIR)/target.mk
$(eval $(call BuildTarget))

112
target/linux/econet/base-files/sbin/en75_chboot Executable file
View File

@ -0,0 +1,112 @@
#!/bin/sh
# SPDX-License-Identifier: GPL-2.0
set -e
part=
offset_blocks=
block_size=
code_openwrt=
code_factory=
code_offset=
read_nand() {
dd "if=$part" "of=$file" "bs=$block_size" "skip=$offset_blocks" count=1 2>/dev/null
}
write_nand() {
flash_erase -N -q "$part" $((offset_blocks * block_size)) 1
dd "if=$file" "of=$part" "bs=$block_size" "seek=$offset_blocks" count=1 2>/dev/null
}
part_named() {
name=$1
pn=$(grep "$name" < /proc/mtd | sed 's/:.*//')
if [ -z "$pn" ]; then
echo "Partition not found: $name"
exit 1
fi
echo "/dev/$pn"
}
to_hex() {
hexdump -v -e '1/1 "%02x"'
}
from_hex() {
sed 's/\([0-9a-fA-F]\{2\}\)/echo -n -e "\\x\1"\n/g' | sh
}
check() {
stored_code=$(dd \
"if=$part" \
bs=1 \
skip=$((offset_blocks * block_size + code_offset)) \
count=$((${#code_openwrt} / 2)) \
2>/dev/null | to_hex
)
if [ "$stored_code" = "$code_openwrt" ]; then
echo "Current boot flag set to OS A (OpenWrt)"
elif [ "$stored_code" = "$code_factory" ]; then
echo "Current boot flag set to OS B (Factory)"
else
echo "Current boot flag unknown: $stored_code"
fi
}
switch() {
switch_to=$1
echo "Switching boot flag to $switch_to"
file=$(mktemp)
read_nand
if [ "$switch_to" = "factory" ]; then
echo "$code_factory" | from_hex | \
dd "of=$file" bs=1 "seek=$code_offset" conv=notrunc 2>/dev/null
elif [ "$switch_to" = "openwrt" ]; then
echo "$code_openwrt" | from_hex | \
dd "of=$file" bs=1 "seek=$code_offset" conv=notrunc 2>/dev/null
else
echo "Invalid switch_to: $switch_to"
exit 1
fi
write_nand
rm "$file"
echo "Flash write complete"
check
}
main() {
machine=$(sed -n -e 's/^machine\s\+:\s\+//p' < /proc/cpuinfo)
if [ "$machine" = "TP-Link Archer VR1200v (v2)" ]; then
# 03fe0000
part=$(part_named '"reserve"')
offset_blocks=0
block_size=$((1024 * 128))
code_offset=0
code_openwrt=0000000101000002
code_factory=0000000101010003
elif [ "$machine" = "SmartFiber XP8421-B" ]; then
# 0dfc0000
part=$(part_named '"reservearea"')
offset_blocks=12
block_size=$((1024 * 128))
code_offset=0
code_openwrt=30000000
code_factory=31000000
else
echo "Unsupported machine: $machine"
exit 1
fi
if [ "$1" = "factory" ]; then
switch factory
elif [ "$1" = "openwrt" ]; then
switch openwrt
else
echo "Usage: $0 factory|openwrt # Change boot flag to Factory OS or OpenWrt"
check
exit 1
fi
}
main "$@"

82
target/linux/econet/dts/en751221.dtsi Normal file
View File

@ -0,0 +1,82 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;
/ {
compatible = "econet,en751221";
#address-cells = <1>;
#size-cells = <1>;
hpt_clock: clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>; /* 200 MHz */
};
cpus: cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "mips,mips34Kc";
reg = <0>;
};
};
cpuintc: interrupt-controller {
compatible = "mti,cpu-interrupt-controller";
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <1>;
};
spi_ctrl: spi_controller@1fa10000 {
compatible = "airoha,en7523-spi";
reg = <0x1fa10000 0x140>;
#address-cells = <1>;
#size-cells = <0>;
spi-rx-bus-width = <2>;
spi-tx-bus-width = <2>;
nand: nand@0 {
compatible = "spi-nand";
reg = <0>;
nand-ecc-engine = <&nand>;
};
};
intc: interrupt-controller@1fb40000 {
compatible = "econet,en751221-intc";
reg = <0x1fb40000 0x100>;
interrupt-parent = <&cpuintc>;
interrupts = <2>;
interrupt-controller;
#interrupt-cells = <1>;
econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
};
uart: serial@1fbf0000 {
compatible = "ns16550";
reg = <0x1fbf0000 0x30>;
reg-io-width = <4>;
reg-shift = <2>;
interrupt-parent = <&intc>;
interrupts = <0>;
/*
* Conversion of baud rate to clock frequency requires a
* computation that is not in the ns16550 driver, so this
* uart is fixed at 115200 baud.
*/
clock-frequency = <1843200>;
};
timer_hpt: timer@1fbf0400 {
compatible = "econet,en751221-timer";
reg = <0x1fbf0400 0x100>;
interrupt-parent = <&intc>;
interrupts = <30>;
clocks = <&hpt_clock>;
};
};

82
target/linux/econet/dts/en751221_smartfiber_xp8421-b.dts Normal file
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@ -0,0 +1,82 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;
#include "en751221.dtsi"
/ {
model = "SmartFiber XP8421-B";
compatible = "smartfiber,xp8421-b", "econet,en751221";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x1c000000>;
};
chosen {
stdout-path = "/serial@1fbf0000:115200";
linux,usable-memory-range = <0x00020000 0x1bfe0000>;
};
};
&nand {
status = "okay";
econet,bmt;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "romfile";
reg = <0x40000 0x40000>;
read-only;
};
partition@80000 {
label = "tclinux";
reg = <0x80000 0x1400000>;
read-only;
econet,enable-remap;
};
/* Nested inside of tclinux */
partition@480000 {
label = "rootfs";
reg = <0x480000 0xf80000>;
linux,rootfs;
read-only;
};
partition@1480000 {
label = "tclinux_alt";
reg = <0x1480000 0x1400000>;
};
partition@2880000 {
label = "openjdk";
reg = <0x2880000 0x2000000>;
};
partition@4880000 {
label = "ubifs";
reg = <0x4880000 0x9100000>;
};
partition@d980000 {
label = "unknown";
reg = <0xd980000 0x4c0000>;
};
partition@de40000 {
label = "reservearea";
reg = <0xde40000 0x1c0000>;
};
};
};

69
target/linux/econet/dts/en751221_tplink_archer-vr1200v-v2.dts Normal file
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@ -0,0 +1,69 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/dts-v1/;
#include "en751221.dtsi"
/ {
model = "TP-Link Archer VR1200v (v2)";
compatible = "tplink,archer-vr1200v-v2", "econet,en751221";
memory@0 {
device_type = "memory";
reg = <0x00000000 0x8000000>;
};
chosen {
stdout-path = "/serial@1fbf0000:115200";
linux,usable-memory-range = <0x00020000 0x07fe0000>;
};
};
&nand {
status = "okay";
econet,bmt;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x0 0x00080000>;
read-only;
};
partition@80000 {
label = "misc";
reg = <0x00080000 0x140000>;
};
partition@1c0200 {
label = "kernel";
reg = <0x001c0000 0x400000>;
};
partition@5c0000 {
label = "rootfs";
reg = <0x005c0000 0x1a40000>;
linux,rootfs;
};
partition@1c0000 {
label = "firmware";
reg = <0x001c0000 0x1e40000>;
};
partition@2000000 {
label = "firmware_factory";
reg = <0x2000000 0x1e40000>;
};
partition@3fe0000 {
label = "reserve";
reg = <0x3fe0000 0x20000>;
};
partition@4000000 {
label = "openwrt_ubi";
/* From the factory this is unallocated space, so it's ours for the taking.
* We have up to 0x35e0000 of space, but we reserve 10 eraseblocks (1.25MB)
* in case the BMT steals them from us.
*/
reg = <0x4000000 0x34a0000>;
};
};
};

205
target/linux/econet/en751221/config-6.12 Normal file
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@ -0,0 +1,205 @@
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_KEEP_MEMBLOCK=y
CONFIG_ARCH_MMAP_RND_BITS_MAX=15
CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=15
CONFIG_ASN1=y
CONFIG_ASSOCIATIVE_ARRAY=y
CONFIG_ASYMMETRIC_KEY_TYPE=y
CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y
CONFIG_CLKSRC_MMIO=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CLZ_TAB=y
CONFIG_COMMON_CLK=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPU_BIG_ENDIAN=y
CONFIG_CPU_GENERIC_DUMP_TLB=y
CONFIG_CPU_HAS_DIEI=y
CONFIG_CPU_HAS_PREFETCH=y
CONFIG_CPU_HAS_RIXI=y
CONFIG_CPU_HAS_SYNC=y
CONFIG_CPU_MIPS32=y
# CONFIG_CPU_MIPS32_R1 is not set
CONFIG_CPU_MIPS32_R2=y
CONFIG_CPU_MIPSR2=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS=y
CONFIG_CPU_R4K_CACHE_TLB=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
CONFIG_CPU_SUPPORTS_HIGHMEM=y
CONFIG_CPU_SUPPORTS_MSA=y
CONFIG_CRC16=y
CONFIG_CRYPTO_CRC32C=m
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_ECB=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_POLY1305_RSIZE=2
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RSA=y
CONFIG_CRYPTO_SIG=y
CONFIG_CRYPTO_SIG2=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_ZBOOT=y
CONFIG_DTB_ECONET_NONE=y
# CONFIG_DTB_ECONET_SMARTFIBER_XP8421_B is not set
CONFIG_DTC=y
CONFIG_EARLY_PRINTK=y
CONFIG_EARLY_PRINTK_8250=y
CONFIG_ECONET=y
CONFIG_ECONET_EN751221_INTC=y
CONFIG_ECONET_EN751221_TIMER=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FS_IOMAP=y
CONFIG_FUNCTION_ALIGNMENT=0
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GENERIC_ATOMIC64=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IOMAP=y
CONFIG_GENERIC_IRQ_CHIP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_LIB_ASHLDI3=y
CONFIG_GENERIC_LIB_ASHRDI3=y
CONFIG_GENERIC_LIB_CMPDI2=y
CONFIG_GENERIC_LIB_LSHRDI3=y
CONFIG_GENERIC_LIB_UCMPDI2=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GPIO_CDEV=y
CONFIG_HARDWARE_WATCHPOINTS=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HZ_PERIODIC=y
CONFIG_INITRAMFS_SOURCE=""
CONFIG_IRQCHIP=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_MIPS_CPU=y
CONFIG_IRQ_WORK=y
# CONFIG_JFFS2_FS is not set
CONFIG_KEYS=y
CONFIG_LIBCRC32C=m
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MIGRATION=y
CONFIG_MIPS=y
CONFIG_MIPS_ASID_BITS=8
CONFIG_MIPS_ASID_SHIFT=0
# CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_MIPS_CMDLINE_FROM_DTB=y
CONFIG_MIPS_L1_CACHE_SHIFT=5
# CONFIG_MIPS_NO_APPENDED_DTB is not set
CONFIG_MIPS_NR_CPU_NR_MAP=2
CONFIG_MIPS_RAW_APPENDED_DTB=y
CONFIG_MIPS_SPRAM=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MPILIB=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_MTK_BMT=y
CONFIG_MTD_SPI_NAND=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=13
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_NEED_SRCU_NMI_SAFE=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_XGRESS=y
CONFIG_NO_GENERIC_PCI_IOPORT_MAP=y
CONFIG_NR_CPUS=2
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OID_REGISTRY=y
CONFIG_PADATA=y
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI_DRIVERS_LEGACY=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PKCS7_MESSAGE_PARSER=y
# CONFIG_PKCS7_TEST_KEY is not set
# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_QUEUED_RWLOCKS=y
CONFIG_QUEUED_SPINLOCKS=y
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RATIONAL=y
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
# CONFIG_SECONDARY_TRUSTED_KEYRING is not set
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_UP=y
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_ECONET_EN751221=y
CONFIG_SPI=y
CONFIG_SPI_AIROHA_EN7523=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_SYSCTL_EXCEPTION_TRACE=y
CONFIG_SYSTEM_DATA_VERIFICATION=y
# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set
CONFIG_SYSTEM_TRUSTED_KEYRING=y
CONFIG_SYS_HAS_CPU_MIPS32_R1=y
CONFIG_SYS_HAS_CPU_MIPS32_R2=y
CONFIG_SYS_HAS_EARLY_PRINTK=y
CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
CONFIG_SYS_SUPPORTS_MIPS16=y
CONFIG_SYS_SUPPORTS_SMP=y
CONFIG_SYS_SUPPORTS_ZBOOT=y
CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y
CONFIG_TARGET_ISA_REV=2
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_ATIME_SUPPORT=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_AUTHENTICATION=y
CONFIG_UBIFS_FS_SECURITY=y
CONFIG_USE_GENERIC_EARLY_PRINTK_8250=y
CONFIG_USE_OF=y
CONFIG_X509_CERTIFICATE_PARSER=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_ZBOOT_LOAD_ADDRESS=0x80020000
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

14
target/linux/econet/en751221/profiles/00-default.mk Normal file
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@ -0,0 +1,14 @@
# SPDX-License-Identifier: GPL-2.0-only
#
# Copyright (C) 2016 OpenWrt.org
# PACKAGES:= kmod-usb2 kmod-ath9k-htc wpad-basic-mbedtls
define Profile/Default
NAME:=Default Profile (all drivers)
endef
define Profile/Default/Description
Default package set compatible with most boards.
endef
$(eval $(call Profile,Default))

8
target/linux/econet/en751221/target.mk Normal file
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@ -0,0 +1,8 @@
BOARDNAME:=en751221
CPU_TYPE:=24kc
KERNELNAME:=vmlinuz.bin
define Target/Description
Build firmware images for EcoNet EN751221 family SoC, including
EN7512, EN7513, EN7521, EN7526 and EN7586.
endef

1439
target/linux/econet/files/drivers/mtd/nand/en75_bmt.c Normal file
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File diff suppressed because it is too large Load Diff

51
target/linux/econet/image/Makefile Normal file
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include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/image.mk
define Target/Description
Build firmware images for EcoNet MIPS based boards.
endef
# tclinux-trx is the default format used in the SDK
define Build/tclinux-trx
./tclinux-trx.sh $@ $(IMAGE_ROOTFS) $(VERSION_DIST)-$(REVISION) > $@.new
mv $@.new $@
endef
# tclinux bootloader requires LZMA, BUT only provides 7.5MB of space
# to decompress into. So we use vmlinuz and decompress twice.
define Device/Default
DEVICE_DTS_DIR := ../dts
KERNEL_SIZE := 7480k
KERNEL_NAME := vmlinuz.bin
KERNEL_LOADADDR := 0x80020000
KERNEL := kernel-bin | append-dtb
endef
define Device/smartfiber_xp8421-b
DEVICE_VENDOR := SmartFiber
DEVICE_MODEL := XP8421-B
DEVICE_DTS := en751221_smartfiber_xp8421-b
IMAGES := tclinux.trx
IMAGE/tclinux.trx := append-kernel | lzma | tclinux-trx
endef
TARGET_DEVICES += smartfiber_xp8421-b
# NOTE: This will not work for upgrading from factory because it requires a cryptographic signature
# however, it it can be flashed, then it will boot correctly.
define Device/tplink_archer-vr1200v-v2
DEVICE_VENDOR := TP-Link
DEVICE_MODEL := Archer vr1200v
DEVICE_VARIANT := v2
TPLINK_FLASHLAYOUT := 16Mmtk
TPLINK_HWID := 0x0b473502
TPLINK_HWREV := 0x0006007c
TPLINK_HWREVADD := 0x0
TPLINK_HVERSION := 3
DEVICE_DTS := en751221_tplink_archer-vr1200v-v2
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | lzma | pad-to 4193792 | append-rootfs | \
tplink-v2-header -R 0x400000
endef
TARGET_DEVICES += tplink_archer-vr1200v-v2
$(eval $(call BuildImage))

118
target/linux/econet/image/tclinux-trx.sh Executable file
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@ -0,0 +1,118 @@
#!/bin/sh
# SPDX-License-Identifier: GPL-2.0
set -e
# This is not necessary, but it makes finding the rootfs easier.
PAD_ROOTFS_OFFSET_TO=4194304
# Constant
HDRLEN=256
die() {
echo "$1" >&2
exit 1
}
[ $# -eq 3 ] || die "SYNTAX: $0 <kernel lzma> <rootfs squashfs> <version string>"
kernel=$1
rootfs=$2
version=$3
which zytrx >/dev/null || die "zytrx not found in PATH $PATH"
[ -f "$kernel" ] || die "Kernel file not found: $kernel"
[ -f "$rootfs" ] || die "Rootfs file not found: $rootfs"
[ "$(echo "$version" | wc -c)" -lt 32 ] || die "Version string too long: $version"
kernel_len=$(stat -c '%s' "$kernel")
header_plus_kernel_len=$(($HDRLEN + $kernel_len))
rootfs_len=$(stat -c '%s' "$rootfs")
if [ "$PAD_ROOTFS_OFFSET_TO" -gt "$header_plus_kernel_len" ]; then
padding_len=$(($PAD_ROOTFS_OFFSET_TO - $header_plus_kernel_len))
else
padding_len=0
fi
echo "padding_len: $padding_len" >&2
padded_rootfs_len=$(($padding_len + $rootfs_len))
echo "padded_rootfs_len: $padded_rootfs_len" >&2
total_len=$(($header_plus_kernel_len + $padded_rootfs_len))
echo "total_len: $total_len" >&2
padding() {
head -c $padding_len /dev/zero | tr '\0' '\377'
}
to_hex() {
hexdump -v -e '1/1 "%02x"'
}
from_hex() {
perl -pe 's/\s+//g; s/(..)/chr(hex($1))/ge'
}
trx_crc32() {
tmpfile=$(mktemp)
outtmpfile=$(mktemp)
cat "$kernel" > "$tmpfile"
padding >> "$tmpfile"
cat "$rootfs" >> "$tmpfile"
# We just need a CRC-32/JAMCRC of the concatnated files
# There's no readily available tool for this, but zytrx does create one when
# creating their TRX header, so we just use that.
zytrx \
-B NR7101 \
-v x \
-i "$tmpfile" \
-o "$outtmpfile" >/dev/null
dd if="$outtmpfile" bs=4 count=1 skip=3 | to_hex
rm "$tmpfile" "$outtmpfile" >/dev/null
}
tclinux_trx_hdr() {
# TRX header magic
printf '2RDH' | to_hex
# Length of the header
printf '%08x\n' "$HDRLEN"
# Length of header + content
printf '%08x\n' "$total_len"
# crc32 of the content
trx_crc32
# version
echo "$version" | to_hex
head -c "$((32 - $(echo "$version" | wc -c)))" /dev/zero | to_hex
# customer version
head -c 32 /dev/zero | to_hex
# kernel length
printf '%08x\n' "$kernel_len"
# rootfs length
printf '%08x\n' "$padded_rootfs_len"
# romfile length (0)
printf '00000000\n'
# "model" (32 bytes of zeros)
head -c 32 /dev/zero | to_hex
# Load address (CONFIG_ZBOOT_LOAD_ADDRESS)
printf '80020000\n'
# "reserved" 128 bytes of zeros
head -c 128 /dev/zero | to_hex
}
tclinux_trx_hdr | from_hex
cat "$kernel"
padding
cat "$rootfs"

98
target/linux/econet/patches-6.12/001-v6.16-dt-bindings-interrupt-controller-Add-EcoNet-EN751221.patch Normal file
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@ -0,0 +1,98 @@
From 9773c540441c6ae15aefb49e67142e94369dbbc0 Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Sun, 30 Mar 2025 17:02:58 +0000
Subject: [PATCH] dt-bindings: interrupt-controller: Add EcoNet EN751221 INTC
Document the device tree binding for the interrupt controller in the
EcoNet EN751221 MIPS SoC.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/all/20250330170306.2584136-3-cjd@cjdns.fr
---
.../econet,en751221-intc.yaml | 78 +++++++++++++++++++
1 file changed, 78 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/econet,en751221-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EcoNet EN751221 Interrupt Controller
+
+maintainers:
+ - Caleb James DeLisle <cjd@cjdns.fr>
+
+description:
+ The EcoNet EN751221 Interrupt Controller is a simple interrupt controller
+ designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can
+ be routed to either VPE but not both, so to support per-CPU interrupts, a
+ secondary IRQ number is allocated to control masking/unmasking on VPE#1. For
+ lack of a better term we call these "shadow interrupts". The assignment of
+ shadow interrupts is defined by the SoC integrator when wiring the interrupt
+ lines, so they are configurable in the device tree.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ const: econet,en751221-intc
+
+ reg:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupt-controller: true
+
+ interrupts:
+ maxItems: 1
+ description: Interrupt line connecting this controller to its parent.
+
+ econet,shadow-interrupts:
+ $ref: /schemas/types.yaml#/definitions/uint32-matrix
+ description:
+ An array of interrupt number pairs where each pair represents a shadow
+ interrupt relationship. The first number in each pair is the primary IRQ,
+ and the second is its shadow IRQ used for VPE#1 control. For example,
+ <8 3> means IRQ 8 is shadowed by IRQ 3, so IRQ 3 cannot be mapped, but
+ when VPE#1 requests IRQ 8, it will manipulate the IRQ 3 mask bit.
+ minItems: 1
+ maxItems: 20
+ items:
+ items:
+ - description: primary per-CPU IRQ
+ - description: shadow IRQ number
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ interrupt-controller@1fb40000 {
+ compatible = "econet,en751221-intc";
+ reg = <0x1fb40000 0x100>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
+ };
+...

353
target/linux/econet/patches-6.12/002-v6.16-irqchip-Add-EcoNet-EN751221-INTC.patch Normal file
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@ -0,0 +1,353 @@
From 1902a59cf5f9d8b99ecf0cb8f122cb00ef7a3f13 Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Sun, 30 Mar 2025 17:02:59 +0000
Subject: [PATCH] irqchip: Add EcoNet EN751221 INTC
Add a driver for the interrupt controller in the EcoNet EN751221 MIPS SoC.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/all/20250330170306.2584136-4-cjd@cjdns.fr
---
drivers/irqchip/Kconfig | 5 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-econet-en751221.c | 309 ++++++++++++++++++++++++++
3 files changed, 315 insertions(+)
create mode 100644 drivers/irqchip/irq-econet-en751221.c
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -147,6 +147,11 @@ config DW_APB_ICTL
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN_HIERARCHY
+config ECONET_EN751221_INTC
+ bool
+ select GENERIC_IRQ_CHIP
+ select IRQ_DOMAIN
+
config FARADAY_FTINTC010
bool
select IRQ_DOMAIN
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_BCM2835) += irq-bcm28
obj-$(CONFIG_ARCH_ACTIONS) += irq-owl-sirq.o
obj-$(CONFIG_DAVINCI_CP_INTC) += irq-davinci-cp-intc.o
obj-$(CONFIG_EXYNOS_IRQ_COMBINER) += exynos-combiner.o
+obj-$(CONFIG_ECONET_EN751221_INTC) += irq-econet-en751221.o
obj-$(CONFIG_FARADAY_FTINTC010) += irq-ftintc010.o
obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
--- /dev/null
+++ b/drivers/irqchip/irq-econet-en751221.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * EN751221 Interrupt Controller Driver.
+ *
+ * The EcoNet EN751221 Interrupt Controller is a simple interrupt controller
+ * designed for the MIPS 34Kc MT SMP processor with 2 VPEs. Each interrupt can
+ * be routed to either VPE but not both, so to support per-CPU interrupts, a
+ * secondary IRQ number is allocated to control masking/unmasking on VPE#1. In
+ * this driver, these are called "shadow interrupts". The assignment of shadow
+ * interrupts is defined by the SoC integrator when wiring the interrupt lines,
+ * so they are configurable in the device tree.
+ *
+ * If an interrupt (say 30) needs per-CPU capability, the SoC integrator
+ * allocates another IRQ number (say 29) to be its shadow. The device tree
+ * reflects this by adding the pair <30 29> to the "econet,shadow-interrupts"
+ * property.
+ *
+ * When VPE#1 requests IRQ 30, the driver manipulates the mask bit for IRQ 29,
+ * telling the hardware to mask VPE#1's view of IRQ 30.
+ *
+ * Copyright (C) 2025 Caleb James DeLisle <cjd@cjdns.fr>
+ */
+
+#include <linux/cleanup.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/chained_irq.h>
+
+#define IRQ_COUNT 40
+
+#define NOT_PERCPU 0xff
+#define IS_SHADOW 0xfe
+
+#define REG_MASK0 0x04
+#define REG_MASK1 0x50
+#define REG_PENDING0 0x08
+#define REG_PENDING1 0x54
+
+/**
+ * @membase: Base address of the interrupt controller registers
+ * @interrupt_shadows: Array of all interrupts, for each value,
+ * - NOT_PERCPU: This interrupt is not per-cpu, so it has no shadow
+ * - IS_SHADOW: This interrupt is a shadow of another per-cpu interrupt
+ * - else: This is a per-cpu interrupt whose shadow is the value
+ */
+static struct {
+ void __iomem *membase;
+ u8 interrupt_shadows[IRQ_COUNT];
+} econet_intc __ro_after_init;
+
+static DEFINE_RAW_SPINLOCK(irq_lock);
+
+/* IRQs must be disabled */
+static void econet_wreg(u32 reg, u32 val, u32 mask)
+{
+ u32 v;
+
+ guard(raw_spinlock)(&irq_lock);
+
+ v = ioread32(econet_intc.membase + reg);
+ v &= ~mask;
+ v |= val & mask;
+ iowrite32(v, econet_intc.membase + reg);
+}
+
+/* IRQs must be disabled */
+static void econet_chmask(u32 hwirq, bool unmask)
+{
+ u32 reg, mask;
+ u8 shadow;
+
+ /*
+ * If the IRQ is a shadow, it should never be manipulated directly.
+ * It should only be masked/unmasked as a result of the "real" per-cpu
+ * irq being manipulated by a thread running on VPE#1.
+ * If it is per-cpu (has a shadow), and we're on VPE#1, the shadow is what we mask.
+ * This is single processor only, so smp_processor_id() never exceeds 1.
+ */
+ shadow = econet_intc.interrupt_shadows[hwirq];
+ if (WARN_ON_ONCE(shadow == IS_SHADOW))
+ return;
+ else if (shadow != NOT_PERCPU && smp_processor_id() == 1)
+ hwirq = shadow;
+
+ if (hwirq >= 32) {
+ reg = REG_MASK1;
+ mask = BIT(hwirq - 32);
+ } else {
+ reg = REG_MASK0;
+ mask = BIT(hwirq);
+ }
+
+ econet_wreg(reg, unmask ? mask : 0, mask);
+}
+
+/* IRQs must be disabled */
+static void econet_intc_mask(struct irq_data *d)
+{
+ econet_chmask(d->hwirq, false);
+}
+
+/* IRQs must be disabled */
+static void econet_intc_unmask(struct irq_data *d)
+{
+ econet_chmask(d->hwirq, true);
+}
+
+static void econet_mask_all(void)
+{
+ /* IRQs are generally disabled during init, but guarding here makes it non-obligatory. */
+ guard(irqsave)();
+ econet_wreg(REG_MASK0, 0, ~0);
+ econet_wreg(REG_MASK1, 0, ~0);
+}
+
+static void econet_intc_handle_pending(struct irq_domain *d, u32 pending, u32 offset)
+{
+ int hwirq;
+
+ while (pending) {
+ hwirq = fls(pending) - 1;
+ generic_handle_domain_irq(d, hwirq + offset);
+ pending &= ~BIT(hwirq);
+ }
+}
+
+static void econet_intc_from_parent(struct irq_desc *desc)
+{
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+ struct irq_domain *domain;
+ u32 pending0, pending1;
+
+ chained_irq_enter(chip, desc);
+
+ pending0 = ioread32(econet_intc.membase + REG_PENDING0);
+ pending1 = ioread32(econet_intc.membase + REG_PENDING1);
+
+ if (unlikely(!(pending0 | pending1))) {
+ spurious_interrupt();
+ } else {
+ domain = irq_desc_get_handler_data(desc);
+ econet_intc_handle_pending(domain, pending0, 0);
+ econet_intc_handle_pending(domain, pending1, 32);
+ }
+
+ chained_irq_exit(chip, desc);
+}
+
+static const struct irq_chip econet_irq_chip;
+
+static int econet_intc_map(struct irq_domain *d, u32 irq, irq_hw_number_t hwirq)
+{
+ int ret;
+
+ if (hwirq >= IRQ_COUNT) {
+ pr_err("%s: hwirq %lu out of range\n", __func__, hwirq);
+ return -EINVAL;
+ } else if (econet_intc.interrupt_shadows[hwirq] == IS_SHADOW) {
+ pr_err("%s: can't map hwirq %lu, it is a shadow interrupt\n", __func__, hwirq);
+ return -EINVAL;
+ }
+
+ if (econet_intc.interrupt_shadows[hwirq] == NOT_PERCPU) {
+ irq_set_chip_and_handler(irq, &econet_irq_chip, handle_level_irq);
+ } else {
+ irq_set_chip_and_handler(irq, &econet_irq_chip, handle_percpu_devid_irq);
+ ret = irq_set_percpu_devid(irq);
+ if (ret)
+ pr_warn("%s: Failed irq_set_percpu_devid for %u: %d\n", d->name, irq, ret);
+ }
+
+ irq_set_chip_data(irq, NULL);
+ return 0;
+}
+
+static const struct irq_chip econet_irq_chip = {
+ .name = "en751221-intc",
+ .irq_unmask = econet_intc_unmask,
+ .irq_mask = econet_intc_mask,
+ .irq_mask_ack = econet_intc_mask,
+};
+
+static const struct irq_domain_ops econet_domain_ops = {
+ .xlate = irq_domain_xlate_onecell,
+ .map = econet_intc_map
+};
+
+static int __init get_shadow_interrupts(struct device_node *node)
+{
+ const char *field = "econet,shadow-interrupts";
+ int num_shadows;
+
+ num_shadows = of_property_count_u32_elems(node, field);
+
+ memset(econet_intc.interrupt_shadows, NOT_PERCPU,
+ sizeof(econet_intc.interrupt_shadows));
+
+ if (num_shadows <= 0) {
+ return 0;
+ } else if (num_shadows % 2) {
+ pr_err("%pOF: %s count is odd, ignoring\n", node, field);
+ return 0;
+ }
+
+ u32 *shadows __free(kfree) = kmalloc_array(num_shadows, sizeof(u32), GFP_KERNEL);
+ if (!shadows)
+ return -ENOMEM;
+
+ if (of_property_read_u32_array(node, field, shadows, num_shadows)) {
+ pr_err("%pOF: Failed to read %s\n", node, field);
+ return -EINVAL;
+ }
+
+ for (int i = 0; i < num_shadows; i += 2) {
+ u32 shadow = shadows[i + 1];
+ u32 target = shadows[i];
+
+ if (shadow > IRQ_COUNT) {
+ pr_err("%pOF: %s[%d] shadow(%d) out of range\n",
+ node, field, i + 1, shadow);
+ continue;
+ }
+
+ if (target >= IRQ_COUNT) {
+ pr_err("%pOF: %s[%d] target(%d) out of range\n", node, field, i, target);
+ continue;
+ }
+
+ if (econet_intc.interrupt_shadows[target] != NOT_PERCPU) {
+ pr_err("%pOF: %s[%d] target(%d) already has a shadow\n",
+ node, field, i, target);
+ continue;
+ }
+
+ if (econet_intc.interrupt_shadows[shadow] != NOT_PERCPU) {
+ pr_err("%pOF: %s[%d] shadow(%d) already has a target\n",
+ node, field, i + 1, shadow);
+ continue;
+ }
+
+ econet_intc.interrupt_shadows[target] = shadow;
+ econet_intc.interrupt_shadows[shadow] = IS_SHADOW;
+ }
+
+ return 0;
+}
+
+static int __init econet_intc_of_init(struct device_node *node, struct device_node *parent)
+{
+ struct irq_domain *domain;
+ struct resource res;
+ int ret, irq;
+
+ ret = get_shadow_interrupts(node);
+ if (ret)
+ return ret;
+
+ irq = irq_of_parse_and_map(node, 0);
+ if (!irq) {
+ pr_err("%pOF: DT: Failed to get IRQ from 'interrupts'\n", node);
+ return -EINVAL;
+ }
+
+ if (of_address_to_resource(node, 0, &res)) {
+ pr_err("%pOF: DT: Failed to get 'reg'\n", node);
+ ret = -EINVAL;
+ goto err_dispose_mapping;
+ }
+
+ if (!request_mem_region(res.start, resource_size(&res), res.name)) {
+ pr_err("%pOF: Failed to request memory\n", node);
+ ret = -EBUSY;
+ goto err_dispose_mapping;
+ }
+
+ econet_intc.membase = ioremap(res.start, resource_size(&res));
+ if (!econet_intc.membase) {
+ pr_err("%pOF: Failed to remap membase\n", node);
+ ret = -ENOMEM;
+ goto err_release;
+ }
+
+ econet_mask_all();
+
+ domain = irq_domain_add_linear(node, IRQ_COUNT, &econet_domain_ops, NULL);
+ if (!domain) {
+ pr_err("%pOF: Failed to add irqdomain\n", node);
+ ret = -ENOMEM;
+ goto err_unmap;
+ }
+
+ irq_set_chained_handler_and_data(irq, econet_intc_from_parent, domain);
+
+ return 0;
+
+err_unmap:
+ iounmap(econet_intc.membase);
+err_release:
+ release_mem_region(res.start, resource_size(&res));
+err_dispose_mapping:
+ irq_dispose_mapping(irq);
+ return ret;
+}
+
+IRQCHIP_DECLARE(econet_en751221_intc, "econet,en751221-intc", econet_intc_of_init);

26
target/linux/econet/patches-6.12/003-v6.16-dt-bindings-vendor-prefixes-Add-EcoNet.patch Normal file
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@ -0,0 +1,26 @@
From 9e0dd98654a528735d2b363d0dc73f7904108652 Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Sun, 30 Mar 2025 17:02:57 +0000
Subject: [PATCH] dt-bindings: vendor-prefixes: Add EcoNet
Add the "econet" vendor prefix for SoC maker
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250330170306.2584136-2-cjd@cjdns.fr
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -420,6 +420,8 @@ patternProperties:
description: EBV Elektronik
"^eckelmann,.*":
description: Eckelmann AG
+ "^econet,.*":
+ description: EcoNet (HK) Limited
"^edgeble,.*":
description: Edgeble AI Technologies Pvt. Ltd.
"^edimax,.*":

100
target/linux/econet/patches-6.12/004-v6.16-dt-bindings-timer-Add-EcoNet-EN751221-HPT-CPU-Timer.patch Normal file
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@ -0,0 +1,100 @@
From 30fddbd5325459102e448c9a26a1bc15ef563381 Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Wed, 7 May 2025 13:44:54 +0000
Subject: [PATCH] dt-bindings: timer: Add EcoNet EN751221 "HPT" CPU Timer
Add device tree bindings for the so-called high-precision timer (HPT)
in the EcoNet EN751221 SoC.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250507134500.390547-2-cjd@cjdns.fr
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../bindings/timer/econet,en751221-timer.yaml | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/econet,en751221-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EcoNet EN751221 High Precision Timer (HPT)
+
+maintainers:
+ - Caleb James DeLisle <cjd@cjdns.fr>
+
+description:
+ The EcoNet High Precision Timer (HPT) is a timer peripheral found in various
+ EcoNet SoCs, including the EN751221 and EN751627 families. It provides per-VPE
+ count/compare registers and a per-CPU control register, with a single interrupt
+ line using a percpu-devid interrupt mechanism.
+
+properties:
+ compatible:
+ oneOf:
+ - const: econet,en751221-timer
+ - items:
+ - const: econet,en751627-timer
+ - const: econet,en751221-timer
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+ description: A percpu-devid timer interrupt shared across CPUs.
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: econet,en751627-timer
+ then:
+ properties:
+ reg:
+ items:
+ - description: VPE timers 0 and 1
+ - description: VPE timers 2 and 3
+ else:
+ properties:
+ reg:
+ items:
+ - description: VPE timers 0 and 1
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@1fbf0400 {
+ compatible = "econet,en751627-timer", "econet,en751221-timer";
+ reg = <0x1fbf0400 0x100>, <0x1fbe0000 0x100>;
+ interrupt-parent = <&intc>;
+ interrupts = <30>;
+ clocks = <&hpt_clock>;
+ };
+ - |
+ timer@1fbf0400 {
+ compatible = "econet,en751221-timer";
+ reg = <0x1fbe0400 0x100>;
+ interrupt-parent = <&intc>;
+ interrupts = <30>;
+ clocks = <&hpt_clock>;
+ };
+...

276
target/linux/econet/patches-6.12/005-v6.16-clocksource-drivers-Add-EcoNet-Timer-HPT-driver.patch Normal file
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@ -0,0 +1,276 @@
From 3b4c33ac87d0d11308f4445ecec2a124e2e77724 Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Wed, 7 May 2025 13:44:55 +0000
Subject: [PATCH] clocksource/drivers: Add EcoNet Timer HPT driver
Introduce a clocksource driver for the so-called high-precision timer (HPT)
in the EcoNet EN751221 and EN751627 MIPS SoCs.
It's a 32 bit upward-counting one-shot timer which relies on the crystal so it
is unaffected by CPU power mode. On MIPS 34K devices (single core) there is
one timer, and on 1004K devices (dual core) there are two.
Each timer has two sets of count/compare registers so that there is one for
each of the VPEs on the core. Because each core has 2 VPEs, register selection
takes the CPU number / 2 for the timer corrisponding to the core, then CPU
number % 2 for the register corrisponding to the VPE.
These timers use a percpu-devid IRQ to route interrupts to the VPE which set
the event.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Link: https://lore.kernel.org/r/20250507134500.390547-3-cjd@cjdns.fr
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/Kconfig | 8 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-econet-en751221.c | 216 ++++++++++++++++++++
3 files changed, 225 insertions(+)
create mode 100644 drivers/clocksource/timer-econet-en751221.c
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -73,6 +73,14 @@ config DW_APB_TIMER_OF
select DW_APB_TIMER
select TIMER_OF
+config ECONET_EN751221_TIMER
+ bool "EcoNet EN751221 High Precision Timer" if COMPILE_TEST
+ depends on HAS_IOMEM
+ select CLKSRC_MMIO
+ select TIMER_OF
+ help
+ Support for CPU timer found on EcoNet MIPS based SoCs.
+
config FTTMR010_TIMER
bool "Faraday Technology timer driver" if COMPILE_TEST
depends on HAS_IOMEM
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_CLKBLD_I8253) += i8253.o
obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
obj-$(CONFIG_DAVINCI_TIMER) += timer-davinci.o
obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
+obj-$(CONFIG_ECONET_EN751221_TIMER) += timer-econet-en751221.o
obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o
obj-$(CONFIG_OMAP_DM_SYSTIMER) += timer-ti-dm-systimer.o
obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
--- /dev/null
+++ b/drivers/clocksource/timer-econet-en751221.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Timer present on EcoNet EN75xx MIPS based SoCs.
+ *
+ * Copyright (C) 2025 by Caleb James DeLisle <cjd@cjdns.fr>
+ */
+
+#include <linux/io.h>
+#include <linux/cpumask.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/sched_clock.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/cpuhotplug.h>
+#include <linux/clk.h>
+
+#define ECONET_BITS 32
+#define ECONET_MIN_DELTA 0x00001000
+#define ECONET_MAX_DELTA GENMASK(ECONET_BITS - 2, 0)
+/* 34Kc hardware has 1 block and 1004Kc has 2. */
+#define ECONET_NUM_BLOCKS DIV_ROUND_UP(NR_CPUS, 2)
+
+static struct {
+ void __iomem *membase[ECONET_NUM_BLOCKS];
+ u32 freq_hz;
+} econet_timer __ro_after_init;
+
+static DEFINE_PER_CPU(struct clock_event_device, econet_timer_pcpu);
+
+/* Each memory block has 2 timers, the order of registers is:
+ * CTL, CMR0, CNT0, CMR1, CNT1
+ */
+static inline void __iomem *reg_ctl(u32 timer_n)
+{
+ return econet_timer.membase[timer_n >> 1];
+}
+
+static inline void __iomem *reg_compare(u32 timer_n)
+{
+ return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x04;
+}
+
+static inline void __iomem *reg_count(u32 timer_n)
+{
+ return econet_timer.membase[timer_n >> 1] + (timer_n & 1) * 0x08 + 0x08;
+}
+
+static inline u32 ctl_bit_enabled(u32 timer_n)
+{
+ return 1U << (timer_n & 1);
+}
+
+static inline u32 ctl_bit_pending(u32 timer_n)
+{
+ return 1U << ((timer_n & 1) + 16);
+}
+
+static bool cevt_is_pending(int cpu_id)
+{
+ return ioread32(reg_ctl(cpu_id)) & ctl_bit_pending(cpu_id);
+}
+
+static irqreturn_t cevt_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *dev = this_cpu_ptr(&econet_timer_pcpu);
+ int cpu = cpumask_first(dev->cpumask);
+
+ /* Each VPE has its own events,
+ * so this will only happen on spurious interrupt.
+ */
+ if (!cevt_is_pending(cpu))
+ return IRQ_NONE;
+
+ iowrite32(ioread32(reg_count(cpu)), reg_compare(cpu));
+ dev->event_handler(dev);
+ return IRQ_HANDLED;
+}
+
+static int cevt_set_next_event(ulong delta, struct clock_event_device *dev)
+{
+ u32 next;
+ int cpu;
+
+ cpu = cpumask_first(dev->cpumask);
+ next = ioread32(reg_count(cpu)) + delta;
+ iowrite32(next, reg_compare(cpu));
+
+ if ((s32)(next - ioread32(reg_count(cpu))) < ECONET_MIN_DELTA / 2)
+ return -ETIME;
+
+ return 0;
+}
+
+static int cevt_init_cpu(uint cpu)
+{
+ struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, cpu);
+ u32 reg;
+
+ pr_debug("%s: Setting up clockevent for CPU %d\n", cd->name, cpu);
+
+ reg = ioread32(reg_ctl(cpu)) | ctl_bit_enabled(cpu);
+ iowrite32(reg, reg_ctl(cpu));
+
+ enable_percpu_irq(cd->irq, IRQ_TYPE_NONE);
+
+ /* Do this last because it synchronously configures the timer */
+ clockevents_config_and_register(cd, econet_timer.freq_hz,
+ ECONET_MIN_DELTA, ECONET_MAX_DELTA);
+
+ return 0;
+}
+
+static u64 notrace sched_clock_read(void)
+{
+ /* Always read from clock zero no matter the CPU */
+ return (u64)ioread32(reg_count(0));
+}
+
+/* Init */
+
+static void __init cevt_dev_init(uint cpu)
+{
+ iowrite32(0, reg_count(cpu));
+ iowrite32(U32_MAX, reg_compare(cpu));
+}
+
+static int __init cevt_init(struct device_node *np)
+{
+ int i, irq, ret;
+
+ irq = irq_of_parse_and_map(np, 0);
+ if (irq <= 0) {
+ pr_err("%pOFn: irq_of_parse_and_map failed", np);
+ return -EINVAL;
+ }
+
+ ret = request_percpu_irq(irq, cevt_interrupt, np->name, &econet_timer_pcpu);
+
+ if (ret < 0) {
+ pr_err("%pOFn: IRQ %d setup failed (%d)\n", np, irq, ret);
+ goto err_unmap_irq;
+ }
+
+ for_each_possible_cpu(i) {
+ struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, i);
+
+ cd->rating = 310,
+ cd->features = CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_C3STOP |
+ CLOCK_EVT_FEAT_PERCPU;
+ cd->set_next_event = cevt_set_next_event;
+ cd->irq = irq;
+ cd->cpumask = cpumask_of(i);
+ cd->name = np->name;
+
+ cevt_dev_init(i);
+ }
+
+ cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
+ "clockevents/econet/timer:starting",
+ cevt_init_cpu, NULL);
+ return 0;
+
+err_unmap_irq:
+ irq_dispose_mapping(irq);
+ return ret;
+}
+
+static int __init timer_init(struct device_node *np)
+{
+ int num_blocks = DIV_ROUND_UP(num_possible_cpus(), 2);
+ struct clk *clk;
+ int ret;
+
+ clk = of_clk_get(np, 0);
+ if (IS_ERR(clk)) {
+ pr_err("%pOFn: Failed to get CPU clock from DT %ld\n", np, PTR_ERR(clk));
+ return PTR_ERR(clk);
+ }
+
+ econet_timer.freq_hz = clk_get_rate(clk);
+
+ for (int i = 0; i < num_blocks; i++) {
+ econet_timer.membase[i] = of_iomap(np, i);
+ if (!econet_timer.membase[i]) {
+ pr_err("%pOFn: failed to map register [%d]\n", np, i);
+ return -ENXIO;
+ }
+ }
+
+ /* For clocksource purposes always read clock zero, whatever the CPU */
+ ret = clocksource_mmio_init(reg_count(0), np->name,
+ econet_timer.freq_hz, 301, ECONET_BITS,
+ clocksource_mmio_readl_up);
+ if (ret) {
+ pr_err("%pOFn: clocksource_mmio_init failed: %d", np, ret);
+ return ret;
+ }
+
+ ret = cevt_init(np);
+ if (ret < 0)
+ return ret;
+
+ sched_clock_register(sched_clock_read, ECONET_BITS,
+ econet_timer.freq_hz);
+
+ pr_info("%pOFn: using %u.%03u MHz high precision timer\n", np,
+ econet_timer.freq_hz / 1000000,
+ (econet_timer.freq_hz / 1000) % 1000);
+
+ return 0;
+}
+
+TIMER_OF_DECLARE(econet_timer_hpt, "econet,en751221-timer", timer_init);

44
target/linux/econet/patches-6.12/006-v6.16-dt-bindings-mips-Add-EcoNet-platform-binding.patch Normal file
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@ -0,0 +1,44 @@
From be8b4173719a61fdd8379e86895d855775cf5f91 Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Wed, 7 May 2025 13:44:56 +0000
Subject: [PATCH] dt-bindings: mips: Add EcoNet platform binding
Document the top-level device tree binding for EcoNet MIPS-based SoCs.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
.../devicetree/bindings/mips/econet.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/econet.yaml
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/econet.yaml
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mips/econet.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: EcoNet MIPS SoCs
+
+maintainers:
+ - Caleb James DeLisle <cjd@cjdns.fr>
+
+properties:
+ $nodename:
+ const: '/'
+
+ compatible:
+ oneOf:
+ - description: Boards with EcoNet EN751221 family SoC
+ items:
+ - enum:
+ - smartfiber,xp8421-b
+ - const: econet,en751221
+
+additionalProperties: true
+
+...

222
target/linux/econet/patches-6.12/007-v6.16-mips-Add-EcoNet-MIPS-platform-support.patch Normal file
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@ -0,0 +1,222 @@
From 35fb26f94dfa1b291086b84b2421f957214824d1 Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Wed, 7 May 2025 13:44:57 +0000
Subject: [PATCH] mips: Add EcoNet MIPS platform support
Add platform support for EcoNet MIPS SoCs.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 25 +++++++++
arch/mips/boot/compressed/uart-16550.c | 5 ++
arch/mips/econet/Kconfig | 37 ++++++++++++
arch/mips/econet/Makefile | 2 +
arch/mips/econet/Platform | 5 ++
arch/mips/econet/init.c | 78 ++++++++++++++++++++++++++
7 files changed, 153 insertions(+)
create mode 100644 arch/mips/econet/Kconfig
create mode 100644 arch/mips/econet/Makefile
create mode 100644 arch/mips/econet/Platform
create mode 100644 arch/mips/econet/init.c
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -11,6 +11,7 @@ platform-$(CONFIG_CAVIUM_OCTEON_SOC) +=
platform-$(CONFIG_EYEQ) += mobileye/
platform-$(CONFIG_MIPS_COBALT) += cobalt/
platform-$(CONFIG_MACH_DECSTATION) += dec/
+platform-$(CONFIG_ECONET) += econet/
platform-$(CONFIG_MIPS_GENERIC) += generic/
platform-$(CONFIG_MACH_JAZZ) += jazz/
platform-$(CONFIG_LANTIQ) += lantiq/
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -388,6 +388,30 @@ config MACH_DECSTATION
otherwise choose R3000.
+config ECONET
+ bool "EcoNet MIPS family"
+ select BOOT_RAW
+ select CPU_BIG_ENDIAN
+ select DEBUG_ZBOOT
+ select EARLY_PRINTK_8250
+ select ECONET_EN751221_TIMER
+ select SERIAL_OF_PLATFORM
+ select SYS_SUPPORTS_BIG_ENDIAN
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_HAS_EARLY_PRINTK
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_MIPS16
+ select SYS_SUPPORTS_ZBOOT_UART16550
+ select USE_GENERIC_EARLY_PRINTK_8250
+ select USE_OF
+ help
+ EcoNet EN75xx MIPS devices are big endian MIPS machines used
+ in XPON (fiber) and DSL applications. They have SPI, PCI, USB,
+ GPIO, and Ethernet, with optional XPON, DSL, and VoIP DSP cores.
+ Don't confuse these with the Airoha ARM devices sometimes referred
+ to as "EcoNet", this family is for MIPS based devices only.
+
config MACH_JAZZ
bool "Jazz family of machines"
select ARC_MEMORY
@@ -1017,6 +1041,7 @@ source "arch/mips/ath79/Kconfig"
source "arch/mips/bcm47xx/Kconfig"
source "arch/mips/bcm63xx/Kconfig"
source "arch/mips/bmips/Kconfig"
+source "arch/mips/econet/Kconfig"
source "arch/mips/generic/Kconfig"
source "arch/mips/ingenic/Kconfig"
source "arch/mips/jazz/Kconfig"
--- a/arch/mips/boot/compressed/uart-16550.c
+++ b/arch/mips/boot/compressed/uart-16550.c
@@ -20,6 +20,11 @@
#define PORT(offset) (CKSEG1ADDR(INGENIC_UART_BASE_ADDR) + (4 * offset))
#endif
+#ifdef CONFIG_ECONET
+#define EN75_UART_BASE 0x1fbf0003
+#define PORT(offset) (CKSEG1ADDR(EN75_UART_BASE) + (4 * (offset)))
+#endif
+
#ifndef IOTYPE
#define IOTYPE char
#endif
--- /dev/null
+++ b/arch/mips/econet/Kconfig
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: GPL-2.0
+if ECONET
+
+choice
+ prompt "EcoNet SoC selection"
+ default SOC_ECONET_EN751221
+ help
+ Select EcoNet MIPS SoC type. Individual SoCs within a family are
+ very similar, so is it enough to select the right family, and
+ then customize to the specific SoC using the device tree only.
+
+ config SOC_ECONET_EN751221
+ bool "EN751221 family"
+ select COMMON_CLK
+ select ECONET_EN751221_INTC
+ select IRQ_MIPS_CPU
+ select SMP
+ select SMP_UP
+ select SYS_SUPPORTS_SMP
+ help
+ The EN751221 family includes EN7512, RN7513, EN7521, EN7526.
+ They are based on single core MIPS 34Kc processors. To boot
+ this kernel, you will need a device tree such as
+ MIPS_RAW_APPENDED_DTB=y, and a root filesystem.
+endchoice
+
+choice
+ prompt "Devicetree selection"
+ default DTB_ECONET_NONE
+ help
+ Select the devicetree.
+
+ config DTB_ECONET_NONE
+ bool "None"
+endchoice
+
+endif
--- /dev/null
+++ b/arch/mips/econet/Makefile
@@ -0,0 +1,2 @@
+
+obj-y := init.o
--- /dev/null
+++ b/arch/mips/econet/Platform
@@ -0,0 +1,5 @@
+# To address a 7.2MB kernel size limit in the EcoNet SDK bootloader,
+# we put the load address well above where the bootloader loads and then use
+# zboot. So please set CONFIG_ZBOOT_LOAD_ADDRESS to the address where your
+# bootloader actually places the kernel.
+load-$(CONFIG_ECONET) += 0xffffffff81000000
--- /dev/null
+++ b/arch/mips/econet/init.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * EcoNet setup code
+ *
+ * Copyright (C) 2025 Caleb James DeLisle <cjd@cjdns.fr>
+ */
+
+#include <linux/init.h>
+#include <linux/of_clk.h>
+#include <linux/irqchip.h>
+
+#include <asm/addrspace.h>
+#include <asm/io.h>
+#include <asm/bootinfo.h>
+#include <asm/time.h>
+#include <asm/prom.h>
+#include <asm/smp-ops.h>
+#include <asm/reboot.h>
+
+#define CR_AHB_RSTCR ((void __iomem *)CKSEG1ADDR(0x1fb00040))
+#define RESET BIT(31)
+
+#define UART_BASE CKSEG1ADDR(0x1fbf0003)
+#define UART_REG_SHIFT 2
+
+static void hw_reset(char *command)
+{
+ iowrite32(RESET, CR_AHB_RSTCR);
+}
+
+/* 1. Bring up early printk. */
+void __init prom_init(void)
+{
+ setup_8250_early_printk_port(UART_BASE, UART_REG_SHIFT, 0);
+ _machine_restart = hw_reset;
+}
+
+/* 2. Parse the DT and find memory */
+void __init plat_mem_setup(void)
+{
+ void *dtb;
+
+ set_io_port_base(KSEG1);
+
+ dtb = get_fdt();
+ if (!dtb)
+ panic("no dtb found");
+
+ __dt_setup_arch(dtb);
+
+ early_init_dt_scan_memory();
+}
+
+/* 3. Overload __weak device_tree_init(), add SMP_UP ops */
+void __init device_tree_init(void)
+{
+ unflatten_and_copy_device_tree();
+
+ register_up_smp_ops();
+}
+
+const char *get_system_type(void)
+{
+ return "EcoNet-EN75xx";
+}
+
+/* 4. Initialize the IRQ subsystem */
+void __init arch_init_irq(void)
+{
+ irqchip_init();
+}
+
+/* 5. Timers */
+void __init plat_time_init(void)
+{
+ of_clk_init(NULL);
+ timer_probe();
+}

29
target/linux/econet/patches-6.12/008-v6.16-dt-bindings-vendor-prefixes-Add-SmartFiber.patch Normal file
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@ -0,0 +1,29 @@
From abc2d0bc2cb7c1412b8b254c0446f94b3e203c7c Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Wed, 7 May 2025 13:44:58 +0000
Subject: [PATCH] dt-bindings: vendor-prefixes: Add SmartFiber
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add "smartfiber" vendor prefix for manufactorer of EcoNet based boards.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -1368,6 +1368,8 @@ patternProperties:
description: SKOV A/S
"^skyworks,.*":
description: Skyworks Solutions, Inc.
+ "^smartfiber,.*":
+ description: ShenZhen Smartfiber Technology Co, Ltd.
"^smartlabs,.*":
description: SmartLabs LLC
"^smartrg,.*":

149
target/linux/econet/patches-6.12/009-v6.16-mips-dts-Add-EcoNet-DTS-with-EN751221-and-SmartFiber.patch Normal file
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@ -0,0 +1,149 @@
From 0ec4887009729297f7c10368084e41a8a9fbbd0e Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Wed, 7 May 2025 13:44:59 +0000
Subject: [PATCH] mips: dts: Add EcoNet DTS with EN751221 and SmartFiber
XP8421-B board
Add DTS files in support of EcoNet platform, including SmartFiber XP8421-B,
a low cost commercially available board based on EN751221.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/econet/Makefile | 2 +
arch/mips/boot/dts/econet/en751221.dtsi | 67 +++++++++++++++++++
.../econet/en751221_smartfiber_xp8421-b.dts | 19 ++++++
arch/mips/econet/Kconfig | 11 +++
5 files changed, 100 insertions(+)
create mode 100644 arch/mips/boot/dts/econet/Makefile
create mode 100644 arch/mips/boot/dts/econet/en751221.dtsi
create mode 100644 arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
subdir-$(CONFIG_BMIPS_GENERIC) += brcm
subdir-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon
+subdir-$(CONFIG_ECONET) += econet
subdir-$(CONFIG_EYEQ) += mobileye
subdir-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += img
subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
--- /dev/null
+++ b/arch/mips/boot/dts/econet/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_DTB_ECONET_SMARTFIBER_XP8421_B) += en751221_smartfiber_xp8421-b.dtb
--- /dev/null
+++ b/arch/mips/boot/dts/econet/en751221.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+/ {
+ compatible = "econet,en751221";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ hpt_clock: clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <200000000>; /* 200 MHz */
+ };
+
+ cpus: cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "mips,mips24KEc";
+ reg = <0>;
+ };
+ };
+
+ cpuintc: interrupt-controller {
+ compatible = "mti,cpu-interrupt-controller";
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ intc: interrupt-controller@1fb40000 {
+ compatible = "econet,en751221-intc";
+ reg = <0x1fb40000 0x100>;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>;
+ };
+
+ uart: serial@1fbf0000 {
+ compatible = "ns16550";
+ reg = <0x1fbf0000 0x30>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&intc>;
+ interrupts = <0>;
+ /*
+ * Conversion of baud rate to clock frequency requires a
+ * computation that is not in the ns16550 driver, so this
+ * uart is fixed at 115200 baud.
+ */
+ clock-frequency = <1843200>;
+ };
+
+ timer_hpt: timer@1fbf0400 {
+ compatible = "econet,en751221-timer";
+ reg = <0x1fbf0400 0x100>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <30>;
+ clocks = <&hpt_clock>;
+ };
+};
--- /dev/null
+++ b/arch/mips/boot/dts/econet/en751221_smartfiber_xp8421-b.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+#include "en751221.dtsi"
+
+/ {
+ model = "SmartFiber XP8421-B";
+ compatible = "smartfiber,xp8421-b", "econet,en751221";
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x00000000 0x1c000000>;
+ };
+
+ chosen {
+ stdout-path = "/serial@1fbf0000:115200";
+ linux,usable-memory-range = <0x00020000 0x1bfe0000>;
+ };
+};
--- a/arch/mips/econet/Kconfig
+++ b/arch/mips/econet/Kconfig
@@ -32,6 +32,17 @@ choice
config DTB_ECONET_NONE
bool "None"
+
+ config DTB_ECONET_SMARTFIBER_XP8421_B
+ bool "EN751221 SmartFiber XP8421-B"
+ depends on SOC_ECONET_EN751221
+ select BUILTIN_DTB
+ help
+ The SmartFiber XP8421-B is a device based on the EN751221 SoC.
+ It has 512MB of memory and 256MB of NAND flash. This kernel
+ needs only an appended initramfs to boot. It can be loaded
+ through XMODEM and booted from memory in the bootloader, or
+ it can be packed in tclinux.trx format and written to flash.
endchoice
endif

38
target/linux/econet/patches-6.12/010-v6.16-MAINTAINERS-Add-entry-for-newly-added-EcoNet-platfor.patch Normal file
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@ -0,0 +1,38 @@
From faefb0a59c5914b7b8f737e2ec5c82822e5bc4c7 Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Wed, 7 May 2025 13:45:00 +0000
Subject: [PATCH] MAINTAINERS: Add entry for newly added EcoNet platform.
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Add a MAINTAINERS entry as part of integration of the EcoNet MIPS platform.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
MAINTAINERS | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8019,6 +8019,18 @@ W: https://linuxtv.org
Q: http://patchwork.linuxtv.org/project/linux-media/list/
F: drivers/media/dvb-frontends/ec100*
+ECONET MIPS PLATFORM
+M: Caleb James DeLisle <cjd@cjdns.fr>
+L: linux-mips@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml
+F: Documentation/devicetree/bindings/mips/econet.yaml
+F: Documentation/devicetree/bindings/timer/econet,en751221-timer.yaml
+F: arch/mips/boot/dts/econet/
+F: arch/mips/econet/
+F: drivers/clocksource/timer-econet-en751221.c
+F: drivers/irqchip/irq-econet-en751221.c
+
ECRYPT FILE SYSTEM
M: Tyler Hicks <code@tyhicks.com>
L: ecryptfs@vger.kernel.org

32
target/linux/econet/patches-6.12/011-v6.16-mips-econet-Fix-incorrect-Kconfig-dependencies.patch Normal file
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@ -0,0 +1,32 @@
From 79ee1d20e37cd553cc961962fca8107e69a0c293 Mon Sep 17 00:00:00 2001
From: Caleb James DeLisle <cjd@cjdns.fr>
Date: Wed, 21 May 2025 21:33:33 +0000
Subject: [PATCH] mips: econet: Fix incorrect Kconfig dependencies
config ECONET selects SERIAL_OF_PLATFORM and that depends on SERIAL_8250
so we need to select SERIAL_8250 directly.
Also do not enable DEBUG_ZBOOT unless DEBUG_KERNEL is set.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202505211654.CBdIsoTq-lkp@intel.com/
Closes: https://lore.kernel.org/oe-kbuild-all/202505211451.WRjyf3a9-lkp@intel.com/
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
arch/mips/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -392,9 +392,10 @@ config ECONET
bool "EcoNet MIPS family"
select BOOT_RAW
select CPU_BIG_ENDIAN
- select DEBUG_ZBOOT
+ select DEBUG_ZBOOT if DEBUG_KERNEL
select EARLY_PRINTK_8250
select ECONET_EN751221_TIMER
+ select SERIAL_8250
select SERIAL_OF_PLATFORM
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_HAS_CPU_MIPS32_R1

341
target/linux/econet/patches-6.12/300-spi-Add-support-for-the-Airoha-EN7523-SoC-SPI-contro.patch Normal file
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@ -0,0 +1,341 @@
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -370,6 +370,12 @@ config SPI_DLN2
This driver can also be built as a module. If so, the module
will be called spi-dln2.
+config SPI_AIROHA_EN7523
+ bool "Airoha EN7523 SPI controller support"
+ depends on ARCH_AIROHA
+ help
+ This enables SPI controller support for the Airoha EN7523 SoC.
+
config SPI_EP93XX
tristate "Cirrus Logic EP93xx SPI controller"
depends on ARCH_EP93XX || COMPILE_TEST
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_SPI_DW_BT1) += spi-dw-bt1.
obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
obj-$(CONFIG_SPI_DW_PCI) += spi-dw-pci.o
obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
+obj-$(CONFIG_SPI_AIROHA_EN7523) += spi-en7523.o
obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
obj-$(CONFIG_SPI_FSI) += spi-fsi.o
obj-$(CONFIG_SPI_FSL_CPM) += spi-fsl-cpm.o
--- /dev/null
+++ b/drivers/spi/spi-en7523.c
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mod_devicetable.h>
+#include <linux/spi/spi.h>
+
+
+#define ENSPI_READ_IDLE_EN 0x0004
+#define ENSPI_MTX_MODE_TOG 0x0014
+#define ENSPI_RDCTL_FSM 0x0018
+#define ENSPI_MANUAL_EN 0x0020
+#define ENSPI_MANUAL_OPFIFO_EMPTY 0x0024
+#define ENSPI_MANUAL_OPFIFO_WDATA 0x0028
+#define ENSPI_MANUAL_OPFIFO_FULL 0x002C
+#define ENSPI_MANUAL_OPFIFO_WR 0x0030
+#define ENSPI_MANUAL_DFIFO_FULL 0x0034
+#define ENSPI_MANUAL_DFIFO_WDATA 0x0038
+#define ENSPI_MANUAL_DFIFO_EMPTY 0x003C
+#define ENSPI_MANUAL_DFIFO_RD 0x0040
+#define ENSPI_MANUAL_DFIFO_RDATA 0x0044
+#define ENSPI_IER 0x0090
+#define ENSPI_NFI2SPI_EN 0x0130
+
+// TODO not in spi block
+#define ENSPI_CLOCK_DIVIDER ((void __iomem *)0x1fa201c4)
+
+#define OP_CSH 0x00
+#define OP_CSL 0x01
+#define OP_CK 0x02
+#define OP_OUTS 0x08
+#define OP_OUTD 0x09
+#define OP_OUTQ 0x0A
+#define OP_INS 0x0C
+#define OP_INS0 0x0D
+#define OP_IND 0x0E
+#define OP_INQ 0x0F
+#define OP_OS2IS 0x10
+#define OP_OS2ID 0x11
+#define OP_OS2IQ 0x12
+#define OP_OD2IS 0x13
+#define OP_OD2ID 0x14
+#define OP_OD2IQ 0x15
+#define OP_OQ2IS 0x16
+#define OP_OQ2ID 0x17
+#define OP_OQ2IQ 0x18
+#define OP_OSNIS 0x19
+#define OP_ODNID 0x1A
+
+#define MATRIX_MODE_AUTO 1
+#define CONF_MTX_MODE_AUTO 0
+#define MANUALEN_AUTO 0
+#define MATRIX_MODE_MANUAL 0
+#define CONF_MTX_MODE_MANUAL 9
+#define MANUALEN_MANUAL 1
+
+#define _ENSPI_MAX_XFER 0x1ff
+
+#define REG(x) (iobase + x)
+
+
+static void __iomem *iobase;
+
+
+static void opfifo_write(u32 cmd, u32 len)
+{
+ u32 tmp = ((cmd & 0x1f) << 9) | (len & 0x1ff);
+
+ writel(tmp, REG(ENSPI_MANUAL_OPFIFO_WDATA));
+
+ /* Wait for room in OPFIFO */
+ while (readl(REG(ENSPI_MANUAL_OPFIFO_FULL)))
+ ;
+
+ /* Shift command into OPFIFO */
+ writel(1, REG(ENSPI_MANUAL_OPFIFO_WR));
+
+ /* Wait for command to finish */
+ while (!readl(REG(ENSPI_MANUAL_OPFIFO_EMPTY)))
+ ;
+}
+
+static void set_cs(int state)
+{
+ if (state)
+ opfifo_write(OP_CSH, 1);
+ else
+ opfifo_write(OP_CSL, 1);
+}
+
+static void manual_begin_cmd(void)
+{
+ /* Disable read idle state */
+ writel(0, REG(ENSPI_READ_IDLE_EN));
+
+ /* Wait for FSM to reach idle state */
+ while (readl(REG(ENSPI_RDCTL_FSM)))
+ ;
+
+ /* Set SPI core to manual mode */
+ writel(CONF_MTX_MODE_MANUAL, REG(ENSPI_MTX_MODE_TOG));
+ writel(MANUALEN_MANUAL, REG(ENSPI_MANUAL_EN));
+}
+
+static void manual_end_cmd(void)
+{
+ /* Set SPI core to auto mode */
+ writel(CONF_MTX_MODE_AUTO, REG(ENSPI_MTX_MODE_TOG));
+ writel(MANUALEN_AUTO, REG(ENSPI_MANUAL_EN));
+
+ /* Enable read idle state */
+ writel(1, REG(ENSPI_READ_IDLE_EN));
+}
+
+static void dfifo_read(u8 *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ /* Wait for requested data to show up in DFIFO */
+ while (readl(REG(ENSPI_MANUAL_DFIFO_EMPTY)))
+ ;
+ buf[i] = readl(REG(ENSPI_MANUAL_DFIFO_RDATA));
+ /* Queue up next byte */
+ writel(1, REG(ENSPI_MANUAL_DFIFO_RD));
+ }
+}
+
+static void dfifo_write(const u8 *buf, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++) {
+ /* Wait for room in DFIFO */
+ while (readl(REG(ENSPI_MANUAL_DFIFO_FULL)))
+ ;
+ writel(buf[i], REG(ENSPI_MANUAL_DFIFO_WDATA));
+ }
+}
+
+#if 0
+static void set_spi_clock_speed(int freq_mhz)
+{
+ u32 tmp, val;
+
+ tmp = readl(ENSPI_CLOCK_DIVIDER);
+ tmp &= 0xffff0000;
+ writel(tmp, ENSPI_CLOCK_DIVIDER);
+
+ val = (400 / (freq_mhz * 2));
+ tmp |= (val << 8) | 1;
+ writel(tmp, ENSPI_CLOCK_DIVIDER);
+}
+#endif
+
+static void init_hw(void)
+{
+ /* Disable manual/auto mode clash interrupt */
+ writel(0, REG(ENSPI_IER));
+
+ // TODO via clk framework
+ // set_spi_clock_speed(50);
+
+ /* Disable DMA */
+ writel(0, REG(ENSPI_NFI2SPI_EN));
+}
+
+static int xfer_read(struct spi_transfer *xfer)
+{
+ int opcode;
+ uint8_t *buf = xfer->rx_buf;
+
+ switch (xfer->rx_nbits) {
+ case SPI_NBITS_SINGLE:
+ opcode = OP_INS;
+ break;
+ case SPI_NBITS_DUAL:
+ opcode = OP_IND;
+ break;
+ case SPI_NBITS_QUAD:
+ opcode = OP_INQ;
+ break;
+ }
+
+ opfifo_write(opcode, xfer->len);
+ dfifo_read(buf, xfer->len);
+
+ return xfer->len;
+}
+
+static int xfer_write(struct spi_transfer *xfer, int next_xfer_is_rx)
+{
+ int opcode;
+ const uint8_t *buf = xfer->tx_buf;
+
+ if (next_xfer_is_rx) {
+ /* need to use Ox2Ix opcode to set the core to input afterwards */
+ switch (xfer->tx_nbits) {
+ case SPI_NBITS_SINGLE:
+ opcode = OP_OS2IS;
+ break;
+ case SPI_NBITS_DUAL:
+ opcode = OP_OS2ID;
+ break;
+ case SPI_NBITS_QUAD:
+ opcode = OP_OS2IQ;
+ break;
+ }
+ } else {
+ switch (xfer->tx_nbits) {
+ case SPI_NBITS_SINGLE:
+ opcode = OP_OUTS;
+ break;
+ case SPI_NBITS_DUAL:
+ opcode = OP_OUTD;
+ break;
+ case SPI_NBITS_QUAD:
+ opcode = OP_OUTQ;
+ break;
+ }
+ }
+
+ opfifo_write(opcode, xfer->len);
+ dfifo_write(buf, xfer->len);
+
+ return xfer->len;
+}
+
+size_t max_transfer_size(struct spi_device *spi)
+{
+ return _ENSPI_MAX_XFER;
+}
+
+int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
+{
+ struct spi_transfer *xfer;
+ int next_xfer_is_rx = 0;
+
+ manual_begin_cmd();
+ set_cs(0);
+ list_for_each_entry(xfer, &msg->transfers, transfer_list) {
+ if (xfer->tx_buf) {
+ if (!list_is_last(&xfer->transfer_list, &msg->transfers)
+ && list_next_entry(xfer, transfer_list)->rx_buf != NULL)
+ next_xfer_is_rx = 1;
+ else
+ next_xfer_is_rx = 0;
+ msg->actual_length += xfer_write(xfer, next_xfer_is_rx);
+ } else if (xfer->rx_buf) {
+ msg->actual_length += xfer_read(xfer);
+ }
+ }
+ set_cs(1);
+ manual_end_cmd();
+
+ msg->status = 0;
+ spi_finalize_current_message(ctrl);
+
+ return 0;
+}
+
+static int spi_probe(struct platform_device *pdev)
+{
+ struct spi_controller *ctrl;
+ int err;
+
+ ctrl = devm_spi_alloc_master(&pdev->dev, 0);
+ if (!ctrl) {
+ dev_err(&pdev->dev, "Error allocating SPI controller\n");
+ return -ENOMEM;
+ }
+
+ iobase = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+ if (IS_ERR(iobase)) {
+ dev_err(&pdev->dev, "Could not map SPI register address");
+ return -ENOMEM;
+ }
+
+ init_hw();
+
+ ctrl->dev.of_node = pdev->dev.of_node;
+ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
+ ctrl->mode_bits = SPI_RX_DUAL | SPI_TX_DUAL;
+ ctrl->max_transfer_size = max_transfer_size;
+ ctrl->transfer_one_message = transfer_one_message;
+ err = devm_spi_register_controller(&pdev->dev, ctrl);
+ if (err) {
+ dev_err(&pdev->dev, "Could not register SPI controller\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id spi_of_ids[] = {
+ { .compatible = "airoha,en7523-spi" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, spi_of_ids);
+
+static struct platform_driver spi_driver = {
+ .probe = spi_probe,
+ .driver = {
+ .name = "airoha-en7523-spi",
+ .of_match_table = spi_of_ids,
+ },
+};
+
+module_platform_driver(spi_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
+MODULE_DESCRIPTION("Airoha EN7523 SPI driver");

56
target/linux/econet/patches-6.12/301-spi-Airoha-adapt-to-support-en75-mips.patch Normal file
View File

@ -0,0 +1,56 @@
Subject: Adapt Airoha EN7523 SPI to work with EcoNet EN751221
The SPI driver from Airoha EN7523 is copied here in it's original form
so this patch makes three updates to it in order to make it work
correctly in the EcoNet EN751221 context.
The main change here is that the chip select operation is sent twice.
This pattern is borrowed from the vendor code and it prevents write
operations from being lost sporadically on the EN751221.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -372,7 +372,7 @@ config SPI_DLN2
config SPI_AIROHA_EN7523
bool "Airoha EN7523 SPI controller support"
- depends on ARCH_AIROHA
+ depends on ARCH_AIROHA || ECONET
help
This enables SPI controller support for the Airoha EN7523 SoC.
--- a/drivers/spi/spi-en7523.c
+++ b/drivers/spi/spi-en7523.c
@@ -82,10 +82,11 @@ static void opfifo_write(u32 cmd, u32 le
static void set_cs(int state)
{
- if (state)
- opfifo_write(OP_CSH, 1);
- else
- opfifo_write(OP_CSL, 1);
+ u32 cmd = state ? OP_CSH : OP_CSL;
+
+ /* EN751221 drops writes if we don't send this twice. */
+ opfifo_write(cmd, 1);
+ opfifo_write(cmd, 1);
}
static void manual_begin_cmd(void)
@@ -226,12 +227,12 @@ static int xfer_write(struct spi_transfe
return xfer->len;
}
-size_t max_transfer_size(struct spi_device *spi)
+static size_t max_transfer_size(struct spi_device *spi)
{
return _ENSPI_MAX_XFER;
}
-int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
+static int transfer_one_message(struct spi_controller *ctrl, struct spi_message *msg)
{
struct spi_transfer *xfer;
int next_xfer_is_rx = 0;

40
target/linux/econet/patches-6.12/901-nand-enable-en75-bbt.patch Normal file
View File

@ -0,0 +1,40 @@
Subject: Add EcoNet bad block table
The EcoNet BBT/BMT is used for resolving bad blocks in the flash.
It is implemented in the EcoNet bootloader so you cannot safely
access flash without using it.
Signed-off-by: Caleb James DeLisle <cjd@cjdns.fr>
---
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -3,7 +3,7 @@
nandcore-objs := core.o bbt.o
obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
-obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
+obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o en75_bmt.o
ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o
else
--- a/drivers/mtd/nand/mtk_bmt.h
+++ b/drivers/mtd/nand/mtk_bmt.h
@@ -77,6 +77,7 @@ extern struct bmt_desc bmtd;
extern const struct mtk_bmt_ops mtk_bmt_v2_ops;
extern const struct mtk_bmt_ops mtk_bmt_bbt_ops;
extern const struct mtk_bmt_ops mtk_bmt_nmbm_ops;
+extern const struct mtk_bmt_ops en75_bmt_ops;
static inline u32 blk_pg(u16 block)
{
--- a/drivers/mtd/nand/mtk_bmt.c
+++ b/drivers/mtd/nand/mtk_bmt.c
@@ -422,6 +422,8 @@ int mtk_bmt_attach(struct mtd_info *mtd)
bmtd.ops = &mtk_bmt_nmbm_ops;
else if (of_property_read_bool(np, "mediatek,bbt"))
bmtd.ops = &mtk_bmt_bbt_ops;
+ else if (of_property_read_bool(np, "econet,bmt"))
+ bmtd.ops = &en75_bmt_ops;
else
return 0;

34
target/linux/econet/patches-6.12/902-snand-mtk-bmt-support.patch Normal file
View File

@ -0,0 +1,34 @@
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -19,6 +19,7 @@
#include <linux/string.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
+#include <linux/mtd/mtk_bmt.h>
static int spinand_read_reg_op(struct spinand_device *spinand, u8 reg, u8 *val)
{
@@ -1525,6 +1526,7 @@ static int spinand_probe(struct spi_mem
if (ret)
return ret;
+ mtk_bmt_attach(mtd);
ret = mtd_device_register(mtd, NULL, 0);
if (ret)
goto err_spinand_cleanup;
@@ -1532,6 +1534,7 @@ static int spinand_probe(struct spi_mem
return 0;
err_spinand_cleanup:
+ mtk_bmt_detach(mtd);
spinand_cleanup(spinand);
return ret;
@@ -1550,6 +1553,7 @@ static int spinand_remove(struct spi_mem
if (ret)
return ret;
+ mtk_bmt_detach(mtd);
spinand_cleanup(spinand);
return 0;

28
target/linux/mediatek/dts/mt7981b-zyxel-nwa50ax-pro.dts
View File

@ -71,7 +71,7 @@
phy-handle = <&phy0>;
nvmem-cells = <&macaddr_mrd_1fff8>;
nvmem-cells = <&macaddr_mrd_1fff8 0>;
nvmem-cell-names = "mac-address";
};
};
@ -155,8 +155,12 @@
#address-cells = <1>;
#size-cells = <1>;
macaddr: macaddr@a {
reg = <0xa 0x6>;
eeprom_factory_0: eeprom@0 {
reg = <0x0 0x1000>;
};
precal_factory_1010: precal@1010 {
reg = <0x1010 0x6f010>;
};
};
};
@ -212,7 +216,9 @@
#size-cells = <1>;
macaddr_mrd_1fff8: macaddr@1fff8 {
compatible = "mac-base";
reg = <0x1fff8 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
@ -237,7 +243,21 @@
};
&wifi {
nvmem-cells = <&eeprom_factory_0>, <&precal_factory_1010>;
nvmem-cell-names = "eeprom", "precal";
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
mediatek,mtd-eeprom = <&factory 0x0>;
band@0 {
reg = <0>;
nvmem-cells = <&macaddr_mrd_1fff8 1>;
nvmem-cell-names = "mac-address";
};
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_mrd_1fff8 2>;
nvmem-cell-names = "mac-address";
};
};

45
target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-common.dtsi
View File

@ -4,12 +4,13 @@
* Author: Sam.Shih <sam.shih@mediatek.com>
*/
#include "mt7986a.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#include "mt7986a.dtsi"
/ {
aliases {
serial0 = &uart0;
@ -192,6 +193,9 @@
reg = <0>;
phy-mode = "2500base-x";
nvmem-cells = <&macaddr_factory_2a 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <2500>;
full-duplex;
@ -202,8 +206,12 @@
gmac1: mac@1 {
compatible = "mediatek,eth-mac";
reg = <1>;
label = "wan";
phy-mode = "2500base-x";
phy = <&phy6>;
nvmem-cells = <&macaddr_factory_24 0>;
nvmem-cell-names = "mac-address";
};
mdio: mdio-bus {
@ -297,10 +305,21 @@
};
&wifi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-names = "default", "dbdc";
pinctrl-0 = <&wf_2g_5g_pins>;
pinctrl-1 = <&wf_dbdc_pins>;
nvmem-cells = <&eeprom_factory>;
nvmem-cell-names = "eeprom";
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_4 1>;
nvmem-cell-names = "mac-address";
};
};
&crypto {
@ -367,12 +386,12 @@
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <MTK_DRIVE_4mA>;
};
};
@ -384,12 +403,12 @@
};
conf {
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
"WF1_TOP_CLK", "WF1_TOP_DATA";
drive-strength = <MTK_DRIVE_4mA>;
};
};

47
target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-stock.dts
View File

@ -5,19 +5,11 @@
*/
/dts-v1/;
#include "mt7986a.dtsi"
#include "mt7986a-zyxel-ex5601-t0-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Zyxel EX5601-T0 (stock layout)";
compatible = "zyxel,ex5601-t0-stock", "mediatek,mt7986a";
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x20000000>;
};
};
&spi_nand {
@ -30,18 +22,18 @@
partition@0 {
label = "BL2";
reg = <0x00000 0x0100000>;
reg = <0x0 0x100000>;
read-only;
};
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
reg = <0x100000 0x80000>;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
reg = <0x180000 0x200000>;
read-only;
nvmem-layout {
@ -54,21 +46,21 @@
reg = <0x0 0x1000>;
};
macaddr_factory_0004: macaddr@4 {
macaddr_factory_4: macaddr@4 {
compatible = "mac-base";
reg = <0x0004 0x6>;
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_factory_0024: macaddr@24 {
macaddr_factory_24: macaddr@24 {
compatible = "mac-base";
reg = <0x0024 0x6>;
reg = <0x24 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_factory_002a: macaddr@2a {
macaddr_factory_2a: macaddr@2a {
compatible = "mac-base";
reg = <0x002a 0x6>;
reg = <0x2a 0x6>;
#nvmem-cell-cells = <1>;
};
};
@ -76,13 +68,13 @@
partition@380000 {
label = "FIP";
reg = <0x380000 0x01C0000>;
reg = <0x380000 0x1c0000>;
read-only;
};
partition@540000 {
label = "zloader";
reg = <0x540000 0x0040000>;
reg = <0x540000 0x40000>;
read-only;
};
@ -99,21 +91,6 @@
partition@8580000 {
label = "zyubi";
reg = <0x8580000 0x15A80000>;
reg = <0x8580000 0x15a80000>;
};
};
&gmac0 {
nvmem-cells = <&macaddr_factory_002a 0>;
nvmem-cell-names = "mac-address";
};
&gmac1 {
nvmem-cells = <&macaddr_factory_0024 0>;
nvmem-cell-names = "mac-address";
};
&wifi {
nvmem-cells = <&eeprom_factory>;
nvmem-cell-names = "eeprom";
};

45
target/linux/mediatek/dts/mt7986a-zyxel-ex5601-t0-ubootmod.dts
View File

@ -5,20 +5,12 @@
*/
/dts-v1/;
#include "mt7986a.dtsi"
#include "mt7986a-zyxel-ex5601-t0-common.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Zyxel EX5601-T0 ubootmod";
compatible = "zyxel,ex5601-t0-ubootmod", "mediatek,mt7986a";
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x20000000>;
};
chosen {
bootargs-append = " root=/dev/fit0 rootwait";
rootdisk = <&ubi_rootdisk>;
@ -34,13 +26,13 @@
partition@100000 {
label = "u-boot-env";
reg = <0x0100000 0x0080000>;
reg = <0x100000 0x80000>;
read-only;
};
factory: partition@180000 {
label = "Factory";
reg = <0x180000 0x0200000>;
label = "factory";
reg = <0x180000 0x200000>;
read-only;
nvmem-layout {
@ -53,21 +45,21 @@
reg = <0x0 0x1000>;
};
macaddr_factory_0004: macaddr@4 {
macaddr_factory_4: macaddr@4 {
compatible = "mac-base";
reg = <0x0004 0x6>;
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_factory_0024: macaddr@24 {
macaddr_factory_24: macaddr@24 {
compatible = "mac-base";
reg = <0x0024 0x6>;
reg = <0x24 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_factory_002a: macaddr@2a {
macaddr_factory_2a: macaddr@2a {
compatible = "mac-base";
reg = <0x002a 0x6>;
reg = <0x2a 0x6>;
#nvmem-cell-cells = <1>;
};
};
@ -75,13 +67,13 @@
partition@380000 {
label = "fip";
reg = <0x380000 0x0200000>;
reg = <0x380000 0x1c0000>;
read-only;
};
partition@540000 {
label = "zloader";
reg = <0x540000 0x0040000>;
reg = <0x540000 0x40000>;
read-only;
};
@ -97,18 +89,3 @@
};
};
};
&gmac0 {
nvmem-cells = <&macaddr_factory_002a 0>;
nvmem-cell-names = "mac-address";
};
&gmac1 {
nvmem-cells = <&macaddr_factory_0024 0>;
nvmem-cell-names = "mac-address";
};
&wifi {
nvmem-cells = <&eeprom_factory>;
nvmem-cell-names = "eeprom";
};

4
target/linux/mediatek/filogic/base-files/etc/board.d/02_network
View File

@ -70,9 +70,7 @@ mediatek_setup_interfaces()
ruijie,rg-x60-pro|\
unielec,u7981-01*|\
zbtlink,zbt-z8102ax|\
zbtlink,zbt-z8102ax-v2|\
zyxel,ex5601-t0-stock|\
zyxel,ex5601-t0-ubootmod)
zbtlink,zbt-z8102ax-v2)
ucidef_set_interfaces_lan_wan "lan1 lan2 lan3 lan4" eth1
;;
asus,tuf-ax6000|\

10
target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac
View File

@ -200,18 +200,8 @@ case "$board" in
zbtlink,zbt-z8102ax|\
zbtlink,zbt-z8102ax-v2|\
zbtlink,zbt-z8103ax|\
zyxel,ex5601-t0-stock|\
zyxel,ex5601-t0-ubootmod)
addr=$(mtd_get_mac_binary "Factory" 0x4)
[ "$PHYNBR" = "1" ] && macaddr_add $addr 1 > /sys${DEVPATH}/macaddress
;;
wavlink,wl-wn573hx3)
addr=$(mtd_get_mac_binary factory 0x04)
[ "$PHYNBR" = "1" ] && macaddr_setbit_la $(macaddr_add $addr -0x300000) > /sys${DEVPATH}/macaddress
;;
zyxel,nwa50ax-pro)
hw_mac_addr="$(mtd_get_mac_binary mrd 0x1fff8)"
[ "$PHYNBR" = "0" ] && macaddr_add $hw_mac_addr 1 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr 2 > /sys${DEVPATH}/macaddress
;;
esac

14
target/linux/ramips/dts/mt7621_comfast_cf-e390ax.dts
View File

@ -51,6 +51,7 @@
led-failsafe = &led_status_red;
led-running = &led_status_blue;
led-upgrade = &led_status_red;
label-mac-device = &gmac0;
};
};
@ -64,6 +65,15 @@
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
#address-cells = <1>;
#size-cells = <0>;
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_8004>;
nvmem-cell-names = "mac-address";
};
};
};
@ -104,6 +114,10 @@
reg = <0x0 0xe00>;
};
macaddr_factory_8004: macaddr@8004 {
reg = <0x8004 0x6>;
};
macaddr_factory_e000: macaddr@e000 {
compatible = "mac-base";
reg = <0xe000 0x6>;

19
target/linux/ramips/dts/mt7621_dlink_dap-x1860-a1.dts
View File

@ -143,7 +143,9 @@
};
macaddr_factory_4: macaddr@4 {
compatible = "mac-base";
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
precal_factory_e10: precal@e10 {
@ -192,6 +194,21 @@
nvmem-cells = <&eeprom_factory_0>, <&precal_factory_e10>;
nvmem-cell-names = "eeprom", "precal";
mediatek,disable-radar-background;
#address-cells = <1>;
#size-cells = <0>;
band@0 {
reg = <0>;
nvmem-cells = <&macaddr_factory_4 1>;
nvmem-cell-names = "mac-address";
};
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_4 4>;
nvmem-cell-names = "mac-address";
};
};
};
@ -200,7 +217,7 @@
};
&gmac0 {
nvmem-cells = <&macaddr_factory_4>;
nvmem-cells = <&macaddr_factory_4 0>;
nvmem-cell-names = "mac-address";
};

19
target/linux/ramips/dts/mt7621_dlink_dir-853-a1.dts
View File

@ -126,7 +126,9 @@
};
macaddr_factory_e000: macaddr@e000 {
compatible = "mac-base";
reg = <0xe000 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_factory_e006: macaddr@e006 {
@ -169,12 +171,25 @@
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
/* The correct Mac addresses are set in 10_fix_wifi_mac. */
#address-cells = <1>;
#size-cells = <0>;
band@0 {
reg = <0>;
nvmem-cells = <&macaddr_factory_e000 1>;
nvmem-cell-names = "mac-address";
};
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_e000 2>;
nvmem-cell-names = "mac-address";
};
};
};
&gmac0 {
nvmem-cells = <&macaddr_factory_e000>;
nvmem-cells = <&macaddr_factory_e000 0>;
nvmem-cell-names = "mac-address";
};

20
target/linux/ramips/dts/mt7621_dlink_dxx-1xx0-x1.dtsi
View File

@ -110,7 +110,9 @@
};
macaddr_factory_e000: macaddr@e000 {
compatible = "mac-base";
reg = <0xe000 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
@ -134,12 +136,26 @@
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
/* The correct MAC addresses are set in 10_fix_wifi_mac. */
#address-cells = <1>;
#size-cells = <0>;
band@0 {
reg = <0>;
nvmem-cells = <&macaddr_factory_e000 1>;
nvmem-cell-names = "mac-address";
};
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_e000 2>;
nvmem-cell-names = "mac-address";
};
};
};
&gmac0 {
nvmem-cells = <&macaddr_factory_e000>;
nvmem-cells = <&macaddr_factory_e000 0>;
nvmem-cell-names = "mac-address";
};

15
target/linux/ramips/dts/mt7621_glinet_gl-mt1300.dts
View File

@ -101,6 +101,12 @@
reg = <0x0 0x4da8>;
};
macaddr_factory_4: macaddr@4 {
compatible = "mac-base";
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_factory_4000: macaddr@4000 {
compatible = "mac-base";
reg = <0x4000 0x6>;
@ -128,6 +134,15 @@
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
#address-cells = <1>;
#size-cells = <0>;
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_4 1>;
nvmem-cell-names = "mac-address";
};
};
};

13
target/linux/ramips/dts/mt7621_keenetic_kn-1910.dts
View File

@ -132,7 +132,9 @@
};
macaddr_factory_4: macaddr@4 {
compatible = "mac-base";
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_factory_28: macaddr@28 {
@ -215,6 +217,15 @@
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
#address-cells = <1>;
#size-cells = <0>;
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_4 2>;
nvmem-cell-names = "mac-address";
};
};
};
@ -223,7 +234,7 @@
};
&gmac0 {
nvmem-cells = <&macaddr_factory_4>;
nvmem-cells = <&macaddr_factory_4 0>;
nvmem-cell-names = "mac-address";
};

19
target/linux/ramips/dts/mt7621_mercusys_mr70x-v1.dts
View File

@ -125,9 +125,24 @@
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_radio_0>, <&macaddr_config_8 0>;
nvmem-cell-names = "eeprom", "mac-address";
nvmem-cells = <&eeprom_radio_0>;
nvmem-cell-names = "eeprom";
mediatek,disable-radar-background;
#address-cells = <1>;
#size-cells = <0>;
band@0 {
reg = <0>;
nvmem-cells = <&macaddr_config_8 0>;
nvmem-cell-names = "mac-address";
};
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_config_8 (-1)>;
nvmem-cell-names = "mac-address";
};
};
};

13
target/linux/ramips/dts/mt7621_snr_snr-cpe-me2-sfp.dts
View File

@ -111,6 +111,10 @@
reg = <0x0 0x4da8>;
};
macaddr_factory_8004: macaddr@8004 {
reg = <0x8004 0x6>;
};
macaddr_factory_e000: macaddr@e000 {
reg = <0xe000 0x6>;
};
@ -200,5 +204,14 @@
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
#address-cells = <1>;
#size-cells = <0>;
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_8004>;
nvmem-cell-names = "mac-address";
};
};
};

15
target/linux/ramips/dts/mt7621_totolink_x5000r.dts
View File

@ -83,6 +83,12 @@
reg = <0x0 0xe00>;
};
macaddr_factory_4: macaddr@0 {
compatible = "mac-base";
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_factory_e000: macaddr@e000 {
reg = <0xe000 0x6>;
};
@ -113,6 +119,15 @@
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
mediatek,disable-radar-background;
#address-cells = <1>;
#size-cells = <0>;
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_4 4>;
nvmem-cell-names = "mac-address";
};
};
};

19
target/linux/ramips/dts/mt7621_tplink_archer-ax23-v1.dts
View File

@ -161,9 +161,24 @@
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_radio_0>, <&macaddr_config_8 0>;
nvmem-cell-names = "eeprom", "mac-address";
nvmem-cells = <&eeprom_radio_0>;
nvmem-cell-names = "eeprom";
mediatek,disable-radar-background;
#address-cells = <1>;
#size-cells = <0>;
band@0 {
reg = <0>;
nvmem-cells = <&macaddr_config_8 0>;
nvmem-cell-names = "mac-address";
};
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_config_8 (-1)>;
nvmem-cell-names = "mac-address";
};
};
};

19
target/linux/ramips/dts/mt7621_tplink_eap613-v1.dts
View File

@ -79,7 +79,9 @@
#size-cells = <1>;
macaddr: macaddr@8 {
compatible = "mac-base";
reg = <0x8 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
@ -145,11 +147,26 @@
nvmem-cells = <&eeprom_radio_0>;
nvmem-cell-names = "eeprom";
mediatek,disable-radar-background;
#address-cells = <1>;
#size-cells = <0>;
band@0 {
reg = <0>;
nvmem-cells = <&macaddr 0>;
nvmem-cell-names = "mac-address";
};
band@1 {
reg = <1>;
nvmem-cells = <&macaddr 1>;
nvmem-cell-names = "mac-address";
};
};
};
&gmac0 {
nvmem-cells = <&macaddr>;
nvmem-cells = <&macaddr 0>;
nvmem-cell-names = "mac-address";
};

21
target/linux/ramips/dts/mt7621_tplink_eap615-wall-v1.dts
View File

@ -99,7 +99,9 @@
#size-cells = <1>;
macaddr_info_8: macaddr@8 {
compatible = "mac-base";
reg = <0x8 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
@ -165,11 +167,26 @@
nvmem-cells = <&eeprom_radio_0>;
nvmem-cell-names = "eeprom";
mediatek,disable-radar-background;
#address-cells = <1>;
#size-cells = <0>;
band@0 {
reg = <0>;
nvmem-cells = <&macaddr_info_8 0>;
nvmem-cell-names = "mac-address";
};
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_info_8 1>;
nvmem-cell-names = "mac-address";
};
};
};
&gmac0 {
nvmem-cells = <&macaddr_info_8>;
nvmem-cells = <&macaddr_info_8 0>;
nvmem-cell-names = "mac-address";
};
@ -178,7 +195,7 @@
label = "lan0";
phy-handle = <&ethphy0>;
nvmem-cells = <&macaddr_info_8>;
nvmem-cells = <&macaddr_info_8 0>;
nvmem-cell-names = "mac-address";
};

19
target/linux/ramips/dts/mt7621_tplink_ex220-v1.dts
View File

@ -199,9 +199,24 @@
wifi@0,0 {
compatible = "mediatek,mt76";
reg = <0x0000 0 0 0 0>;
nvmem-cells = <&eeprom_radio_0>, <&precal_radio_e10>, <&macaddr_rom_file_f100 0>;
nvmem-cell-names = "eeprom", "precal", "mac-address";
nvmem-cells = <&eeprom_radio_0>, <&precal_radio_e10>;
nvmem-cell-names = "eeprom", "precal";
mediatek,disable-radar-background;
#address-cells = <1>;
#size-cells = <0>;
band@0 {
reg = <0>;
nvmem-cells = <&macaddr_rom_file_f100 0>;
nvmem-cell-names = "mac-address";
};
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_rom_file_f100 2>;
nvmem-cell-names = "mac-address";
};
};
};

15
target/linux/ramips/dts/mt7621_z-router_zr-2660.dts
View File

@ -135,6 +135,12 @@
reg = <0x0 0xe00>;
};
macaddr_factory_4: macaddr@4 {
compatible = "mac-base";
reg = <0x4 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_factory_3fff4: macaddr@3fff4 {
reg = <0x3fff4 0x6>;
};
@ -179,6 +185,15 @@
nvmem-cells = <&eeprom_factory_0>;
nvmem-cell-names = "eeprom";
#address-cells = <1>;
#size-cells = <0>;
band@1 {
reg = <1>;
nvmem-cells = <&macaddr_factory_4 1>;
nvmem-cell-names = "mac-address";
};
};
};

30
target/linux/ramips/dts/mt7628an_tplink_re305-v1.dts
View File

@ -5,6 +5,23 @@
/ {
compatible = "tplink,re305-v1", "mediatek,mt7628an-soc";
model = "TP-Link RE305 v1";
virtual_flash {
compatible = "mtd-concat";
devices = <&fwconcat0>, <&fwconcat1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
compatible = "tplink,firmware";
label = "firmware";
reg = <0x0 0x0>;
};
};
};
};
&spi0 {
@ -26,9 +43,8 @@
read-only;
};
partition@20000 {
compatible = "tplink,firmware";
label = "firmware";
fwconcat0: partition@20000 {
label = "fwconcat0";
reg = <0x20000 0x5e0000>;
};
@ -50,10 +66,10 @@
};
};
/*
The flash space between 0x650000 and 0x7f0000 is blank in the
stock firmware so it is left out as well.
*/
fwconcat1: partition@650000 {
label = "fwconcat1";
reg = <0x650000 0x1a0000>;
};
partition@7f0000 {
label = "radio";

8
target/linux/ramips/image/mt76x8.mk
View File

@ -902,10 +902,16 @@ TARGET_DEVICES += tplink_re220-v2
define Device/tplink_re305-v1
$(Device/tplink-safeloader)
IMAGE_SIZE := 6016k
IMAGE_SIZE := 7680k
KERNEL_SIZE := 6016k
DEVICE_MODEL := RE305
DEVICE_VARIANT := v1
DEVICE_PACKAGES := kmod-mt76x2
DEVICE_COMPAT_VERSION := 2.0
DEVICE_COMPAT_MESSAGE := Partition design has changed compared to older versions due to size restrictions and unsused flash. \
Upgrade via sysupgrade mechanism is not possible, so new installation via TFTP is required.
IMAGES := sysupgrade.bin
IMAGE/sysupgrade.bin := append-kernel | append-rootfs | pad-rootfs | check-size | append-metadata
TPLINK_BOARD_ID := RE305-V1
endef
TARGET_DEVICES += tplink_re305-v1

5
target/linux/ramips/mt7621/base-files/etc/board.d/02_network
View File

@ -244,11 +244,6 @@ ramips_setup_macs()
lan_mac=$wan_mac
label_mac=$wan_mac
;;
comfast,cf-e390ax)
lan_mac=$(cat /sys/class/net/eth0/address)
label_mac=$lan_mac
wan_mac=$(macaddr_add "$lan_mac" 1)
;;
dlink,covr-x1860-a1)
label_mac=$(mtd_get_mac_ascii config2 factory_mac)
wan_mac=$(macaddr_add "$label_mac" 3)

52
target/linux/ramips/mt7621/base-files/etc/hotplug.d/ieee80211/10_fix_wifi_mac
View File

@ -44,25 +44,12 @@ case "$board" in
c-life,xg1)
[ "$PHYNBR" = "1" ] && macaddr_setbit_la "$(macaddr_add $(get_mac_label) 1)" > /sys${DEVPATH}/macaddress
;;
comfast,cf-e390ax)
[ "$PHYNBR" = "0" ] && echo -n "$(mtd_get_mac_binary factory 0x0004)" > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && echo -n "$(mtd_get_mac_binary factory 0x8004)" > /sys${DEVPATH}/macaddress
;;
cudy,x6-v1|\
cudy,x6-v2)
hw_mac_addr="$(mtd_get_mac_binary bdinfo 0xde00)"
[ "$PHYNBR" = "1" ] && \
macaddr_setbit_la "$(macaddr_add $hw_mac_addr 0x100000)" > /sys${DEVPATH}/macaddress
;;
dlink,dap-1620-b1|\
dlink,dir-853-a1|\
dlink,dra-1360-a1)
lan_mac_addr="$(mtd_get_mac_binary factory 0xe000)"
[ "$PHYNBR" = "0" ] && \
macaddr_add $lan_mac_addr 1 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && \
macaddr_add $lan_mac_addr 2 > /sys${DEVPATH}/macaddress
;;
dlink,covr-x1860-a1)
label_mac=$(mtd_get_mac_ascii config2 factory_mac)
[ "$PHYNBR" = "0" ] && \
@ -70,13 +57,6 @@ case "$board" in
[ "$PHYNBR" = "1" ] && \
macaddr_add $label_mac 2 > /sys${DEVPATH}/macaddress
;;
dlink,dap-x1860-a1)
hw_mac_addr="$(mtd_get_mac_binary factory 0x4)"
[ "$PHYNBR" = "0" ] && \
macaddr_add $hw_mac_addr 1 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && \
macaddr_add $hw_mac_addr 4 > /sys${DEVPATH}/macaddress
;;
dlink,dir-3040-a1)
lan_mac_addr="$(mtd_get_mac_binary factory 0xe000)"
[ "$PHYNBR" = "0" ] && \
@ -94,11 +74,6 @@ case "$board" in
macaddr_setbit_la "$base_mac" > /sys${DEVPATH}/macaddress
fi
;;
glinet,gl-mt1300|\
z-router,zr-2660)
[ "$PHYNBR" = "1" ] && \
macaddr_add "$(mtd_get_mac_binary factory 0x4)" 1 > /sys${DEVPATH}/macaddress
;;
h3c,tx1800-plus|\
h3c,tx1801-plus|\
h3c,tx1806)
@ -139,11 +114,6 @@ case "$board" in
[ "$PHYNBR" = "0" ] && echo $hw_mac_addr > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr 0x800000 > /sys${DEVPATH}/macaddress
;;
keenetic,kn-1910)
lan_mac_addr="$(mtd_get_mac_binary RF-EEPROM 0x4)"
[ "$PHYNBR" = "1" ] && \
macaddr_add $lan_mac_addr 2 > /sys${DEVPATH}/macaddress
;;
keenetic,kn-3510)
[ "$PHYNBR" = "1" ] && \
macaddr_setbit_la "$(mtd_get_mac_binary rf-eeprom 0x4)" > /sys${DEVPATH}/macaddress
@ -188,11 +158,6 @@ case "$board" in
[ "$PHYNBR" = "0" ] && echo -n "$hw_mac_2g" > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && echo -n "$hw_mac_5g" > /sys${DEVPATH}/macaddress
;;
mercusys,mr70x-v1|\
tplink,archer-ax23-v1)
hw_mac_addr="$(mtd_get_mac_binary config 0x8)"
[ "$PHYNBR" = "1" ] && macaddr_add "$hw_mac_addr" -1 > "/sys${DEVPATH}/macaddress"
;;
mts,wg430223)
hw_mac_addr=$(macaddr_add $(mtd_get_mac_encrypted_arcadyan "board_data") 1)
[ "$PHYNBR" = "0" ] && echo -n "$hw_mac_addr" > /sys${DEVPATH}/macaddress
@ -216,27 +181,10 @@ case "$board" in
[ "$PHYNBR" = "0" ] && macaddr_add $hw_mac_addr 1 > /sys${DEVPATH}/macaddress
[ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr 2 > /sys${DEVPATH}/macaddress
;;
snr,snr-cpe-me2-sfp)
hw_mac_addr="$(mtd_get_mac_binary factory 0x8004)"
[ "$PHYNBR" = "1" ] && echo -n "$hw_mac_addr" > /sys${DEVPATH}/macaddress
;;
tenbay,t-mb5eu-v01)
hw_mac_addr="$(mtd_get_mac_binary factory 0x4)"
[ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr "0x100000" > /sys${DEVPATH}/macaddress
;;
totolink,x5000r)
hw_mac_addr="$(mtd_get_mac_binary factory 0x4)"
[ "$PHYNBR" = "1" ] && macaddr_add $hw_mac_addr 4 > /sys${DEVPATH}/macaddress
;;
tplink,eap613-v1|\
tplink,eap615-wall-v1)
hw_mac_addr="$(mtd_get_mac_binary product-info 0x8)"
macaddr_add "$hw_mac_addr" "$PHYNBR" > "/sys${DEVPATH}/macaddress"
;;
tplink,ex220-v1)
hw_mac_addr="$(mtd_get_mac_binary rom_file 0xf100)"
[ "$PHYNBR" = "1" ] && macaddr_add "$hw_mac_addr" 2 > "/sys${DEVPATH}/macaddress"
;;
yuncore,ax820|\
yuncore,g720)
[ "$PHYNBR" = "1" ] && \

15
target/linux/ramips/mt76x8/base-files/etc/board.d/05_compat-version Normal file
View File

@ -0,0 +1,15 @@
. /lib/functions.sh
. /lib/functions/uci-defaults.sh
board_config_update
case "$(board_name)" in
tplink,re305-v1)
ucidef_set_compat_version "2.0"
;;
esac
board_config_flush
exit 0

317
target/linux/realtek/files-6.12/arch/mips/include/asm/mach-rtl838x/mach-rtl83xx.h
View File

@ -13,215 +13,11 @@
* Register access macros
*/
#define RTL838X_SW_BASE ((volatile void *) 0xBB000000)
#define RTL838X_SW_BASE ((volatile void *) 0xBB000000)
#define rtl83xx_r32(reg) readl(reg)
#define rtl83xx_w32(val, reg) writel(val, reg)
#define rtl83xx_w32_mask(clear, set, reg) rtl83xx_w32((rtl83xx_r32(reg) & ~(clear)) | (set), reg)
#define rtl83xx_r8(reg) readb(reg)
#define rtl83xx_w8(val, reg) writeb(val, reg)
#define sw_r32(reg) readl(RTL838X_SW_BASE + reg)
#define sw_w32(val, reg) writel(val, RTL838X_SW_BASE + reg)
#define sw_w32_mask(clear, set, reg) \
sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
#define sw_r64(reg) ((((u64)readl(RTL838X_SW_BASE + reg)) << 32) | \
readl(RTL838X_SW_BASE + reg + 4))
#define sw_w64(val, reg) do { \
writel((u32)((val) >> 32), RTL838X_SW_BASE + reg); \
writel((u32)((val) & 0xffffffff), \
RTL838X_SW_BASE + reg + 4); \
} while (0)
/*
* SPRAM
*/
#define RTL838X_ISPRAM_BASE 0x0
#define RTL838X_DSPRAM_BASE 0x0
/*
* IRQ Controller
*/
#define RTL838X_IRQ_CPU_BASE 0
#define RTL838X_IRQ_CPU_NUM 8
#define RTL838X_IRQ_ICTL_BASE (RTL838X_IRQ_CPU_BASE + RTL838X_IRQ_CPU_NUM)
#define RTL838X_IRQ_ICTL_NUM 32
#define RTL83XX_IRQ_UART0 31
#define RTL83XX_IRQ_UART1 30
#define RTL83XX_IRQ_TC0 29
#define RTL83XX_IRQ_TC1 28
#define RTL83XX_IRQ_OCPTO 27
#define RTL83XX_IRQ_HLXTO 26
#define RTL83XX_IRQ_SLXTO 25
#define RTL83XX_IRQ_NIC 24
#define RTL83XX_IRQ_GPIO_ABCD 23
#define RTL83XX_IRQ_GPIO_EFGH 22
#define RTL83XX_IRQ_RTC 21
#define RTL83XX_IRQ_SWCORE 20
#define RTL83XX_IRQ_WDT_IP1 19
#define RTL83XX_IRQ_WDT_IP2 18
#define RTL9300_UART1_IRQ 31
#define RTL9300_UART0_IRQ 30
#define RTL9300_USB_H2_IRQ 28
#define RTL9300_NIC_IRQ 24
#define RTL9300_SWCORE_IRQ 23
#define RTL9300_GPIO_ABC_IRQ 13
#define RTL9300_TC4_IRQ 11
#define RTL9300_TC3_IRQ 10
#define RTL9300_TC2_IRQ 9
#define RTL9300_TC1_IRQ 8
#define RTL9300_TC0_IRQ 7
/*
* MIPS32R2 counter
*/
#define RTL838X_COMPARE_IRQ (RTL838X_IRQ_CPU_BASE + 7)
/*
* ICTL
* Base address 0xb8003000UL
*/
#define RTL838X_ICTL1_IRQ (RTL838X_IRQ_CPU_BASE + 2)
#define RTL838X_ICTL2_IRQ (RTL838X_IRQ_CPU_BASE + 3)
#define RTL838X_ICTL3_IRQ (RTL838X_IRQ_CPU_BASE + 4)
#define RTL838X_ICTL4_IRQ (RTL838X_IRQ_CPU_BASE + 5)
#define RTL838X_ICTL5_IRQ (RTL838X_IRQ_CPU_BASE + 6)
#define GIMR (0x00)
#define UART0_IE (1 << 31)
#define UART1_IE (1 << 30)
#define TC0_IE (1 << 29)
#define TC1_IE (1 << 28)
#define OCPTO_IE (1 << 27)
#define HLXTO_IE (1 << 26)
#define SLXTO_IE (1 << 25)
#define NIC_IE (1 << 24)
#define GPIO_ABCD_IE (1 << 23)
#define GPIO_EFGH_IE (1 << 22)
#define RTC_IE (1 << 21)
#define WDT_IP1_IE (1 << 19)
#define WDT_IP2_IE (1 << 18)
#define GISR (0x04)
#define UART0_IP (1 << 31)
#define UART1_IP (1 << 30)
#define TC0_IP (1 << 29)
#define TC1_IP (1 << 28)
#define OCPTO_IP (1 << 27)
#define HLXTO_IP (1 << 26)
#define SLXTO_IP (1 << 25)
#define NIC_IP (1 << 24)
#define GPIO_ABCD_IP (1 << 23)
#define GPIO_EFGH_IP (1 << 22)
#define RTC_IP (1 << 21)
#define WDT_IP1_IP (1 << 19)
#define WDT_IP2_IP (1 << 18)
/* Interrupt Routing Selection */
#define UART0_RS 2
#define UART1_RS 1
#define TC0_RS 5
#define TC1_RS 1
#define OCPTO_RS 1
#define HLXTO_RS 1
#define SLXTO_RS 1
#define NIC_RS 4
#define GPIO_ABCD_RS 4
#define GPIO_EFGH_RS 4
#define RTC_RS 4
#define SWCORE_RS 3
#define WDT_IP1_RS 4
#define WDT_IP2_RS 5
/* Interrupt IRQ Assignments */
#define UART0_IRQ 31
#define UART1_IRQ 30
#define TC0_IRQ 29
#define TC1_IRQ 28
#define OCPTO_IRQ 27
#define HLXTO_IRQ 26
#define SLXTO_IRQ 25
#define NIC_IRQ 24
#define GPIO_ABCD_IRQ 23
#define GPIO_EFGH_IRQ 22
#define RTC_IRQ 21
#define SWCORE_IRQ 20
#define WDT_IP1_IRQ 19
#define WDT_IP2_IRQ 18
#define SYSTEM_FREQ 200000000
#define RTL838X_UART0_BASE ((volatile void *)(0xb8002000UL))
#define RTL838X_UART0_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
#define RTL838X_UART0_FREQ (SYSTEM_FREQ - RTL838X_UART0_BAUD * 24)
#define RTL838X_UART0_MAPBASE 0x18002000UL
#define RTL838X_UART0_MAPSIZE 0x100
#define RTL838X_UART0_IRQ UART0_IRQ
#define RTL838X_UART1_BASE ((volatile void *)(0xb8002100UL))
#define RTL838X_UART1_BAUD 38400 /* ex. 19200 or 38400 or 57600 or 115200 */
#define RTL838X_UART1_FREQ (SYSTEM_FREQ - RTL838X_UART1_BAUD * 24)
#define RTL838X_UART1_MAPBASE 0x18002100UL
#define RTL838X_UART1_MAPSIZE 0x100
#define RTL838X_UART1_IRQ UART1_IRQ
#define UART0_RBR (RTL838X_UART0_BASE + 0x000)
#define UART0_THR (RTL838X_UART0_BASE + 0x000)
#define UART0_DLL (RTL838X_UART0_BASE + 0x000)
#define UART0_IER (RTL838X_UART0_BASE + 0x004)
#define UART0_DLM (RTL838X_UART0_BASE + 0x004)
#define UART0_IIR (RTL838X_UART0_BASE + 0x008)
#define UART0_FCR (RTL838X_UART0_BASE + 0x008)
#define UART0_LCR (RTL838X_UART0_BASE + 0x00C)
#define UART0_MCR (RTL838X_UART0_BASE + 0x010)
#define UART0_LSR (RTL838X_UART0_BASE + 0x014)
#define UART1_RBR (RTL838X_UART1_BASE + 0x000)
#define UART1_THR (RTL838X_UART1_BASE + 0x000)
#define UART1_DLL (RTL838X_UART1_BASE + 0x000)
#define UART1_IER (RTL838X_UART1_BASE + 0x004)
#define UART1_DLM (RTL838X_UART1_BASE + 0x004)
#define UART1_IIR (RTL838X_UART1_BASE + 0x008)
#define UART1_FCR (RTL838X_UART1_BASE + 0x008)
#define UART1_LCR (RTL838X_UART1_BASE + 0x00C)
#define UART1_MCR (RTL838X_UART1_BASE + 0x010)
#define UART1_LSR (RTL838X_UART1_BASE + 0x014)
/*
* Memory Controller
*/
#define MC_MCR 0xB8001000
#define MC_MCR_VAL 0x00000000
#define MC_DCR 0xB8001004
#define MC_DCR0_VAL 0x54480000
#define MC_DTCR 0xB8001008
#define MC_DTCR_VAL 0xFFFF05C0
/*
* GPIO
*/
#define GPIO_CTRL_REG_BASE ((volatile void *) 0xb8003500)
#define RTL838X_GPIO_PABC_CNR (GPIO_CTRL_REG_BASE + 0x0)
#define RTL838X_GPIO_PABC_TYPE (GPIO_CTRL_REG_BASE + 0x04)
#define RTL838X_GPIO_PABC_DIR (GPIO_CTRL_REG_BASE + 0x8)
#define RTL838X_GPIO_PABC_DATA (GPIO_CTRL_REG_BASE + 0xc)
#define RTL838X_GPIO_PABC_ISR (GPIO_CTRL_REG_BASE + 0x10)
#define RTL838X_GPIO_PAB_IMR (GPIO_CTRL_REG_BASE + 0x14)
#define RTL838X_GPIO_PC_IMR (GPIO_CTRL_REG_BASE + 0x18)
#define RTL930X_GPIO_CTRL_REG_BASE ((volatile void *) 0xb8003300)
#define RTL930X_GPIO_PABCD_DIR (RTL930X_GPIO_CTRL_REG_BASE + 0x8)
#define RTL930X_GPIO_PABCD_DAT (RTL930X_GPIO_CTRL_REG_BASE + 0xc)
#define RTL930X_GPIO_PABCD_ISR (RTL930X_GPIO_CTRL_REG_BASE + 0x10)
#define RTL930X_GPIO_PAB_IMR (RTL930X_GPIO_CTRL_REG_BASE + 0x14)
#define RTL930X_GPIO_PCD_IMR (RTL930X_GPIO_CTRL_REG_BASE + 0x18)
#define sw_r32(reg) readl(RTL838X_SW_BASE + reg)
#define sw_w32(val, reg) writel(val, RTL838X_SW_BASE + reg)
#define sw_w32_mask(clear, set, reg) sw_w32((sw_r32(reg) & ~(clear)) | (set), reg)
#define RTL838X_MODEL_NAME_INFO (0x00D4)
#define RTL838X_CHIP_INFO (0x00D8)
@ -232,67 +28,16 @@
#define RTL838X_LED_GLB_CTRL (0xA000)
#define RTL839X_LED_GLB_CTRL (0x00E4)
#define RTL9302_LED_GLB_CTRL (0xcc00)
#define RTL930X_LED_GLB_CTRL (0xCC00)
#define RTL931X_LED_GLB_CTRL (0x0600)
#define RTL930X_EXT_GPIO_GLB_CTRL (0xC600)
#define RTL931X_EXT_GPIO_GLB_CTRL (0x07D4)
#define RTL838X_EXT_GPIO_DIR (0xA08C)
#define RTL839X_EXT_GPIO_DIR (0x0214)
#define RTL930X_EXT_GPIO_DIR (0xC608)
#define RTL931X_EXT_GPIO_DIR (0x07DC)
#define RTL838X_EXT_GPIO_DATA (0xA094)
#define RTL839X_EXT_GPIO_DATA (0x021c)
#define RTL930X_EXT_GPIO_DATA (0xC614)
#define RTL931X_EXT_GPIO_DATA (0x07E8)
#define RTL838X_EXT_GPIO_INDRT_ACCESS (0xA09C)
#define RTL839X_EXT_GPIO_INDRT_ACCESS (0x0224)
#define RTL930X_EXT_GPIO_INDRT_ACCESS (0xC620)
#define RTL931X_EXT_GPIO_INDRT_ACCESS (0x07F4)
#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0)
#define RTL838X_DMY_REG5 (0x0144)
#define RTL838X_EXTRA_GPIO_CTRL (0xA0E0)
#define RTL838X_GMII_INTF_SEL (0x1000)
#define RTL838X_IO_DRIVING_ABILITY_CTRL (0x1010)
#define RTL838X_GPIO_A7 31
#define RTL838X_GPIO_A6 30
#define RTL838X_GPIO_A5 29
#define RTL838X_GPIO_A4 28
#define RTL838X_GPIO_A3 27
#define RTL838X_GPIO_A2 26
#define RTL838X_GPIO_A1 25
#define RTL838X_GPIO_A0 24
#define RTL838X_GPIO_B7 23
#define RTL838X_GPIO_B6 22
#define RTL838X_GPIO_B5 21
#define RTL838X_GPIO_B4 20
#define RTL838X_GPIO_B3 19
#define RTL838X_GPIO_B2 18
#define RTL838X_GPIO_B1 17
#define RTL838X_GPIO_B0 16
#define RTL838X_GPIO_C7 15
#define RTL838X_GPIO_C6 14
#define RTL838X_GPIO_C5 13
#define RTL838X_GPIO_C4 12
#define RTL838X_GPIO_C3 11
#define RTL838X_GPIO_C2 10
#define RTL838X_GPIO_C1 9
#define RTL838X_GPIO_C0 8
#define RTL838X_INT_RW_CTRL (0x0058)
#define RTL838X_EXT_VERSION (0x00D0)
#define RTL838X_PLL_CML_CTRL (0x0FF8)
#define RTL838X_STRAP_DBG (0x100C)
/*
* Reset
*/
#define RGCR (0x1E70)
#define RTL838X_RST_GLB_CTRL_0 (0x003c)
#define RTL838X_RST_GLB_CTRL_1 (0x0040)
#define RTL839X_RST_GLB_CTRL (0x0014)
@ -316,7 +61,7 @@
#define RTL838X_LED2_SW_P_EN_CTRL (0xA018)
#define RTL839X_LED2_SW_P_EN_CTRL (0x0134)
#define RTL838X_LED_SW_P_CTRL (0xA01C)
#define RTL838X_LED_SW_P_CTRL_PORT(p) (RTL838X_LED_SW_P_CTRL + (((p) << 2)))
#define RTL838X_LED_SW_P_CTRL_PORT(p) (RTL838X_LED_SW_P_CTRL + (((p) << 2)))
#define RTL839X_LED_SW_P_CTRL (0x0144)
#define RTL839X_MAC_EFUSE_CTRL (0x02ac)
@ -325,45 +70,13 @@
* MDIO via Realtek's SMI interface
*/
#define RTL838X_SMI_GLB_CTRL (0xa100)
#define RTL838X_SMI_ACCESS_PHY_CTRL_0 (0xa1b8)
#define RTL838X_SMI_ACCESS_PHY_CTRL_1 (0xa1bc)
#define RTL838X_SMI_ACCESS_PHY_CTRL_2 (0xa1c0)
#define RTL838X_SMI_ACCESS_PHY_CTRL_3 (0xa1c4)
#define RTL838X_SMI_PORT0_5_ADDR_CTRL (0xa1c8)
#define RTL838X_SMI_POLL_CTRL (0xa17c)
#define RTL839X_SMI_GLB_CTRL (0x03f8)
#define RTL839X_SMI_PORT_POLLING_CTRL (0x03fc)
#define RTL839X_PHYREG_ACCESS_CTRL (0x03DC)
#define RTL839X_PHYREG_CTRL (0x03E0)
#define RTL839X_PHYREG_PORT_CTRL (0x03E4)
#define RTL839X_PHYREG_DATA_CTRL (0x03F0)
#define RTL839X_PHYREG_MMD_CTRL (0x3F4)
#define RTL930X_SMI_GLB_CTRL (0xCA00)
#define RTL930X_SMI_POLL_CTRL (0xca90)
#define RTL930X_SMI_PORT0_15_POLLING_SEL (0xCA08)
#define RTL930X_SMI_PORT16_27_POLLING_SEL (0xCA0C)
#define RTL930X_SMI_PORT0_5_ADDR (0xCB80)
#define RTL930X_SMI_ACCESS_PHY_CTRL_0 (0xCB70)
#define RTL930X_SMI_ACCESS_PHY_CTRL_1 (0xCB74)
#define RTL930X_SMI_ACCESS_PHY_CTRL_2 (0xCB78)
#define RTL930X_SMI_ACCESS_PHY_CTRL_3 (0xCB7C)
#define RTL931X_SMI_GLB_CTRL1 (0x0CBC)
#define RTL931X_SMI_GLB_CTRL0 (0x0CC0)
#define RTL931X_SMI_PORT_POLLING_CTRL (0x0CCC)
#define RTL931X_SMI_PORT_ADDR (0x0C74)
#define RTL931X_SMI_PORT_POLLING_SEL (0x0C9C)
#define RTL9310_SMI_PORT_POLLING_CTRL (0x0CCC)
#define RTL931X_SMI_INDRT_ACCESS_CTRL_0 (0x0C00)
#define RTL931X_SMI_INDRT_ACCESS_CTRL_1 (0x0C04)
#define RTL931X_SMI_INDRT_ACCESS_CTRL_2 (0x0C08)
#define RTL931X_SMI_INDRT_ACCESS_CTRL_3 (0x0C10)
#define RTL931X_SMI_INDRT_ACCESS_BC_PHYID_CTRL (0x0C14)
#define RTL931X_SMI_INDRT_ACCESS_MMD_CTRL (0xC18)
#define RTL931X_MAC_L2_GLOBAL_CTRL2 (0x1358)
#define RTL931X_MAC_L2_GLOBAL_CTRL1 (0x5548)
/* Switch interrupts */
#define RTL838X_IMR_GLB (0x1100)
@ -387,19 +100,19 @@
#define RTL931X_ISR_PORT_LINK_STS_CHG (0x12B8)
/* Definition of family IDs */
#define RTL8380_FAMILY_ID (0x8380)
#define RTL8390_FAMILY_ID (0x8390)
#define RTL9300_FAMILY_ID (0x9300)
#define RTL9310_FAMILY_ID (0x9310)
#define RTL8380_FAMILY_ID (0x8380)
#define RTL8390_FAMILY_ID (0x8390)
#define RTL9300_FAMILY_ID (0x9300)
#define RTL9310_FAMILY_ID (0x9310)
/* SPI Support */
#define RTL931X_SPI_CTRL0 (0x103C)
/* Basic SoC Features */
#define RTL838X_CPU_PORT 28
#define RTL839X_CPU_PORT 52
#define RTL930X_CPU_PORT 28
#define RTL931X_CPU_PORT 56
#define RTL838X_CPU_PORT 28
#define RTL839X_CPU_PORT 52
#define RTL930X_CPU_PORT 28
#define RTL931X_CPU_PORT 56
struct rtl83xx_soc_info {
unsigned char *name;
@ -409,9 +122,7 @@ struct rtl83xx_soc_info {
unsigned int cpu;
bool testchip;
unsigned char *compatible;
volatile void *sw_base;
volatile void *icu_base;
int cpu_port;
};
#endif /* _MACH_RTL838X_H_ */
#endif /* _MACH_RTL838X_H_ */