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rockchip: refresh kernel patches
Fixes: #1292 Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen
parent
3f9c612189
commit
e628dadacf
@ -17,7 +17,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
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--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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+++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
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@@ -245,7 +245,7 @@ static int rockchip_combphy_exit(struct
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@@ -248,7 +248,7 @@ static int rockchip_combphy_exit(struct
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return 0;
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}
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@ -26,7 +26,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
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.init = rockchip_combphy_init,
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.exit = rockchip_combphy_exit,
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.owner = THIS_MODULE,
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@@ -352,7 +352,7 @@ static int rockchip_combphy_probe(struct
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@@ -364,7 +364,7 @@ static int rockchip_combphy_probe(struct
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return ret;
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}
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@ -37,7 +37,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
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return PTR_ERR(priv->phy);
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--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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@@ -187,7 +187,7 @@ static const struct rockchip_p3phy_ops r
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@@ -182,7 +182,7 @@ static const struct rockchip_p3phy_ops r
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.phy_init = rockchip_p3phy_rk3588_init,
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};
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@ -46,7 +46,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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int ret;
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@@ -210,7 +210,7 @@ static int rochchip_p3phy_init(struct ph
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@@ -205,7 +205,7 @@ static int rochchip_p3phy_init(struct ph
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return ret;
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}
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@ -55,7 +55,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
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{
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struct rockchip_p3phy_priv *priv = phy_get_drvdata(phy);
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@@ -219,9 +219,9 @@ static int rochchip_p3phy_exit(struct ph
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@@ -214,9 +214,9 @@ static int rochchip_p3phy_exit(struct ph
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return 0;
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}
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@ -68,7 +68,7 @@ Signed-off-by: Vinod Koul <vkoul@kernel.org>
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.set_mode = rockchip_p3phy_set_mode,
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.owner = THIS_MODULE,
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};
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@@ -280,7 +280,7 @@ static int rockchip_p3phy_probe(struct p
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@@ -275,7 +275,7 @@ static int rockchip_p3phy_probe(struct p
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return priv->num_lanes;
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}
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@ -1,95 +0,0 @@
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From f8020dfb311d2b6cf657668792aaa5fa8863a7dd Mon Sep 17 00:00:00 2001
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From: Michal Tomek <mtdev79b@gmail.com>
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Date: Thu, 4 Apr 2024 19:11:26 +0200
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Subject: [PATCH] phy: rockchip-snps-pcie3: fix bifurcation on rk3588
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So far all RK3588 boards use fully aggregated PCIe. CM3588 is one
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of the few boards using this feature and apparently it is broken.
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The PHY offers the following mapping options:
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port 0 lane 0 - always mapped to controller 0 (4L)
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port 0 lane 1 - to controller 0 or 2 (1L0)
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port 1 lane 0 - to controller 0 or 1 (2L)
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port 1 lane 1 - to controller 0, 1 or 3 (1L1)
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The data-lanes DT property maps these as follows:
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0 = no controller (unsupported by the HW)
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1 = 4L
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2 = 2L
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3 = 1L0
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4 = 1L1
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That allows the following configurations with first column being the
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mainline data-lane mapping, second column being the downstream name,
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third column being PCIE3PHY_GRF_CMN_CON0 and PHP_GRF_PCIESEL register
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values and final column being the user visible lane setup:
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<1 1 1 1> = AGGREG = [4 0] = x4 (aggregation)
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<1 1 2 2> = NANBNB = [0 0] = x2 x2 (no bif.)
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<1 3 2 2> = NANBBI = [1 1] = x2 x1x1 (bif. of port 0)
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<1 1 2 4> = NABINB = [2 2] = x1x1 x2 (bif. of port 1)
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<1 3 2 4> = NABIBI = [3 3] = x1x1 x1x1 (bif. of both ports)
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The driver currently does not program PHP_GRF_PCIESEL correctly, which
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is fixed by this patch. As a side-effect the new logic is much simpler
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than the old logic.
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Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3")
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Signed-off-by: Michal Tomek <mtdev79b@gmail.com>
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Acked-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-1-9907136eeafd@kernel.org
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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.../phy/rockchip/phy-rockchip-snps-pcie3.c | 24 +++++++------------
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1 file changed, 8 insertions(+), 16 deletions(-)
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--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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@@ -132,7 +132,7 @@ static const struct rockchip_p3phy_ops r
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static int rockchip_p3phy_rk3588_init(struct rockchip_p3phy_priv *priv)
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{
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u32 reg = 0;
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- u8 mode = 0;
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+ u8 mode = RK3588_LANE_AGGREGATION; /* default */
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int ret;
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/* Deassert PCIe PMA output clamp mode */
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@@ -140,28 +140,20 @@ static int rockchip_p3phy_rk3588_init(st
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/* Set bifurcation if needed */
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for (int i = 0; i < priv->num_lanes; i++) {
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- if (!priv->lanes[i])
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- mode |= (BIT(i) << 3);
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-
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if (priv->lanes[i] > 1)
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- mode |= (BIT(i) >> 1);
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- }
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-
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- if (!mode)
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- reg = RK3588_LANE_AGGREGATION;
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- else {
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- if (mode & (BIT(0) | BIT(1)))
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- reg |= RK3588_BIFURCATION_LANE_0_1;
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-
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- if (mode & (BIT(2) | BIT(3)))
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- reg |= RK3588_BIFURCATION_LANE_2_3;
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+ mode &= ~RK3588_LANE_AGGREGATION;
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+ if (priv->lanes[i] == 3)
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+ mode |= RK3588_BIFURCATION_LANE_0_1;
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+ if (priv->lanes[i] == 4)
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+ mode |= RK3588_BIFURCATION_LANE_2_3;
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}
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+ reg = mode;
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
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/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
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if (!IS_ERR(priv->pipe_grf)) {
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- reg = (mode & (BIT(6) | BIT(7))) >> 6;
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+ reg = mode & 3;
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if (reg)
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regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
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(reg << 16) | reg);
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@ -1,52 +0,0 @@
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From 55491a5fa163bf15158f34f3650b3985f25622b9 Mon Sep 17 00:00:00 2001
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From: Sebastian Reichel <sebastian.reichel@collabora.com>
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Date: Thu, 4 Apr 2024 19:11:27 +0200
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Subject: [PATCH] phy: rockchip-snps-pcie3: fix clearing PHP_GRF_PCIESEL_CON
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bits
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Currently the PCIe v3 PHY driver only sets the pcie1ln_sel bits, but
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does not clear them because of an incorrect write mask. This fixes up
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the issue by using a newly introduced constant for the write mask.
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While at it also introduces a proper GENMASK based constant for the
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PCIE30_PHY_MODE.
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Fixes: 2e9bffc4f713 ("phy: rockchip: Support PCIe v3")
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Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
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Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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Link: https://lore.kernel.org/r/20240404-rk3588-pcie-bifurcation-fixes-v1-2-9907136eeafd@kernel.org
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Signed-off-by: Vinod Koul <vkoul@kernel.org>
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---
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drivers/phy/rockchip/phy-rockchip-snps-pcie3.c | 9 ++++++---
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1 file changed, 6 insertions(+), 3 deletions(-)
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--- a/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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+++ b/drivers/phy/rockchip/phy-rockchip-snps-pcie3.c
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@@ -40,6 +40,8 @@
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#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
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#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
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#define RK3588_LANE_AGGREGATION BIT(2)
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+#define RK3588_PCIE1LN_SEL_EN (GENMASK(1, 0) << 16)
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+#define RK3588_PCIE30_PHY_MODE_EN (GENMASK(2, 0) << 16)
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struct rockchip_p3phy_ops;
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@@ -149,14 +151,15 @@ static int rockchip_p3phy_rk3588_init(st
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}
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reg = mode;
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- regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0, (0x7<<16) | reg);
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+ regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
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+ RK3588_PCIE30_PHY_MODE_EN | reg);
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/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
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if (!IS_ERR(priv->pipe_grf)) {
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- reg = mode & 3;
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+ reg = mode & (RK3588_BIFURCATION_LANE_0_1 | RK3588_BIFURCATION_LANE_2_3);
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if (reg)
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regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
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- (reg << 16) | reg);
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+ RK3588_PCIE1LN_SEL_EN | reg);
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}
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reset_control_deassert(priv->p30phy);
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@ -715,7 +715,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231108001259.15123-11-dakr
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--- a/include/drm/drm_gem.h
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+++ b/include/drm/drm_gem.h
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@@ -571,7 +571,7 @@ int drm_gem_evict(struct drm_gem_object
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@@ -584,7 +584,7 @@ static inline bool drm_gem_object_is_sha
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* drm_gem_gpuva_init() - initialize the gpuva list of a GEM object
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* @obj: the &drm_gem_object
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*
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@ -724,7 +724,7 @@ Link: https://patchwork.freedesktop.org/patch/msgid/20231108001259.15123-11-dakr
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*
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* Calling this function is only necessary for drivers intending to support the
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* &drm_driver_feature DRIVER_GEM_GPUVA.
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@@ -584,28 +584,28 @@ static inline void drm_gem_gpuva_init(st
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@@ -597,28 +597,28 @@ static inline void drm_gem_gpuva_init(st
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}
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/**
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@ -1,6 +1,6 @@
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--- a/drivers/irqchip/irq-gic-v3-its.c
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+++ b/drivers/irqchip/irq-gic-v3-its.c
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@@ -4761,7 +4761,9 @@ static bool __maybe_unused its_enable_rk
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@@ -4756,7 +4756,9 @@ static bool __maybe_unused its_enable_rk
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{
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struct its_node *its = data;
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@ -83,7 +83,7 @@ Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
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if (alloc_lpis) {
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lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
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if (lpi_map)
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@@ -5096,6 +5112,7 @@ static int __init its_probe_one(struct i
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@@ -5091,6 +5107,7 @@ static int __init its_probe_one(struct i
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struct page *page;
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u32 ctlr;
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int err;
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@ -91,7 +91,7 @@ Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
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its_enable_quirks(its);
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@@ -5129,7 +5146,10 @@ static int __init its_probe_one(struct i
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@@ -5124,7 +5141,10 @@ static int __init its_probe_one(struct i
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}
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}
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@ -24,6 +24,7 @@ CONFIG_ARM64_VA_BITS=39
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CONFIG_ARM64_VA_BITS_39=y
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CONFIG_ARM_AMBA=y
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CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND=y
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# CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set
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CONFIG_ARM_GIC_V3=y
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CONFIG_ARM_GIC_V3_ITS=y
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CONFIG_ARM_SMCCC_SOC_ID=y
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