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https://github.com/hzyitc/openwrt-redmi-ax3000.git
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89 lines
3.1 KiB
Diff
89 lines
3.1 KiB
Diff
From 47e22e1fc494cd7f11043f80819665d7203effa7 Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <mdalam@codeaurora.org>
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Date: Wed, 30 Dec 2020 02:23:30 +0530
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Subject: [PATCH 6/7] mtd: rawnand: qcom: Update bits of
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QPIC_NAND_FLASH_SPI_CFG reg
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This change will update bits of QPIC_NAND_FLASH_SPI_CFG register
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to select serial nand functionality in QPIC controller.
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Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
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Change-Id: I643bb47b37cc326783d57d6c0f13618f8e216a37
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Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/468d4aa56157d9e742a9eb90fe29b1eeb0151b60
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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drivers/mtd/nand/raw/qcom_nandc.c | 17 +++++++++--------
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1 file changed, 9 insertions(+), 8 deletions(-)
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diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
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index 0a6b67ddcda2..dc723a7ffa0e 100644
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--- a/drivers/mtd/nand/raw/qcom_nandc.c
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+++ b/drivers/mtd/nand/raw/qcom_nandc.c
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@@ -62,7 +62,6 @@
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#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
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#define NAND_QSPI_MSTR_CONFIG 0xf60
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-
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/* dummy register offsets, used by write_reg_dma */
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#define NAND_DEV_CMD1_RESTORE 0xdead
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#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
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@@ -2781,21 +2859,6 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
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return 0;
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}
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-static void qspi_write_reg_bam(struct qcom_nand_controller *nandc,
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- unsigned int val, unsigned int reg)
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-{
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- int ret;
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-
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- clear_bam_transaction(nandc);
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- nandc_set_reg(chip, reg, val);
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- write_reg_dma(nandc, reg, 1, NAND_BAM_NEXT_SGL);
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-
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- ret = submit_descs(nandc);
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- if (ret)
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- dev_err(nandc->dev, "Error in submitting descriptor to write config reg\n");
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- free_descs(nandc);
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-}
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-
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static void qspi_nand_init(struct qcom_nand_controller *nandc)
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{
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u32 spi_cfg_val = 0x0;
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@@ -2960,13 +2959,14 @@ static void qspi_nand_init(struct qcom_nand_controller *nandc)
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u32 spi_cfg_val = 0x0;
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u32 reg = 0x0;
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- spi_cfg_val |= (LOAD_CLK_CNTR_INIT_EN | CLK_CNTR_INIT_VAL_VEC
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- | FEA_STATUS_DEV_ADDR | SPI_CFG);
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+ spi_cfg_val |= (LOAD_CLK_CNTR_INIT_EN | (CLK_CNTR_INIT_VAL_VEC << 16)
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+ | (FEA_STATUS_DEV_ADDR << 8) | SPI_CFG);
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- qspi_write_reg_bam(nandc, 0x0, NAND_FLASH_SPI_CFG);
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- qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG);
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+ reg = dev_cmd_reg_addr(nandc, NAND_FLASH_SPI_CFG);
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+ nandc_write(nandc, reg, 0);
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+ nandc_write(nandc, reg, spi_cfg_val);
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spi_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
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- qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG);
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+ nandc_write(nandc, reg, spi_cfg_val);
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reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD0);
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nandc_write(nandc, reg, CMD0_VAL);
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@@ -2977,8 +2977,9 @@ static void qspi_nand_init(struct qcom_nand_controller *nandc)
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reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD3);
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nandc_write(nandc, reg, CMD3_VAL);
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- qspi_write_reg_bam(nandc, SPI_NUM_ADDR, NAND_SPI_NUM_ADDR_CYCLES);
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- qspi_write_reg_bam(nandc, WAIT_CNT, NAND_SPI_BUSY_CHECK_WAIT_CNT);
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+ reg = dev_cmd_reg_addr(nandc, NAND_SPI_NUM_ADDR_CYCLES);
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+ nandc_write(nandc, reg, SPI_NUM_ADDR);
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+ nandc_write(nandc, reg + 4, WAIT_CNT);
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}
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static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
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--
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2.25.1
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