mirror of
https://github.com/hzyitc/openwrt-redmi-ax3000.git
synced 2025-12-16 08:22:16 +00:00
ipq50xx: Add Qualcomm Atheros IPQ50xx target
This commit is contained in:
hzy
parent
01170d518d
commit
e121f8e1b8
20
target/linux/ipq50xx/Makefile
Normal file
20
target/linux/ipq50xx/Makefile
Normal file
@ -0,0 +1,20 @@
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include $(TOPDIR)/rules.mk
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BOARD:=ipq50xx
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BOARDNAME:=Qualcomm Atheros IPQ50XX
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SUBTARGETS:=arm aarch64
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CPU_TYPE:=cortex-a53
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FEATURES:=fpu ramdisk nand squashfs pcie
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KERNEL_PATCHVER:=5.15
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include $(INCLUDE_DIR)/target.mk
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KERNELNAME:=Image dtbs
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DEFAULT_PACKAGES += \
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kmod-gpio-button-hotplug \
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uboot-envtools
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$(eval $(call BuildTarget))
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73
target/linux/ipq50xx/aarch64/config-default
Normal file
73
target/linux/ipq50xx/aarch64/config-default
Normal file
@ -0,0 +1,73 @@
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# CONFIG_32BIT is not set
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CONFIG_64BIT=y
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# CONFIG_ACPI is not set
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# CONFIG_ARCH_BCM_IPROC is not set
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# CONFIG_ARCH_EXYNOS7 is not set
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CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y
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CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y
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# CONFIG_ARCH_LAYERSCAPE is not set
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CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
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# CONFIG_ARCH_SEATTLE is not set
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CONFIG_ARCH_SELECT_MEMORY_MODEL=y
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CONFIG_ARCH_SPARSEMEM_DEFAULT=y
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CONFIG_ARCH_SPARSEMEM_ENABLE=y
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# CONFIG_ARCH_SPRD is not set
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# CONFIG_ARCH_STRATIX10 is not set
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# CONFIG_ARCH_THUNDER is not set
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CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y
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CONFIG_ARCH_WANT_FRAME_POINTERS=y
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CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y
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# CONFIG_ARCH_XGENE is not set
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# CONFIG_ARCH_ZYNQMP is not set
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CONFIG_ARM64=y
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# CONFIG_ARM64_16K_PAGES is not set
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CONFIG_ARM64_4K_PAGES=y
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# CONFIG_ARM64_64K_PAGES is not set
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# CONFIG_ARM64_CRYPTO is not set
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# CONFIG_ARM64_ERRATUM_819472 is not set
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# CONFIG_ARM64_ERRATUM_824069 is not set
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# CONFIG_ARM64_ERRATUM_826319 is not set
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# CONFIG_ARM64_ERRATUM_827319 is not set
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# CONFIG_ARM64_ERRATUM_832075 is not set
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# CONFIG_ARM64_ERRATUM_843419 is not set
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# CONFIG_ARM64_ERRATUM_845719 is not set
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CONFIG_ARM64_HW_AFDBM=y
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# CONFIG_ARM64_LSE_ATOMICS is not set
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CONFIG_ARM64_PAN=y
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# CONFIG_ARM64_PTDUMP is not set
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# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set
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CONFIG_ARM64_VA_BITS=39
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CONFIG_ARM64_VA_BITS_39=y
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# CONFIG_ARM64_VA_BITS_48 is not set
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# CONFIG_ARMV8_DEPRECATED is not set
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# CONFIG_CAVIUM_ERRATUM_22375 is not set
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# CONFIG_CAVIUM_ERRATUM_23154 is not set
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# CONFIG_CAVIUM_ERRATUM_27456 is not set
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# CONFIG_COMMON_CLK_VERSATILE is not set
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CONFIG_COMMON_CLK_XGENE=y
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CONFIG_COMPAT=y
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CONFIG_COMPAT_BINFMT_ELF=y
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# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
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# CONFIG_DEBUG_ALIGN_RODATA is not set
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CONFIG_FRAME_WARN=2048
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# CONFIG_GPIO_XGENE is not set
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# CONFIG_HUGETLBFS is not set
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CONFIG_IPQ_APSS_5018=y
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# CONFIG_I2C_CADENCE is not set
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# CONFIG_KASAN is not set
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# CONFIG_KVM is not set
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# CONFIG_NET_VENDOR_CAVIUM is not set
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# CONFIG_PCI_HISI is not set
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CONFIG_PHYS_ADDR_T_64BIT=y
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# CONFIG_PHY_XGENE is not set
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# CONFIG_POWER_RESET_XGENE is not set
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CONFIG_QCOM_SCM_64=y
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# CONFIG_RTC_DRV_EFI is not set
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CONFIG_SPARSEMEM=y
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CONFIG_SPARSEMEM_EXTREME=y
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CONFIG_SPARSEMEM_MANUAL=y
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CONFIG_SPARSEMEM_VMEMMAP=y
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CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y
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CONFIG_VIRTUALIZATION=y
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CONFIG_ZONE_DMA32=y
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5
target/linux/ipq50xx/aarch64/target.mk
Normal file
5
target/linux/ipq50xx/aarch64/target.mk
Normal file
@ -0,0 +1,5 @@
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SUBTARGET:=aarch64
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BOARDNAME:=AArch64 64Bit
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ARCH:=aarch64
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CPU_TYPE:=cortex-a53
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7
target/linux/ipq50xx/arm/config-default
Normal file
7
target/linux/ipq50xx/arm/config-default
Normal file
@ -0,0 +1,7 @@
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CONFIG_ARCH_IPQ5018=y
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CONFIG_ARCH_MMAP_RND_BITS=8
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CONFIG_IPQ_APSS_5018=y
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CONFIG_PCIE_DW_PLAT=y
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# CONFIG_USB_QCOM_DIAG_BRIDGE is not set
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CONFIG_VMSPLIT_2G=y
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# CONFIG_VMSPLIT_3G is not set
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6
target/linux/ipq50xx/arm/target.mk
Normal file
6
target/linux/ipq50xx/arm/target.mk
Normal file
@ -0,0 +1,6 @@
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SUBTARGET:=arm
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BOARDNAME:=ARM 32Bit
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ARCH:=arm
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CPU_TYPE:=cortex-a7
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CPU_SUBTYPE:=neon-vfpv4
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20
target/linux/ipq50xx/base-files/lib/upgrade/platform.sh
Normal file
20
target/linux/ipq50xx/base-files/lib/upgrade/platform.sh
Normal file
@ -0,0 +1,20 @@
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. /lib/functions.sh
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platform_check_image() {
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local board=$(board_name)
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case $board in
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*)
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v "Sysupgrade is not supported on your board($board) yet."
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return 1
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;;
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esac
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}
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platform_do_upgrade() {
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local board=$(board_name)
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case $board in
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*)
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default_do_upgrade "$1"
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;;
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esac
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}
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1297
target/linux/ipq50xx/config-5.15
Normal file
1297
target/linux/ipq50xx/config-5.15
Normal file
File diff suppressed because it is too large
Load Diff
10
target/linux/ipq50xx/dts/ipq5018.dtsi
Normal file
10
target/linux/ipq50xx/dts/ipq5018.dtsi
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@ -0,0 +1,10 @@
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#ifdef __ARM32__
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// Search in arch/arm/boot/dts/
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#include <../../../arm64/boot/dts/qcom/ipq5018.dtsi>
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#include <qcom-ipq5018.dtsi>
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#elif __AARCH64__
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// Search in arch/arm64/boot/dts/
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#include <qcom/ipq5018.dtsi>
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#else
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#error "Please define __ARM32__ or __AARCH64__ when compiling dts"
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#endif
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34
target/linux/ipq50xx/image/Makefile
Normal file
34
target/linux/ipq50xx/image/Makefile
Normal file
@ -0,0 +1,34 @@
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include $(TOPDIR)/rules.mk
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include $(INCLUDE_DIR)/image.mk
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ifeq ($(SUBTARGET),arm)
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KERNEL_LOADADDR := 0x41208000
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DTS_CPPFLAGS-y += -D__ARM32__
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else
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KERNEL_LOADADDR := 0x41000000
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DTS_CPPFLAGS-y += -D__AARCH64__
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endif
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define Device/Default
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PROFILES := Default
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DEVICE_DTS_DIR := ../dts
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DEVICE_DTS = $$(SOC)-$(lastword $(subst _, ,$(1)))
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DTS_CPPFLAGS += $(DTS_CPPFLAGS-y)
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IMAGES := sysupgrade.tar
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IMAGE/sysupgrade.tar := sysupgrade-tar | append-metadata
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endef
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define Device/FitImage
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KERNEL_SUFFIX := -fit-uImage.itb
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KERNEL = kernel-bin | lzma | fit lzma $$(KDIR)/image-$$(DEVICE_DTS).dtb
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KERNEL_NAME := Image
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endef
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define Device/UbiFit
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KERNEL_IN_UBI := 1
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IMAGES := nand-factory.ubi nand-sysupgrade.bin
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IMAGE/nand-factory.ubi := append-ubi
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IMAGE/nand-sysupgrade.bin := sysupgrade-tar | append-metadata
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endef
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$(eval $(call BuildImage))
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@ -0,0 +1,256 @@
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From 5f016bd100af39ca781d4adb4123447378b2f9ac Mon Sep 17 00:00:00 2001
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From: Varadarajan Narayanan <varada@codeaurora.org>
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Date: Mon, 28 Sep 2020 10:45:34 +0530
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Subject: [PATCH 1/7] clk: qcom: clk-alpha-pll: Add support for Stromer PLLs
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Add programming sequence support for managing the Stromer
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PLLs.
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Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
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Pick from <1601270140-4306-2-git-send-email-varada@codeaurora.org>
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Add missing test_ctl_val and test_ctl_hi_val member variables.
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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drivers/clk/qcom/clk-alpha-pll.c | 156 ++++++++++++++++++++++++++++++-
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drivers/clk/qcom/clk-alpha-pll.h | 7 ++
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2 files changed, 162 insertions(+), 1 deletion(-)
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diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
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index a69f53e435ed..ed8a26fac199 100644
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--- a/drivers/clk/qcom/clk-alpha-pll.c
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+++ b/drivers/clk/qcom/clk-alpha-pll.c
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@@ -114,6 +114,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
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[PLL_OFF_OPMODE] = 0x38,
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[PLL_OFF_ALPHA_VAL] = 0x40,
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},
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+
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+ [CLK_ALPHA_PLL_TYPE_STROMER] = {
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+ [PLL_OFF_L_VAL] = 0x08,
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+ [PLL_OFF_ALPHA_VAL] = 0x10,
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+ [PLL_OFF_ALPHA_VAL_U] = 0x14,
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+ [PLL_OFF_USER_CTL] = 0x18,
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+ [PLL_OFF_USER_CTL_U] = 0x1c,
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+ [PLL_OFF_CONFIG_CTL] = 0x20,
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+ [PLL_OFF_CONFIG_CTL_U] = 0xff,
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+ [PLL_OFF_TEST_CTL] = 0x30,
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+ [PLL_OFF_TEST_CTL_U] = 0x34,
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+ [PLL_OFF_STATUS] = 0x28,
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+ },
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};
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EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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@@ -125,6 +138,8 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
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#define ALPHA_BITWIDTH 32U
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#define ALPHA_SHIFT(w) min(w, ALPHA_BITWIDTH)
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+#define PLL_STATUS_REG_SHIFT 8
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+
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#define PLL_HUAYRA_M_WIDTH 8
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#define PLL_HUAYRA_M_SHIFT 8
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#define PLL_HUAYRA_M_MASK 0xff
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@@ -206,7 +221,7 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
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void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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const struct alpha_pll_config *config)
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{
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- u32 val, mask;
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+ u32 val, val_u, mask, mask_u;
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regmap_write(regmap, PLL_L_VAL(pll), config->l);
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regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
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@@ -236,14 +251,143 @@ void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
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mask |= config->pre_div_mask;
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mask |= config->post_div_mask;
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mask |= config->vco_mask;
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+ mask |= config->alpha_en_mask;
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+ mask |= config->alpha_mode_mask;
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regmap_update_bits(regmap, PLL_USER_CTL(pll), mask, val);
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+ /* Stromer APSS PLL does not enable LOCK_DET by default, so enable it */
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+ val_u = config->status_reg_val << PLL_STATUS_REG_SHIFT;
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+ val_u |= config->lock_det;
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+
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+ mask_u = config->status_reg_mask;
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+ mask_u |= config->lock_det;
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+
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+ if (val_u != 0)
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+ regmap_update_bits(regmap, PLL_USER_CTL_U(pll), mask_u, val_u);
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+
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+ if (config->test_ctl_val != 0)
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+ regmap_write(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
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+
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+ if (config->test_ctl_hi_val != 0)
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+ regmap_write(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
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+
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if (pll->flags & SUPPORTS_FSM_MODE)
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qcom_pll_set_fsm_mode(regmap, PLL_MODE(pll), 6, 0);
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}
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EXPORT_SYMBOL_GPL(clk_alpha_pll_configure);
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+static unsigned long
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+alpha_pll_stromer_calc_rate(u64 prate, u32 l, u64 a)
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+{
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+ return (prate * l) + ((prate * a) >> ALPHA_REG_BITWIDTH);
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+}
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+
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+static unsigned long
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+alpha_pll_stromer_round_rate(unsigned long rate, unsigned long prate, u32 *l, u64 *a)
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+{
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+ u64 remainder;
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+ u64 quotient;
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+
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+ quotient = rate;
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+ remainder = do_div(quotient, prate);
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+ *l = quotient;
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+
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+ if (!remainder) {
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+ *a = 0;
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+ return rate;
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+ }
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+
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+ quotient = remainder << ALPHA_REG_BITWIDTH;
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+
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+ remainder = do_div(quotient, prate);
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+
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+ if (remainder)
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+ quotient++;
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+
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+ *a = quotient;
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+ return alpha_pll_stromer_calc_rate(prate, *l, *a);
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+}
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+
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+static unsigned long
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+clk_alpha_pll_stromer_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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+{
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+ u32 l, low, high, ctl;
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+ u64 a = 0, prate = parent_rate;
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+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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+
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+ regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
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+
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+ regmap_read(pll->clkr.regmap, PLL_USER_CTL(pll), &ctl);
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+ if (ctl & PLL_ALPHA_EN) {
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+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &low);
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+ regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
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+ &high);
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+ a = (u64)high << ALPHA_BITWIDTH | low;
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+ }
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+
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+ return alpha_pll_stromer_calc_rate(prate, l, a);
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+}
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+
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+static int clk_alpha_pll_stromer_determine_rate(struct clk_hw *hw,
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+ struct clk_rate_request *req)
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+{
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+ unsigned long rate = req->rate;
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+ u32 l;
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+ u64 a;
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+
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+ rate = alpha_pll_stromer_round_rate(rate, req->best_parent_rate, &l, &a);
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+
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+ return 0;
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+}
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+
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+static int clk_alpha_pll_stromer_set_rate(struct clk_hw *hw, unsigned long rate,
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+ unsigned long prate)
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+{
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+ struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
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+ u32 l;
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+ int ret;
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+ u64 a;
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+
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+ rate = alpha_pll_stromer_round_rate(rate, prate, &l, &a);
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+
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+ /* Write desired values to registers */
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+ regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
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+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
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+ regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL_U(pll),
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+ a >> ALPHA_BITWIDTH);
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+
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+ regmap_update_bits(pll->clkr.regmap, PLL_USER_CTL(pll),
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+ PLL_ALPHA_EN, PLL_ALPHA_EN);
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+
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+ if (!clk_hw_is_enabled(hw))
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+ return 0;
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+
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+ /* Stromer PLL supports Dynamic programming.
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+ * It allows the PLL frequency to be changed on-the-fly without first
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+ * execution of a shutdown procedure followed by a bring up procedure.
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+ */
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+
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+ regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), PLL_UPDATE,
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+ PLL_UPDATE);
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+ /* Make sure PLL_UPDATE request goes through */
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+ mb();
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+
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+ /* Wait for PLL_UPDATE to be cleared */
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+ ret = wait_for_pll_update(pll);
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+ if (ret)
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+ return ret;
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+
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+ /* Wait 11or more PLL clk_ref ticks[to be explored more on wait] */
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+
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+ /* Poll LOCK_DET for one */
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+ ret = wait_for_pll_enable_lock(pll);
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+ if (ret)
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+ return ret;
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+
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+ return 0;
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+}
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+
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static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
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{
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int ret;
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@@ -905,6 +1049,16 @@ const struct clk_ops clk_alpha_pll_hwfsm_ops = {
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.set_rate = clk_alpha_pll_hwfsm_set_rate,
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};
|
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EXPORT_SYMBOL_GPL(clk_alpha_pll_hwfsm_ops);
|
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+
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+const struct clk_ops clk_alpha_pll_stromer_ops = {
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+ .enable = clk_alpha_pll_enable,
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+ .disable = clk_alpha_pll_disable,
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+ .is_enabled = clk_alpha_pll_is_enabled,
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+ .recalc_rate = clk_alpha_pll_stromer_recalc_rate,
|
||||
+ .determine_rate = clk_alpha_pll_stromer_determine_rate,
|
||||
+ .set_rate = clk_alpha_pll_stromer_set_rate,
|
||||
+};
|
||||
+EXPORT_SYMBOL_GPL(clk_alpha_pll_stromer_ops);
|
||||
|
||||
const struct clk_ops clk_trion_fixed_pll_ops = {
|
||||
.enable = clk_trion_pll_enable,
|
||||
diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
|
||||
index 15f27f4b06df..68a2d2494f5d 100644
|
||||
--- a/drivers/clk/qcom/clk-alpha-pll.h
|
||||
+++ b/drivers/clk/qcom/clk-alpha-pll.h
|
||||
@@ -14,6 +14,7 @@ enum {
|
||||
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
|
||||
CLK_ALPHA_PLL_TYPE_AGERA,
|
||||
CLK_ALPHA_PLL_TYPE_ZONDA,
|
||||
+ CLK_ALPHA_PLL_TYPE_STROMER,
|
||||
CLK_ALPHA_PLL_TYPE_MAX,
|
||||
};
|
||||
|
||||
@@ -106,6 +107,9 @@ struct alpha_pll_config {
|
||||
u32 post_div_mask;
|
||||
u32 vco_val;
|
||||
u32 vco_mask;
|
||||
+ u32 status_reg_val;
|
||||
+ u32 status_reg_mask;
|
||||
+ u32 lock_det;
|
||||
};
|
||||
|
||||
extern const struct clk_ops clk_alpha_pll_ops;
|
||||
@@ -113,6 +119,7 @@ extern const struct clk_ops clk_alpha_pll_hwfsm_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_postdiv_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_huayra_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_postdiv_ro_ops;
|
||||
+extern const struct clk_ops clk_alpha_pll_stromer_ops;
|
||||
|
||||
extern const struct clk_ops clk_alpha_pll_fabia_ops;
|
||||
extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,360 @@
|
||||
From 519997f7779e6a40b327ffab1b1629f2b3320176 Mon Sep 17 00:00:00 2001
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Mon, 28 Sep 2020 10:45:35 +0530
|
||||
Subject: [PATCH 2/7] dt-bindings: arm64: ipq5018: Add binding descriptions for
|
||||
clock and reset
|
||||
|
||||
This patch adds support for the global clock controller found on
|
||||
the IPQ5018 based devices.
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
|
||||
Pick from <1601270140-4306-3-git-send-email-varada@codeaurora.org>
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
.../devicetree/bindings/clock/qcom,gcc.yaml | 1 +
|
||||
include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 ++++++++++++++++++
|
||||
include/dt-bindings/reset/qcom,gcc-ipq5018.h | 119 ++++++++++++
|
||||
3 files changed, 303 insertions(+)
|
||||
create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h
|
||||
create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
|
||||
index d14362ad4132..530a8fe2687c 100644
|
||||
--- a/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
|
||||
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc.yaml
|
||||
@@ -17,6 +17,8 @@
|
||||
- dt-bindings/clock/qcom,gcc-apq8084.h
|
||||
- dt-bindings/reset/qcom,gcc-apq8084.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq4019.h
|
||||
+ - dt-bindings/clock/qcom,gcc-ipq5018.h
|
||||
+ - dt-bindings/reset/qcom,gcc-ipq5018.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/reset/qcom,gcc-ipq6018.h
|
||||
- dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
|
||||
@@ -39,6 +40,7 @@ Required properties :
|
||||
enum:
|
||||
- qcom,gcc-apq8084
|
||||
- qcom,gcc-ipq4019
|
||||
+ - qcom,gcc-ipq5018
|
||||
- qcom,gcc-ipq6018
|
||||
- qcom,gcc-ipq8064
|
||||
- qcom,gcc-mdm9607
|
||||
diff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h
|
||||
new file mode 100644
|
||||
index 000000000000..069165f73d0b
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h
|
||||
@@ -0,0 +1,183 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+
|
||||
+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
|
||||
+#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H
|
||||
+
|
||||
+#define GPLL0_MAIN 0
|
||||
+#define GPLL0 1
|
||||
+#define GPLL2_MAIN 2
|
||||
+#define GPLL2 3
|
||||
+#define GPLL4_MAIN 4
|
||||
+#define GPLL4 5
|
||||
+#define UBI32_PLL_MAIN 6
|
||||
+#define UBI32_PLL 7
|
||||
+#define APSS_AHB_CLK_SRC 9
|
||||
+#define APSS_AHB_POSTDIV_CLK_SRC 10
|
||||
+#define APSS_AXI_CLK_SRC 11
|
||||
+#define BLSP1_QUP1_I2C_APPS_CLK_SRC 12
|
||||
+#define BLSP1_QUP1_SPI_APPS_CLK_SRC 13
|
||||
+#define BLSP1_QUP2_I2C_APPS_CLK_SRC 14
|
||||
+#define BLSP1_QUP2_SPI_APPS_CLK_SRC 15
|
||||
+#define BLSP1_QUP3_I2C_APPS_CLK_SRC 16
|
||||
+#define BLSP1_QUP3_SPI_APPS_CLK_SRC 17
|
||||
+#define BLSP1_UART1_APPS_CLK_SRC 18
|
||||
+#define BLSP1_UART2_APPS_CLK_SRC 19
|
||||
+#define CRYPTO_CLK_SRC 20
|
||||
+#define GCC_APSS_AHB_CLK 23
|
||||
+#define GCC_APSS_AXI_CLK 24
|
||||
+#define GCC_BLSP1_AHB_CLK 25
|
||||
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK 26
|
||||
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK 27
|
||||
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK 28
|
||||
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK 29
|
||||
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK 30
|
||||
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK 31
|
||||
+#define GCC_BLSP1_UART1_APPS_CLK 33
|
||||
+#define GCC_BLSP1_UART2_APPS_CLK 34
|
||||
+#define GCC_BTSS_LPO_CLK 36
|
||||
+#define GCC_CMN_BLK_AHB_CLK 40
|
||||
+#define GCC_CMN_BLK_SYS_CLK 41
|
||||
+#define GCC_CRYPTO_AHB_CLK 44
|
||||
+#define GCC_CRYPTO_AXI_CLK 45
|
||||
+#define GCC_CRYPTO_CLK 46
|
||||
+#define GCC_CRYPTO_PPE_CLK 47
|
||||
+#define GCC_DCC_CLK 48
|
||||
+#define GCC_GEPHY_RX_CLK 53
|
||||
+#define GCC_GEPHY_TX_CLK 54
|
||||
+#define GCC_GMAC0_CFG_CLK 55
|
||||
+#define GCC_GMAC0_PTP_CLK 56
|
||||
+#define GCC_GMAC0_RX_CLK 57
|
||||
+#define GCC_GMAC0_SYS_CLK 58
|
||||
+#define GCC_GMAC0_TX_CLK 59
|
||||
+#define GCC_GMAC1_CFG_CLK 60
|
||||
+#define GCC_GMAC1_PTP_CLK 61
|
||||
+#define GCC_GMAC1_RX_CLK 62
|
||||
+#define GCC_GMAC1_SYS_CLK 63
|
||||
+#define GCC_GMAC1_TX_CLK 64
|
||||
+#define GCC_GP1_CLK 65
|
||||
+#define GCC_GP2_CLK 66
|
||||
+#define GCC_GP3_CLK 67
|
||||
+#define GCC_LPASS_CORE_AXIM_CLK 69
|
||||
+#define GCC_LPASS_SWAY_CLK 70
|
||||
+#define GCC_MDIO0_AHB_CLK 71
|
||||
+#define GCC_MDIO1_AHB_CLK 72
|
||||
+#define GCC_PCIE0_AHB_CLK 74
|
||||
+#define GCC_PCIE0_AUX_CLK 75
|
||||
+#define GCC_PCIE0_AXI_M_CLK 76
|
||||
+#define GCC_PCIE0_AXI_S_BRIDGE_CLK 77
|
||||
+#define GCC_PCIE0_AXI_S_CLK 78
|
||||
+#define GCC_PCIE1_AHB_CLK 79
|
||||
+#define GCC_PCIE1_AUX_CLK 80
|
||||
+#define GCC_PCIE1_AXI_M_CLK 81
|
||||
+#define GCC_PCIE1_AXI_S_BRIDGE_CLK 82
|
||||
+#define GCC_PCIE1_AXI_S_CLK 83
|
||||
+#define GCC_PRNG_AHB_CLK 84
|
||||
+#define GCC_Q6_AXIM_CLK 85
|
||||
+#define GCC_Q6_AXIM2_CLK 86
|
||||
+#define GCC_Q6_AXIS_CLK 87
|
||||
+#define GCC_Q6_AHB_CLK 88
|
||||
+#define GCC_Q6_AHB_S_CLK 89
|
||||
+#define GCC_Q6_TSCTR_1TO2_CLK 90
|
||||
+#define GCC_Q6SS_ATBM_CLK 91
|
||||
+#define GCC_Q6SS_PCLKDBG_CLK 92
|
||||
+#define GCC_Q6SS_TRIG_CLK 93
|
||||
+#define GCC_QDSS_AT_CLK 94
|
||||
+#define GCC_QDSS_CFG_AHB_CLK 95
|
||||
+#define GCC_QDSS_DAP_AHB_CLK 96
|
||||
+#define GCC_QDSS_DAP_CLK 97
|
||||
+#define GCC_QDSS_ETR_USB_CLK 98
|
||||
+#define GCC_QDSS_EUD_AT_CLK 99
|
||||
+#define GCC_QDSS_STM_CLK 100
|
||||
+#define GCC_QDSS_TRACECLKIN_CLK 101
|
||||
+#define GCC_QDSS_TSCTR_DIV8_CLK 102
|
||||
+#define GCC_QPIC_AHB_CLK 103
|
||||
+#define GCC_QPIC_CLK 104
|
||||
+#define GCC_QPIC_IO_MACRO_CLK 105
|
||||
+#define GCC_SDCC1_AHB_CLK 107
|
||||
+#define GCC_SDCC1_APPS_CLK 108
|
||||
+#define GCC_SLEEP_CLK_SRC 109
|
||||
+#define GCC_SNOC_GMAC0_AHB_CLK 110
|
||||
+#define GCC_SNOC_GMAC0_AXI_CLK 111
|
||||
+#define GCC_SNOC_GMAC1_AHB_CLK 112
|
||||
+#define GCC_SNOC_GMAC1_AXI_CLK 113
|
||||
+#define GCC_SNOC_LPASS_AXIM_CLK 114
|
||||
+#define GCC_SNOC_LPASS_SWAY_CLK 115
|
||||
+#define GCC_SNOC_UBI0_AXI_CLK 118
|
||||
+#define GCC_SYS_NOC_PCIE0_AXI_CLK 119
|
||||
+#define GCC_SYS_NOC_PCIE1_AXI_CLK 120
|
||||
+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 121
|
||||
+#define GCC_SYS_NOC_USB0_AXI_CLK 123
|
||||
+#define GCC_SYS_NOC_WCSS_AHB_CLK 124
|
||||
+#define GCC_UBI0_AXI_CLK 128
|
||||
+#define GCC_UBI0_CFG_CLK 129
|
||||
+#define GCC_UBI0_CORE_CLK 130
|
||||
+#define GCC_UBI0_DBG_CLK 131
|
||||
+#define GCC_UBI0_NC_AXI_CLK 132
|
||||
+#define GCC_UBI0_UTCM_CLK 133
|
||||
+#define GCC_UNIPHY_AHB_CLK 134
|
||||
+#define GCC_UNIPHY_RX_CLK 135
|
||||
+#define GCC_UNIPHY_SYS_CLK 136
|
||||
+#define GCC_UNIPHY_TX_CLK 137
|
||||
+#define GCC_USB0_AUX_CLK 138
|
||||
+#define GCC_USB0_EUD_AT_CLK 139
|
||||
+#define GCC_USB0_LFPS_CLK 140
|
||||
+#define GCC_USB0_MASTER_CLK 141
|
||||
+#define GCC_USB0_MOCK_UTMI_CLK 142
|
||||
+#define GCC_USB0_PHY_CFG_AHB_CLK 143
|
||||
+#define GCC_USB0_SLEEP_CLK 144
|
||||
+#define GCC_WCSS_ACMT_CLK 145
|
||||
+#define GCC_WCSS_AHB_S_CLK 146
|
||||
+#define GCC_WCSS_AXI_M_CLK 147
|
||||
+#define GCC_WCSS_AXI_S_CLK 148
|
||||
+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 149
|
||||
+#define GCC_WCSS_DBG_IFC_APB_CLK 150
|
||||
+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 151
|
||||
+#define GCC_WCSS_DBG_IFC_ATB_CLK 152
|
||||
+#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 153
|
||||
+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 154
|
||||
+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 155
|
||||
+#define GCC_WCSS_DBG_IFC_NTS_CLK 156
|
||||
+#define GCC_WCSS_ECAHB_CLK 157
|
||||
+#define GCC_XO_CLK 158
|
||||
+#define GCC_XO_CLK_SRC 159
|
||||
+#define GMAC0_RX_CLK_SRC 161
|
||||
+#define GMAC0_TX_CLK_SRC 162
|
||||
+#define GMAC1_RX_CLK_SRC 163
|
||||
+#define GMAC1_TX_CLK_SRC 164
|
||||
+#define GMAC_CLK_SRC 165
|
||||
+#define GP1_CLK_SRC 166
|
||||
+#define GP2_CLK_SRC 167
|
||||
+#define GP3_CLK_SRC 168
|
||||
+#define LPASS_AXIM_CLK_SRC 169
|
||||
+#define LPASS_SWAY_CLK_SRC 170
|
||||
+#define PCIE0_AUX_CLK_SRC 171
|
||||
+#define PCIE0_AXI_CLK_SRC 172
|
||||
+#define PCIE1_AUX_CLK_SRC 173
|
||||
+#define PCIE1_AXI_CLK_SRC 174
|
||||
+#define PCNOC_BFDCD_CLK_SRC 175
|
||||
+#define Q6_AXI_CLK_SRC 176
|
||||
+#define QDSS_AT_CLK_SRC 177
|
||||
+#define QDSS_STM_CLK_SRC 178
|
||||
+#define QDSS_TSCTR_CLK_SRC 179
|
||||
+#define QDSS_TRACECLKIN_CLK_SRC 180
|
||||
+#define QPIC_IO_MACRO_CLK_SRC 181
|
||||
+#define SDCC1_APPS_CLK_SRC 182
|
||||
+#define SYSTEM_NOC_BFDCD_CLK_SRC 184
|
||||
+#define UBI0_AXI_CLK_SRC 185
|
||||
+#define UBI0_CORE_CLK_SRC 186
|
||||
+#define USB0_AUX_CLK_SRC 187
|
||||
+#define USB0_LFPS_CLK_SRC 188
|
||||
+#define USB0_MASTER_CLK_SRC 189
|
||||
+#define USB0_MOCK_UTMI_CLK_SRC 190
|
||||
+#define WCSS_AHB_CLK_SRC 191
|
||||
+#define PCIE0_PIPE_CLK_SRC 192
|
||||
+#define PCIE1_PIPE_CLK_SRC 193
|
||||
+#define GCC_PCIE0_PIPE_CLK 194
|
||||
+#define GCC_PCIE1_PIPE_CLK 195
|
||||
+#define USB0_PIPE_CLK_SRC 196
|
||||
+#define GCC_USB0_PIPE_CLK 197
|
||||
+#define GMAC0_RX_DIV_CLK_SRC 198
|
||||
+#define GMAC0_TX_DIV_CLK_SRC 199
|
||||
+#define GMAC1_RX_DIV_CLK_SRC 200
|
||||
+#define GMAC1_TX_DIV_CLK_SRC 201
|
||||
+#endif
|
||||
diff --git a/include/dt-bindings/reset/qcom,gcc-ipq5018.h b/include/dt-bindings/reset/qcom,gcc-ipq5018.h
|
||||
new file mode 100644
|
||||
index 000000000000..cd9c4e1d19e8
|
||||
--- /dev/null
|
||||
+++ b/include/dt-bindings/reset/qcom,gcc-ipq5018.h
|
||||
@@ -0,0 +1,119 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
+
|
||||
+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H
|
||||
+#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H
|
||||
+
|
||||
+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR 0
|
||||
+#define GCC_BLSP1_BCR 1
|
||||
+#define GCC_BLSP1_QUP1_BCR 2
|
||||
+#define GCC_BLSP1_QUP2_BCR 3
|
||||
+#define GCC_BLSP1_QUP3_BCR 4
|
||||
+#define GCC_BLSP1_UART1_BCR 5
|
||||
+#define GCC_BLSP1_UART2_BCR 6
|
||||
+#define GCC_BOOT_ROM_BCR 7
|
||||
+#define GCC_BTSS_BCR 8
|
||||
+#define GCC_CMN_BLK_BCR 9
|
||||
+#define GCC_CMN_LDO_BCR 10
|
||||
+#define GCC_CE_BCR 11
|
||||
+#define GCC_CRYPTO_BCR 12
|
||||
+#define GCC_DCC_BCR 13
|
||||
+#define GCC_DCD_BCR 14
|
||||
+#define GCC_DDRSS_BCR 15
|
||||
+#define GCC_EDPD_BCR 16
|
||||
+#define GCC_GEPHY_BCR 17
|
||||
+#define GCC_GEPHY_MDC_SW_ARES 18
|
||||
+#define GCC_GEPHY_DSP_HW_ARES 19
|
||||
+#define GCC_GEPHY_RX_ARES 20
|
||||
+#define GCC_GEPHY_TX_ARES 21
|
||||
+#define GCC_GMAC0_BCR 22
|
||||
+#define GCC_GMAC0_CFG_ARES 23
|
||||
+#define GCC_GMAC0_SYS_ARES 24
|
||||
+#define GCC_GMAC1_BCR 25
|
||||
+#define GCC_GMAC1_CFG_ARES 26
|
||||
+#define GCC_GMAC1_SYS_ARES 27
|
||||
+#define GCC_IMEM_BCR 28
|
||||
+#define GCC_LPASS_BCR 29
|
||||
+#define GCC_MDIO0_BCR 30
|
||||
+#define GCC_MDIO1_BCR 31
|
||||
+#define GCC_MPM_BCR 32
|
||||
+#define GCC_PCIE0_BCR 33
|
||||
+#define GCC_PCIE0_LINK_DOWN_BCR 34
|
||||
+#define GCC_PCIE0_PHY_BCR 35
|
||||
+#define GCC_PCIE0PHY_PHY_BCR 36
|
||||
+#define GCC_PCIE0_PIPE_ARES 37
|
||||
+#define GCC_PCIE0_SLEEP_ARES 38
|
||||
+#define GCC_PCIE0_CORE_STICKY_ARES 39
|
||||
+#define GCC_PCIE0_AXI_MASTER_ARES 40
|
||||
+#define GCC_PCIE0_AXI_SLAVE_ARES 41
|
||||
+#define GCC_PCIE0_AHB_ARES 42
|
||||
+#define GCC_PCIE0_AXI_MASTER_STICKY_ARES 43
|
||||
+#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES 44
|
||||
+#define GCC_PCIE1_BCR 45
|
||||
+#define GCC_PCIE1_LINK_DOWN_BCR 46
|
||||
+#define GCC_PCIE1_PHY_BCR 47
|
||||
+#define GCC_PCIE1PHY_PHY_BCR 48
|
||||
+#define GCC_PCIE1_PIPE_ARES 49
|
||||
+#define GCC_PCIE1_SLEEP_ARES 50
|
||||
+#define GCC_PCIE1_CORE_STICKY_ARES 51
|
||||
+#define GCC_PCIE1_AXI_MASTER_ARES 52
|
||||
+#define GCC_PCIE1_AXI_SLAVE_ARES 53
|
||||
+#define GCC_PCIE1_AHB_ARES 54
|
||||
+#define GCC_PCIE1_AXI_MASTER_STICKY_ARES 55
|
||||
+#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES 56
|
||||
+#define GCC_PCNOC_BCR 57
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT10_BCR 68
|
||||
+#define GCC_PCNOC_BUS_TIMEOUT11_BCR 69
|
||||
+#define GCC_PRNG_BCR 70
|
||||
+#define GCC_Q6SS_DBG_ARES 71
|
||||
+#define GCC_Q6_AHB_S_ARES 72
|
||||
+#define GCC_Q6_AHB_ARES 73
|
||||
+#define GCC_Q6_AXIM2_ARES 74
|
||||
+#define GCC_Q6_AXIM_ARES 75
|
||||
+#define GCC_Q6_AXIS_ARES 76
|
||||
+#define GCC_QDSS_BCR 77
|
||||
+#define GCC_QPIC_BCR 78
|
||||
+#define GCC_QUSB2_0_PHY_BCR 79
|
||||
+#define GCC_SDCC1_BCR 80
|
||||
+#define GCC_SEC_CTRL_BCR 81
|
||||
+#define GCC_SPDM_BCR 82
|
||||
+#define GCC_SYSTEM_NOC_BCR 83
|
||||
+#define GCC_TCSR_BCR 84
|
||||
+#define GCC_TLMM_BCR 85
|
||||
+#define GCC_UBI0_AXI_ARES 86
|
||||
+#define GCC_UBI0_AHB_ARES 87
|
||||
+#define GCC_UBI0_NC_AXI_ARES 88
|
||||
+#define GCC_UBI0_DBG_ARES 89
|
||||
+#define GCC_UBI0_UTCM_ARES 90
|
||||
+#define GCC_UBI0_CORE_ARES 91
|
||||
+#define GCC_UBI32_BCR 92
|
||||
+#define GCC_UNIPHY_BCR 93
|
||||
+#define GCC_UNIPHY_AHB_ARES 94
|
||||
+#define GCC_UNIPHY_SYS_ARES 95
|
||||
+#define GCC_UNIPHY_RX_ARES 96
|
||||
+#define GCC_UNIPHY_TX_ARES 97
|
||||
+#define GCC_USB0_BCR 98
|
||||
+#define GCC_USB0_PHY_BCR 99
|
||||
+#define GCC_WCSS_BCR 100
|
||||
+#define GCC_WCSS_DBG_ARES 101
|
||||
+#define GCC_WCSS_ECAHB_ARES 102
|
||||
+#define GCC_WCSS_ACMT_ARES 103
|
||||
+#define GCC_WCSS_DBG_BDG_ARES 104
|
||||
+#define GCC_WCSS_AHB_S_ARES 105
|
||||
+#define GCC_WCSS_AXI_M_ARES 106
|
||||
+#define GCC_WCSS_AXI_S_ARES 107
|
||||
+#define GCC_WCSS_Q6_BCR 108
|
||||
+#define GCC_WCSSAON_RESET 109
|
||||
+#define GCC_UNIPHY_SOFT_RESET 110
|
||||
+#define GCC_GEPHY_MISC_ARES 111
|
||||
+
|
||||
+#endif
|
||||
--
|
||||
2.25.1
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,172 @@
|
||||
From f73d46914ae5bd46f7fcbec12a680dbb62c383d6 Mon Sep 17 00:00:00 2001
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Mon, 28 Sep 2020 10:45:37 +0530
|
||||
Subject: [PATCH 4/7] dt-bindings: pinctrl: qcom: Add ipq5018 pinctrl bindings
|
||||
|
||||
Add device tree binding Documentation details for ipq5018
|
||||
pinctrl driver.
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
|
||||
Pick from <1601270140-4306-5-git-send-email-varada@codeaurora.org>
|
||||
|
||||
Fix gpio-ranges
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
.../pinctrl/qcom,ipq5018-pinctrl.yaml | 143 ++++++++++++++++++
|
||||
1 file changed, 143 insertions(+)
|
||||
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml
|
||||
new file mode 100644
|
||||
index 000000000000..237ef50a9562
|
||||
--- /dev/null
|
||||
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq5018-pinctrl.yaml
|
||||
@@ -0,0 +1,143 @@
|
||||
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
+%YAML 1.2
|
||||
+---
|
||||
+$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5018-pinctrl.yaml#
|
||||
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
+
|
||||
+title: Qualcomm Technologies, Inc. IPQ5018 TLMM block
|
||||
+
|
||||
+maintainers:
|
||||
+ - Nitheesh Sekar <nsekar@codeaurora.org>
|
||||
+
|
||||
+description: |
|
||||
+ This binding describes the Top Level Mode Multiplexer block found in the
|
||||
+ IPQ5018 platform.
|
||||
+
|
||||
+properties:
|
||||
+ compatible:
|
||||
+ const: qcom,ipq5018-pinctrl
|
||||
+
|
||||
+ reg:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ interrupts:
|
||||
+ description: Specifies the TLMM summary IRQ
|
||||
+ maxItems: 1
|
||||
+
|
||||
+ interrupt-controller: true
|
||||
+
|
||||
+ '#interrupt-cells':
|
||||
+ description:
|
||||
+ Specifies the PIN numbers and Flags, as defined in defined in
|
||||
+ include/dt-bindings/interrupt-controller/irq.h
|
||||
+ const: 2
|
||||
+
|
||||
+ gpio-controller: true
|
||||
+
|
||||
+ '#gpio-cells':
|
||||
+ description: Specifying the pin number and flags, as defined in
|
||||
+ include/dt-bindings/gpio/gpio.h
|
||||
+ const: 2
|
||||
+
|
||||
+ gpio-ranges:
|
||||
+ maxItems: 1
|
||||
+
|
||||
+#PIN CONFIGURATION NODES
|
||||
+patternProperties:
|
||||
+ '-pinmux$':
|
||||
+ type: object
|
||||
+ description:
|
||||
+ Pinctrl node's client devices use subnodes for desired pin configuration.
|
||||
+ Client device subnodes use below standard properties.
|
||||
+ $ref: "/schemas/pinctrl/pincfg-node.yaml"
|
||||
+
|
||||
+ properties:
|
||||
+ pins:
|
||||
+ description:
|
||||
+ List of gpio pins affected by the properties specified in this
|
||||
+ subnode.
|
||||
+ items:
|
||||
+ oneOf:
|
||||
+ - pattern: "^gpio([1-9]|[1-7][0-9]|80)$"
|
||||
+ minItems: 1
|
||||
+ maxItems: 4
|
||||
+
|
||||
+ function:
|
||||
+ description:
|
||||
+ Specify the alternative function to be configured for the specified
|
||||
+ pins.
|
||||
+ enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
|
||||
+ audio_pdm0, audio_pdm1, audio_rxbclk, audio_rxd, audio_rxfsync,
|
||||
+ audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync, audio_txmclk,
|
||||
+ blsp0_i2c, blsp0_spi, blsp0_uart0, blsp0_uart1, blsp1_i2c0,
|
||||
+ blsp1_i2c1, blsp1_spi0, blsp1_spi1, blsp1_uart0, blsp1_uart1,
|
||||
+ blsp1_uart2, blsp2_i2c0, blsp2_i2c1, blsp2_spi, blsp2_spi0,
|
||||
+ blsp2_spi1, btss0, btss1, btss10, btss11, btss12, btss13, btss2,
|
||||
+ btss3, btss4, btss5, btss6, btss7, btss8, btss9, burn0, burn1,
|
||||
+ cri_trng, cri_trng0, cri_trng1, cxc_clk, cxc_data, dbg_out, eud_gpio,
|
||||
+ gcc_plltest, gcc_tlmm, gpio, mac0, mac1, mdc, mdio, pcie0_clk,
|
||||
+ pcie0_wake, pcie1_clk, pcie1_wake, pll_test, prng_rosc, pwm0, pwm1,
|
||||
+ pwm2, pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
|
||||
+ qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
|
||||
+ qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1,
|
||||
+ qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, qdss_tracectl_b,
|
||||
+ qdss_tracedata_a, qdss_tracedata_b, qspi_clk, qspi_cs, qspi0, qspi1,
|
||||
+ qspi2, qspi3, reset_out, sdc1_clk, sdc1_cmd, sdc10, sdc11, sdc12,
|
||||
+ sdc13, wci0, wci1, wci2, wci3, wci4, wci5, wci6, wci7, wsa_swrm,
|
||||
+ wsi_clk3, wsi_data3, wsis_reset, xfem0, xfem1, xfem2, xfem3, xfem4,
|
||||
+ xfem5, xfem6, xfem7 ]
|
||||
+
|
||||
+ drive-strength:
|
||||
+ enum: [2, 4, 6, 8, 10, 12, 14, 16]
|
||||
+ default: 2
|
||||
+ description:
|
||||
+ Selects the drive strength for the specified pins, in mA.
|
||||
+
|
||||
+ bias-pull-down: true
|
||||
+
|
||||
+ bias-pull-up: true
|
||||
+
|
||||
+ bias-disable: true
|
||||
+
|
||||
+ output-high: true
|
||||
+
|
||||
+ output-low: true
|
||||
+
|
||||
+ required:
|
||||
+ - pins
|
||||
+ - function
|
||||
+
|
||||
+ additionalProperties: false
|
||||
+
|
||||
+required:
|
||||
+ - compatible
|
||||
+ - reg
|
||||
+ - interrupts
|
||||
+ - interrupt-controller
|
||||
+ - '#interrupt-cells'
|
||||
+ - gpio-controller
|
||||
+ - '#gpio-cells'
|
||||
+ - gpio-ranges
|
||||
+
|
||||
+additionalProperties: false
|
||||
+
|
||||
+examples:
|
||||
+ - |
|
||||
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+ tlmm: pinctrl@1000000 {
|
||||
+ compatible = "qcom,ipq5018-pinctrl";
|
||||
+ reg = <0x01000000 0x300000>;
|
||||
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <2>;
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ gpio-ranges = <&tlmm 0 0 80>;
|
||||
+
|
||||
+ serial3-pinmux {
|
||||
+ pins = "gpio44", "gpio45";
|
||||
+ function = "blsp2_uart";
|
||||
+ drive-strength = <8>;
|
||||
+ bias-pull-down;
|
||||
+ };
|
||||
+ };
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,964 @@
|
||||
From 0031239077dbc526fea08039641c605508680098 Mon Sep 17 00:00:00 2001
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Mon, 28 Sep 2020 10:45:38 +0530
|
||||
Subject: [PATCH 5/7] pinctrl: qcom: Add IPQ5018 pinctrl driver
|
||||
|
||||
This adds the pinctrl definitions for the TLMM of IPQ5018.
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
|
||||
Pick from <1601270140-4306-6-git-send-email-varada@codeaurora.org>
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
drivers/pinctrl/qcom/Kconfig | 10 +
|
||||
drivers/pinctrl/qcom/Makefile | 1 +
|
||||
drivers/pinctrl/qcom/pinctrl-ipq5018.c | 903 +++++++++++++++++++++++++
|
||||
3 files changed, 914 insertions(+)
|
||||
create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c
|
||||
|
||||
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
|
||||
index 32fc2458b8eb..480a562ba96e 100644
|
||||
--- a/drivers/pinctrl/qcom/Kconfig
|
||||
+++ b/drivers/pinctrl/qcom/Kconfig
|
||||
@@ -32,6 +32,16 @@ config PINCTRL_IPQ4019
|
||||
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
|
||||
Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.
|
||||
|
||||
+config PINCTRL_IPQ5018
|
||||
+ tristate "Qualcomm Technologies, Inc. IPQ5018 pin controller driver"
|
||||
+ depends on GPIOLIB && OF
|
||||
+ select PINCTRL_MSM
|
||||
+ help
|
||||
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for
|
||||
+ the Qualcomm Technologies Inc. TLMM block found on the
|
||||
+ Qualcomm Technologies Inc. IPQ5018 platform. Select this for
|
||||
+ IPQ5018.
|
||||
+
|
||||
config PINCTRL_IPQ8064
|
||||
tristate "Qualcomm IPQ8064 pin controller driver"
|
||||
depends on GPIOLIB && OF
|
||||
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
|
||||
index f8bb0c265381..3b14cb92d443 100644
|
||||
--- a/drivers/pinctrl/qcom/Makefile
|
||||
+++ b/drivers/pinctrl/qcom/Makefile
|
||||
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
|
||||
obj-$(CONFIG_PINCTRL_APQ8064) += pinctrl-apq8064.o
|
||||
obj-$(CONFIG_PINCTRL_APQ8084) += pinctrl-apq8084.o
|
||||
obj-$(CONFIG_PINCTRL_IPQ4019) += pinctrl-ipq4019.o
|
||||
+obj-$(CONFIG_PINCTRL_IPQ5018) += pinctrl-ipq5018.o
|
||||
obj-$(CONFIG_PINCTRL_IPQ8064) += pinctrl-ipq8064.o
|
||||
obj-$(CONFIG_PINCTRL_IPQ8074) += pinctrl-ipq8074.o
|
||||
obj-$(CONFIG_PINCTRL_MSM8660) += pinctrl-msm8660.o
|
||||
diff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
|
||||
new file mode 100644
|
||||
index 000000000000..92b38c4297e0
|
||||
--- /dev/null
|
||||
+++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c
|
||||
@@ -0,0 +1,903 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0-only
|
||||
+/*
|
||||
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
|
||||
+ */
|
||||
+
|
||||
+#include <linux/module.h>
|
||||
+#include <linux/of.h>
|
||||
+#include <linux/platform_device.h>
|
||||
+#include <linux/pinctrl/pinctrl.h>
|
||||
+
|
||||
+#include "pinctrl-msm.h"
|
||||
+
|
||||
+#define FUNCTION(fname) \
|
||||
+ [msm_mux_##fname] = { \
|
||||
+ .name = #fname, \
|
||||
+ .groups = fname##_groups, \
|
||||
+ .ngroups = ARRAY_SIZE(fname##_groups), \
|
||||
+ }
|
||||
+
|
||||
+#define REG_SIZE 0x1000
|
||||
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
|
||||
+ { \
|
||||
+ .name = "gpio" #id, \
|
||||
+ .pins = gpio##id##_pins, \
|
||||
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
|
||||
+ .funcs = (int[]){ \
|
||||
+ msm_mux_gpio, /* gpio mode */ \
|
||||
+ msm_mux_##f1, \
|
||||
+ msm_mux_##f2, \
|
||||
+ msm_mux_##f3, \
|
||||
+ msm_mux_##f4, \
|
||||
+ msm_mux_##f5, \
|
||||
+ msm_mux_##f6, \
|
||||
+ msm_mux_##f7, \
|
||||
+ msm_mux_##f8, \
|
||||
+ msm_mux_##f9 \
|
||||
+ }, \
|
||||
+ .nfuncs = 10, \
|
||||
+ .ctl_reg = REG_SIZE * id, \
|
||||
+ .io_reg = 0x4 + REG_SIZE * id, \
|
||||
+ .intr_cfg_reg = 0x8 + REG_SIZE * id, \
|
||||
+ .intr_status_reg = 0xc + REG_SIZE * id, \
|
||||
+ .intr_target_reg = 0x8 + REG_SIZE * id, \
|
||||
+ .mux_bit = 2, \
|
||||
+ .pull_bit = 0, \
|
||||
+ .drv_bit = 6, \
|
||||
+ .oe_bit = 9, \
|
||||
+ .in_bit = 0, \
|
||||
+ .out_bit = 1, \
|
||||
+ .intr_enable_bit = 0, \
|
||||
+ .intr_status_bit = 0, \
|
||||
+ .intr_target_bit = 5, \
|
||||
+ .intr_target_kpss_val = 3, \
|
||||
+ .intr_raw_status_bit = 4, \
|
||||
+ .intr_polarity_bit = 1, \
|
||||
+ .intr_detection_bit = 2, \
|
||||
+ .intr_detection_width = 2, \
|
||||
+ }
|
||||
+
|
||||
+static const struct pinctrl_pin_desc ipq5018_pins[] = {
|
||||
+ PINCTRL_PIN(0, "GPIO_0"),
|
||||
+ PINCTRL_PIN(1, "GPIO_1"),
|
||||
+ PINCTRL_PIN(2, "GPIO_2"),
|
||||
+ PINCTRL_PIN(3, "GPIO_3"),
|
||||
+ PINCTRL_PIN(4, "GPIO_4"),
|
||||
+ PINCTRL_PIN(5, "GPIO_5"),
|
||||
+ PINCTRL_PIN(6, "GPIO_6"),
|
||||
+ PINCTRL_PIN(7, "GPIO_7"),
|
||||
+ PINCTRL_PIN(8, "GPIO_8"),
|
||||
+ PINCTRL_PIN(9, "GPIO_9"),
|
||||
+ PINCTRL_PIN(10, "GPIO_10"),
|
||||
+ PINCTRL_PIN(11, "GPIO_11"),
|
||||
+ PINCTRL_PIN(12, "GPIO_12"),
|
||||
+ PINCTRL_PIN(13, "GPIO_13"),
|
||||
+ PINCTRL_PIN(14, "GPIO_14"),
|
||||
+ PINCTRL_PIN(15, "GPIO_15"),
|
||||
+ PINCTRL_PIN(16, "GPIO_16"),
|
||||
+ PINCTRL_PIN(17, "GPIO_17"),
|
||||
+ PINCTRL_PIN(18, "GPIO_18"),
|
||||
+ PINCTRL_PIN(19, "GPIO_19"),
|
||||
+ PINCTRL_PIN(20, "GPIO_20"),
|
||||
+ PINCTRL_PIN(21, "GPIO_21"),
|
||||
+ PINCTRL_PIN(22, "GPIO_22"),
|
||||
+ PINCTRL_PIN(23, "GPIO_23"),
|
||||
+ PINCTRL_PIN(24, "GPIO_24"),
|
||||
+ PINCTRL_PIN(25, "GPIO_25"),
|
||||
+ PINCTRL_PIN(26, "GPIO_26"),
|
||||
+ PINCTRL_PIN(27, "GPIO_27"),
|
||||
+ PINCTRL_PIN(28, "GPIO_28"),
|
||||
+ PINCTRL_PIN(29, "GPIO_29"),
|
||||
+ PINCTRL_PIN(30, "GPIO_30"),
|
||||
+ PINCTRL_PIN(31, "GPIO_31"),
|
||||
+ PINCTRL_PIN(32, "GPIO_32"),
|
||||
+ PINCTRL_PIN(33, "GPIO_33"),
|
||||
+ PINCTRL_PIN(34, "GPIO_34"),
|
||||
+ PINCTRL_PIN(35, "GPIO_35"),
|
||||
+ PINCTRL_PIN(36, "GPIO_36"),
|
||||
+ PINCTRL_PIN(37, "GPIO_37"),
|
||||
+ PINCTRL_PIN(38, "GPIO_38"),
|
||||
+ PINCTRL_PIN(39, "GPIO_39"),
|
||||
+ PINCTRL_PIN(40, "GPIO_40"),
|
||||
+ PINCTRL_PIN(41, "GPIO_41"),
|
||||
+ PINCTRL_PIN(42, "GPIO_42"),
|
||||
+ PINCTRL_PIN(43, "GPIO_43"),
|
||||
+ PINCTRL_PIN(44, "GPIO_44"),
|
||||
+ PINCTRL_PIN(45, "GPIO_45"),
|
||||
+ PINCTRL_PIN(46, "GPIO_46"),
|
||||
+};
|
||||
+
|
||||
+#define DECLARE_MSM_GPIO_PINS(pin) \
|
||||
+ static const unsigned int gpio##pin##_pins[] = { pin }
|
||||
+DECLARE_MSM_GPIO_PINS(0);
|
||||
+DECLARE_MSM_GPIO_PINS(1);
|
||||
+DECLARE_MSM_GPIO_PINS(2);
|
||||
+DECLARE_MSM_GPIO_PINS(3);
|
||||
+DECLARE_MSM_GPIO_PINS(4);
|
||||
+DECLARE_MSM_GPIO_PINS(5);
|
||||
+DECLARE_MSM_GPIO_PINS(6);
|
||||
+DECLARE_MSM_GPIO_PINS(7);
|
||||
+DECLARE_MSM_GPIO_PINS(8);
|
||||
+DECLARE_MSM_GPIO_PINS(9);
|
||||
+DECLARE_MSM_GPIO_PINS(10);
|
||||
+DECLARE_MSM_GPIO_PINS(11);
|
||||
+DECLARE_MSM_GPIO_PINS(12);
|
||||
+DECLARE_MSM_GPIO_PINS(13);
|
||||
+DECLARE_MSM_GPIO_PINS(14);
|
||||
+DECLARE_MSM_GPIO_PINS(15);
|
||||
+DECLARE_MSM_GPIO_PINS(16);
|
||||
+DECLARE_MSM_GPIO_PINS(17);
|
||||
+DECLARE_MSM_GPIO_PINS(18);
|
||||
+DECLARE_MSM_GPIO_PINS(19);
|
||||
+DECLARE_MSM_GPIO_PINS(20);
|
||||
+DECLARE_MSM_GPIO_PINS(21);
|
||||
+DECLARE_MSM_GPIO_PINS(22);
|
||||
+DECLARE_MSM_GPIO_PINS(23);
|
||||
+DECLARE_MSM_GPIO_PINS(24);
|
||||
+DECLARE_MSM_GPIO_PINS(25);
|
||||
+DECLARE_MSM_GPIO_PINS(26);
|
||||
+DECLARE_MSM_GPIO_PINS(27);
|
||||
+DECLARE_MSM_GPIO_PINS(28);
|
||||
+DECLARE_MSM_GPIO_PINS(29);
|
||||
+DECLARE_MSM_GPIO_PINS(30);
|
||||
+DECLARE_MSM_GPIO_PINS(31);
|
||||
+DECLARE_MSM_GPIO_PINS(32);
|
||||
+DECLARE_MSM_GPIO_PINS(33);
|
||||
+DECLARE_MSM_GPIO_PINS(34);
|
||||
+DECLARE_MSM_GPIO_PINS(35);
|
||||
+DECLARE_MSM_GPIO_PINS(36);
|
||||
+DECLARE_MSM_GPIO_PINS(37);
|
||||
+DECLARE_MSM_GPIO_PINS(38);
|
||||
+DECLARE_MSM_GPIO_PINS(39);
|
||||
+DECLARE_MSM_GPIO_PINS(40);
|
||||
+DECLARE_MSM_GPIO_PINS(41);
|
||||
+DECLARE_MSM_GPIO_PINS(42);
|
||||
+DECLARE_MSM_GPIO_PINS(43);
|
||||
+DECLARE_MSM_GPIO_PINS(44);
|
||||
+DECLARE_MSM_GPIO_PINS(45);
|
||||
+DECLARE_MSM_GPIO_PINS(46);
|
||||
+
|
||||
+enum ipq5018_functions {
|
||||
+ msm_mux_atest_char,
|
||||
+ msm_mux_atest_char0,
|
||||
+ msm_mux_atest_char1,
|
||||
+ msm_mux_atest_char2,
|
||||
+ msm_mux_atest_char3,
|
||||
+ msm_mux_audio_pdm0,
|
||||
+ msm_mux_audio_pdm1,
|
||||
+ msm_mux_audio_rxbclk,
|
||||
+ msm_mux_audio_rxd,
|
||||
+ msm_mux_audio_rxfsync,
|
||||
+ msm_mux_audio_rxmclk,
|
||||
+ msm_mux_audio_txbclk,
|
||||
+ msm_mux_audio_txd,
|
||||
+ msm_mux_audio_txfsync,
|
||||
+ msm_mux_audio_txmclk,
|
||||
+ msm_mux_blsp0_i2c,
|
||||
+ msm_mux_blsp0_spi,
|
||||
+ msm_mux_blsp0_uart0,
|
||||
+ msm_mux_blsp0_uart1,
|
||||
+ msm_mux_blsp1_i2c0,
|
||||
+ msm_mux_blsp1_i2c1,
|
||||
+ msm_mux_blsp1_spi0,
|
||||
+ msm_mux_blsp1_spi1,
|
||||
+ msm_mux_blsp1_uart0,
|
||||
+ msm_mux_blsp1_uart1,
|
||||
+ msm_mux_blsp1_uart2,
|
||||
+ msm_mux_blsp2_i2c0,
|
||||
+ msm_mux_blsp2_i2c1,
|
||||
+ msm_mux_blsp2_spi,
|
||||
+ msm_mux_blsp2_spi0,
|
||||
+ msm_mux_blsp2_spi1,
|
||||
+ msm_mux_btss0,
|
||||
+ msm_mux_btss1,
|
||||
+ msm_mux_btss10,
|
||||
+ msm_mux_btss11,
|
||||
+ msm_mux_btss12,
|
||||
+ msm_mux_btss13,
|
||||
+ msm_mux_btss2,
|
||||
+ msm_mux_btss3,
|
||||
+ msm_mux_btss4,
|
||||
+ msm_mux_btss5,
|
||||
+ msm_mux_btss6,
|
||||
+ msm_mux_btss7,
|
||||
+ msm_mux_btss8,
|
||||
+ msm_mux_btss9,
|
||||
+ msm_mux_burn0,
|
||||
+ msm_mux_burn1,
|
||||
+ msm_mux_cri_trng,
|
||||
+ msm_mux_cri_trng0,
|
||||
+ msm_mux_cri_trng1,
|
||||
+ msm_mux_cxc_clk,
|
||||
+ msm_mux_cxc_data,
|
||||
+ msm_mux_dbg_out,
|
||||
+ msm_mux_eud_gpio,
|
||||
+ msm_mux_gcc_plltest,
|
||||
+ msm_mux_gcc_tlmm,
|
||||
+ msm_mux_gpio,
|
||||
+ msm_mux_mac0,
|
||||
+ msm_mux_mac1,
|
||||
+ msm_mux_mdc,
|
||||
+ msm_mux_mdio,
|
||||
+ msm_mux_pcie0_clk,
|
||||
+ msm_mux_pcie0_wake,
|
||||
+ msm_mux_pcie1_clk,
|
||||
+ msm_mux_pcie1_wake,
|
||||
+ msm_mux_pll_test,
|
||||
+ msm_mux_prng_rosc,
|
||||
+ msm_mux_pwm0,
|
||||
+ msm_mux_pwm1,
|
||||
+ msm_mux_pwm2,
|
||||
+ msm_mux_pwm3,
|
||||
+ msm_mux_qdss_cti_trig_in_a0,
|
||||
+ msm_mux_qdss_cti_trig_in_a1,
|
||||
+ msm_mux_qdss_cti_trig_in_b0,
|
||||
+ msm_mux_qdss_cti_trig_in_b1,
|
||||
+ msm_mux_qdss_cti_trig_out_a0,
|
||||
+ msm_mux_qdss_cti_trig_out_a1,
|
||||
+ msm_mux_qdss_cti_trig_out_b0,
|
||||
+ msm_mux_qdss_cti_trig_out_b1,
|
||||
+ msm_mux_qdss_traceclk_a,
|
||||
+ msm_mux_qdss_traceclk_b,
|
||||
+ msm_mux_qdss_tracectl_a,
|
||||
+ msm_mux_qdss_tracectl_b,
|
||||
+ msm_mux_qdss_tracedata_a,
|
||||
+ msm_mux_qdss_tracedata_b,
|
||||
+ msm_mux_qspi_clk,
|
||||
+ msm_mux_qspi_cs,
|
||||
+ msm_mux_qspi0,
|
||||
+ msm_mux_qspi1,
|
||||
+ msm_mux_qspi2,
|
||||
+ msm_mux_qspi3,
|
||||
+ msm_mux_reset_out,
|
||||
+ msm_mux_sdc1_clk,
|
||||
+ msm_mux_sdc1_cmd,
|
||||
+ msm_mux_sdc10,
|
||||
+ msm_mux_sdc11,
|
||||
+ msm_mux_sdc12,
|
||||
+ msm_mux_sdc13,
|
||||
+ msm_mux_wci0,
|
||||
+ msm_mux_wci1,
|
||||
+ msm_mux_wci2,
|
||||
+ msm_mux_wci3,
|
||||
+ msm_mux_wci4,
|
||||
+ msm_mux_wci5,
|
||||
+ msm_mux_wci6,
|
||||
+ msm_mux_wci7,
|
||||
+ msm_mux_wsa_swrm,
|
||||
+ msm_mux_wsi_clk3,
|
||||
+ msm_mux_wsi_data3,
|
||||
+ msm_mux_wsis_reset,
|
||||
+ msm_mux_xfem0,
|
||||
+ msm_mux_xfem1,
|
||||
+ msm_mux_xfem2,
|
||||
+ msm_mux_xfem3,
|
||||
+ msm_mux_xfem4,
|
||||
+ msm_mux_xfem5,
|
||||
+ msm_mux_xfem6,
|
||||
+ msm_mux_xfem7,
|
||||
+ msm_mux__,
|
||||
+};
|
||||
+
|
||||
+static const char * const atest_char0_groups[] = {
|
||||
+ "gpio0",
|
||||
+};
|
||||
+static const char * const _groups[] = {
|
||||
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
|
||||
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
|
||||
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
|
||||
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
|
||||
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
|
||||
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
|
||||
+ "gpio43", "gpio44", "gpio45", "gpio46",
|
||||
+};
|
||||
+static const char * const wci0_groups[] = {
|
||||
+ "gpio0", "gpio0",
|
||||
+};
|
||||
+static const char * const qdss_cti_trig_out_a0_groups[] = {
|
||||
+ "gpio0",
|
||||
+};
|
||||
+static const char * const xfem0_groups[] = {
|
||||
+ "gpio0",
|
||||
+};
|
||||
+static const char * const atest_char1_groups[] = {
|
||||
+ "gpio1",
|
||||
+};
|
||||
+static const char * const qdss_cti_trig_in_a0_groups[] = {
|
||||
+ "gpio1",
|
||||
+};
|
||||
+static const char * const wci1_groups[] = {
|
||||
+ "gpio1", "gpio1",
|
||||
+};
|
||||
+static const char * const xfem1_groups[] = {
|
||||
+ "gpio1",
|
||||
+};
|
||||
+static const char * const atest_char2_groups[] = {
|
||||
+ "gpio2",
|
||||
+};
|
||||
+static const char * const qdss_cti_trig_out_a1_groups[] = {
|
||||
+ "gpio2",
|
||||
+};
|
||||
+static const char * const wci2_groups[] = {
|
||||
+ "gpio2", "gpio2",
|
||||
+};
|
||||
+static const char * const xfem2_groups[] = {
|
||||
+ "gpio2",
|
||||
+};
|
||||
+static const char * const atest_char3_groups[] = {
|
||||
+ "gpio3",
|
||||
+};
|
||||
+static const char * const qdss_cti_trig_in_a1_groups[] = {
|
||||
+ "gpio3",
|
||||
+};
|
||||
+static const char * const wci3_groups[] = {
|
||||
+ "gpio3", "gpio3",
|
||||
+};
|
||||
+static const char * const xfem3_groups[] = {
|
||||
+ "gpio3",
|
||||
+};
|
||||
+static const char * const sdc13_groups[] = {
|
||||
+ "gpio4",
|
||||
+};
|
||||
+static const char * const qspi3_groups[] = {
|
||||
+ "gpio4",
|
||||
+};
|
||||
+static const char * const blsp1_spi1_groups[] = {
|
||||
+ "gpio4", "gpio5", "gpio6", "gpio7",
|
||||
+};
|
||||
+static const char * const btss0_groups[] = {
|
||||
+ "gpio4",
|
||||
+};
|
||||
+static const char * const dbg_out_groups[] = {
|
||||
+ "gpio4",
|
||||
+};
|
||||
+static const char * const qdss_traceclk_a_groups[] = {
|
||||
+ "gpio4",
|
||||
+};
|
||||
+static const char * const burn0_groups[] = {
|
||||
+ "gpio4",
|
||||
+};
|
||||
+static const char * const sdc12_groups[] = {
|
||||
+ "gpio5",
|
||||
+};
|
||||
+static const char * const qspi2_groups[] = {
|
||||
+ "gpio5",
|
||||
+};
|
||||
+static const char * const cxc_clk_groups[] = {
|
||||
+ "gpio5",
|
||||
+};
|
||||
+static const char * const blsp1_i2c1_groups[] = {
|
||||
+ "gpio5", "gpio6",
|
||||
+};
|
||||
+static const char * const btss1_groups[] = {
|
||||
+ "gpio5",
|
||||
+};
|
||||
+static const char * const qdss_tracectl_a_groups[] = {
|
||||
+ "gpio5",
|
||||
+};
|
||||
+static const char * const burn1_groups[] = {
|
||||
+ "gpio5",
|
||||
+};
|
||||
+static const char * const sdc11_groups[] = {
|
||||
+ "gpio6",
|
||||
+};
|
||||
+static const char * const qspi1_groups[] = {
|
||||
+ "gpio6",
|
||||
+};
|
||||
+static const char * const cxc_data_groups[] = {
|
||||
+ "gpio6",
|
||||
+};
|
||||
+static const char * const btss2_groups[] = {
|
||||
+ "gpio6",
|
||||
+};
|
||||
+static const char * const qdss_tracedata_a_groups[] = {
|
||||
+ "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", "gpio12",
|
||||
+ "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
|
||||
+ "gpio20", "gpio21",
|
||||
+};
|
||||
+static const char * const sdc10_groups[] = {
|
||||
+ "gpio7",
|
||||
+};
|
||||
+static const char * const qspi0_groups[] = {
|
||||
+ "gpio7",
|
||||
+};
|
||||
+static const char * const mac0_groups[] = {
|
||||
+ "gpio7",
|
||||
+};
|
||||
+static const char * const btss3_groups[] = {
|
||||
+ "gpio7",
|
||||
+};
|
||||
+static const char * const sdc1_cmd_groups[] = {
|
||||
+ "gpio8",
|
||||
+};
|
||||
+static const char * const qspi_cs_groups[] = {
|
||||
+ "gpio8",
|
||||
+};
|
||||
+static const char * const mac1_groups[] = {
|
||||
+ "gpio8",
|
||||
+};
|
||||
+static const char * const btss4_groups[] = {
|
||||
+ "gpio8",
|
||||
+};
|
||||
+static const char * const sdc1_clk_groups[] = {
|
||||
+ "gpio9",
|
||||
+};
|
||||
+static const char * const qspi_clk_groups[] = {
|
||||
+ "gpio9",
|
||||
+};
|
||||
+static const char * const blsp0_spi_groups[] = {
|
||||
+ "gpio10", "gpio11", "gpio12", "gpio13",
|
||||
+};
|
||||
+static const char * const blsp1_uart0_groups[] = {
|
||||
+ "gpio10", "gpio11", "gpio12", "gpio13",
|
||||
+};
|
||||
+static const char * const gcc_plltest_groups[] = {
|
||||
+ "gpio10", "gpio12",
|
||||
+};
|
||||
+static const char * const gcc_tlmm_groups[] = {
|
||||
+ "gpio11",
|
||||
+};
|
||||
+static const char * const blsp0_i2c_groups[] = {
|
||||
+ "gpio12", "gpio13",
|
||||
+};
|
||||
+static const char * const pcie0_clk_groups[] = {
|
||||
+ "gpio14",
|
||||
+};
|
||||
+static const char * const cri_trng0_groups[] = {
|
||||
+ "gpio14",
|
||||
+};
|
||||
+static const char * const cri_trng1_groups[] = {
|
||||
+ "gpio15",
|
||||
+};
|
||||
+static const char * const pcie0_wake_groups[] = {
|
||||
+ "gpio16",
|
||||
+};
|
||||
+static const char * const cri_trng_groups[] = {
|
||||
+ "gpio16",
|
||||
+};
|
||||
+static const char * const pcie1_clk_groups[] = {
|
||||
+ "gpio17",
|
||||
+};
|
||||
+static const char * const btss5_groups[] = {
|
||||
+ "gpio17",
|
||||
+};
|
||||
+static const char * const prng_rosc_groups[] = {
|
||||
+ "gpio17",
|
||||
+};
|
||||
+static const char * const blsp1_spi0_groups[] = {
|
||||
+ "gpio18", "gpio19", "gpio20", "gpio21",
|
||||
+};
|
||||
+static const char * const btss6_groups[] = {
|
||||
+ "gpio18",
|
||||
+};
|
||||
+static const char * const pcie1_wake_groups[] = {
|
||||
+ "gpio19",
|
||||
+};
|
||||
+static const char * const blsp1_i2c0_groups[] = {
|
||||
+ "gpio19", "gpio20",
|
||||
+};
|
||||
+static const char * const btss7_groups[] = {
|
||||
+ "gpio19",
|
||||
+};
|
||||
+static const char * const blsp0_uart0_groups[] = {
|
||||
+ "gpio20", "gpio21",
|
||||
+};
|
||||
+static const char * const pll_test_groups[] = {
|
||||
+ "gpio22",
|
||||
+};
|
||||
+static const char * const eud_gpio_groups[] = {
|
||||
+ "gpio22", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
|
||||
+};
|
||||
+static const char * const audio_rxmclk_groups[] = {
|
||||
+ "gpio23", "gpio23",
|
||||
+};
|
||||
+static const char * const audio_pdm0_groups[] = {
|
||||
+ "gpio23", "gpio24",
|
||||
+};
|
||||
+static const char * const blsp2_spi1_groups[] = {
|
||||
+ "gpio23", "gpio24", "gpio25", "gpio26",
|
||||
+};
|
||||
+static const char * const blsp1_uart2_groups[] = {
|
||||
+ "gpio23", "gpio24", "gpio25", "gpio26",
|
||||
+};
|
||||
+static const char * const btss8_groups[] = {
|
||||
+ "gpio23",
|
||||
+};
|
||||
+static const char * const qdss_tracedata_b_groups[] = {
|
||||
+ "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
|
||||
+ "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
|
||||
+ "gpio37", "gpio38",
|
||||
+};
|
||||
+static const char * const audio_rxbclk_groups[] = {
|
||||
+ "gpio24",
|
||||
+};
|
||||
+static const char * const btss9_groups[] = {
|
||||
+ "gpio24",
|
||||
+};
|
||||
+static const char * const audio_rxfsync_groups[] = {
|
||||
+ "gpio25",
|
||||
+};
|
||||
+static const char * const audio_pdm1_groups[] = {
|
||||
+ "gpio25", "gpio26",
|
||||
+};
|
||||
+static const char * const blsp2_i2c1_groups[] = {
|
||||
+ "gpio25", "gpio26",
|
||||
+};
|
||||
+static const char * const btss10_groups[] = {
|
||||
+ "gpio25",
|
||||
+};
|
||||
+static const char * const audio_rxd_groups[] = {
|
||||
+ "gpio26",
|
||||
+};
|
||||
+static const char * const btss11_groups[] = {
|
||||
+ "gpio26",
|
||||
+};
|
||||
+static const char * const audio_txmclk_groups[] = {
|
||||
+ "gpio27", "gpio27",
|
||||
+};
|
||||
+static const char * const wsa_swrm_groups[] = {
|
||||
+ "gpio27", "gpio28",
|
||||
+};
|
||||
+static const char * const blsp2_spi_groups[] = {
|
||||
+ "gpio27",
|
||||
+};
|
||||
+static const char * const btss12_groups[] = {
|
||||
+ "gpio27",
|
||||
+};
|
||||
+static const char * const audio_txbclk_groups[] = {
|
||||
+ "gpio28",
|
||||
+};
|
||||
+static const char * const blsp0_uart1_groups[] = {
|
||||
+ "gpio28", "gpio29",
|
||||
+};
|
||||
+static const char * const btss13_groups[] = {
|
||||
+ "gpio28",
|
||||
+};
|
||||
+static const char * const audio_txfsync_groups[] = {
|
||||
+ "gpio29",
|
||||
+};
|
||||
+static const char * const audio_txd_groups[] = {
|
||||
+ "gpio30",
|
||||
+};
|
||||
+static const char * const wsis_reset_groups[] = {
|
||||
+ "gpio30",
|
||||
+};
|
||||
+static const char * const blsp2_spi0_groups[] = {
|
||||
+ "gpio31", "gpio32", "gpio33", "gpio34",
|
||||
+};
|
||||
+static const char * const blsp1_uart1_groups[] = {
|
||||
+ "gpio31", "gpio32", "gpio33", "gpio34",
|
||||
+};
|
||||
+static const char * const blsp2_i2c0_groups[] = {
|
||||
+ "gpio33", "gpio34",
|
||||
+};
|
||||
+static const char * const mdc_groups[] = {
|
||||
+ "gpio36",
|
||||
+};
|
||||
+static const char * const wsi_clk3_groups[] = {
|
||||
+ "gpio36",
|
||||
+};
|
||||
+static const char * const mdio_groups[] = {
|
||||
+ "gpio37",
|
||||
+};
|
||||
+static const char * const atest_char_groups[] = {
|
||||
+ "gpio37",
|
||||
+};
|
||||
+static const char * const wsi_data3_groups[] = {
|
||||
+ "gpio37",
|
||||
+};
|
||||
+static const char * const qdss_traceclk_b_groups[] = {
|
||||
+ "gpio39",
|
||||
+};
|
||||
+static const char * const reset_out_groups[] = {
|
||||
+ "gpio40",
|
||||
+};
|
||||
+static const char * const qdss_tracectl_b_groups[] = {
|
||||
+ "gpio40",
|
||||
+};
|
||||
+static const char * const pwm0_groups[] = {
|
||||
+ "gpio42",
|
||||
+};
|
||||
+static const char * const qdss_cti_trig_out_b0_groups[] = {
|
||||
+ "gpio42",
|
||||
+};
|
||||
+static const char * const wci4_groups[] = {
|
||||
+ "gpio42", "gpio42",
|
||||
+};
|
||||
+static const char * const xfem4_groups[] = {
|
||||
+ "gpio42",
|
||||
+};
|
||||
+static const char * const pwm1_groups[] = {
|
||||
+ "gpio43",
|
||||
+};
|
||||
+static const char * const qdss_cti_trig_in_b0_groups[] = {
|
||||
+ "gpio43",
|
||||
+};
|
||||
+static const char * const wci5_groups[] = {
|
||||
+ "gpio43", "gpio43",
|
||||
+};
|
||||
+static const char * const xfem5_groups[] = {
|
||||
+ "gpio43",
|
||||
+};
|
||||
+static const char * const pwm2_groups[] = {
|
||||
+ "gpio44",
|
||||
+};
|
||||
+static const char * const qdss_cti_trig_out_b1_groups[] = {
|
||||
+ "gpio44",
|
||||
+};
|
||||
+static const char * const wci6_groups[] = {
|
||||
+ "gpio44", "gpio44",
|
||||
+};
|
||||
+static const char * const xfem6_groups[] = {
|
||||
+ "gpio44",
|
||||
+};
|
||||
+static const char * const pwm3_groups[] = {
|
||||
+ "gpio45",
|
||||
+};
|
||||
+static const char * const qdss_cti_trig_in_b1_groups[] = {
|
||||
+ "gpio45",
|
||||
+};
|
||||
+static const char * const wci7_groups[] = {
|
||||
+ "gpio45", "gpio45",
|
||||
+};
|
||||
+static const char * const xfem7_groups[] = {
|
||||
+ "gpio45",
|
||||
+};
|
||||
+
|
||||
+static const char * const gpio_groups[] = {
|
||||
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
|
||||
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
|
||||
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
|
||||
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
|
||||
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
|
||||
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
|
||||
+ "gpio43", "gpio44", "gpio45", "gpio46",
|
||||
+};
|
||||
+
|
||||
+static const struct msm_function ipq5018_functions[] = {
|
||||
+ FUNCTION(atest_char),
|
||||
+ FUNCTION(atest_char0),
|
||||
+ FUNCTION(atest_char1),
|
||||
+ FUNCTION(atest_char2),
|
||||
+ FUNCTION(atest_char3),
|
||||
+ FUNCTION(audio_pdm0),
|
||||
+ FUNCTION(audio_pdm1),
|
||||
+ FUNCTION(audio_rxbclk),
|
||||
+ FUNCTION(audio_rxd),
|
||||
+ FUNCTION(audio_rxfsync),
|
||||
+ FUNCTION(audio_rxmclk),
|
||||
+ FUNCTION(audio_txbclk),
|
||||
+ FUNCTION(audio_txd),
|
||||
+ FUNCTION(audio_txfsync),
|
||||
+ FUNCTION(audio_txmclk),
|
||||
+ FUNCTION(blsp0_i2c),
|
||||
+ FUNCTION(blsp0_spi),
|
||||
+ FUNCTION(blsp0_uart0),
|
||||
+ FUNCTION(blsp0_uart1),
|
||||
+ FUNCTION(blsp1_i2c0),
|
||||
+ FUNCTION(blsp1_i2c1),
|
||||
+ FUNCTION(blsp1_spi0),
|
||||
+ FUNCTION(blsp1_spi1),
|
||||
+ FUNCTION(blsp1_uart0),
|
||||
+ FUNCTION(blsp1_uart1),
|
||||
+ FUNCTION(blsp1_uart2),
|
||||
+ FUNCTION(blsp2_i2c0),
|
||||
+ FUNCTION(blsp2_i2c1),
|
||||
+ FUNCTION(blsp2_spi),
|
||||
+ FUNCTION(blsp2_spi0),
|
||||
+ FUNCTION(blsp2_spi1),
|
||||
+ FUNCTION(btss0),
|
||||
+ FUNCTION(btss1),
|
||||
+ FUNCTION(btss10),
|
||||
+ FUNCTION(btss11),
|
||||
+ FUNCTION(btss12),
|
||||
+ FUNCTION(btss13),
|
||||
+ FUNCTION(btss2),
|
||||
+ FUNCTION(btss3),
|
||||
+ FUNCTION(btss4),
|
||||
+ FUNCTION(btss5),
|
||||
+ FUNCTION(btss6),
|
||||
+ FUNCTION(btss7),
|
||||
+ FUNCTION(btss8),
|
||||
+ FUNCTION(btss9),
|
||||
+ FUNCTION(burn0),
|
||||
+ FUNCTION(burn1),
|
||||
+ FUNCTION(cri_trng),
|
||||
+ FUNCTION(cri_trng0),
|
||||
+ FUNCTION(cri_trng1),
|
||||
+ FUNCTION(cxc_clk),
|
||||
+ FUNCTION(cxc_data),
|
||||
+ FUNCTION(dbg_out),
|
||||
+ FUNCTION(eud_gpio),
|
||||
+ FUNCTION(gcc_plltest),
|
||||
+ FUNCTION(gcc_tlmm),
|
||||
+ FUNCTION(gpio),
|
||||
+ FUNCTION(mac0),
|
||||
+ FUNCTION(mac1),
|
||||
+ FUNCTION(mdc),
|
||||
+ FUNCTION(mdio),
|
||||
+ FUNCTION(pcie0_clk),
|
||||
+ FUNCTION(pcie0_wake),
|
||||
+ FUNCTION(pcie1_clk),
|
||||
+ FUNCTION(pcie1_wake),
|
||||
+ FUNCTION(pll_test),
|
||||
+ FUNCTION(prng_rosc),
|
||||
+ FUNCTION(pwm0),
|
||||
+ FUNCTION(pwm1),
|
||||
+ FUNCTION(pwm2),
|
||||
+ FUNCTION(pwm3),
|
||||
+ FUNCTION(qdss_cti_trig_in_a0),
|
||||
+ FUNCTION(qdss_cti_trig_in_a1),
|
||||
+ FUNCTION(qdss_cti_trig_in_b0),
|
||||
+ FUNCTION(qdss_cti_trig_in_b1),
|
||||
+ FUNCTION(qdss_cti_trig_out_a0),
|
||||
+ FUNCTION(qdss_cti_trig_out_a1),
|
||||
+ FUNCTION(qdss_cti_trig_out_b0),
|
||||
+ FUNCTION(qdss_cti_trig_out_b1),
|
||||
+ FUNCTION(qdss_traceclk_a),
|
||||
+ FUNCTION(qdss_traceclk_b),
|
||||
+ FUNCTION(qdss_tracectl_a),
|
||||
+ FUNCTION(qdss_tracectl_b),
|
||||
+ FUNCTION(qdss_tracedata_a),
|
||||
+ FUNCTION(qdss_tracedata_b),
|
||||
+ FUNCTION(qspi_clk),
|
||||
+ FUNCTION(qspi_cs),
|
||||
+ FUNCTION(qspi0),
|
||||
+ FUNCTION(qspi1),
|
||||
+ FUNCTION(qspi2),
|
||||
+ FUNCTION(qspi3),
|
||||
+ FUNCTION(reset_out),
|
||||
+ FUNCTION(sdc1_clk),
|
||||
+ FUNCTION(sdc1_cmd),
|
||||
+ FUNCTION(sdc10),
|
||||
+ FUNCTION(sdc11),
|
||||
+ FUNCTION(sdc12),
|
||||
+ FUNCTION(sdc13),
|
||||
+ FUNCTION(wci0),
|
||||
+ FUNCTION(wci1),
|
||||
+ FUNCTION(wci2),
|
||||
+ FUNCTION(wci3),
|
||||
+ FUNCTION(wci4),
|
||||
+ FUNCTION(wci5),
|
||||
+ FUNCTION(wci6),
|
||||
+ FUNCTION(wci7),
|
||||
+ FUNCTION(wsa_swrm),
|
||||
+ FUNCTION(wsi_clk3),
|
||||
+ FUNCTION(wsi_data3),
|
||||
+ FUNCTION(wsis_reset),
|
||||
+ FUNCTION(xfem0),
|
||||
+ FUNCTION(xfem1),
|
||||
+ FUNCTION(xfem2),
|
||||
+ FUNCTION(xfem3),
|
||||
+ FUNCTION(xfem4),
|
||||
+ FUNCTION(xfem5),
|
||||
+ FUNCTION(xfem6),
|
||||
+ FUNCTION(xfem7),
|
||||
+};
|
||||
+static const struct msm_pingroup ipq5018_groups[] = {
|
||||
+ PINGROUP(0, atest_char0, _, qdss_cti_trig_out_a0, wci0, wci0, xfem0,
|
||||
+ _, _, _),
|
||||
+ PINGROUP(1, atest_char1, _, qdss_cti_trig_in_a0, wci1, wci1, xfem1,
|
||||
+ _, _, _),
|
||||
+ PINGROUP(2, atest_char2, _, qdss_cti_trig_out_a1, wci2, wci2, xfem2,
|
||||
+ _, _, _),
|
||||
+ PINGROUP(3, atest_char3, _, qdss_cti_trig_in_a1, wci3, wci3, xfem3,
|
||||
+ _, _, _),
|
||||
+ PINGROUP(4, sdc13, qspi3, blsp1_spi1, btss0, dbg_out, qdss_traceclk_a,
|
||||
+ _, burn0, _),
|
||||
+ PINGROUP(5, sdc12, qspi2, cxc_clk, blsp1_spi1, blsp1_i2c1, btss1, _,
|
||||
+ qdss_tracectl_a, _),
|
||||
+ PINGROUP(6, sdc11, qspi1, cxc_data, blsp1_spi1, blsp1_i2c1, btss2, _,
|
||||
+ qdss_tracedata_a, _),
|
||||
+ PINGROUP(7, sdc10, qspi0, mac0, blsp1_spi1, btss3, _,
|
||||
+ qdss_tracedata_a, _, _),
|
||||
+ PINGROUP(8, sdc1_cmd, qspi_cs, mac1, btss4, _, qdss_tracedata_a, _,
|
||||
+ _, _),
|
||||
+ PINGROUP(9, sdc1_clk, qspi_clk, _, qdss_tracedata_a, _, _, _, _,
|
||||
+ _),
|
||||
+ PINGROUP(10, blsp0_spi, blsp1_uart0, _, gcc_plltest, qdss_tracedata_a,
|
||||
+ _, _, _, _),
|
||||
+ PINGROUP(11, blsp0_spi, blsp1_uart0, _, gcc_tlmm, qdss_tracedata_a,
|
||||
+ _, _, _, _),
|
||||
+ PINGROUP(12, blsp0_spi, blsp0_i2c, blsp1_uart0, _, gcc_plltest,
|
||||
+ qdss_tracedata_a, _, _, _),
|
||||
+ PINGROUP(13, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a,
|
||||
+ _, _, _, _),
|
||||
+ PINGROUP(14, pcie0_clk, _, _, cri_trng0, qdss_tracedata_a, _, _, _, _),
|
||||
+ PINGROUP(15, _, _, cri_trng1, qdss_tracedata_a, _, _, _, _, _),
|
||||
+ PINGROUP(16, pcie0_wake, _, _, cri_trng, qdss_tracedata_a, _, _, _, _),
|
||||
+ PINGROUP(17, pcie1_clk, btss5, _, prng_rosc, qdss_tracedata_a, _, _,
|
||||
+ _, _),
|
||||
+ PINGROUP(18, blsp1_spi0, btss6, _, qdss_tracedata_a, _, _, _, _, _),
|
||||
+ PINGROUP(19, pcie1_wake, blsp1_spi0, blsp1_i2c0, btss7, _,
|
||||
+ qdss_tracedata_a, _, _, _),
|
||||
+ PINGROUP(20, blsp0_uart0, blsp1_spi0, blsp1_i2c0, _, qdss_tracedata_a,
|
||||
+ _, _, _, _),
|
||||
+ PINGROUP(21, blsp0_uart0, blsp1_spi0, _, qdss_tracedata_a, _, _, _,
|
||||
+ _, _),
|
||||
+ PINGROUP(22, _, pll_test, eud_gpio, _, _, _, _, _, _),
|
||||
+ PINGROUP(23, audio_rxmclk, audio_pdm0, audio_rxmclk, blsp2_spi1,
|
||||
+ blsp1_uart2, btss8, _, qdss_tracedata_b, _),
|
||||
+ PINGROUP(24, audio_rxbclk, audio_pdm0, blsp2_spi1, blsp1_uart2, btss9,
|
||||
+ _, qdss_tracedata_b, _, _),
|
||||
+ PINGROUP(25, audio_rxfsync, audio_pdm1, blsp2_i2c1, blsp2_spi1,
|
||||
+ blsp1_uart2, btss10, _, qdss_tracedata_b, _),
|
||||
+ PINGROUP(26, audio_rxd, audio_pdm1, blsp2_i2c1, blsp2_spi1,
|
||||
+ blsp1_uart2, btss11, _, qdss_tracedata_b, _),
|
||||
+ PINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss12,
|
||||
+ _, qdss_tracedata_b, _, _),
|
||||
+ PINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss13,
|
||||
+ qdss_tracedata_b, _, _, _, _),
|
||||
+ PINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _,
|
||||
+ _, _, _),
|
||||
+ PINGROUP(30, audio_txd, qdss_tracedata_b, _, wsis_reset, _, _, _,
|
||||
+ _, _),
|
||||
+ PINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio,
|
||||
+ _, _, _, _),
|
||||
+ PINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio,
|
||||
+ _, _, _, _),
|
||||
+ PINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b,
|
||||
+ eud_gpio, _, _, _),
|
||||
+ PINGROUP(34, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b,
|
||||
+ eud_gpio, _, _, _),
|
||||
+ PINGROUP(35, _, qdss_tracedata_b, eud_gpio, _, _, _, _, _, _),
|
||||
+ PINGROUP(36, mdc, qdss_tracedata_b, _, wsi_clk3, _, _, _, _, _),
|
||||
+ PINGROUP(37, mdio, atest_char, qdss_tracedata_b, _, wsi_data3, _, _,
|
||||
+ _, _),
|
||||
+ PINGROUP(38, qdss_tracedata_b, _, _, _, _, _, _, _, _),
|
||||
+ PINGROUP(39, qdss_traceclk_b, _, _, _, _, _, _, _, _),
|
||||
+ PINGROUP(40, reset_out, qdss_tracectl_b, _, _, _, _, _, _, _),
|
||||
+ PINGROUP(41, _, _, _, _, _, _, _, _, _),
|
||||
+ PINGROUP(42, pwm0, qdss_cti_trig_out_b0, wci4, wci4, xfem4, _, _, _,
|
||||
+ _),
|
||||
+ PINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci5, wci5, xfem5, _, _, _, _),
|
||||
+ PINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci6, wci6, xfem6, _, _, _,
|
||||
+ _),
|
||||
+ PINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci7, wci7, xfem7, _, _, _, _),
|
||||
+ PINGROUP(46, _, _, _, _, _, _, _, _, _),
|
||||
+};
|
||||
+
|
||||
+static const struct msm_pinctrl_soc_data ipq5018_pinctrl = {
|
||||
+ .pins = ipq5018_pins,
|
||||
+ .npins = ARRAY_SIZE(ipq5018_pins),
|
||||
+ .functions = ipq5018_functions,
|
||||
+ .nfunctions = ARRAY_SIZE(ipq5018_functions),
|
||||
+ .groups = ipq5018_groups,
|
||||
+ .ngroups = ARRAY_SIZE(ipq5018_groups),
|
||||
+ .ngpios = 47,
|
||||
+};
|
||||
+
|
||||
+static int ipq5018_pinctrl_probe(struct platform_device *pdev)
|
||||
+{
|
||||
+ return msm_pinctrl_probe(pdev, &ipq5018_pinctrl);
|
||||
+}
|
||||
+
|
||||
+static const struct of_device_id ipq5018_pinctrl_of_match[] = {
|
||||
+ { .compatible = "qcom,ipq5018-pinctrl", },
|
||||
+ { },
|
||||
+};
|
||||
+
|
||||
+static struct platform_driver ipq5018_pinctrl_driver = {
|
||||
+ .driver = {
|
||||
+ .name = "ipq5018-pinctrl",
|
||||
+ .of_match_table = ipq5018_pinctrl_of_match,
|
||||
+ },
|
||||
+ .probe = ipq5018_pinctrl_probe,
|
||||
+ .remove = msm_pinctrl_remove,
|
||||
+};
|
||||
+
|
||||
+static int __init ipq5018_pinctrl_init(void)
|
||||
+{
|
||||
+ return platform_driver_register(&ipq5018_pinctrl_driver);
|
||||
+}
|
||||
+arch_initcall(ipq5018_pinctrl_init);
|
||||
+
|
||||
+static void __exit ipq5018_pinctrl_exit(void)
|
||||
+{
|
||||
+ platform_driver_unregister(&ipq5018_pinctrl_driver);
|
||||
+}
|
||||
+module_exit(ipq5018_pinctrl_exit);
|
||||
+
|
||||
+MODULE_DESCRIPTION("Qualcomm Technologies Inc ipq5018 pinctrl driver");
|
||||
+MODULE_LICENSE("GPL v2");
|
||||
+MODULE_DEVICE_TABLE(of, ipq5018_pinctrl_of_match);
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,314 @@
|
||||
From 9bb7293b6c0c097df32d778347fe523cfa6c0bc6 Mon Sep 17 00:00:00 2001
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Mon, 28 Sep 2020 10:45:39 +0530
|
||||
Subject: [PATCH 6/7] arm64: dts: Add ipq5018 SoC and MP03 board support
|
||||
|
||||
Add initial device tree support for the Qualcomm IPQ5018 SoC and
|
||||
MP03.1-C2 board.
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
|
||||
Pick from <1601270140-4306-7-git-send-email-varada@codeaurora.org>
|
||||
|
||||
Fix gpio-ranges
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
.../devicetree/bindings/arm/qcom.yaml | 7 +
|
||||
arch/arm64/boot/dts/qcom/Makefile | 1 +
|
||||
.../arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts | 30 +++
|
||||
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 201 ++++++++++++++++++
|
||||
4 files changed, 239 insertions(+)
|
||||
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
|
||||
create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
|
||||
diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml
|
||||
index 3de6182cde97..515eb93879a6 100644
|
||||
--- a/Documentation/devicetree/bindings/arm/qcom.yaml
|
||||
+++ b/Documentation/devicetree/bindings/arm/qcom.yaml
|
||||
@@ -28,6 +28,7 @@ description: |
|
||||
apq8074
|
||||
apq8084
|
||||
apq8096
|
||||
+ ipq5018
|
||||
ipq6018
|
||||
ipq8074
|
||||
mdm9615
|
||||
@@ -59,6 +60,7 @@ description: |
|
||||
hk10-c2
|
||||
idp
|
||||
liquid
|
||||
+ mp03
|
||||
mtp
|
||||
qrd
|
||||
sbc
|
||||
@@ -134,6 +136,11 @@ properties:
|
||||
- qcom,ipq4019-dk04.1-c1
|
||||
- const: qcom,ipq4019
|
||||
|
||||
+ - items:
|
||||
+ - enum:
|
||||
+ - qcom,ipq5018-mp03
|
||||
+ - const: qcom,ipq5018
|
||||
+
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq8064-ap148
|
||||
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
|
||||
index 6498a1ec893f..0d8b516362bc 100644
|
||||
--- a/arch/arm64/boot/dts/qcom/Makefile
|
||||
+++ b/arch/arm64/boot/dts/qcom/Makefile
|
||||
@@ -1,6 +1,7 @@
|
||||
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
|
||||
+dtb-$(CONFIG_ARCH_QCOM) += ipq5018-mp03.1-c2.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
|
||||
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
|
||||
diff --git a/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
|
||||
new file mode 100644
|
||||
index 000000000000..41bb3b3acb49
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts
|
||||
@@ -0,0 +1,30 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
+/*
|
||||
+ * IPQ5018 CP01 board device tree source
|
||||
+ *
|
||||
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
+ */
|
||||
+
|
||||
+/dts-v1/;
|
||||
+
|
||||
+#include "ipq5018.dtsi"
|
||||
+
|
||||
+/ {
|
||||
+ model = "Qualcomm Technologies, Inc. IPQ5018/AP-MP03-C2";
|
||||
+ compatible = "qcom,ipq5018-mp03", "qcom,ipq5018";
|
||||
+
|
||||
+ aliases {
|
||||
+ serial0 = &blsp1_uart1;
|
||||
+ };
|
||||
+
|
||||
+ chosen {
|
||||
+ stdout-path = "serial0:115200n8";
|
||||
+ bootargs-append = " swiotlb=1";
|
||||
+ };
|
||||
+};
|
||||
+
|
||||
+&blsp1_uart1 {
|
||||
+ pinctrl-0 = <&serial_1_pins>;
|
||||
+ pinctrl-names = "default";
|
||||
+ status = "ok";
|
||||
+};
|
||||
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
new file mode 100644
|
||||
index 000000000000..487cc15da457
|
||||
--- /dev/null
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -0,0 +1,201 @@
|
||||
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
+/*
|
||||
+ * IPQ5018 SoC device tree source
|
||||
+ *
|
||||
+ * Copyright (c) 2019, The Linux Foundation. All rights reserved.
|
||||
+ */
|
||||
+
|
||||
+#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
+#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
|
||||
+#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
|
||||
+
|
||||
+/ {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ interrupt-parent = <&intc>;
|
||||
+
|
||||
+ clocks {
|
||||
+ sleep_clk: sleep-clk {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <32000>;
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+
|
||||
+ xo: xo {
|
||||
+ compatible = "fixed-clock";
|
||||
+ clock-frequency = <24000000>;
|
||||
+ #clock-cells = <0>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ cpus: cpus {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+
|
||||
+ CPU0: cpu@0 {
|
||||
+ device_type = "cpu";
|
||||
+ compatible = "arm,cortex-a53";
|
||||
+ reg = <0x0>;
|
||||
+ enable-method = "psci";
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ };
|
||||
+
|
||||
+ CPU1: cpu@1 {
|
||||
+ device_type = "cpu";
|
||||
+ compatible = "arm,cortex-a53";
|
||||
+ enable-method = "psci";
|
||||
+ reg = <0x1>;
|
||||
+ next-level-cache = <&L2_0>;
|
||||
+ };
|
||||
+
|
||||
+ L2_0: l2-cache {
|
||||
+ compatible = "cache";
|
||||
+ cache-level = <0x2>;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ pmuv8: pmu {
|
||||
+ compatible = "arm,cortex-a53-pmu";
|
||||
+ interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
+ IRQ_TYPE_LEVEL_HIGH)>;
|
||||
+ };
|
||||
+
|
||||
+ psci: psci {
|
||||
+ compatible = "arm,psci-1.0";
|
||||
+ method = "smc";
|
||||
+ };
|
||||
+
|
||||
+ reserved-memory {
|
||||
+ #address-cells = <2>;
|
||||
+ #size-cells = <2>;
|
||||
+ ranges;
|
||||
+
|
||||
+ tz: tz@4ac00000 {
|
||||
+ reg = <0x0 0x4ac00000 0x0 0x00400000>;
|
||||
+ no-map;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ soc: soc {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges = <0 0 0 0xffffffff>;
|
||||
+ dma-ranges;
|
||||
+ compatible = "simple-bus";
|
||||
+
|
||||
+ tlmm: pinctrl@1000000 {
|
||||
+ compatible = "qcom,ipq5018-pinctrl";
|
||||
+ reg = <0x01000000 0x300000>;
|
||||
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ gpio-controller;
|
||||
+ #gpio-cells = <2>;
|
||||
+ gpio-ranges = <&tlmm 0 0 80>;
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <2>;
|
||||
+
|
||||
+ serial_1_pins: serial1-pinmux {
|
||||
+ pins = "gpio31", "gpio32", "gpio33", "gpio34";
|
||||
+ function = "blsp1_uart1";
|
||||
+ drive-strength = <8>;
|
||||
+ bias-pull-down;
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
+ gcc: gcc@1800000 {
|
||||
+ compatible = "qcom,gcc-ipq5018";
|
||||
+ reg = <0x01800000 0x80000>;
|
||||
+ clocks = <&xo>, <&sleep_clk>;
|
||||
+ clock-names = "xo", "sleep_clk";
|
||||
+ #clock-cells = <1>;
|
||||
+ #reset-cells = <1>;
|
||||
+ };
|
||||
+
|
||||
+ blsp1_uart1: serial@78af000 {
|
||||
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
+ reg = <0x078af000 0x200>;
|
||||
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
|
||||
+ <&gcc GCC_BLSP1_AHB_CLK>;
|
||||
+ clock-names = "core", "iface";
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ intc: interrupt-controller@b000000 {
|
||||
+ compatible = "qcom,msm-qgic2";
|
||||
+ interrupt-controller;
|
||||
+ #interrupt-cells = <0x3>;
|
||||
+ reg = <0x0b000000 0x1000>, /*GICD*/
|
||||
+ <0x0b002000 0x1000>, /*GICC*/
|
||||
+ <0x0b001000 0x1000>, /*GICH*/
|
||||
+ <0x0b004000 0x1000>; /*GICV*/
|
||||
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ };
|
||||
+
|
||||
+ timer {
|
||||
+ compatible = "arm,armv8-timer";
|
||||
+ interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
+ <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
+ };
|
||||
+
|
||||
+ timer@b120000 {
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+ ranges;
|
||||
+ compatible = "arm,armv7-timer-mem";
|
||||
+ reg = <0x0b120000 0x1000>;
|
||||
+ clock-frequency = <19200000>;
|
||||
+
|
||||
+ frame@b120000 {
|
||||
+ frame-number = <0>;
|
||||
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg = <0x0b121000 0x1000>,
|
||||
+ <0x0b122000 0x1000>;
|
||||
+ };
|
||||
+
|
||||
+ frame@b123000 {
|
||||
+ frame-number = <1>;
|
||||
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg = <0xb123000 0x1000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ frame@b124000 {
|
||||
+ frame-number = <2>;
|
||||
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg = <0x0b124000 0x1000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ frame@b125000 {
|
||||
+ frame-number = <3>;
|
||||
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg = <0x0b125000 0x1000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ frame@b126000 {
|
||||
+ frame-number = <4>;
|
||||
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg = <0x0b126000 0x1000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ frame@b127000 {
|
||||
+ frame-number = <5>;
|
||||
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg = <0x0b127000 0x1000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ frame@b128000 {
|
||||
+ frame-number = <6>;
|
||||
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ reg = <0x0b128000 0x1000>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+ };
|
||||
+ };
|
||||
+};
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,39 @@
|
||||
From 0bb78c90f9a682277e73301e8325953d47ca6990 Mon Sep 17 00:00:00 2001
|
||||
From: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
Date: Mon, 28 Sep 2020 10:45:40 +0530
|
||||
Subject: [PATCH 7/7] arm64: defconfig: Enable IPQ5018 SoC base configs
|
||||
|
||||
Enables clk & pinctrl related configs
|
||||
|
||||
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
|
||||
|
||||
Pick from <1601270140-4306-8-git-send-email-varada@codeaurora.org>
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
arch/arm64/configs/defconfig | 2 ++
|
||||
1 file changed, 2 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
|
||||
index c9a867ac32d4..dd04f9414c4d 100644
|
||||
--- a/arch/arm64/configs/defconfig
|
||||
+++ b/arch/arm64/configs/defconfig
|
||||
@@ -401,6 +401,7 @@ CONFIG_PINCTRL_IMX8MM=y
|
||||
CONFIG_PINCTRL_IMX8QXP=y
|
||||
CONFIG_PINCTRL_IMX8DXL=y
|
||||
CONFIG_PINCTRL_MSM=y
|
||||
+CONFIG_PINCTRL_IPQ5018=y
|
||||
CONFIG_PINCTRL_IPQ8074=y
|
||||
CONFIG_PINCTRL_IPQ6018=y
|
||||
CONFIG_PINCTRL_MSM8916=y
|
||||
@@ -702,6 +703,7 @@ CONFIG_QCOM_A53PLL=y
|
||||
CONFIG_QCOM_CLK_APCS_MSM8916=y
|
||||
CONFIG_QCOM_CLK_SMD_RPM=y
|
||||
CONFIG_QCOM_CLK_RPMH=y
|
||||
+CONFIG_IPQ_GCC_5018=y
|
||||
CONFIG_IPQ_GCC_8074=y
|
||||
CONFIG_IPQ_GCC_6018=y
|
||||
CONFIG_MSM_GCC_8916=y
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,30 @@
|
||||
From 7c7f17c89b150040be98b754c201221294378f8d Mon Sep 17 00:00:00 2001
|
||||
From: hzy <hzyitc@outlook.com>
|
||||
Date: Tue, 7 Mar 2023 07:32:05 +0000
|
||||
Subject: [PATCH 1/2] arm64: dts: qcom: ipq5018: Add scm node
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
index 487cc15da457..fdfa0f25c52b 100644
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -65,6 +65,12 @@
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
+ firmware {
|
||||
+ scm {
|
||||
+ compatible = "qcom,scm";
|
||||
+ };
|
||||
+ };
|
||||
+
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,25 @@
|
||||
From 6f376e7ce60d9043579f78e4e7fd820651bbe144 Mon Sep 17 00:00:00 2001
|
||||
From: hzy <hzyitc@outlook.com>
|
||||
Date: Tue, 7 Mar 2023 07:36:50 +0000
|
||||
Subject: [PATCH 2/2] arm64: Kconfig: enable qcom scm
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
arch/arm64/Kconfig.platforms | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
|
||||
index 90202e5608d1..c1d672bb8c83 100644
|
||||
--- a/arch/arm64/Kconfig.platforms
|
||||
+++ b/arch/arm64/Kconfig.platforms
|
||||
@@ -184,6 +184,7 @@ config ARCH_QCOM
|
||||
bool "Qualcomm Platforms"
|
||||
select GPIOLIB
|
||||
select PINCTRL
|
||||
+ select QCOM_SCM
|
||||
help
|
||||
This enables support for the ARMv8 based Qualcomm chipsets.
|
||||
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,60 @@
|
||||
From 83a1c64c1234193aacea56c5857afa6adf5507a7 Mon Sep 17 00:00:00 2001
|
||||
From: hzy <hzyitc@outlook.com>
|
||||
Date: Tue, 7 Mar 2023 09:24:22 +0000
|
||||
Subject: [PATCH 1/2] firmware: qcom_scm: Disable SDI
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
drivers/firmware/qcom_scm.c | 16 ++++++++++++++++
|
||||
drivers/firmware/qcom_scm.h | 1 +
|
||||
2 files changed, 17 insertions(+)
|
||||
|
||||
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
|
||||
index 70fe261c0cd8..a85466cfda58 100644
|
||||
--- a/drivers/firmware/qcom_scm.c
|
||||
+++ b/drivers/firmware/qcom_scm.c
|
||||
@@ -360,6 +360,20 @@ void qcom_scm_cpu_power_down(u32 flags)
|
||||
}
|
||||
EXPORT_SYMBOL(qcom_scm_cpu_power_down);
|
||||
|
||||
+static int qcom_scm_disable_sdi(void)
|
||||
+{
|
||||
+ struct qcom_scm_desc desc = {
|
||||
+ .svc = QCOM_SCM_SVC_BOOT,
|
||||
+ .cmd = QCOM_SCM_BOOT_DISABLE_SDI,
|
||||
+ .arginfo = QCOM_SCM_ARGS(2),
|
||||
+ .args[0] = 1, /* Disable wdog debug */
|
||||
+ .args[1] = 0, /* SDI Enable */
|
||||
+ .owner = ARM_SMCCC_OWNER_SIP,
|
||||
+ };
|
||||
+
|
||||
+ return qcom_scm_call(__scm->dev, &desc, NULL);
|
||||
+}
|
||||
+
|
||||
int qcom_scm_set_remote_state(u32 state, u32 id)
|
||||
{
|
||||
struct qcom_scm_desc desc = {
|
||||
@@ -1322,6 +1322,8 @@ static int qcom_scm_probe(struct platform_device *pdev)
|
||||
|
||||
__get_convention();
|
||||
|
||||
+ qcom_scm_disable_sdi();
|
||||
+
|
||||
/*
|
||||
* If requested enable "download mode", from this point on warmboot
|
||||
* will cause the the boot stages to enter download mode, unless
|
||||
diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h
|
||||
index 428da03635f0..343ba3a470b5 100644
|
||||
--- a/drivers/firmware/qcom_scm.h
|
||||
+++ b/drivers/firmware/qcom_scm.h
|
||||
@@ -74,6 +74,7 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
|
||||
#define QCOM_SCM_SVC_BOOT 0x01
|
||||
#define QCOM_SCM_BOOT_SET_ADDR 0x01
|
||||
#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
|
||||
+#define QCOM_SCM_BOOT_DISABLE_SDI 0x09
|
||||
#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
|
||||
#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
|
||||
#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,37 @@
|
||||
From 3e4c7ccd6acfe21232df62d3fb663e7f8b5a8b02 Mon Sep 17 00:00:00 2001
|
||||
From: hzy <hzyitc@outlook.com>
|
||||
Date: Tue, 7 Mar 2023 07:34:31 +0000
|
||||
Subject: [PATCH 2/2] arm64: dts: qcom: ipq5018: set download mode
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 6 ++++++
|
||||
1 file changed, 6 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
index fdfa0f25c52b..668a931c892e 100644
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -68,6 +68,7 @@
|
||||
firmware {
|
||||
scm {
|
||||
compatible = "qcom,scm";
|
||||
+ qcom,dload-mode = <&tcsr_boot_misc 0>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -116,6 +117,11 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
+ tcsr_boot_misc: syscon@193d100 {
|
||||
+ compatible = "syscon";
|
||||
+ reg = <0x0193d100 0x4>;
|
||||
+ };
|
||||
+
|
||||
blsp1_uart1: serial@78af000 {
|
||||
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
|
||||
reg = <0x078af000 0x200>;
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,42 @@
|
||||
From dd355a413cad48f795a6187a79b10f37ad1e59bd Mon Sep 17 00:00:00 2001
|
||||
From: hzy <hzyitc@outlook.com>
|
||||
Date: Thu, 2 Mar 2023 17:04:24 +0000
|
||||
Subject: [PATCH 1/2] ARM: mach-qcom: Add support for IPQ50xx
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
arch/arm/Makefile | 1 +
|
||||
arch/arm/mach-qcom/Kconfig | 5 +++++
|
||||
2 files changed, 6 insertions(+)
|
||||
|
||||
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
|
||||
index 4f098edfbf20..23aff930c2de 100644
|
||||
--- a/arch/arm/Makefile
|
||||
+++ b/arch/arm/Makefile
|
||||
@@ -152,6 +152,7 @@ textofs-$(CONFIG_PM_H1940) := 0x00108000
|
||||
textofs-$(CONFIG_SA1111) := 0x00208000
|
||||
endif
|
||||
textofs-$(CONFIG_ARCH_IPQ40XX) := 0x00208000
|
||||
+textofs-$(CONFIG_ARCH_IPQ50XX) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
|
||||
textofs-$(CONFIG_ARCH_MESON) := 0x00208000
|
||||
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
|
||||
index ecbf3c4eb878..9870d1b1f604 100644
|
||||
--- a/arch/arm/mach-qcom/Kconfig
|
||||
+++ b/arch/arm/mach-qcom/Kconfig
|
||||
@@ -12,6 +12,11 @@ menuconfig ARCH_QCOM
|
||||
select CLKSRC_QCOM
|
||||
select HAVE_ARM_ARCH_TIMER
|
||||
|
||||
+config ARCH_IPQ50XX
|
||||
+ bool "Enable support for IPQ50XX"
|
||||
+ select CLKSRC_QCOM
|
||||
+ select HAVE_ARM_ARCH_TIMER
|
||||
+
|
||||
config ARCH_MSM8X60
|
||||
bool "Enable support for MSM8X60"
|
||||
select CLKSRC_QCOM
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,52 @@
|
||||
From 206c1e12a3836ce6863b259bd3273863af195586 Mon Sep 17 00:00:00 2001
|
||||
From: hzy <hzyitc@outlook.com>
|
||||
Date: Thu, 2 Mar 2023 17:04:24 +0000
|
||||
Subject: [PATCH 2/2] arm: dts: qcom: Add ipq5018 support
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
arch/arm/boot/dts/Makefile | 1 +
|
||||
arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts | 4 ++++
|
||||
arch/arm/boot/dts/qcom-ipq5018.dtsi | 7 +++++++
|
||||
3 files changed, 12 insertions(+)
|
||||
create mode 100644 arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts
|
||||
create mode 100644 arch/arm/boot/dts/qcom-ipq5018.dtsi
|
||||
|
||||
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
|
||||
index b21b3a64641a..6f88cb1c5d84 100644
|
||||
--- a/arch/arm/boot/dts/Makefile
|
||||
+++ b/arch/arm/boot/dts/Makefile
|
||||
@@ -842,6 +842,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
|
||||
qcom-ipq4019-ap.dk04.1-c3.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c1.dtb \
|
||||
qcom-ipq4019-ap.dk07.1-c2.dtb \
|
||||
+ qcom-ipq5018-mp03.1-c2.dtb \
|
||||
qcom-ipq8064-ap148.dtb \
|
||||
qcom-ipq8064-rb3011.dtb \
|
||||
qcom-msm8226-samsung-s3ve3g.dtb \
|
||||
diff --git a/arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts b/arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts
|
||||
new file mode 100644
|
||||
index 000000000000..361695870ed6
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq5018-mp03.1-c2.dts
|
||||
@@ -0,0 +1,4 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0+
|
||||
+
|
||||
+#include "../../../arm64/boot/dts/qcom/ipq5018-mp03.1-c2.dts"
|
||||
+#include "qcom-ipq5018.dtsi"
|
||||
diff --git a/arch/arm/boot/dts/qcom-ipq5018.dtsi b/arch/arm/boot/dts/qcom-ipq5018.dtsi
|
||||
new file mode 100644
|
||||
index 000000000000..b14bd7558d3b
|
||||
--- /dev/null
|
||||
+++ b/arch/arm/boot/dts/qcom-ipq5018.dtsi
|
||||
@@ -0,0 +1,7 @@
|
||||
+// SPDX-License-Identifier: GPL-2.0
|
||||
+
|
||||
+/ {
|
||||
+ pmu {
|
||||
+ compatible = "arm,cortex-a7-pmu";
|
||||
+ };
|
||||
+};
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,51 @@
|
||||
From 8f98c5c71e78abddd533d5e65a9bbb20365b30e7 Mon Sep 17 00:00:00 2001
|
||||
From: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
|
||||
Date: Thu, 12 Mar 2020 14:19:16 +0530
|
||||
Subject: [PATCH 1/7] mtd: nand: qcom: use the ecc strength from device
|
||||
parameter
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
Currently the driver uses the ECC strength specified in
|
||||
device tree. The ONFI or JEDEC device parameter page
|
||||
contains the ‘ECC correctability’ field which indicates the
|
||||
number of bits that the host should be able to correct per
|
||||
512 bytes of data. The NAND base layer reads this parameter
|
||||
during device scan time. Since QPIC NAND controller supports
|
||||
8 bit ECC and same board can have different ECC strength
|
||||
devices, so device ECC strength can be used.
|
||||
|
||||
Change-Id: I4924ed4a3a0db56a217aabd0b7e7699078b4e7d5
|
||||
Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
|
||||
(cherry picked from commit f9b2c1442788f6cb9652c79557c9795faefe3513)
|
||||
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
|
||||
|
||||
Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/43a13a5bf504b9d09ac703d67c1b85934ef758e1
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/qcom_nandc.c | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
index 5af3bef6c230..673468d35d28 100644
|
||||
--- a/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
@@ -2477,6 +2477,13 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
|
||||
wide_bus = chip->options & NAND_BUSWIDTH_16 ? true : false;
|
||||
cwperpage = mtd->writesize / NANDC_STEP_SIZE;
|
||||
|
||||
+ /*
|
||||
+ * Read the required ecc strength from NAND device and overwrite the
|
||||
+ * device tree ecc strength
|
||||
+ */
|
||||
+ if (chip->base.ecc.requirements.strength >= 8)
|
||||
+ ecc->strength = 8;
|
||||
+
|
||||
/*
|
||||
* Each CW has 4 available OOB bytes which will be protected with ECC
|
||||
* so remaining bytes can be used for ECC.
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,37 @@
|
||||
From da56d8fc20c95ece57600126c8e7bc14d7a5e8c2 Mon Sep 17 00:00:00 2001
|
||||
From: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
|
||||
Date: Thu, 28 May 2020 11:24:49 +0530
|
||||
Subject: [PATCH 2/7] mtd: nand: ipq: add compatible used in linux older
|
||||
version
|
||||
|
||||
Added compatible string which was used in the NAND driver of linux
|
||||
older version. So that u-boot can work with linux-5.4 without any changes.
|
||||
|
||||
Signed-off-by: Rajkumar Ayyasamy <arajkuma@codeaurora.org>
|
||||
Change-Id: I2437cc37de9646fbf61864b6a328c914a6f677a7
|
||||
|
||||
Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/cd490bba1bbab70c69e7e8b6e8a5e026a7bd18bf
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/qcom_nandc.c | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
index 673468d35d28..375ae6a2d799 100644
|
||||
--- a/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
@@ -3042,6 +3042,10 @@ static const struct of_device_id qcom_nandc_of_match[] = {
|
||||
.compatible = "qcom,ipq8074-nand",
|
||||
.data = &ipq8074_nandc_props,
|
||||
},
|
||||
+ {
|
||||
+ .compatible = "qcom,ebi2-nandc-bam-v1.5.0",
|
||||
+ .data = &ipq8074_nandc_props,
|
||||
+ },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,397 @@
|
||||
From 64cb8eaaa6b3f987d5e8126278f6f829d252d4e8 Mon Sep 17 00:00:00 2001
|
||||
From: Md Sadre Alam <mdalam@codeaurora.org>
|
||||
Date: Wed, 8 Jul 2020 10:40:59 +0530
|
||||
Subject: [PATCH 3/7] mtd: rawnand: qcom: Add initial support for qspi nand
|
||||
|
||||
This change will add initial support for qspi (serial nand).
|
||||
|
||||
QPIC Version v.2.0 onwards supports serial nand as well so this
|
||||
change will initialize all required register to enable qspi (serial
|
||||
nand).
|
||||
|
||||
This change is supporting very basic functionality of qspi nand flash.
|
||||
|
||||
1. Reset device (Reset QSPI NAND device).
|
||||
|
||||
2. Device detection (Read id QSPI NAND device).
|
||||
|
||||
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
|
||||
Change-Id: I5f29df80bcb8e58a1938eced1a8d88c237aceb1d
|
||||
|
||||
Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/dbd01aa96d9d5bf5978e3c6ef2a4118ce7cc0bba
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/nand_ids.c | 13 +++
|
||||
drivers/mtd/nand/raw/qcom_nandc.c | 168 ++++++++++++++++++++++++++++--
|
||||
2 files changed, 171 insertions(+), 10 deletions(-)
|
||||
|
||||
diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
|
||||
index ba27902fc54b..03e472055d9e 100644
|
||||
--- a/drivers/mtd/nand/raw/nand_ids.c
|
||||
+++ b/drivers/mtd/nand/raw/nand_ids.c
|
||||
@@ -53,6 +53,19 @@ struct nand_flash_dev nand_flash_ids[] = {
|
||||
SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
|
||||
NAND_ECC_INFO(40, SZ_1K), 4 },
|
||||
|
||||
+ {"GD5F1GQ4RE9IG SPI NAND 1G 1.8V 4-bit",
|
||||
+ { .id = {0xc8, 0xc1} },
|
||||
+ SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) },
|
||||
+ {"GD5F1GQ4RE9IH SPI NAND 1G 1.8V 4-bit",
|
||||
+ { .id = {0xc8, 0xc9} },
|
||||
+ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) },
|
||||
+ {"GD5F2GQ5REYIH SPI NAND 2G 4-bit",
|
||||
+ { .id = {0xc8, 0x22} },
|
||||
+ SZ_2K, SZ_256, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) },
|
||||
+ {"MT29F1G01ABBFDWB-IT SPI NAND 1G 1.8V 4-bit",
|
||||
+ { .id = {0x2c, 0x15} },
|
||||
+ SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) },
|
||||
+
|
||||
LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
|
||||
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
index 375ae6a2d799..361ee116422f 100644
|
||||
--- a/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
@@ -35,22 +35,33 @@
|
||||
#define NAND_DEV_CMD1 0xa4
|
||||
#define NAND_DEV_CMD2 0xa8
|
||||
#define NAND_DEV_CMD_VLD 0xac
|
||||
+#define NAND_DEV_CMD7 0xb0
|
||||
+#define NAND_DEV_CMD8 0xb4
|
||||
+#define NAND_DEV_CMD9 0xb8
|
||||
+#define NAND_FLASH_SPI_CFG 0xc0
|
||||
+#define NAND_SPI_NUM_ADDR_CYCLES 0xc4
|
||||
+#define NAND_SPI_BUSY_CHECK_WAIT_CNT 0xc8
|
||||
+#define NAND_DEV_CMD3 0xd0
|
||||
+#define NAND_DEV_CMD4 0xd4
|
||||
+#define NAND_DEV_CMD5 0xd8
|
||||
+#define NAND_DEV_CMD6 0xdc
|
||||
#define SFLASHC_BURST_CFG 0xe0
|
||||
#define NAND_ERASED_CW_DETECT_CFG 0xe8
|
||||
#define NAND_ERASED_CW_DETECT_STATUS 0xec
|
||||
#define NAND_EBI2_ECC_BUF_CFG 0xf0
|
||||
#define FLASH_BUF_ACC 0x100
|
||||
-
|
||||
#define NAND_CTRL 0xf00
|
||||
#define NAND_VERSION 0xf08
|
||||
#define NAND_READ_LOCATION_0 0xf20
|
||||
#define NAND_READ_LOCATION_1 0xf24
|
||||
#define NAND_READ_LOCATION_2 0xf28
|
||||
#define NAND_READ_LOCATION_3 0xf2c
|
||||
#define NAND_READ_LOCATION_LAST_CW_0 0xf40
|
||||
#define NAND_READ_LOCATION_LAST_CW_1 0xf44
|
||||
#define NAND_READ_LOCATION_LAST_CW_2 0xf48
|
||||
#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
|
||||
+#define NAND_QSPI_MSTR_CONFIG 0xf60
|
||||
+
|
||||
|
||||
/* dummy register offsets, used by write_reg_dma */
|
||||
#define NAND_DEV_CMD1_RESTORE 0xdead
|
||||
@@ -179,6 +194,28 @@
|
||||
#define ECC_BCH_4BIT BIT(2)
|
||||
#define ECC_BCH_8BIT BIT(3)
|
||||
|
||||
+/* QSPI NAND config reg bits */
|
||||
+#define LOAD_CLK_CNTR_INIT_EN (1 << 28)
|
||||
+#define CLK_CNTR_INIT_VAL_VEC 0x924
|
||||
+#define FEA_STATUS_DEV_ADDR 0xc0
|
||||
+#define SPI_CFG (1 << 0)
|
||||
+
|
||||
+/* CMD register value for qspi nand */
|
||||
+#define CMD0_VAL 0x1080D8D8
|
||||
+#define CMD1_VAL 0xF00F3000
|
||||
+#define CMD2_VAL 0xF0FF709F
|
||||
+#define CMD3_VAL 0x3F310015
|
||||
+#define CMD7_VAL 0x04061F0F
|
||||
+#define CMD_VLD_VAL 0xd
|
||||
+#define SPI_NUM_ADDR 0xDA4DB
|
||||
+#define WAIT_CNT 0x10
|
||||
+
|
||||
+/* QSPI NAND CMD reg bits value */
|
||||
+#define SPI_WP (1 << 28)
|
||||
+#define SPI_HOLD (1 << 27)
|
||||
+#define SPI_TRANSFER_MODE_x1 (1 << 29)
|
||||
+#define SPI_TRANSFER_MODE_x4 (3 << 29)
|
||||
+
|
||||
#define nandc_set_read_loc_first(chip, reg, cw_offset, read_size, is_last_read_loc) \
|
||||
nandc_set_reg(chip, reg, \
|
||||
((cw_offset) << READ_LOCATION_OFFSET) | \
|
||||
@@ -314,6 +351,9 @@ struct nandc_regs {
|
||||
__le32 read_location_last1;
|
||||
__le32 read_location_last2;
|
||||
__le32 read_location_last3;
|
||||
+ __le32 spi_cfg;
|
||||
+ __le32 num_addr_cycle;
|
||||
+ __le32 busy_wait_cnt;
|
||||
|
||||
__le32 erased_cw_detect_cfg_clr;
|
||||
__le32 erased_cw_detect_cfg_set;
|
||||
@@ -367,6 +407,7 @@ struct qcom_nand_controller {
|
||||
|
||||
struct clk *core_clk;
|
||||
struct clk *aon_clk;
|
||||
+ struct clk *iomacro_clk;
|
||||
|
||||
union {
|
||||
/* will be used only by QPIC for BAM DMA */
|
||||
@@ -460,13 +501,15 @@ struct qcom_nand_host {
|
||||
* @is_qpic - whether NAND CTRL is part of qpic IP
|
||||
* @qpic_v2 - flag to indicate QPIC IP version 2
|
||||
* @dev_cmd_reg_start - NAND_DEV_CMD_* registers starting offset
|
||||
+ * @is_serial_nand - QSPI nand flag, whether QPIC support serial nand or not
|
||||
*/
|
||||
struct qcom_nandc_props {
|
||||
u32 ecc_modes;
|
||||
bool is_bam;
|
||||
bool is_qpic;
|
||||
bool qpic_v2;
|
||||
u32 dev_cmd_reg_start;
|
||||
+ bool is_serial_nand;
|
||||
};
|
||||
|
||||
/* Frees the BAM transaction memory */
|
||||
@@ -640,6 +683,12 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
|
||||
return ®s->read_location_last2;
|
||||
case NAND_READ_LOCATION_LAST_CW_3:
|
||||
return ®s->read_location_last3;
|
||||
+ case NAND_FLASH_SPI_CFG:
|
||||
+ return ®s->spi_cfg;
|
||||
+ case NAND_SPI_NUM_ADDR_CYCLES:
|
||||
+ return ®s->num_addr_cycle;
|
||||
+ case NAND_SPI_BUSY_CHECK_WAIT_CNT:
|
||||
+ return ®s->busy_wait_cnt;
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
@@ -1244,11 +1293,23 @@ static int read_id(struct qcom_nand_host *host, int column)
|
||||
{
|
||||
struct nand_chip *chip = &host->chip;
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
+ u32 cmd = OP_FETCH_ID;
|
||||
|
||||
if (column == -1)
|
||||
return 0;
|
||||
|
||||
- nandc_set_reg(chip, NAND_FLASH_CMD, OP_FETCH_ID);
|
||||
+ if (nandc->props->is_serial_nand) {
|
||||
+ cmd |= (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1);
|
||||
+ /* For spi nand read 2-bytes id only
|
||||
+ * else if nandc->buf_count == 4; then the id value
|
||||
+ * will repeat and the SLC device will be detect as MLC.
|
||||
+ * by nand base layer
|
||||
+ * so overwrite the nandc->buf_count == 2;
|
||||
+ */
|
||||
+ nandc->buf_count = 2;
|
||||
+ }
|
||||
+
|
||||
+ nandc_set_reg(chip, NAND_FLASH_CMD, cmd);
|
||||
nandc_set_reg(chip, NAND_ADDR0, column);
|
||||
nandc_set_reg(chip, NAND_ADDR1, 0);
|
||||
nandc_set_reg(chip, NAND_FLASH_CHIP_SELECT,
|
||||
@@ -1268,8 +1329,13 @@ static int reset(struct qcom_nand_host *host)
|
||||
{
|
||||
struct nand_chip *chip = &host->chip;
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
+ int cmd_rst;
|
||||
+
|
||||
+ cmd_rst = OP_RESET_DEVICE;
|
||||
+ if (nandc->props->is_serial_nand)
|
||||
+ cmd_rst |= (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1);
|
||||
|
||||
- nandc_set_reg(chip, NAND_FLASH_CMD, OP_RESET_DEVICE);
|
||||
+ nandc_set_reg(chip, NAND_FLASH_CMD, cmd_rst);
|
||||
nandc_set_reg(chip, NAND_EXEC_CMD, 1);
|
||||
|
||||
write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
|
||||
@@ -2471,6 +2537,8 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
|
||||
int cwperpage, bad_block_byte, ret;
|
||||
bool wide_bus;
|
||||
int ecc_mode = 1;
|
||||
+ int num_addr_cycle = 5, dsbl_sts_aftr_write = 0;
|
||||
+ int wr_rd_bsy_gap = 2, recovery_cycle = 7;
|
||||
|
||||
/* controller only supports 512 bytes data steps */
|
||||
ecc->size = NANDC_STEP_SIZE;
|
||||
@@ -2579,33 +2647,43 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
|
||||
host->cw_size = host->cw_data + ecc->bytes;
|
||||
bad_block_byte = mtd->writesize - host->cw_size * (cwperpage - 1) + 1;
|
||||
|
||||
+ /* For QSPI serial nand QPIC config register value got changed
|
||||
+ * so configure the new value for qspi serial nand
|
||||
+ */
|
||||
+ if (nandc->props->is_serial_nand) {
|
||||
+ num_addr_cycle = 3;
|
||||
+ dsbl_sts_aftr_write = 1;
|
||||
+ wr_rd_bsy_gap = 20;
|
||||
+ recovery_cycle = 0;
|
||||
+ }
|
||||
+
|
||||
host->cfg0 = (cwperpage - 1) << CW_PER_PAGE
|
||||
| host->cw_data << UD_SIZE_BYTES
|
||||
- | 0 << DISABLE_STATUS_AFTER_WRITE
|
||||
- | 5 << NUM_ADDR_CYCLES
|
||||
+ | dsbl_sts_aftr_write << DISABLE_STATUS_AFTER_WRITE
|
||||
+ | num_addr_cycle << NUM_ADDR_CYCLES
|
||||
| host->ecc_bytes_hw << ECC_PARITY_SIZE_BYTES_RS
|
||||
| 0 << STATUS_BFR_READ
|
||||
| 1 << SET_RD_MODE_AFTER_STATUS
|
||||
| host->spare_bytes << SPARE_SIZE_BYTES;
|
||||
|
||||
- host->cfg1 = 7 << NAND_RECOVERY_CYCLES
|
||||
+ host->cfg1 = recovery_cycle << NAND_RECOVERY_CYCLES
|
||||
| 0 << CS_ACTIVE_BSY
|
||||
| bad_block_byte << BAD_BLOCK_BYTE_NUM
|
||||
| 0 << BAD_BLOCK_IN_SPARE_AREA
|
||||
- | 2 << WR_RD_BSY_GAP
|
||||
+ | wr_rd_bsy_gap << WR_RD_BSY_GAP
|
||||
| wide_bus << WIDE_FLASH
|
||||
| host->bch_enabled << ENABLE_BCH_ECC;
|
||||
|
||||
host->cfg0_raw = (cwperpage - 1) << CW_PER_PAGE
|
||||
| host->cw_size << UD_SIZE_BYTES
|
||||
- | 5 << NUM_ADDR_CYCLES
|
||||
+ | num_addr_cycle << NUM_ADDR_CYCLES
|
||||
| 0 << SPARE_SIZE_BYTES;
|
||||
|
||||
- host->cfg1_raw = 7 << NAND_RECOVERY_CYCLES
|
||||
+ host->cfg1_raw = recovery_cycle << NAND_RECOVERY_CYCLES
|
||||
| 0 << CS_ACTIVE_BSY
|
||||
| 17 << BAD_BLOCK_BYTE_NUM
|
||||
| 1 << BAD_BLOCK_IN_SPARE_AREA
|
||||
- | 2 << WR_RD_BSY_GAP
|
||||
+ | wr_rd_bsy_gap << WR_RD_BSY_GAP
|
||||
| wide_bus << WIDE_FLASH
|
||||
| 1 << DEV0_CFG1_ECC_DISABLE;
|
||||
|
||||
@@ -2781,6 +2859,47 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
+static void qspi_write_reg_bam(struct qcom_nand_controller *nandc,
|
||||
+ unsigned int val, unsigned int reg)
|
||||
+{
|
||||
+ int ret;
|
||||
+
|
||||
+ clear_bam_transaction(nandc);
|
||||
+ nandc_set_reg(chip, reg, val);
|
||||
+ write_reg_dma(nandc, reg, 1, NAND_BAM_NEXT_SGL);
|
||||
+
|
||||
+ ret = submit_descs(nandc);
|
||||
+ if (ret)
|
||||
+ dev_err(nandc->dev, "Error in submitting descriptor to write config reg\n");
|
||||
+ free_descs(nandc);
|
||||
+}
|
||||
+
|
||||
+static void qspi_nand_init(struct qcom_nand_controller *nandc)
|
||||
+{
|
||||
+ u32 spi_cfg_val = 0x0;
|
||||
+ u32 reg = 0x0;
|
||||
+
|
||||
+ spi_cfg_val |= (LOAD_CLK_CNTR_INIT_EN | CLK_CNTR_INIT_VAL_VEC
|
||||
+ | FEA_STATUS_DEV_ADDR | SPI_CFG);
|
||||
+
|
||||
+ qspi_write_reg_bam(nandc, 0x0, NAND_FLASH_SPI_CFG);
|
||||
+ qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG);
|
||||
+ spi_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
|
||||
+ qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG);
|
||||
+
|
||||
+ reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD0);
|
||||
+ nandc_write(nandc, reg, CMD0_VAL);
|
||||
+ nandc_write(nandc, reg + 4, CMD1_VAL);
|
||||
+ nandc_write(nandc, reg + 8, CMD2_VAL);
|
||||
+ nandc_write(nandc, reg + 12, CMD_VLD_VAL);
|
||||
+ nandc_write(nandc, reg + 16, CMD7_VAL);
|
||||
+ reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD3);
|
||||
+ nandc_write(nandc, reg, CMD3_VAL);
|
||||
+
|
||||
+ qspi_write_reg_bam(nandc, SPI_NUM_ADDR, NAND_SPI_NUM_ADDR_CYCLES);
|
||||
+ qspi_write_reg_bam(nandc, WAIT_CNT, NAND_SPI_BUSY_CHECK_WAIT_CNT);
|
||||
+}
|
||||
+
|
||||
static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
|
||||
struct qcom_nand_host *host,
|
||||
struct device_node *dn)
|
||||
@@ -2830,6 +2949,9 @@ static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
|
||||
/* set up initial status value */
|
||||
host->status = NAND_STATUS_READY | NAND_STATUS_WP;
|
||||
|
||||
+ if (nandc->props->is_serial_nand)
|
||||
+ qspi_nand_init(nandc);
|
||||
+
|
||||
ret = nand_scan(chip, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -2934,6 +3056,12 @@ static int qcom_nandc_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(nandc->aon_clk))
|
||||
return PTR_ERR(nandc->aon_clk);
|
||||
|
||||
+ if (nandc->props->is_serial_nand) {
|
||||
+ nandc->iomacro_clk = devm_clk_get(dev, "io_macro");
|
||||
+ if (IS_ERR(nandc->iomacro_clk))
|
||||
+ return PTR_ERR(nandc->iomacro_clk);
|
||||
+ }
|
||||
+
|
||||
ret = qcom_nandc_parse_dt(pdev);
|
||||
if (ret)
|
||||
return ret;
|
||||
@@ -2962,6 +3090,12 @@ static int qcom_nandc_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
goto err_nandc_alloc;
|
||||
|
||||
+ if (nandc->props->is_serial_nand) {
|
||||
+ ret = clk_prepare_enable(nandc->iomacro_clk);
|
||||
+ if (ret)
|
||||
+ goto err_setup;
|
||||
+ }
|
||||
+
|
||||
ret = qcom_nandc_setup(nandc);
|
||||
if (ret)
|
||||
goto err_setup;
|
||||
@@ -3009,6 +3143,7 @@ static const struct qcom_nandc_props ipq806x_nandc_props = {
|
||||
.ecc_modes = (ECC_RS_4BIT | ECC_BCH_8BIT),
|
||||
.is_bam = false,
|
||||
.dev_cmd_reg_start = 0x0,
|
||||
+ .is_serial_nand = false,
|
||||
};
|
||||
|
||||
static const struct qcom_nandc_props ipq4019_nandc_props = {
|
||||
@@ -3016,6 +3151,7 @@ static const struct qcom_nandc_props ipq4019_nandc_props = {
|
||||
.is_bam = true,
|
||||
.is_qpic = true,
|
||||
.dev_cmd_reg_start = 0x0,
|
||||
+ .is_serial_nand = false,
|
||||
};
|
||||
|
||||
static const struct qcom_nandc_props ipq8074_nandc_props = {
|
||||
@@ -3023,6 +3159,15 @@ static const struct qcom_nandc_props ipq8074_nandc_props = {
|
||||
.is_bam = true,
|
||||
.is_qpic = true,
|
||||
.dev_cmd_reg_start = 0x7000,
|
||||
+ .is_serial_nand = false,
|
||||
+};
|
||||
+
|
||||
+static const struct qcom_nandc_props ipq5018_nandc_props = {
|
||||
+ .ecc_modes = (ECC_BCH_4BIT | ECC_BCH_8BIT),
|
||||
+ .is_bam = true,
|
||||
+ .qpic_v2 = true,
|
||||
+ .dev_cmd_reg_start = 0x7000,
|
||||
+ .is_serial_nand = true,
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -3046,6 +3190,10 @@ static const struct of_device_id qcom_nandc_of_match[] = {
|
||||
.compatible = "qcom,ebi2-nandc-bam-v1.5.0",
|
||||
.data = &ipq8074_nandc_props,
|
||||
},
|
||||
+ {
|
||||
+ .compatible = "qcom,ebi2-nandc-bam-v2.1.1",
|
||||
+ .data = &ipq5018_nandc_props,
|
||||
+ },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, qcom_nandc_of_match);
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,60 @@
|
||||
From 13bae86b4d3ed01f885e111eda4224a2985ed9a4 Mon Sep 17 00:00:00 2001
|
||||
From: Md Sadre Alam <mdalam@codeaurora.org>
|
||||
Date: Tue, 21 Jul 2020 21:19:58 +0530
|
||||
Subject: [PATCH 4/7] mtd: rawnand: qcom: Read QPIC version
|
||||
|
||||
This change will add support to read QPIC version.
|
||||
QPIC version V2.0 onwards some new register introduced
|
||||
in QPIC. So based on hw_version we will update those
|
||||
register.
|
||||
|
||||
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
|
||||
Change-Id: Iadc95a12145e03b8edf0deb6537b819ad4baec22
|
||||
|
||||
Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/bfd90c9e9e90c0fa9150d25d2b2e6d4d321610f0
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/qcom_nandc.c | 12 ++++++++++++
|
||||
1 file changed, 12 insertions(+)
|
||||
|
||||
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
index 361ee116422f..e19074062348 100644
|
||||
--- a/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
@@ -442,6 +442,7 @@ struct qcom_nand_controller {
|
||||
|
||||
u32 cmd1, vld;
|
||||
const struct qcom_nandc_props *props;
|
||||
+ u32 hw_version;
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -2539,6 +2540,7 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
|
||||
int ecc_mode = 1;
|
||||
int num_addr_cycle = 5, dsbl_sts_aftr_write = 0;
|
||||
int wr_rd_bsy_gap = 2, recovery_cycle = 7;
|
||||
+ u32 version_reg;
|
||||
|
||||
/* controller only supports 512 bytes data steps */
|
||||
ecc->size = NANDC_STEP_SIZE;
|
||||
@@ -2552,6 +2554,16 @@ static int qcom_nand_attach_chip(struct nand_chip *chip)
|
||||
if (chip->base.eccreq.strength >= 8)
|
||||
ecc->strength = 8;
|
||||
|
||||
+ /* Read QPIC version register */
|
||||
+ version_reg = (NAND_VERSION + 0x4000);
|
||||
+ nandc->hw_version = nandc_read(nandc, version_reg);
|
||||
+ pr_info("QPIC controller hw version Major:%d, Minor:%d\n",
|
||||
+ ((nandc->hw_version & NAND_VERSION_MAJOR_MASK)
|
||||
+ >> NAND_VERSION_MAJOR_SHIFT),
|
||||
+ ((nandc->hw_version & NAND_VERSION_MINOR_MASK)
|
||||
+ >> NAND_VERSION_MINOR_SHIFT));
|
||||
+ nandc->hw_version = ((nandc->hw_version & NAND_VERSION_MAJOR_MASK)
|
||||
+ >> NAND_VERSION_MAJOR_SHIFT);
|
||||
/*
|
||||
* Each CW has 4 available OOB bytes which will be protected with ECC
|
||||
* so remaining bytes can be used for ECC.
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,66 @@
|
||||
From a5ba59a246e3842ee997e4f2d1ac8cecc8be464c Mon Sep 17 00:00:00 2001
|
||||
From: Md Sadre Alam <mdalam@codeaurora.org>
|
||||
Date: Tue, 1 Sep 2020 11:28:09 +0530
|
||||
Subject: [PATCH 5/7] mtd: rawnand: qcom: Enable support for erase,read & write
|
||||
for serial nand.
|
||||
|
||||
This change will enable support for erase, read & write support for
|
||||
QSPI serial nand. In QPIC V2.0 onwards, to read last code word new
|
||||
regiater is introduced. So to read for first three code word we have to
|
||||
use LOCATION_n register and for last code word we ahve to use LAST_CW_n.
|
||||
|
||||
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
|
||||
Change-Id: Iafe34e238754dfc006363dd400a48cf9fc8d92d9
|
||||
|
||||
Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/17e85de9e7933a94461f76fe40a5b88334dfdad6
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/qcom_nandc.c | 97 ++++++++++++++++++++++++++-----
|
||||
1 file changed, 83 insertions(+), 14 deletions(-)
|
||||
|
||||
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
index e19074062348..0a6b67ddcda2 100644
|
||||
--- a/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
@@ -733,13 +752,18 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
u32 cmd, cfg0, cfg1, ecc_bch_cfg;
|
||||
|
||||
+ cmd = (PAGE_ACC | LAST_PAGE);
|
||||
+
|
||||
+ if (nandc->props->is_serial_nand)
|
||||
+ cmd |= (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD);
|
||||
+
|
||||
if (read) {
|
||||
if (host->use_ecc)
|
||||
- cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
|
||||
+ cmd |= OP_PAGE_READ_WITH_ECC;
|
||||
else
|
||||
- cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE;
|
||||
+ cmd |= OP_PAGE_READ;
|
||||
} else {
|
||||
- cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
|
||||
+ cmd |= OP_PROGRAM_PAGE;
|
||||
}
|
||||
|
||||
if (host->use_ecc) {
|
||||
@@ -1265,9 +1298,13 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
|
||||
{
|
||||
struct nand_chip *chip = &host->chip;
|
||||
struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
|
||||
+ u32 ers_cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE;
|
||||
|
||||
- nandc_set_reg(chip, NAND_FLASH_CMD,
|
||||
- OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
|
||||
+ if (nandc->props->is_serial_nand) {
|
||||
+ ers_cmd |= (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1);
|
||||
+ page_addr <<= 16;
|
||||
+ }
|
||||
+ nandc_set_reg(chip, NAND_FLASH_CMD, ers_cmd);
|
||||
nandc_set_reg(chip, NAND_ADDR0, page_addr);
|
||||
nandc_set_reg(chip, NAND_ADDR1, 0);
|
||||
nandc_set_reg(chip, NAND_DEV0_CFG0,
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,88 @@
|
||||
From 47e22e1fc494cd7f11043f80819665d7203effa7 Mon Sep 17 00:00:00 2001
|
||||
From: Md Sadre Alam <mdalam@codeaurora.org>
|
||||
Date: Wed, 30 Dec 2020 02:23:30 +0530
|
||||
Subject: [PATCH 6/7] mtd: rawnand: qcom: Update bits of
|
||||
QPIC_NAND_FLASH_SPI_CFG reg
|
||||
|
||||
This change will update bits of QPIC_NAND_FLASH_SPI_CFG register
|
||||
to select serial nand functionality in QPIC controller.
|
||||
|
||||
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
|
||||
Change-Id: I643bb47b37cc326783d57d6c0f13618f8e216a37
|
||||
|
||||
Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/468d4aa56157d9e742a9eb90fe29b1eeb0151b60
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/qcom_nandc.c | 17 +++++++++--------
|
||||
1 file changed, 9 insertions(+), 8 deletions(-)
|
||||
|
||||
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
index 0a6b67ddcda2..dc723a7ffa0e 100644
|
||||
--- a/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
|
||||
@@ -62,7 +62,6 @@
|
||||
#define NAND_READ_LOCATION_LAST_CW_3 0xf4c
|
||||
#define NAND_QSPI_MSTR_CONFIG 0xf60
|
||||
|
||||
-
|
||||
/* dummy register offsets, used by write_reg_dma */
|
||||
#define NAND_DEV_CMD1_RESTORE 0xdead
|
||||
#define NAND_DEV_CMD_VLD_RESTORE 0xbeef
|
||||
@@ -2781,21 +2859,6 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
|
||||
return 0;
|
||||
}
|
||||
|
||||
-static void qspi_write_reg_bam(struct qcom_nand_controller *nandc,
|
||||
- unsigned int val, unsigned int reg)
|
||||
-{
|
||||
- int ret;
|
||||
-
|
||||
- clear_bam_transaction(nandc);
|
||||
- nandc_set_reg(chip, reg, val);
|
||||
- write_reg_dma(nandc, reg, 1, NAND_BAM_NEXT_SGL);
|
||||
-
|
||||
- ret = submit_descs(nandc);
|
||||
- if (ret)
|
||||
- dev_err(nandc->dev, "Error in submitting descriptor to write config reg\n");
|
||||
- free_descs(nandc);
|
||||
-}
|
||||
-
|
||||
static void qspi_nand_init(struct qcom_nand_controller *nandc)
|
||||
{
|
||||
u32 spi_cfg_val = 0x0;
|
||||
@@ -2960,13 +2959,14 @@ static void qspi_nand_init(struct qcom_nand_controller *nandc)
|
||||
u32 spi_cfg_val = 0x0;
|
||||
u32 reg = 0x0;
|
||||
|
||||
- spi_cfg_val |= (LOAD_CLK_CNTR_INIT_EN | CLK_CNTR_INIT_VAL_VEC
|
||||
- | FEA_STATUS_DEV_ADDR | SPI_CFG);
|
||||
+ spi_cfg_val |= (LOAD_CLK_CNTR_INIT_EN | (CLK_CNTR_INIT_VAL_VEC << 16)
|
||||
+ | (FEA_STATUS_DEV_ADDR << 8) | SPI_CFG);
|
||||
|
||||
- qspi_write_reg_bam(nandc, 0x0, NAND_FLASH_SPI_CFG);
|
||||
- qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG);
|
||||
+ reg = dev_cmd_reg_addr(nandc, NAND_FLASH_SPI_CFG);
|
||||
+ nandc_write(nandc, reg, 0);
|
||||
+ nandc_write(nandc, reg, spi_cfg_val);
|
||||
spi_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
|
||||
- qspi_write_reg_bam(nandc, spi_cfg_val, NAND_FLASH_SPI_CFG);
|
||||
+ nandc_write(nandc, reg, spi_cfg_val);
|
||||
|
||||
reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD0);
|
||||
nandc_write(nandc, reg, CMD0_VAL);
|
||||
@@ -2977,8 +2977,9 @@ static void qspi_nand_init(struct qcom_nand_controller *nandc)
|
||||
reg = dev_cmd_reg_addr(nandc, NAND_DEV_CMD3);
|
||||
nandc_write(nandc, reg, CMD3_VAL);
|
||||
|
||||
- qspi_write_reg_bam(nandc, SPI_NUM_ADDR, NAND_SPI_NUM_ADDR_CYCLES);
|
||||
- qspi_write_reg_bam(nandc, WAIT_CNT, NAND_SPI_BUSY_CHECK_WAIT_CNT);
|
||||
+ reg = dev_cmd_reg_addr(nandc, NAND_SPI_NUM_ADDR_CYCLES);
|
||||
+ nandc_write(nandc, reg, SPI_NUM_ADDR);
|
||||
+ nandc_write(nandc, reg + 4, WAIT_CNT);
|
||||
}
|
||||
|
||||
static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc,
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,75 @@
|
||||
From 8963f2d66180d5002209b93cfdc1dca4b9c521e1 Mon Sep 17 00:00:00 2001
|
||||
From: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
|
||||
Date: Tue, 2 Nov 2021 17:30:11 +0530
|
||||
Subject: [PATCH 7/7] drivers: mtd: nand: add SPI NAND devices
|
||||
|
||||
This changes add the below given list of SPI NAND
|
||||
1. W25N01JW
|
||||
2. GD5F1GQ5REYIG
|
||||
3. F50D1G41LB
|
||||
4. GD5F4GQ6REYIHR
|
||||
5. W25N02JWZEIF
|
||||
6. MX35UF1GE4AC
|
||||
7. F50D2G41KA-83YIG2V
|
||||
8. DS35M1GA
|
||||
9. GD5F2GQ5REYIG
|
||||
|
||||
Change-Id: Ib8f669b86e8cb8a30462a868fb4bbc5606142bba
|
||||
Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
|
||||
|
||||
Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/d9b8a8fcc227d9da867dca22f9c6e9a1e690650d
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
drivers/mtd/nand/raw/nand_ids.c | 35 +++++++++++++++++++++++++++++++++
|
||||
1 file changed, 35 insertions(+)
|
||||
|
||||
diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
|
||||
index 03e472055d9e..b91ef498c9e3 100644
|
||||
--- a/drivers/mtd/nand/raw/nand_ids.c
|
||||
+++ b/drivers/mtd/nand/raw/nand_ids.c
|
||||
@@ -66,6 +66,41 @@ struct nand_flash_dev nand_flash_ids[] = {
|
||||
{ .id = {0x2c, 0x15} },
|
||||
SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) },
|
||||
|
||||
+ {"MX35UF4GE4AD-Z4I SPI NAND 1G 1.8V",
|
||||
+ { .id = {0xc2, 0xb7} },
|
||||
+ SZ_4K, SZ_512, SZ_256K, 0, 2, 256, NAND_ECC_INFO(8, SZ_512) },
|
||||
+ {"GD5F1GQ5REYIH SPI NAND 1G 1.8V",
|
||||
+ { .id = {0xc8, 0x21} },
|
||||
+ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) },
|
||||
+ {"W25N01JW SPI NAND 1.8V 1G-BIT",
|
||||
+ { .id = {0xef, 0xbc} },
|
||||
+ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) },
|
||||
+ {"GD5F1GQ5REYIG SPI NAND 1G",
|
||||
+ { .id = {0xc8, 0x41} },
|
||||
+ SZ_2K, SZ_128, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) },
|
||||
+ {"F50D1G41LB(2M) SPI NAND 1G 1.8V",
|
||||
+ { .id = {0xc8, 0x11} },
|
||||
+ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) },
|
||||
+ {"GD5F4GQ6REYIHR SPI NAND 4G 1.8V",
|
||||
+ { .id = {0xc8, 0x25} },
|
||||
+ SZ_2K, SZ_512, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) },
|
||||
+ {"W25N02JWZEIF SPI NAND 2G 1.8V",
|
||||
+ { .id = {0xef, 0xbf} },
|
||||
+ SZ_2K, SZ_256, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) },
|
||||
+ {"MX35UF1GE4AC SPI NAND 1G 1.8V",
|
||||
+ { .id = {0xc2, 0x92} },
|
||||
+ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) },
|
||||
+ {"F50D2G41KA-83YIG2V SPI NAND 2G 1.8V",
|
||||
+ { .id = {0xc8, 0x51} },
|
||||
+ SZ_2K, SZ_256, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) },
|
||||
+ {"DS35M1GA SPI NAND 1G 1.8V",
|
||||
+ { .id = {0xe5, 0x21} },
|
||||
+ SZ_2K, SZ_128, SZ_128K, 0, 2, 64, NAND_ECC_INFO(4, SZ_512) },
|
||||
+ {"GD5F2GQ5REYIG SPI NAND 2G",
|
||||
+ { .id = {0xc8, 0x42} },
|
||||
+ SZ_2K, SZ_256, SZ_128K, 0, 2, 128, NAND_ECC_INFO(8, SZ_512) },
|
||||
+
|
||||
+
|
||||
LEGACY_ID_NAND("NAND 4MiB 5V 8-bit", 0x6B, 4, SZ_8K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE3, 4, SZ_8K, SP_OPTIONS),
|
||||
LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xE5, 4, SZ_8K, SP_OPTIONS),
|
||||
--
|
||||
2.25.1
|
||||
|
||||
@ -0,0 +1,65 @@
|
||||
From 84f2d1697645ce75c61b4888ee397f272d3dd6b2 Mon Sep 17 00:00:00 2001
|
||||
From: hzy <hzyitc@outlook.com>
|
||||
Date: Fri, 10 Mar 2023 16:34:30 +0000
|
||||
Subject: [PATCH 1/1] arm64: dts: qcom: ipq5018: Add nand node
|
||||
|
||||
Signed-off-by: hzy <hzyitc@outlook.com>
|
||||
---
|
||||
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 42 +++++++++++++++++++++++++++
|
||||
1 file changed, 42 insertions(+)
|
||||
|
||||
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
index 668a931c892e..c214ac5580eb 100644
|
||||
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
||||
@@ -209,5 +209,47 @@
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
+
|
||||
+ qpic_bam: dma@7984000 {
|
||||
+ compatible = "qcom,bam-v1.7.0";
|
||||
+ reg = <0x7984000 0x1c000>;
|
||||
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
|
||||
+ clocks = <&gcc GCC_QPIC_AHB_CLK>;
|
||||
+ clock-names = "bam_clk";
|
||||
+ #dma-cells = <1>;
|
||||
+ qcom,ee = <0>;
|
||||
+ status = "disabled";
|
||||
+ };
|
||||
+
|
||||
+ nand: qpic-nand@79b0000 {
|
||||
+ compatible = "qcom,ebi2-nandc-bam-v2.1.1";
|
||||
+ reg = <0x79b0000 0x10000>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <0>;
|
||||
+ clocks = <&gcc GCC_QPIC_CLK>,
|
||||
+ <&gcc GCC_QPIC_AHB_CLK>,
|
||||
+ <&gcc GCC_QPIC_IO_MACRO_CLK>;
|
||||
+ clock-names = "core", "aon", "io_macro";
|
||||
+
|
||||
+ dmas = <&qpic_bam 0>,
|
||||
+ <&qpic_bam 1>,
|
||||
+ <&qpic_bam 2>,
|
||||
+ <&qpic_bam 3>;
|
||||
+ dma-names = "tx", "rx", "cmd", "status";
|
||||
+
|
||||
+ qpic,io_macro_clk_rates = <24000000 100000000 200000000 320000000>;
|
||||
+ status = "disabled";
|
||||
+
|
||||
+ nandcs@0 {
|
||||
+ compatible = "qcom,nandcs";
|
||||
+ reg = <0>;
|
||||
+ #address-cells = <1>;
|
||||
+ #size-cells = <1>;
|
||||
+
|
||||
+ nand-ecc-strength = <4>;
|
||||
+ nand-ecc-step-size = <512>;
|
||||
+ nand-bus-width = <8>;
|
||||
+ };
|
||||
+ };
|
||||
};
|
||||
};
|
||||
--
|
||||
2.25.1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user