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67 lines
2.4 KiB
Diff
67 lines
2.4 KiB
Diff
From a5ba59a246e3842ee997e4f2d1ac8cecc8be464c Mon Sep 17 00:00:00 2001
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From: Md Sadre Alam <mdalam@codeaurora.org>
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Date: Tue, 1 Sep 2020 11:28:09 +0530
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Subject: [PATCH 5/7] mtd: rawnand: qcom: Enable support for erase,read & write
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for serial nand.
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This change will enable support for erase, read & write support for
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QSPI serial nand. In QPIC V2.0 onwards, to read last code word new
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regiater is introduced. So to read for first three code word we have to
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use LOCATION_n register and for last code word we ahve to use LAST_CW_n.
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Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
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Change-Id: Iafe34e238754dfc006363dd400a48cf9fc8d92d9
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Pick from https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit/17e85de9e7933a94461f76fe40a5b88334dfdad6
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Signed-off-by: hzy <hzyitc@outlook.com>
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---
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drivers/mtd/nand/raw/qcom_nandc.c | 97 ++++++++++++++++++++++++++-----
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1 file changed, 83 insertions(+), 14 deletions(-)
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diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
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index e19074062348..0a6b67ddcda2 100644
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--- a/drivers/mtd/nand/raw/qcom_nandc.c
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+++ b/drivers/mtd/nand/raw/qcom_nandc.c
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@@ -733,13 +752,18 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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u32 cmd, cfg0, cfg1, ecc_bch_cfg;
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+ cmd = (PAGE_ACC | LAST_PAGE);
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+
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+ if (nandc->props->is_serial_nand)
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+ cmd |= (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD);
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+
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if (read) {
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if (host->use_ecc)
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- cmd = OP_PAGE_READ_WITH_ECC | PAGE_ACC | LAST_PAGE;
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+ cmd |= OP_PAGE_READ_WITH_ECC;
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else
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- cmd = OP_PAGE_READ | PAGE_ACC | LAST_PAGE;
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+ cmd |= OP_PAGE_READ;
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} else {
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- cmd = OP_PROGRAM_PAGE | PAGE_ACC | LAST_PAGE;
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+ cmd |= OP_PROGRAM_PAGE;
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}
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if (host->use_ecc) {
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@@ -1265,9 +1298,13 @@ static int erase_block(struct qcom_nand_host *host, int page_addr)
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{
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struct nand_chip *chip = &host->chip;
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struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
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+ u32 ers_cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE;
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- nandc_set_reg(chip, NAND_FLASH_CMD,
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- OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE);
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+ if (nandc->props->is_serial_nand) {
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+ ers_cmd |= (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1);
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+ page_addr <<= 16;
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+ }
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+ nandc_set_reg(chip, NAND_FLASH_CMD, ers_cmd);
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nandc_set_reg(chip, NAND_ADDR0, page_addr);
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nandc_set_reg(chip, NAND_ADDR1, 0);
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nandc_set_reg(chip, NAND_DEV0_CFG0,
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--
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2.25.1
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