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Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
This commit is contained in:
Tianling Shen 2025-11-07 22:48:43 +08:00
commit ca38cca007
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GPG Key ID: 6850B6345C862176
243 changed files with 10072 additions and 34705 deletions
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2
include/cmake.mk
View File

@ -113,7 +113,7 @@ define Build/Configure/Default
-DCMAKE_NM="$(CMAKE_NM)" \
-DCMAKE_RANLIB="$(CMAKE_RANLIB)" \
-DCMAKE_FIND_ROOT_PATH="$(CMAKE_FIND_ROOT_PATH)" \
-DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=BOTH \
-DCMAKE_FIND_ROOT_PATH_MODE_PROGRAM=NEVER \
-DCMAKE_FIND_ROOT_PATH_MODE_LIBRARY=ONLY \
-DCMAKE_FIND_ROOT_PATH_MODE_INCLUDE=ONLY \
-DCMAKE_STRIP=: \

2
include/download.mk
View File

@ -159,7 +159,7 @@ $(if $(if $(MIRROR), \
( $(3) ) \
$(if $(filter-out x,$(MIRROR_HASH)), && ( \
file_hash="$$$$($(MKHASH) sha256 "$(DL_DIR)/$(FILE)")"; \
[ "$$$$file_hash" = "$(MIRROR_HASH)" ] || { \
[ "$$$$file_hash" = "$(MIRROR_HASH)" ] || [ "$(MIRROR_HASH)" = "skip" ] || { \
echo "Hash mismatch for file $(FILE): expected $(MIRROR_HASH), got $$$$file_hash"; \
false; \
}; \

64
package/boot/arm-trusted-firmware-mediatek/Makefile
View File

@ -38,6 +38,7 @@ define Trusted-Firmware-A/Default
USE_UBI:=
FIP_OFFSET:=
FIP_SIZE:=
SPIM_CTRL:=
endef
define Trusted-Firmware-A/mt7622-nor-1ddr
@ -393,6 +394,61 @@ define Trusted-Firmware-A/mt7986-spim-nand-ubi-ddr3
USE_UBI:=1
endef
define Trusted-Firmware-A/mt7987-emmc-comb
NAME:=MediaTek MT7987 (eMMC)
BOOT_DEVICE:=emmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7987
DRAM_USE_COMB:=1
endef
define Trusted-Firmware-A/mt7987-nor-comb
NAME:=MediaTek MT7987 (NOR)
BOOT_DEVICE:=nor
BUILD_SUBTARGET:=filogic
PLAT:=mt7987
DRAM_USE_COMB:=1
endef
define Trusted-Firmware-A/mt7987-sdmmc-comb
NAME:=MediaTek MT7987 (SD card)
BOOT_DEVICE:=sdmmc
BUILD_SUBTARGET:=filogic
PLAT:=mt7987
DRAM_USE_COMB:=1
endef
define Trusted-Firmware-A/mt7987-spim-nand0-ubi-comb
NAME:=MediaTek MT7987 (SPI-NAND via SPIM, UBI)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7987
DRAM_USE_COMB:=1
USE_UBI:=1
SPIM_CTRL:=0
endef
define Trusted-Firmware-A/mt7987-spim-nand2-ubi-comb
NAME:=MediaTek MT7987 (SPI-NAND via SPIM, UBI)
BOOT_DEVICE:=spim-nand
BUILD_SUBTARGET:=filogic
PLAT:=mt7987
DRAM_USE_COMB:=1
USE_UBI:=1
SPIM_CTRL:=2
endef
define Trusted-Firmware-A/mt7987-ram-comb
NAME:=MediaTek MT7987 (RAM)
BOOT_DEVICE:=ram
BUILD_SUBTARGET:=filogic
PLAT:=mt7987
DRAM_USE_COMB:=1
RAM_BOOT_UART_DL:=1
HIDDEN:=
DEFAULT:=TARGET_mediatek_filogic
endef
define Trusted-Firmware-A/mt7988-nor-ddr3
NAME:=MediaTek MT7988 (SPI-NOR, DDR3)
BOOT_DEVICE:=nor
@ -615,6 +671,12 @@ TFA_TARGETS:= \
mt7986-spim-nand-ddr4 \
mt7986-spim-nand-ubi-ddr4 \
mt7986-spim-nand-4k-ddr4 \
mt7987-emmc-comb \
mt7987-nor-comb \
mt7987-sdmmc-comb \
mt7987-spim-nand0-ubi-comb \
mt7987-spim-nand2-ubi-comb \
mt7987-ram-comb \
mt7988-emmc-ddr3 \
mt7988-nor-ddr3 \
mt7988-sdmmc-ddr3 \
@ -653,6 +715,7 @@ TFA_MAKE_FLAGS += \
$(if $(USE_UBI),UBI=1 $(if $(findstring mt7986,$(PLAT)),OVERRIDE_UBI_START_ADDR=0x200000)) \
$(if $(FIP_OFFSET),OVERRIDE_FIP_BASE=$(FIP_OFFSET)) \
$(if $(FIP_SIZE),OVERRIDE_FIP_SIZE=$(FIP_SIZE)) \
$(if $(SPIM_CTRL),SPIM_CTRL=$(SPIM_CTRL)) \
$(if $(RAM_BOOT_UART_DL),bl2,all)
define Package/trusted-firmware-a-ram/install
@ -665,6 +728,7 @@ Package/trusted-firmware-a-mt7981-ram-ddr3/install = $(Package/trusted-firmware-
Package/trusted-firmware-a-mt7981-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7986-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7986-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7987-ram-comb/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7988-ram-comb/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7988-ram-ddr3/install = $(Package/trusted-firmware-a-ram/install)
Package/trusted-firmware-a-mt7988-ram-ddr4/install = $(Package/trusted-firmware-a-ram/install)

128
package/boot/arm-trusted-firmware-mediatek/patches/0005-mt7987-make-SPI-controller-configurable.patch Normal file
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@ -0,0 +1,128 @@
From e2e43103c00b5f7ccedbdbdece0f622cb420b4a5 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Fri, 3 Oct 2025 12:53:10 +0100
Subject: [PATCH] mt7987: make SPI controller configurable
Allow selecting the SPI controller used for SPIM-NAND or SPI-NOR boot
devices (either SPI0 or SPI2).
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
plat/mediatek/apsoc_common/Config.in | 1 +
plat/mediatek/mt7987/Config.in | 29 +++++++++++++++++++++
plat/mediatek/mt7987/bl2/bl2.mk | 12 +++++++++
plat/mediatek/mt7987/bl2/bl2_dev_spi_nand.c | 10 ++++++-
plat/mediatek/mt7987/platform.mk | 4 +--
5 files changed, 53 insertions(+), 3 deletions(-)
create mode 100644 plat/mediatek/mt7987/Config.in
--- a/plat/mediatek/apsoc_common/Config.in
+++ b/plat/mediatek/apsoc_common/Config.in
@@ -783,6 +783,7 @@ config ENABLE_BL31_RUNTIME_LOG
default 1
depends on _ENABLE_BL31_RUNTIME_LOG
+source "plat/mediatek/mt7987/Config.in"
source "plat/mediatek/mt7988/Config.in"
endmenu # Platform configurations
--- /dev/null
+++ b/plat/mediatek/mt7987/Config.in
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Copyright (c) 2025 Daniel Golle <daniel@makrotopia.org>
+#
+# MT7987 platform-specific configurations
+#
+
+if _PLAT_MT7987
+
+choice
+ prompt "SPI controller"
+ depends on (_BOOT_DEVICE_SPIM_NAND || _BOOT_DEVICE_SPI_NOR)
+ default _SPIM_CTRL_0 if _BOOT_DEVICE_SPIM_NAND
+ default _SPIM_CTRL_2 if _BOOT_DEVICE_SPI_NOR
+
+ config _SPIM_CTRL_0
+ bool "0"
+
+ config _SPIM_CTRL_2
+ bool "2"
+
+endchoice
+
+config SPIM_CTRL
+ int
+ default 0 if _SPIM_CTRL_0
+ default 2 if _SPIM_CTRL_2
+
+endif # _PLAT_MT7987
--- a/plat/mediatek/mt7987/bl2/bl2.mk
+++ b/plat/mediatek/mt7987/bl2/bl2.mk
@@ -91,7 +91,11 @@ endif # END OF BOOT_DEVICE = ram
ifeq ($(BOOT_DEVICE),nor)
$(eval $(call BL2_BOOT_NOR))
BL2_SOURCES += $(MTK_PLAT_SOC)/bl2/bl2_dev_spi_nor.c
+ifeq ($(SPIM_CTRL),0)
+DTS_NAME := mt7987-spi0
+else
DTS_NAME := mt7987-spi2
+endif
endif # END OF BOOTDEVICE = nor
ifeq ($(BOOT_DEVICE),emmc)
@@ -112,10 +116,18 @@ ifeq ($(BOOT_DEVICE),spim-nand)
$(eval $(call BL2_BOOT_SPI_NAND,0,0))
BL2_SOURCES += $(MTK_PLAT_SOC)/bl2/bl2_dev_spi_nand.c
NAND_TYPE ?= spim:2k+64
+ifeq ($(SPIM_CTRL),2)
+DTS_NAME := mt7987-spi2
+else
DTS_NAME := mt7987-spi0
+endif
$(eval $(call BL2_BOOT_NAND_TYPE_CHECK,$(NAND_TYPE),spim:2k+64 spim:2k+128 spim:4k+256))
endif # END OF BOOTDEVICE = spim-nand
+ifneq ($(SPIM_CTRL),)
+BL2_CPPFLAGS += -DSPIM_CTRL=$(SPIM_CTRL)
+endif
+
ifeq ($(BROM_HEADER_TYPE),)
$(error BOOT_DEVICE has invalid value. Please re-check.)
endif
--- a/plat/mediatek/mt7987/bl2/bl2_dev_spi_nand.c
+++ b/plat/mediatek/mt7987/bl2/bl2_dev_spi_nand.c
@@ -12,10 +12,18 @@
#define MTK_QSPI_SRC_CLK CB_MPLL_D2
+#if SPIM_CTRL == 0
+#define SELECTED_SPIM SPIM0
+#elif SPIM_CTRL == 2
+#define SELECTED_SPIM SPIM2
+#else
+#error "Invalid SPI controller selection"
+#endif
+
uint32_t mtk_plat_get_qspi_src_clk(void)
{
/* config GPIO pinmux to spi mode */
- mtk_spi_gpio_init(SPIM0);
+ mtk_spi_gpio_init(SELECTED_SPIM);
/* select 208M clk */
mtk_spi_source_clock_select(MTK_QSPI_SRC_CLK);
--- a/plat/mediatek/mt7987/platform.mk
+++ b/plat/mediatek/mt7987/platform.mk
@@ -56,8 +56,8 @@ include make_helpers/dep.mk
$(call GEN_DEP_RULES,bl2,emicfg bl2_boot_ram bl2_boot_nand_nmbm bl2_dev_mmc bl2_plat_init bl2_plat_setup mt7987_gpio dtb)
$(call MAKE_DEP,bl2,emicfg,DDR4_4BG_MODE DRAM_DEBUG_LOG DDR3_FREQ_2133 DDR3_FREQ_1866 DDR4_FREQ_3200 DDR4_FREQ_2666)
-$(call MAKE_DEP,bl2,bl2_plat_init,BL2_COMPRESS)
-$(call MAKE_DEP,bl2,bl2_plat_setup,BOOT_DEVICE TRUSTED_BOARD_BOOT BL32_TZRAM_BASE BL32_TZRAM_SIZE BL32_LOAD_OFFSET)
+$(call MAKE_DEP,bl2,bl2_plat_init,BL2_COMPRESS SPIM_CTRL)
+$(call MAKE_DEP,bl2,bl2_plat_setup,BOOT_DEVICE TRUSTED_BOARD_BOOT BL32_TZRAM_BASE BL32_TZRAM_SIZE BL32_LOAD_OFFSET SPIM_CTRL)
$(call MAKE_DEP,bl2,bl2_dev_mmc,BOOT_DEVICE)
$(call MAKE_DEP,bl2,bl2_boot_ram,RAM_BOOT_DEBUGGER_HOOK RAM_BOOT_UART_DL)
$(call MAKE_DEP,bl2,bl2_boot_nand_nmbm,NMBM_MAX_RATIO NMBM_MAX_RESERVED_BLOCKS NMBM_DEFAULT_LOG_LEVEL)

24
package/boot/arm-trusted-firmware-mediatek/patches/0006-hack-mt7987-mmc-use-4-bit-bus-width-for-eMMC.patch Normal file
View File

@ -0,0 +1,24 @@
From 0a09912eb336bee788443b919ea5b99b195f5a91 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Sat, 4 Oct 2025 22:13:49 +0100
Subject: [PATCH] hack: mt7987: mmc: use 4-bit bus-width for eMMC
The BananaPi R4 Lite has broken DAT5 signal of the MMC bus, which
results in 8-bit buswidth not working well for the eMMC.
Reduce to 4-bit buswidth fixes it (and makes all other boards with
eMMC a tiny bit slower to boot, but it's in the milliseconds).
---
plat/mediatek/mt7987/bl2/bl2_dev_mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/plat/mediatek/mt7987/bl2/bl2_dev_mmc.c
+++ b/plat/mediatek/mt7987/bl2/bl2_dev_mmc.c
@@ -74,7 +74,7 @@ static const struct mt7987_msdc_conf {
{
.base = MSDC0_BASE,
.top_base = MSDC0_TOP_BASE,
- .bus_width = MMC_BUS_WIDTH_8,
+ .bus_width = MMC_BUS_WIDTH_4,
.type = MMC_IS_EMMC,
.src_clk = 200000000,
.dev_comp = &mt7987_msdc_compat,

27
package/boot/arm-trusted-firmware-mediatek/patches/0007-hack-mt7987-bl2-move-FIP-offset-to-0x100000.patch Normal file
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@ -0,0 +1,27 @@
From 6725bb3c2aa9330f37a591e1e539badf67021b47 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Sat, 4 Oct 2025 23:59:54 +0100
Subject: [PATCH] hack: mt7987: bl2: move FIP offset to 0x100000
There is no use in allocating more than 2MB to the factory partition.
After all, even for WiFi 7 tri-band devices the calibration data is
still in the kilobytes range.
Move FIP offset to 0x100000 to not waste so much space on small NOR
flash.
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
plat/mediatek/mt7987/bl2/bl2_dev_spi_nor.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/plat/mediatek/mt7987/bl2/bl2_dev_spi_nor.c
+++ b/plat/mediatek/mt7987/bl2/bl2_dev_spi_nor.c
@@ -7,7 +7,7 @@
#include <stdint.h>
#include <boot_spi.h>
-#define FIP_BASE 0x250000
+#define FIP_BASE 0x100000
#define FIP_SIZE 0x80000
#define MTK_QSPI_SRC_CLK CB_MPLL_D2

91
package/boot/uboot-mediatek/Makefile
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@ -870,6 +870,55 @@ define U-Boot/mt7986_zyxel_ex5601-t0
DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-4k-ddr4
endef
define U-Boot/mt7987_bananapi_bpi-r4-lite-emmc
NAME:=BananaPi BPi-R4 Lite
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=bananapi_bpi-r4-lite
UBOOT_CONFIG:=mt7987a_bpi-r4-lite-emmc
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=emmc
BL2_SOC:=mt7987
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7987-emmc-comb
endef
define U-Boot/mt7987_bananapi_bpi-r4-lite-sdmmc
NAME:=BananaPi BPi-R4 Lite
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=bananapi_bpi-r4-lite
UBOOT_CONFIG:=mt7987a_bpi-r4-lite-sd
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=sdmmc
BL2_SOC:=mt7987
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7987-sdmmc-comb
endef
define U-Boot/mt7987_bananapi_bpi-r4-lite-snand
NAME:=BananaPi BPi-R4 Lite
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=bananapi_bpi-r4-lite
UBOOT_CONFIG:=mt7987a_bpi-r4-lite-snand
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=spim-nand2-ubi
BL2_SOC:=mt7987
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7987-spim-nand2-ubi-comb
endef
define U-Boot/mt7987_bananapi_bpi-r4-lite-nor
NAME:=BananaPi BPi-R4 Lite
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=bananapi_bpi-r4-lite
UBOOT_CONFIG:=mt7987a_bpi-r4-lite-nor
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=nor
BL2_SOC:=mt7987
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7987-nor-comb
FIP_COMPRESS:=1
endef
define U-Boot/mt7988_arcadyan_mozart
NAME:=Arcadyan Mozart
BUILD_SUBTARGET:=filogic
@ -1000,6 +1049,41 @@ define U-Boot/mt7988_tplink_tl-7dr7250-v1
BL2_SOC:=mt7988
BL2_DDRTYPE:=ddr4
DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ddr4
define U-Boot/mt7987_rfb-emmc
NAME:=MT7987 Reference Board
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=mediatek_mt7987a-rfb
UBOOT_CONFIG:=mt7987_emmc_rfb
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=sdmmc
BL2_SOC:=mt7987
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7987-emmc-comb
endef
define U-Boot/mt7987_rfb-spim-nand
NAME:=MT7987 Reference Board
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=mediatek_mt7987a-rfb
UBOOT_CONFIG:=mt7987_rfb
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=spim-nand0-ubi
BL2_SOC:=mt7987
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7987-spim-nand0-ubi-comb
endef
define U-Boot/mt7987_rfb-sd
NAME:=MT7987 Reference Board
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=mediatek_mt7987a-rfb
UBOOT_CONFIG:=mt7987_sd_rfb
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=sdmmc
BL2_SOC:=mt7987
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7987-sdmmc-comb
endef
define U-Boot/mt7988_rfb-spim-nand
@ -1137,6 +1221,13 @@ UBOOT_TARGETS := \
mt7986_xiaomi_redmi-router-ax6000 \
mt7986_zyxel_ex5601-t0 \
mt7986_rfb \
mt7987_bananapi_bpi-r4-lite-emmc \
mt7987_bananapi_bpi-r4-lite-sdmmc \
mt7987_bananapi_bpi-r4-lite-snand \
mt7987_bananapi_bpi-r4-lite-nor \
mt7987_rfb-emmc \
mt7987_rfb-sd \
mt7987_rfb-spim-nand \
mt7988_arcadyan_mozart \
mt7988_asus_zenwifi-bt8 \
mt7988_bananapi_bpi-r4-emmc \

26
package/boot/uboot-mediatek/patches/007-ARM-dts-build-DT-for-MT7987-RFB.patch Normal file
View File

@ -0,0 +1,26 @@
From a4d4096d6b80a2b6f5bc800426380cdc60d9b037 Mon Sep 17 00:00:00 2001
From: Daniel Golle <daniel@makrotopia.org>
Date: Thu, 2 Oct 2025 14:57:16 +0100
Subject: [PATCH] ARM: dts: build DT for MT7987 RFB
Compile the added device tree sources into blobs, which was forgotten
when adding the source files.
Fixes: 2d6962e0618 (arm: mediatek: add support for MediaTek MT7987 SoC)
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
arch/arm/dts/Makefile | 3 +++
1 file changed, 3 insertions(+)
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1131,6 +1131,9 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986b-sd-rfb.dtb \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
+ mt7987a-emmc-rfb.dtb \
+ mt7987a-rfb.dtb \
+ mt7987a-sd-rfb.dtb \
mt7988-rfb.dtb \
mt7988-sd-rfb.dtb \
mt8183-pumpkin.dtb \

40
package/boot/uboot-mediatek/patches/306-mt7987-generic-reset-button-ignore-env.patch Normal file
View File

@ -0,0 +1,40 @@
--- a/board/mediatek/mt7987/mt7987_rfb.c
+++ b/board/mediatek/mt7987/mt7987_rfb.c
@@ -4,3 +4,37 @@
* Author: Sam Shih <sam.shih@mediatek.com>
*/
+#include <config.h>
+#include <dm.h>
+#include <button.h>
+#include <env.h>
+#include <init.h>
+#include <asm/global_data.h>
+#include <linux/delay.h>
+
+#ifndef CONFIG_RESET_BUTTON_LABEL
+#define CONFIG_RESET_BUTTON_LABEL "reset"
+#endif
+
+int board_late_init(void)
+{
+ gd->env_valid = 1; //to load environment variable from persistent store
+ struct udevice *dev;
+
+ gd->env_valid = ENV_VALID;
+ if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) {
+ puts("reset button found\n");
+#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY
+ if (CONFIG_RESET_BUTTON_SETTLE_DELAY > 0) {
+ button_get_state(dev);
+ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY);
+ }
+#endif
+ if (button_get_state(dev) == BUTTON_ON) {
+ puts("button pushed, resetting environment\n");
+ gd->env_valid = ENV_INVALID;
+ }
+ }
+ env_relocate();
+ return 0;
+}

67
package/boot/uboot-mediatek/patches/315-mt7987-select-rootdisk.patch Normal file
View File

@ -0,0 +1,67 @@
--- a/board/mediatek/mt7987/mt7987_rfb.c
+++ b/board/mediatek/mt7987/mt7987_rfb.c
@@ -10,7 +10,9 @@
#include <env.h>
#include <init.h>
#include <asm/global_data.h>
+#include <asm/io.h>
#include <linux/delay.h>
+#include <linux/libfdt.h>
#ifndef CONFIG_RESET_BUTTON_LABEL
#define CONFIG_RESET_BUTTON_LABEL "reset"
@@ -38,3 +40,54 @@ int board_late_init(void)
env_relocate();
return 0;
}
+
+#define MT7987_BOOT_SD 0
+#define MT7987_BOOT_NOR 1
+#define MT7987_BOOT_SPIM_NAND 2
+#define MT7987_BOOT_EMMC 3
+
+int mtk_ft_system_setup(void *blob, struct bd_info *bd)
+{
+ const u32 *media_handle_p;
+ int chosen, len, ret;
+ const char *media;
+ u32 media_handle;
+
+ switch ((readl(0x1001f6f0) & 0xc0) >> 6) {
+ case MT7987_BOOT_SD:
+ media = "rootdisk-sd";
+ break
+ ;;
+ case MT7987_BOOT_NOR:
+ media = "rootdisk-nor";
+ break
+ ;;
+ case MT7987_BOOT_SPIM_NAND:
+ media = "rootdisk-spim-nand";
+ break
+ ;;
+ case MT7987_BOOT_EMMC:
+ media = "rootdisk-emmc";
+ break
+ ;;
+ }
+
+ chosen = fdt_path_offset(blob, "/chosen");
+ if (chosen <= 0)
+ return 0;
+
+ media_handle_p = fdt_getprop(blob, chosen, media, &len);
+ if (media_handle_p <= 0 || len != 4)
+ return 0;
+
+ media_handle = *media_handle_p;
+ ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle));
+ if (ret) {
+ printf("cannot set media phandle %s as rootdisk /chosen node\n", media);
+ return ret;
+ }
+
+ printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle));
+
+ return 0;
+}

1349
package/boot/uboot-mediatek/patches/470-add-bpi-r4-lite.patch Normal file
View File

File diff suppressed because it is too large Load Diff

30
package/boot/uboot-mediatek/patches/500-adapt-mt7987-rfb.patch Normal file
View File

@ -0,0 +1,30 @@
--- a/configs/mt7987_rfb_defconfig
+++ b/configs/mt7987_rfb_defconfig
@@ -70,6 +70,7 @@ CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_ZBIT=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_PHY_ETHERNET_ID=y
CONFIG_MEDIATEK_ETH=y
CONFIG_PINCTRL=y
--- a/configs/mt7987_emmc_rfb_defconfig
+++ b/configs/mt7987_emmc_rfb_defconfig
@@ -75,6 +75,7 @@ CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_ZBIT=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_PHY_ETHERNET_ID=y
CONFIG_MEDIATEK_ETH=y
CONFIG_PINCTRL=y
--- a/configs/mt7987_sd_rfb_defconfig
+++ b/configs/mt7987_sd_rfb_defconfig
@@ -75,6 +75,7 @@ CONFIG_SPI_FLASH_XTX=y
CONFIG_SPI_FLASH_ZBIT=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI=y
+CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_PHY_ETHERNET_ID=y
CONFIG_MEDIATEK_ETH=y
CONFIG_PINCTRL=y

1
package/boot/uboot-tools/uboot-envtools/files/mediatek_filogic
View File

@ -70,6 +70,7 @@ asus,rt-ax59u)
bananapi,bpi-r3|\
bananapi,bpi-r3-mini|\
bananapi,bpi-r4|\
bananapi,bpi-r4-lite|\
bananapi,bpi-r4-poe|\
cmcc,rax3000m|\
cmcc,rax3000me|\

56
package/kernel/linux/modules/video.mk
View File

@ -371,19 +371,6 @@ endef
$(eval $(call KernelPackage,drm-exec))
define KernelPackage/drm-gem-shmem-helper
SUBMENU:=$(VIDEO_MENU)
TITLE:=GEM shmem helper functions
DEPENDS:=@DISPLAY_SUPPORT +kmod-drm +!LINUX_6_6:kmod-drm-kms-helper \
+!LINUX_6_6:kmod-fb-sys-fops +!LINUX_6_6:kmod-fb-sys-ram
KCONFIG:=CONFIG_DRM_GEM_SHMEM_HELPER
FILES:=$(LINUX_DIR)/drivers/gpu/drm/drm_shmem_helper.ko
AUTOLOAD:=$(call AutoProbe,drm_shmem_helper)
endef
$(eval $(call KernelPackage,drm-gem-shmem-helper))
define KernelPackage/drm-dma-helper
SUBMENU:=$(VIDEO_MENU)
HIDDEN:=1
@ -400,6 +387,24 @@ endef
$(eval $(call KernelPackage,drm-dma-helper))
define KernelPackage/drm-shmem-helper
SUBMENU:=$(VIDEO_MENU)
HIDDEN:=1
TITLE:=GEM SHMEM helper functions
DEPENDS:=@DISPLAY_SUPPORT +kmod-drm-kms-helper
KCONFIG:=CONFIG_DRM_GEM_SHMEM_HELPER
FILES:=$(LINUX_DIR)/drivers/gpu/drm/drm_shmem_helper.ko
AUTOLOAD:=$(call AutoProbe,drm_shmem_helper)
endef
define KernelPackage/drm-shmem-helper/description
GEM SHMEM helper functions.
endef
$(eval $(call KernelPackage,drm-shmem-helper))
define KernelPackage/drm-mipi-dbi
SUBMENU:=$(VIDEO_MENU)
HIDDEN:=1
@ -416,6 +421,25 @@ endef
$(eval $(call KernelPackage,drm-mipi-dbi))
define KernelPackage/drm-sched
SUBMENU:=$(VIDEO_MENU)
HIDDEN:=1
TITLE:=GPU scheduler
DEPENDS:=@DISPLAY_SUPPORT +kmod-drm
KCONFIG:=CONFIG_DRM_SCHED
FILES:=$(LINUX_DIR)/drivers/gpu/drm/scheduler/gpu-sched.ko
AUTOLOAD:=$(call AutoProbe,gpu-sched)
endef
define KernelPackage/drm-sched/description
The GPU scheduler provides entities which allow userspace to push jobs
into software queues which are then scheduled on a hardware run queue.
endef
$(eval $(call KernelPackage,drm-sched))
define KernelPackage/drm-ttm
SUBMENU:=$(VIDEO_MENU)
TITLE:=GPU memory management subsystem
@ -664,7 +688,7 @@ $(eval $(call KernelPackage,drm-imx-ldb))
define KernelPackage/drm-lima
SUBMENU:=$(VIDEO_MENU)
TITLE:=Mali-4xx GPU support
DEPENDS:=@(TARGET_rockchip||TARGET_sunxi) +kmod-drm +kmod-drm-gem-shmem-helper
DEPENDS:=@(TARGET_rockchip||TARGET_sunxi) +kmod-drm +kmod-drm-shmem-helper
KCONFIG:= \
CONFIG_DRM_VGEM \
CONFIG_DRM_GEM_CMA_HELPER=y \
@ -685,7 +709,7 @@ $(eval $(call KernelPackage,drm-lima))
define KernelPackage/drm-panfrost
SUBMENU:=$(VIDEO_MENU)
TITLE:=DRM support for ARM Mali Midgard/Bifrost GPUs
DEPENDS:=@(TARGET_rockchip||TARGET_sunxi) +kmod-drm +kmod-drm-gem-shmem-helper
DEPENDS:=@(TARGET_rockchip||TARGET_sunxi) +kmod-drm +kmod-drm-shmem-helper
KCONFIG:=CONFIG_DRM_PANFROST
FILES:= \
$(LINUX_DIR)/drivers/gpu/drm/panfrost/panfrost.ko \
@ -704,7 +728,7 @@ define KernelPackage/drm-panthor
SUBMENU:=$(VIDEO_MENU)
TITLE:=DRM support for ARM Mali CSF-based GPUs
DEPENDS:=@TARGET_rockchip +kmod-drm +kmod-drm-exec \
+kmod-drm-gem-shmem-helper +panthor-firmware
+kmod-drm-shmem-helper +panthor-firmware
KCONFIG:= \
CONFIG_DRM_GPUVM \
CONFIG_DRM_PANTHOR

65
package/kernel/mac80211/patches/ath11k/453-ath11k-add-ath11k_mac_op_flush_sta-to-properly-flush.patch Normal file
View File

@ -0,0 +1,65 @@
From b5ade0e0e1c1622a85fbfd2c93b41caff479f305 Mon Sep 17 00:00:00 2001
From: Florian Maurer <f.maurer@outlook.de>
Date: Fri, 3 Oct 2025 12:56:13 +0200
Subject: [PATCH] ath11k: add ath11k_mac_op_flush_sta to properly flush pending
packets
When a STA is marked as no longer authorized, if the driver doesn't
implement flush_sta(), mac80211 calls ieee80211_flush_queues() to
flush hardware queues to avoid sending unencrypted frames.
This has became a problem for ath11k because ieee80211_flush_queues()
will stop all traffic and call ath11k_flush, which waits until the
whole HW queue is empty. In a busy environment this will trigger a
timeout warning and stalls other STAs.
Fix this by implementing flush_sta method using WMI command to flush
frames of a specific STA.
Flushed frames will be marked as discard in tx complete indication.
warning print "ath11k c000000.wifi: failed to flush transmit queue 0"
was observed on various openwrt devices, and is fixed through this patch.
Tested-by: Florian Maurer <f.maurer@outlook.de>
Tested-by: Flole <flole@flole.de>
Co-developed-by: Benjamin Berg <benjamin@sipsolutions.net>
Signed-off-by: Benjamin Berg <benjamin@sipsolutions.net>
Signed-off-by: Florian Maurer <f.maurer@outlook.de>
---
drivers/net/wireless/ath/ath11k/mac.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/drivers/net/wireless/ath/ath11k/mac.c
+++ b/drivers/net/wireless/ath/ath11k/mac.c
@@ -8248,6 +8248,23 @@ static void ath11k_mac_op_flush(struct i
ath11k_mac_flush_tx_complete(ar);
}
+static void ath11k_mac_op_flush_sta(struct ieee80211_hw *hw,
+ struct ieee80211_vif *vif,
+ struct ieee80211_sta *sta)
+{
+ struct ath11k_vif *arvif = (void *)vif->drv_priv;
+ struct ath11k *ar = hw->priv;
+ struct peer_flush_params params = {
+ .peer_tid_bitmap = 0xFF,
+ .vdev_id = arvif->vdev_id,
+ };
+ int ret;
+
+ ret = ath11k_wmi_send_peer_flush_tids_cmd(ar, sta->addr, &params);
+ if (ret)
+ ath11k_warn(ar->ab, "failed to flush sta %pM: %d\n", sta->addr, ret);
+}
+
static bool
ath11k_mac_has_single_legacy_rate(struct ath11k *ar,
enum nl80211_band band,
@@ -9823,6 +9840,7 @@ static const struct ieee80211_ops ath11k
.set_bitrate_mask = ath11k_mac_op_set_bitrate_mask,
.get_survey = ath11k_mac_op_get_survey,
.flush = ath11k_mac_op_flush,
+ .flush_sta = ath11k_mac_op_flush_sta,
.sta_statistics = ath11k_mac_op_sta_statistics,
CFG80211_TESTMODE_CMD(ath11k_tm_cmd)

4
package/kernel/mac80211/patches/ath11k/941-ath11k-fix_sleeping-in-atomic_in_ath11k_mac_op_set_bitrate_mask.patch
View File

@ -39,7 +39,7 @@ Signed-off-by: Sasha Levin <sashal@kernel.org>
--- a/drivers/net/wireless/ath/ath11k/mac.c
+++ b/drivers/net/wireless/ath/ath11k/mac.c
@@ -8740,9 +8740,9 @@ ath11k_mac_op_set_bitrate_mask(struct ie
@@ -8757,9 +8757,9 @@ ath11k_mac_op_set_bitrate_mask(struct ie
arvif->vdev_id, ret);
return ret;
}
@ -52,7 +52,7 @@ Signed-off-by: Sasha Levin <sashal@kernel.org>
} else if (ath11k_mac_bitrate_mask_get_single_nss(ar, arvif, band, mask,
&single_nss)) {
rate = WMI_FIXED_RATE_NONE;
@@ -8809,9 +8809,9 @@ ath11k_mac_op_set_bitrate_mask(struct ie
@@ -8826,9 +8826,9 @@ ath11k_mac_op_set_bitrate_mask(struct ie
}
mutex_lock(&ar->conf_mutex);

2
package/kernel/mac80211/patches/ath11k/945-ath11k-fix_group_data_packet_drops_during_rekey.patch
View File

@ -213,7 +213,7 @@ Signed-off-by: Sasha Levin <sashal@kernel.org>
}
static u32 ath11k_mac_ieee80211_sta_bw_to_wmi(struct ath11k *ar,
@@ -9536,6 +9614,21 @@ static int ath11k_mac_station_add(struct
@@ -9553,6 +9631,21 @@ static int ath11k_mac_station_add(struct
goto exit;
}

6
package/kernel/mt76/Makefile
View File

@ -8,9 +8,9 @@ PKG_LICENSE_FILES:=
PKG_SOURCE_URL:=https://github.com/openwrt/mt76
PKG_SOURCE_PROTO:=git
PKG_SOURCE_DATE:=2025-10-20
PKG_SOURCE_VERSION:=c63db0fcadb88680b35bec202b5142cfd016c10f
PKG_MIRROR_HASH:=38c3c84f5c58b6967283acf524412f6e13628d50add6f09d539f1239fb02b486
PKG_SOURCE_DATE:=2025-11-06
PKG_SOURCE_VERSION:=eb567bc7f9b692bbf1ddfe31dd740861c58ec85b
PKG_MIRROR_HASH:=7cfe242a5494cdf5d8e8eea86633778a525717528bcce70aedef96eee5594383
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
PKG_USE_NINJA:=0

8
package/libs/jansson/patches/001-cmake-ver.patch Normal file
View File

@ -0,0 +1,8 @@
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,4 +1,4 @@
-cmake_minimum_required (VERSION 3.1)
+cmake_minimum_required (VERSION 3.10)
project(jansson C)
# Options

11
package/libs/libevent2/patches/002-cmake4.patch Normal file
View File

@ -0,0 +1,11 @@
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -19,7 +19,7 @@
# start libevent.sln
#
-cmake_minimum_required(VERSION 3.1 FATAL_ERROR)
+cmake_minimum_required(VERSION 3.10)
if (POLICY CMP0054)
cmake_policy(SET CMP0054 NEW)

20
package/libs/libjson-c/patches/002-cmake-version.patch Normal file
View File

@ -0,0 +1,20 @@
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -3,7 +3,7 @@
# and many OpenWRT packages require, much newer CMake packages.
# We're stopping before 3.10 because that version starts requiring
# c++11, which isn't available on e.g HPUX.
-cmake_minimum_required(VERSION 3.9...3.12)
+cmake_minimum_required(VERSION 3.10)
# JSON-C library is C only project.
# PROJECT_VERSION{,_MAJOR,_MINOR,_PATCH} set by project():
--- a/apps/CMakeLists.txt
+++ b/apps/CMakeLists.txt
@@ -1,5 +1,5 @@
-cmake_minimum_required(VERSION 2.8) # see ../CMakeLists.txt for why 2.8
+cmake_minimum_required(VERSION 3.10)
if(POLICY CMP0075)
cmake_policy(SET CMP0075 NEW)

13
package/libs/openssl/Makefile
View File

@ -356,34 +356,31 @@ OPENSSL_TARGET:=linux-$(call qstrip,$(CONFIG_ARCH))-openwrt
STAMP_CONFIGURED := $(STAMP_CONFIGURED)_$(shell echo $(OPENSSL_OPTIONS) | $(MKHASH) md5)
TARGET_CFLAGS += $(FPIC)
define Build/Configure
(cd $(PKG_BUILD_DIR); \
CFLAGS="$(TARGET_CFLAGS)" \
CPPFLAGS="$(TARGET_CPPFLAGS)" \
LDFLAGS="$(TARGET_LDFLAGS)" \
./Configure $(OPENSSL_TARGET) \
--prefix=/usr \
--libdir=lib \
--openssldir=/etc/ssl \
--cross-compile-prefix="$(TARGET_CROSS)" \
$(TARGET_CFLAGS) \
$(TARGET_CPPFLAGS) \
$(TARGET_LDFLAGS) \
$(OPENSSL_OPTIONS) && \
{ [ -f $(STAMP_CONFIGURED) ] || make clean; } \
)
endef
TARGET_CFLAGS += $(FPIC)
define Build/Compile
+$(MAKE) $(PKG_JOBS) -C $(PKG_BUILD_DIR) \
CC="$(TARGET_CC)" \
SOURCE_DATE_EPOCH=$(SOURCE_DATE_EPOCH) \
OPENWRT_OPTIMIZATION_FLAGS="$(TARGET_CFLAGS)" \
$(OPENSSL_MAKEFLAGS) \
all
$(MAKE) -C $(PKG_BUILD_DIR) \
CC="$(TARGET_CC)" \
DESTDIR="$(PKG_INSTALL_DIR)" \
$(OPENSSL_MAKEFLAGS) \
install_sw install_ssldirs
endef

36
package/libs/openssl/patches/110-openwrt_targets.patch
View File

@ -9,63 +9,59 @@ Signed-off-by: Eneas U de Queiroz <cote2004-github@yahoo.com>
--- /dev/null
+++ b/Configurations/25-openwrt.conf
@@ -0,0 +1,59 @@
@@ -0,0 +1,55 @@
+## Openwrt "CONFIG_ARCH" matching targets.
+
+# The targets need to end in '-openwrt' for the AFALG patch to work
+
+my %targets = (
+ "openwrt" => {
+ template => 1,
+ CFLAGS => add("\$(OPENWRT_OPTIMIZATION_FLAGS)"),
+ },
+ "linux-aarch64-openwrt" => {
+ inherit_from => [ "linux-aarch64", "openwrt" ],
+ inherit_from => [ "linux-aarch64" ],
+ },
+ "linux-arc-openwrt" => {
+ inherit_from => [ "linux-latomic", "openwrt" ],
+ inherit_from => [ "linux-latomic" ],
+ },
+ "linux-arm-openwrt" => {
+ inherit_from => [ "linux-armv4", "openwrt" ],
+ inherit_from => [ "linux-armv4" ],
+ },
+ "linux-armeb-openwrt" => {
+ inherit_from => [ "linux-armv4", "openwrt" ],
+ inherit_from => [ "linux-armv4" ],
+ },
+ "linux-i386-openwrt" => {
+ inherit_from => [ "linux-x86", "openwrt" ],
+ inherit_from => [ "linux-x86" ],
+ },
+ "linux-loongarch64-openwrt" => {
+ inherit_from => [ "linux64-loongarch64", "openwrt" ],
+ inherit_from => [ "linux64-loongarch64" ],
+ },
+ "linux-mips-openwrt" => {
+ inherit_from => [ "linux-mips32", "openwrt" ],
+ inherit_from => [ "linux-mips32" ],
+ },
+ "linux-mips64-openwrt" => {
+ inherit_from => [ "linux64-mips64", "openwrt" ],
+ inherit_from => [ "linux64-mips64" ],
+ },
+ "linux-mips64el-openwrt" => {
+ inherit_from => [ "linux64-mips64", "openwrt" ],
+ inherit_from => [ "linux64-mips64" ],
+ },
+ "linux-mipsel-openwrt" => {
+ inherit_from => [ "linux-mips32", "openwrt" ],
+ inherit_from => [ "linux-mips32" ],
+ },
+ "linux-powerpc-openwrt" => {
+ inherit_from => [ "linux-ppc", "openwrt" ],
+ inherit_from => [ "linux-ppc" ],
+ },
+ "linux-powerpc64-openwrt" => {
+ inherit_from => [ "linux-ppc64", "openwrt" ],
+ inherit_from => [ "linux-ppc64" ],
+ perlasm_scheme => "linux64v2",
+ },
+ "linux-riscv64-openwrt" => {
+ inherit_from => [ "linux-generic64", "openwrt" ],
+ inherit_from => [ "linux-generic64" ],
+ perlasm_scheme => "linux64",
+ },
+ "linux-x86_64-openwrt" => {
+ inherit_from => [ "linux-x86_64", "openwrt" ],
+ inherit_from => [ "linux-x86_64" ],
+ },
+
+### Basic default option
+ "linux-generic32-openwrt" => {
+ inherit_from => [ "linux-generic32", "openwrt" ],
+ inherit_from => [ "linux-generic32" ],
+ },
+);

1
package/libs/xcrypt/libcrypt-compat/Makefile
View File

@ -1,6 +1,7 @@
include $(TOPDIR)/rules.mk
include ../libxcrypt-common.mk
PKG_NAME:=libcrypt-compat
PKG_INSTALL:=1
PKG_BUILD_PARALLEL:=1
PKG_BUILD_DIR:=$(BUILD_DIR)/libcrypt-compat/$(PKG_SOURCE_NAME)-$(PKG_VERSION)

1
package/libs/xcrypt/libxcrypt/Makefile
View File

@ -1,6 +1,7 @@
include $(TOPDIR)/rules.mk
include ../libxcrypt-common.mk
PKG_NAME:=libxcrypt
PKG_INSTALL:=1
PKG_BUILD_PARALLEL:=1
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_SOURCE_NAME)-$(PKG_VERSION)

2
package/network/ipv6/map/src/CMakeLists.txt
View File

@ -1,4 +1,4 @@
cmake_minimum_required(VERSION 2.8.1)
cmake_minimum_required(VERSION 3.10)
project(mapcalc C)

11
package/network/ipv6/odhcp6c/Makefile
View File

@ -12,17 +12,16 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcp6c.git
PKG_SOURCE_DATE:=2025-10-21
PKG_SOURCE_VERSION:=77e1ae21e67f81840024ffe5bb7cf69a8fb0d2f0
PKG_MIRROR_HASH:=78f1c2342330da5f6bf08a4be89df1d771661966bbff13bd15462035de46837b
PKG_SOURCE_DATE:=2025-11-04
PKG_SOURCE_VERSION:=b3e1db42b4dbb5f99705e4d1057ca49b44f4f5ee
PKG_MIRROR_HASH:=37ddaf182eba190efc091d7b9c963e84dfe0537ce498ad4be1c268bea134782e
PKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>
PKG_LICENSE:=GPL-2.0
include $(INCLUDE_DIR)/package.mk
include $(INCLUDE_DIR)/cmake.mk
CMAKE_OPTIONS += \
-DUSE_LIBUBOX=on
CMAKE_OPTIONS += -DUBUS=1
ifneq ($(CONFIG_PACKAGE_odhcp6c_ext_cer_id),0)
CMAKE_OPTIONS += -DEXT_CER_ID=$(CONFIG_PACKAGE_odhcp6c_ext_cer_id)
@ -32,7 +31,7 @@ define Package/odhcp6c
SECTION:=net
CATEGORY:=Network
TITLE:=Embedded DHCPv6-client for OpenWrt
DEPENDS:=@IPV6 +libubox
DEPENDS:=@IPV6 +libubox +libubus
endef
define Package/odhcp6c/config

12
package/network/ipv6/odhcp6c/files/dhcpv6.script
View File

@ -150,6 +150,11 @@ setup_interface () {
proto_send_update "$INTERFACE"
# If the flag '$DYNAMIC' is set to '0' (default=1), then the dynamic
# interfaces for the proto 'map', 'dslite' or '464xlat' are not
# created, even if the requirements are met.
[ "$DYNAMIC" = 0 ] && return
MAPTYPE=""
MAPRULE=""
@ -166,7 +171,7 @@ setup_interface () {
[ -n "$ZONE" ] || ZONE=$(fw3 -q network $INTERFACE 2>/dev/null)
if [ "$IFACE_MAP" != 0 -a -n "$MAPTYPE" -a -n "$MAPRULE" ]; then
if [ "$IFACE_MAP" != 0 ] && [ -n "$MAPTYPE" ] && [ -n "$MAPRULE" ]; then
[ -z "$IFACE_MAP" -o "$IFACE_MAP" = 1 ] && IFACE_MAP=${INTERFACE}_4
json_init
json_add_string name "$IFACE_MAP"
@ -183,7 +188,7 @@ setup_interface () {
[ -n "$IFACE_MAP_DELEGATE" ] && json_add_boolean delegate "$IFACE_MAP_DELEGATE"
json_close_object
ubus call network add_dynamic "$(json_dump)"
elif [ -n "$AFTR" -a "$IFACE_DSLITE" != 0 -a -f /lib/netifd/proto/dslite.sh ]; then
elif [ -n "$AFTR" ] && [ "$IFACE_DSLITE" != 0 ] && [ -f /lib/netifd/proto/dslite.sh ]; then
[ -z "$IFACE_DSLITE" -o "$IFACE_DSLITE" = 1 ] && IFACE_DSLITE=${INTERFACE}_4
json_init
json_add_string name "$IFACE_DSLITE"
@ -193,11 +198,12 @@ setup_interface () {
json_add_string tunlink "$INTERFACE"
[ -n "$ZONE_DSLITE" ] || ZONE_DSLITE=$ZONE
[ -n "$ZONE_DSLITE" ] && json_add_string zone "$ZONE_DSLITE"
[ -n "$MTU_DSLITE" ] && json_add_string mtu "$MTU_DSLITE"
[ -n "$ENCAPLIMIT_DSLITE" ] && json_add_string encaplimit "$ENCAPLIMIT_DSLITE"
[ -n "$IFACE_DSLITE_DELEGATE" ] && json_add_boolean delegate "$IFACE_DSLITE_DELEGATE"
json_close_object
ubus call network add_dynamic "$(json_dump)"
elif [ "$IFACE_464XLAT" != 0 -a -f /lib/netifd/proto/464xlat.sh ]; then
elif [ "$IFACE_464XLAT" != 0 ] && [ -f /lib/netifd/proto/464xlat.sh ]; then
[ -z "$IFACE_464XLAT" -o "$IFACE_464XLAT" = 1 ] && IFACE_464XLAT=${INTERFACE}_4
json_init
json_add_string name "$IFACE_464XLAT"

30
package/network/ipv6/odhcp6c/files/dhcpv6.sh
View File

@ -24,6 +24,7 @@ proto_dhcpv6_init_config() {
proto_config_add_string iface_dslite
proto_config_add_string zone_dslite
proto_config_add_string encaplimit_dslite
proto_config_add_int mtu_dslite
proto_config_add_string iface_map
proto_config_add_string zone_map
proto_config_add_string encaplimit_map
@ -42,6 +43,7 @@ proto_dhcpv6_init_config() {
proto_config_add_boolean keep_ra_dnslifetime
proto_config_add_int "ra_holdoff"
proto_config_add_boolean verbose
proto_config_add_boolean dynamic
}
proto_dhcpv6_add_prefix() {
@ -56,11 +58,28 @@ proto_dhcpv6_setup() {
local config="$1"
local iface="$2"
local reqaddress reqprefix clientid reqopts defaultreqopts noslaaconly forceprefix extendprefix norelease noserverunicast noclientfqdn noacceptreconfig ip6prefix ip6prefixes iface_dslite iface_map iface_464xlat ip6ifaceid userclass vendorclass sendopts delegate zone_dslite zone_map zone_464xlat zone encaplimit_dslite encaplimit_map skpriority soltimeout fakeroutes sourcefilter keep_ra_dnslifetime ra_holdoff verbose
json_get_vars reqaddress reqprefix clientid reqopts defaultreqopts noslaaconly forceprefix extendprefix norelease noserverunicast noclientfqdn noacceptreconfig iface_dslite iface_map iface_464xlat ip6ifaceid userclass vendorclass delegate zone_dslite zone_map zone_464xlat zone encaplimit_dslite encaplimit_map skpriority soltimeout fakeroutes sourcefilter keep_ra_dnslifetime ra_holdoff verbose
local reqaddress reqprefix clientid reqopts defaultreqopts
local noslaaconly forceprefix extendprefix norelease
local noserverunicast noclientfqdn noacceptreconfig iface_dslite
local iface_map iface_464xlat ip6ifaceid userclass vendorclass
local delegate zone_dslite zone_map zone_464xlat zone encaplimit_dslite
local encaplimit_map skpriority soltimeout fakeroutes sourcefilter
local keep_ra_dnslifetime ra_holdoff verbose mtu_dslite dynamic
local ip6prefix ip6prefixes
json_get_vars reqaddress reqprefix clientid reqopts defaultreqopts
json_get_vars noslaaconly forceprefix extendprefix norelease
json_get_vars noserverunicast noclientfqdn noacceptreconfig iface_dslite
json_get_vars iface_map iface_464xlat ip6ifaceid userclass vendorclass
json_get_vars delegate zone_dslite zone_map zone_464xlat zone encaplimit_dslite
json_get_vars encaplimit_map skpriority soltimeout fakeroutes sourcefilter
json_get_vars keep_ra_dnslifetime ra_holdoff verbose mtu_dslite dynamic
json_for_each_item proto_dhcpv6_add_prefix ip6prefix ip6prefixes
# Configure
local sendopts
local opts=""
[ -n "$reqaddress" ] && append opts "-N$reqaddress"
@ -120,6 +139,7 @@ proto_dhcpv6_setup() {
[ -n "$ip6prefixes" ] && proto_export "USERPREFIX=$ip6prefixes"
[ -n "$iface_dslite" ] && proto_export "IFACE_DSLITE=$iface_dslite"
[ -n "$mtu_dslite" ] && proto_export "MTU_DSLITE=$mtu_dslite"
[ -n "$iface_map" ] && proto_export "IFACE_MAP=$iface_map"
[ -n "$iface_464xlat" ] && proto_export "IFACE_464XLAT=$iface_464xlat"
[ "$delegate" = "0" ] && proto_export "IFACE_DSLITE_DELEGATE=0"
@ -135,6 +155,12 @@ proto_dhcpv6_setup() {
[ "$sourcefilter" = "0" ] && proto_export "NOSOURCEFILTER=1"
[ "$extendprefix" = "1" ] && proto_export "EXTENDPREFIX=1"
if [ "$dynamic" = 0 ]; then
proto_export "DYNAMIC=0"
else
proto_export "DYNAMIC=1"
fi
proto_export "INTERFACE=$config"
proto_run_command "$config" odhcp6c \
-s /lib/netifd/dhcpv6.script \

7
package/network/services/dnsmasq/files/dnsmasq.init
View File

@ -170,7 +170,9 @@ append_rev_server() {
}
append_address() {
local address_as_local="$2"
xappend "--address=$1"
[ $address_as_local -gt 0 ] && xappend "--local=${1%/*}/"
}
append_connmark_allowlist() {
@ -1036,7 +1038,10 @@ dnsmasq_start()
config_list_foreach "$cfg" "listen_address" append_listenaddress
config_list_foreach "$cfg" "server" append_server
config_list_foreach "$cfg" "rev_server" append_rev_server
config_list_foreach "$cfg" "address" append_address
local address_as_local
config_get address_as_local "$cfg" address_as_local 0
config_list_foreach "$cfg" "address" append_address "$address_as_local"
local connmark_allowlist_enable
config_get connmark_allowlist_enable "$cfg" connmark_allowlist_enable 0

12
package/network/services/hostapd/files/wpa_supplicant.uc
View File

@ -732,6 +732,15 @@ function iface_ubus_remove(ifname)
delete wpas.data.iface_ubus[ifname];
}
function iface_ubus_notify(ifname, event)
{
let obj = wpas.data.iface_ubus[ifname];
if (!obj)
return;
obj.notify('ctrl-event', { event }, null, null, null, -1);
}
function iface_ubus_add(ifname)
{
let ubus = wpas.data.ubus;
@ -813,6 +822,9 @@ return {
iface_event("remove", name);
iface_ubus_remove(name);
},
ctrl_event: function(name, iface, ev) {
iface_ubus_notify(name, ev);
},
state: function(ifname, iface, state) {
let event_data = iface.status();
event_data.name = ifname;

18
package/network/services/hostapd/patches/601-ucode_support.patch
View File

@ -995,3 +995,21 @@ as adding/removing interfaces.
switch (event) {
case EVENT_AUTH:
#ifdef CONFIG_FST
--- a/wpa_supplicant/ctrl_iface_unix.c
+++ b/wpa_supplicant/ctrl_iface_unix.c
@@ -28,6 +28,7 @@
#include "config.h"
#include "wpa_supplicant_i.h"
#include "ctrl_iface.h"
+#include "ucode.h"
/* Per-interface ctrl_iface */
@@ -436,6 +437,7 @@ static void wpa_supplicant_ctrl_iface_ms
if (wpa_s == NULL)
return;
+ wpas_ucode_ctrl_event(wpa_s, txt, len);
gpriv = wpa_s->global->ctrl_iface;
if (type != WPA_MSG_NO_GLOBAL && gpriv &&

21
package/network/services/hostapd/src/wpa_supplicant/ucode.c
View File

@ -157,6 +157,27 @@ void wpas_ucode_event(struct wpa_supplicant *wpa_s, int event, union wpa_event_d
ucv_put(wpa_ucode_call(4));
}
void wpas_ucode_ctrl_event(struct wpa_supplicant *wpa_s, const char *str, size_t len)
{
uc_value_t *val;
#define _EV_PREFIX "CTRL-EVENT-"
if (strncmp(str, _EV_PREFIX, sizeof(_EV_PREFIX) - 1) != 0)
return;
val = wpa_ucode_registry_get(iface_registry, wpa_s->ucode.idx);
if (!val)
return;
if (wpa_ucode_call_prepare("ctrl_event"))
return;
uc_value_push(ucv_string_new(wpa_s->ifname));
uc_value_push(ucv_get(val));
uc_value_push(ucv_string_new_length(str, len));
ucv_put(wpa_ucode_call(3));
}
void wpas_ucode_wps_complete(struct wpa_supplicant *wpa_s,
const struct wps_credential *cred)
{

5
package/network/services/hostapd/src/wpa_supplicant/ucode.h
View File

@ -22,6 +22,7 @@ void wpas_ucode_add_bss(struct wpa_supplicant *wpa_s);
void wpas_ucode_free_bss(struct wpa_supplicant *wpa_s);
void wpas_ucode_update_state(struct wpa_supplicant *wpa_s);
void wpas_ucode_event(struct wpa_supplicant *wpa_s, int event, union wpa_event_data *data);
void wpas_ucode_ctrl_event(struct wpa_supplicant *wpa_s, const char *str, size_t len);
bool wpas_ucode_bss_allowed(struct wpa_supplicant *wpa_s, struct wpa_bss *bss);
void wpas_ucode_wps_complete(struct wpa_supplicant *wpa_s,
const struct wps_credential *cred);
@ -49,6 +50,10 @@ static inline void wpas_ucode_event(struct wpa_supplicant *wpa_s, int event, uni
{
}
static inline void wpas_ucode_ctrl_event(struct wpa_supplicant *wpa_s, const char *str, size_t len)
{
}
static inline bool wpas_ucode_bss_allowed(struct wpa_supplicant *wpa_s, struct wpa_bss *bss)
{
return true;

6
package/network/services/odhcpd/Makefile
View File

@ -12,9 +12,9 @@ PKG_RELEASE:=1
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/odhcpd.git
PKG_MIRROR_HASH:=acb086731fd7d072ddddc1d5f3bad9377e89a05597ce004d24bd0cdb60586f0a
PKG_SOURCE_DATE:=2025-10-26
PKG_SOURCE_VERSION:=fc27940fe9939f99aeb988d021c7edfa54460123
PKG_MIRROR_HASH:=7e7b331972ca1e9847c49dd65e37fbb16c9c3b04dec479a1fa6f2b216a5f53f1
PKG_SOURCE_DATE:=2025-11-04
PKG_SOURCE_VERSION:=d44af6dd8f4e1dd0d858ae19419057ab4f319310
PKG_MAINTAINER:=Hans Dedecker <dedeckeh@gmail.com>
PKG_LICENSE:=GPL-2.0

6
package/system/opkg/Makefile
View File

@ -12,9 +12,9 @@ PKG_FLAGS:=essential
PKG_SOURCE_PROTO:=git
PKG_SOURCE_URL=$(PROJECT_GIT)/project/opkg-lede.git
PKG_SOURCE_DATE:=2024-10-16
PKG_SOURCE_VERSION:=38eccbb1fd694d4798ac1baf88f9ba83d1eac616
PKG_MIRROR_HASH:=de58ff1c99c14789f9ba8946623c8c1e58d022e7e2a659d6f97c6fde54f2c4f4
PKG_SOURCE_DATE:=2025-11-05
PKG_SOURCE_VERSION:=80503d94e356476250adaf1f669ee955ec26de76
PKG_MIRROR_HASH:=41fb2c79ce6014e28f7dd0cd8c65efe803986278f2587d1d4681883d8847d87c
PKG_LICENSE:=GPL-2.0
PKG_LICENSE_FILES:=COPYING

2
package/utils/fritz-tools/src/CMakeLists.txt
View File

@ -1,4 +1,4 @@
cmake_minimum_required(VERSION 2.6)
cmake_minimum_required(VERSION 3.10)
PROJECT(fritz-tools C)
ADD_DEFINITIONS(-Wall -Werror --std=gnu99 -Wmissing-declarations)

2
package/utils/jboot-tools/src/CMakeLists.txt
View File

@ -1,4 +1,4 @@
cmake_minimum_required(VERSION 2.6)
cmake_minimum_required(VERSION 3.10)
PROJECT(jboot-tools C)
ADD_DEFINITIONS(-Wall -Werror --std=gnu99 -Wmissing-declarations)

2
package/utils/uencrypt/src/CMakeLists.txt
View File

@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# Copyright (C) 2022 Eneas Ulir de Queiroz
cmake_minimum_required(VERSION 2.8.12 FATAL_ERROR)
cmake_minimum_required(VERSION 3.10)
project(uencrypt LANGUAGES C)
option(USE_WOLFSSL "Use WolfSSL as crypto provider" OFF)

435
target/linux/airoha/patches-6.12/028-v6.13-spi-airoha-do-not-keep-tx-rx-dma-buffer-always-mappe.patch
View File

@ -1,435 +0,0 @@
From 7a4b3ebf1d60349587fee21872536e7bd6a4cf39 Mon Sep 17 00:00:00 2001
From: Lorenzo Bianconi <lorenzo@kernel.org>
Date: Sun, 22 Sep 2024 19:38:30 +0200
Subject: [PATCH] spi: airoha: do not keep {tx,rx} dma buffer always mapped
DMA map txrx_buf on demand in airoha_snand_dirmap_read and
airoha_snand_dirmap_write routines and do not keep it always mapped.
This patch is not fixing any bug or introducing any functional change
to the driver, it just simplifies the code and improve code readability
without introducing any performance degradation according to the results
obtained from the mtd_speedtest kernel module test.
root@OpenWrt:# insmod mtd_test.ko
root@OpenWrt:# insmod mtd_speedtest.ko dev=5
[ 49.849869] =================================================
[ 49.855659] mtd_speedtest: MTD device: 5
[ 49.859583] mtd_speedtest: MTD device size 8388608, eraseblock size 131072, page size 2048, count of eraseblocks 64, pages per eraseblock 64, OOB size 128
[ 49.874622] mtd_test: scanning for bad eraseblocks
[ 49.879433] mtd_test: scanned 64 eraseblocks, 0 are bad
[ 50.106372] mtd_speedtest: testing eraseblock write speed
[ 53.083380] mtd_speedtest: eraseblock write speed is 2756 KiB/s
[ 53.089322] mtd_speedtest: testing eraseblock read speed
[ 54.143360] mtd_speedtest: eraseblock read speed is 7811 KiB/s
[ 54.370365] mtd_speedtest: testing page write speed
[ 57.349480] mtd_speedtest: page write speed is 2754 KiB/s
[ 57.354895] mtd_speedtest: testing page read speed
[ 58.410431] mtd_speedtest: page read speed is 7796 KiB/s
[ 58.636805] mtd_speedtest: testing 2 page write speed
[ 61.612427] mtd_speedtest: 2 page write speed is 2757 KiB/s
[ 61.618021] mtd_speedtest: testing 2 page read speed
[ 62.672653] mtd_speedtest: 2 page read speed is 7804 KiB/s
[ 62.678159] mtd_speedtest: Testing erase speed
[ 62.903617] mtd_speedtest: erase speed is 37063 KiB/s
[ 62.908678] mtd_speedtest: Testing 2x multi-block erase speed
[ 63.134083] mtd_speedtest: 2x multi-block erase speed is 37292 KiB/s
[ 63.140442] mtd_speedtest: Testing 4x multi-block erase speed
[ 63.364262] mtd_speedtest: 4x multi-block erase speed is 37566 KiB/s
[ 63.370632] mtd_speedtest: Testing 8x multi-block erase speed
[ 63.595740] mtd_speedtest: 8x multi-block erase speed is 37344 KiB/s
[ 63.602089] mtd_speedtest: Testing 16x multi-block erase speed
[ 63.827426] mtd_speedtest: 16x multi-block erase speed is 37320 KiB/s
[ 63.833860] mtd_speedtest: Testing 32x multi-block erase speed
[ 64.059389] mtd_speedtest: 32x multi-block erase speed is 37288 KiB/s
[ 64.065833] mtd_speedtest: Testing 64x multi-block erase speed
[ 64.290609] mtd_speedtest: 64x multi-block erase speed is 37415 KiB/s
[ 64.297063] mtd_speedtest: finished
[ 64.300555] =================================================
Tested-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20240922-airoha-spi-fixes-v3-1-f958802b3d68@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
---
drivers/spi/spi-airoha-snfi.c | 154 ++++++++++++++++------------------
1 file changed, 71 insertions(+), 83 deletions(-)
--- a/drivers/spi/spi-airoha-snfi.c
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -206,13 +206,6 @@ enum airoha_snand_cs {
SPI_CHIP_SEL_LOW,
};
-struct airoha_snand_dev {
- size_t buf_len;
-
- u8 *txrx_buf;
- dma_addr_t dma_addr;
-};
-
struct airoha_snand_ctrl {
struct device *dev;
struct regmap *regmap_ctrl;
@@ -617,9 +610,9 @@ static bool airoha_snand_supports_op(str
static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
- struct airoha_snand_dev *as_dev = spi_get_ctldata(desc->mem->spi);
+ u8 *txrx_buf = spi_get_ctldata(desc->mem->spi);
- if (!as_dev->txrx_buf)
+ if (!txrx_buf)
return -EINVAL;
if (desc->info.offset + desc->info.length > U32_MAX)
@@ -634,10 +627,11 @@ static int airoha_snand_dirmap_create(st
static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, void *buf)
{
- struct spi_device *spi = desc->mem->spi;
- struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct spi_device *spi = desc->mem->spi;
struct airoha_snand_ctrl *as_ctrl;
+ u8 *txrx_buf = spi_get_ctldata(spi);
+ dma_addr_t dma_addr;
u32 val, rd_mode;
int err;
@@ -662,14 +656,17 @@ static ssize_t airoha_snand_dirmap_read(
if (err)
return err;
- dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
- as_dev->buf_len, DMA_BIDIRECTIONAL);
+ dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE,
+ DMA_FROM_DEVICE);
+ err = dma_mapping_error(as_ctrl->dev, dma_addr);
+ if (err)
+ return err;
/* set dma addr */
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
- as_dev->dma_addr);
+ dma_addr);
if (err)
- return err;
+ goto error_dma_unmap;
/* set cust sec size */
val = as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num;
@@ -678,58 +675,58 @@ static ssize_t airoha_snand_dirmap_read(
REG_SPI_NFI_SNF_MISC_CTL2,
SPI_NFI_READ_DATA_BYTE_NUM, val);
if (err)
- return err;
+ goto error_dma_unmap;
/* set read command */
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL2,
op->cmd.opcode);
if (err)
- return err;
+ goto error_dma_unmap;
/* set read mode */
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, rd_mode));
if (err)
- return err;
+ goto error_dma_unmap;
/* set read addr */
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0);
if (err)
- return err;
+ goto error_dma_unmap;
/* set nfi read */
err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
SPI_NFI_OPMODE,
FIELD_PREP(SPI_NFI_OPMODE, 6));
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
SPI_NFI_READ_MODE | SPI_NFI_DMA_MODE);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x0);
if (err)
- return err;
+ goto error_dma_unmap;
/* trigger dma start read */
err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
SPI_NFI_RD_TRIG);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
SPI_NFI_RD_TRIG);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
REG_SPI_NFI_SNF_STA_CTL1, val,
(val & SPI_NFI_READ_FROM_CACHE_DONE),
0, 1 * USEC_PER_SEC);
if (err)
- return err;
+ goto error_dma_unmap;
/*
* SPI_NFI_READ_FROM_CACHE_DONE bit must be written at the end
@@ -739,35 +736,41 @@ static ssize_t airoha_snand_dirmap_read(
SPI_NFI_READ_FROM_CACHE_DONE,
SPI_NFI_READ_FROM_CACHE_DONE);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
val, (val & SPI_NFI_AHB_DONE), 0,
1 * USEC_PER_SEC);
if (err)
- return err;
+ goto error_dma_unmap;
/* DMA read need delay for data ready from controller to DRAM */
udelay(1);
- dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
- as_dev->buf_len, DMA_BIDIRECTIONAL);
+ dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
+ DMA_FROM_DEVICE);
err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
if (err < 0)
return err;
- memcpy(buf, as_dev->txrx_buf + offs, len);
+ memcpy(buf, txrx_buf + offs, len);
return len;
+
+error_dma_unmap:
+ dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
+ DMA_FROM_DEVICE);
+ return err;
}
static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, const void *buf)
{
- struct spi_device *spi = desc->mem->spi;
- struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct spi_device *spi = desc->mem->spi;
+ u8 *txrx_buf = spi_get_ctldata(spi);
struct airoha_snand_ctrl *as_ctrl;
+ dma_addr_t dma_addr;
u32 wr_mode, val;
int err;
@@ -776,19 +779,20 @@ static ssize_t airoha_snand_dirmap_write
if (err < 0)
return err;
- dma_sync_single_for_cpu(as_ctrl->dev, as_dev->dma_addr,
- as_dev->buf_len, DMA_BIDIRECTIONAL);
- memcpy(as_dev->txrx_buf + offs, buf, len);
- dma_sync_single_for_device(as_ctrl->dev, as_dev->dma_addr,
- as_dev->buf_len, DMA_BIDIRECTIONAL);
+ memcpy(txrx_buf + offs, buf, len);
+ dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE,
+ DMA_TO_DEVICE);
+ err = dma_mapping_error(as_ctrl->dev, dma_addr);
+ if (err)
+ return err;
err = airoha_snand_set_mode(as_ctrl, SPI_MODE_DMA);
if (err < 0)
- return err;
+ goto error_dma_unmap;
err = airoha_snand_nfi_config(as_ctrl);
if (err)
- return err;
+ goto error_dma_unmap;
if (op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_QUAD ||
op->cmd.opcode == SPI_NAND_OP_PROGRAM_LOAD_RAMDON_QUAD)
@@ -797,9 +801,9 @@ static ssize_t airoha_snand_dirmap_write
wr_mode = 0;
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
- as_dev->dma_addr);
+ dma_addr);
if (err)
- return err;
+ goto error_dma_unmap;
val = FIELD_PREP(SPI_NFI_PROG_LOAD_BYTE_NUM,
as_ctrl->nfi_cfg.sec_size * as_ctrl->nfi_cfg.sec_num);
@@ -807,65 +811,65 @@ static ssize_t airoha_snand_dirmap_write
REG_SPI_NFI_SNF_MISC_CTL2,
SPI_NFI_PROG_LOAD_BYTE_NUM, val);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL1,
FIELD_PREP(SPI_NFI_PG_LOAD_CMD,
op->cmd.opcode));
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_SNF_MISC_CTL,
FIELD_PREP(SPI_NFI_DATA_READ_WR_MODE, wr_mode));
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
SPI_NFI_READ_MODE);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_update_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
SPI_NFI_OPMODE,
FIELD_PREP(SPI_NFI_OPMODE, 3));
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CNFG,
SPI_NFI_DMA_MODE);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_CMD, 0x80);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_clear_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
SPI_NFI_WR_TRIG);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_set_bits(as_ctrl->regmap_nfi, REG_SPI_NFI_CON,
SPI_NFI_WR_TRIG);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_read_poll_timeout(as_ctrl->regmap_nfi, REG_SPI_NFI_INTR,
val, (val & SPI_NFI_AHB_DONE), 0,
1 * USEC_PER_SEC);
if (err)
- return err;
+ goto error_dma_unmap;
err = regmap_read_poll_timeout(as_ctrl->regmap_nfi,
REG_SPI_NFI_SNF_STA_CTL1, val,
(val & SPI_NFI_LOAD_TO_CACHE_DONE),
0, 1 * USEC_PER_SEC);
if (err)
- return err;
+ goto error_dma_unmap;
/*
* SPI_NFI_LOAD_TO_CACHE_DONE bit must be written at the end
@@ -875,13 +879,20 @@ static ssize_t airoha_snand_dirmap_write
SPI_NFI_LOAD_TO_CACHE_DONE,
SPI_NFI_LOAD_TO_CACHE_DONE);
if (err)
- return err;
+ goto error_dma_unmap;
+ dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
+ DMA_TO_DEVICE);
err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
if (err < 0)
return err;
return len;
+
+error_dma_unmap:
+ dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
+ DMA_TO_DEVICE);
+ return err;
}
static int airoha_snand_exec_op(struct spi_mem *mem,
@@ -956,42 +967,20 @@ static const struct spi_controller_mem_o
static int airoha_snand_setup(struct spi_device *spi)
{
struct airoha_snand_ctrl *as_ctrl;
- struct airoha_snand_dev *as_dev;
-
- as_ctrl = spi_controller_get_devdata(spi->controller);
-
- as_dev = devm_kzalloc(as_ctrl->dev, sizeof(*as_dev), GFP_KERNEL);
- if (!as_dev)
- return -ENOMEM;
+ u8 *txrx_buf;
/* prepare device buffer */
- as_dev->buf_len = SPI_NAND_CACHE_SIZE;
- as_dev->txrx_buf = devm_kzalloc(as_ctrl->dev, as_dev->buf_len,
- GFP_KERNEL);
- if (!as_dev->txrx_buf)
- return -ENOMEM;
-
- as_dev->dma_addr = dma_map_single(as_ctrl->dev, as_dev->txrx_buf,
- as_dev->buf_len, DMA_BIDIRECTIONAL);
- if (dma_mapping_error(as_ctrl->dev, as_dev->dma_addr))
+ as_ctrl = spi_controller_get_devdata(spi->controller);
+ txrx_buf = devm_kzalloc(as_ctrl->dev, SPI_NAND_CACHE_SIZE,
+ GFP_KERNEL);
+ if (!txrx_buf)
return -ENOMEM;
- spi_set_ctldata(spi, as_dev);
+ spi_set_ctldata(spi, txrx_buf);
return 0;
}
-static void airoha_snand_cleanup(struct spi_device *spi)
-{
- struct airoha_snand_dev *as_dev = spi_get_ctldata(spi);
- struct airoha_snand_ctrl *as_ctrl;
-
- as_ctrl = spi_controller_get_devdata(spi->controller);
- dma_unmap_single(as_ctrl->dev, as_dev->dma_addr,
- as_dev->buf_len, DMA_BIDIRECTIONAL);
- spi_set_ctldata(spi, NULL);
-}
-
static int airoha_snand_nfi_setup(struct airoha_snand_ctrl *as_ctrl)
{
u32 val, sec_size, sec_num;
@@ -1093,7 +1082,6 @@ static int airoha_snand_probe(struct pla
ctrl->bits_per_word_mask = SPI_BPW_MASK(8);
ctrl->mode_bits = SPI_RX_DUAL;
ctrl->setup = airoha_snand_setup;
- ctrl->cleanup = airoha_snand_cleanup;
device_set_node(&ctrl->dev, dev_fwnode(dev));
err = airoha_snand_nfi_setup(as_ctrl);

33
target/linux/airoha/patches-6.12/029-01-spi-airoha-return-an-error-for-continuous-mode-di.patch
View File

@ -1,33 +0,0 @@
From 4aac08add11979d838335ebff0dc42c532f05c98 Mon Sep 17 00:00:00 2001
From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Date: Mon, 4 Aug 2025 21:45:46 +0300
Subject: [PATCH v6 01/13] spi: airoha: return an error for continuous mode
dirmap creation cases
This driver can accelerate single page operations only, thus
continuous reading mode should not be used.
Continuous reading will use sizes up to the size of one erase block.
This size is much larger than the size of single flash page. Use this
difference to identify continuous reading and return an error.
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/spi/spi-airoha-snfi.c | 4 ++++
1 file changed, 4 insertions(+)
--- a/drivers/spi/spi-airoha-snfi.c
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -618,6 +618,10 @@ static int airoha_snand_dirmap_create(st
if (desc->info.offset + desc->info.length > U32_MAX)
return -EINVAL;
+ /* continuous reading is not supported */
+ if (desc->info.length > SPI_NAND_CACHE_SIZE)
+ return -E2BIG;
+
if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl))
return -EOPNOTSUPP;

2
target/linux/airoha/patches-6.12/029-02-spi-airoha-remove-unnecessary-restriction-length.patch
View File

@ -15,7 +15,7 @@ Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com
--- a/drivers/spi/spi-airoha-snfi.c
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -579,13 +579,6 @@ static int airoha_snand_adjust_op_size(s
@@ -619,13 +619,6 @@ static int airoha_snand_adjust_op_size(s
if (op->data.nbytes > max_len)
op->data.nbytes = max_len;

209
target/linux/airoha/patches-6.12/029-03-spi-airoha-add-support-of-dual-quad-wires-spi-mod.patch
View File

@ -1,209 +0,0 @@
From 703b10241666b468484a6ec5eb5c7c71fb2463ef Mon Sep 17 00:00:00 2001
From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Date: Sat, 7 Jun 2025 09:09:38 +0300
Subject: [PATCH v6 03/13] spi: airoha: add support of dual/quad wires spi
modes to exec_op() handler
Booting without this patch and disabled dirmap support results in
[ 2.980719] spi-nand spi0.0: Micron SPI NAND was found.
[ 2.986040] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
[ 2.994709] 2 fixed-partitions partitions found on MTD device spi0.0
[ 3.001075] Creating 2 MTD partitions on "spi0.0":
[ 3.005862] 0x000000000000-0x000000020000 : "bl2"
[ 3.011272] 0x000000020000-0x000010000000 : "ubi"
...
[ 6.195594] ubi0: attaching mtd1
[ 13.338398] ubi0: scanning is finished
[ 13.342188] ubi0 error: ubi_read_volume_table: the layout volume was not found
[ 13.349784] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22
[ 13.356897] UBI error: cannot attach mtd1
If dirmap is disabled or not supported in the spi driver, the dirmap requests
will be executed via exec_op() handler. Thus, if the hardware supports
dual/quad spi modes, then corresponding requests will be sent to exec_op()
handler. Current driver does not support such requests, so error is arrised.
As result the flash can't be read/write.
This patch adds support of dual and quad wires spi modes to exec_op() handler.
Fixes: a403997c12019 ("spi: airoha: add SPI-NAND Flash controller driver")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/spi/spi-airoha-snfi.c | 108 ++++++++++++++++++++++++++--------
1 file changed, 82 insertions(+), 26 deletions(-)
--- a/drivers/spi/spi-airoha-snfi.c
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -192,6 +192,14 @@
#define SPI_NAND_OP_RESET 0xff
#define SPI_NAND_OP_DIE_SELECT 0xc2
+/* SNAND FIFO commands */
+#define SNAND_FIFO_TX_BUSWIDTH_SINGLE 0x08
+#define SNAND_FIFO_TX_BUSWIDTH_DUAL 0x09
+#define SNAND_FIFO_TX_BUSWIDTH_QUAD 0x0a
+#define SNAND_FIFO_RX_BUSWIDTH_SINGLE 0x0c
+#define SNAND_FIFO_RX_BUSWIDTH_DUAL 0x0e
+#define SNAND_FIFO_RX_BUSWIDTH_QUAD 0x0f
+
#define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
#define SPI_MAX_TRANSFER_SIZE 511
@@ -387,10 +395,26 @@ static int airoha_snand_set_mode(struct
return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
}
-static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
- const u8 *data, int len)
+static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl,
+ const u8 *data, int len, int buswidth)
{
int i, data_len;
+ u8 cmd;
+
+ switch (buswidth) {
+ case 0:
+ case 1:
+ cmd = SNAND_FIFO_TX_BUSWIDTH_SINGLE;
+ break;
+ case 2:
+ cmd = SNAND_FIFO_TX_BUSWIDTH_DUAL;
+ break;
+ case 4:
+ cmd = SNAND_FIFO_TX_BUSWIDTH_QUAD;
+ break;
+ default:
+ return -EINVAL;
+ }
for (i = 0; i < len; i += data_len) {
int err;
@@ -409,16 +433,32 @@ static int airoha_snand_write_data(struc
return 0;
}
-static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
- int len)
+static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl,
+ u8 *data, int len, int buswidth)
{
int i, data_len;
+ u8 cmd;
+
+ switch (buswidth) {
+ case 0:
+ case 1:
+ cmd = SNAND_FIFO_RX_BUSWIDTH_SINGLE;
+ break;
+ case 2:
+ cmd = SNAND_FIFO_RX_BUSWIDTH_DUAL;
+ break;
+ case 4:
+ cmd = SNAND_FIFO_RX_BUSWIDTH_QUAD;
+ break;
+ default:
+ return -EINVAL;
+ }
for (i = 0; i < len; i += data_len) {
int err;
data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
- err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
+ err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
if (err)
return err;
@@ -895,12 +935,28 @@ error_dma_unmap:
static int airoha_snand_exec_op(struct spi_mem *mem,
const struct spi_mem_op *op)
{
- u8 data[8], cmd, opcode = op->cmd.opcode;
struct airoha_snand_ctrl *as_ctrl;
+ int op_len, addr_len, dummy_len;
+ u8 buf[20], *data;
int i, err;
as_ctrl = spi_controller_get_devdata(mem->spi->controller);
+ op_len = op->cmd.nbytes;
+ addr_len = op->addr.nbytes;
+ dummy_len = op->dummy.nbytes;
+
+ if (op_len + dummy_len + addr_len > sizeof(buf))
+ return -EIO;
+
+ data = buf;
+ for (i = 0; i < op_len; i++)
+ *data++ = op->cmd.opcode >> (8 * (op_len - i - 1));
+ for (i = 0; i < addr_len; i++)
+ *data++ = op->addr.val >> (8 * (addr_len - i - 1));
+ for (i = 0; i < dummy_len; i++)
+ *data++ = 0xff;
+
/* switch to manual mode */
err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
if (err < 0)
@@ -911,40 +967,40 @@ static int airoha_snand_exec_op(struct s
return err;
/* opcode */
- err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode));
+ data = buf;
+ err = airoha_snand_write_data(as_ctrl, data, op_len,
+ op->cmd.buswidth);
if (err)
return err;
/* addr part */
- cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
- put_unaligned_be64(op->addr.val, data);
-
- for (i = ARRAY_SIZE(data) - op->addr.nbytes;
- i < ARRAY_SIZE(data); i++) {
- err = airoha_snand_write_data(as_ctrl, cmd, &data[i],
- sizeof(data[0]));
+ data += op_len;
+ if (addr_len) {
+ err = airoha_snand_write_data(as_ctrl, data, addr_len,
+ op->addr.buswidth);
if (err)
return err;
}
/* dummy */
- data[0] = 0xff;
- for (i = 0; i < op->dummy.nbytes; i++) {
- err = airoha_snand_write_data(as_ctrl, 0x8, &data[0],
- sizeof(data[0]));
+ data += addr_len;
+ if (dummy_len) {
+ err = airoha_snand_write_data(as_ctrl, data, dummy_len,
+ op->dummy.buswidth);
if (err)
return err;
}
/* data */
- if (op->data.dir == SPI_MEM_DATA_IN) {
- err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
- op->data.nbytes);
- if (err)
- return err;
- } else {
- err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out,
- op->data.nbytes);
+ if (op->data.nbytes) {
+ if (op->data.dir == SPI_MEM_DATA_IN)
+ err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
+ op->data.nbytes,
+ op->data.buswidth);
+ else
+ err = airoha_snand_write_data(as_ctrl, op->data.buf.out,
+ op->data.nbytes,
+ op->data.buswidth);
if (err)
return err;
}

2
target/linux/airoha/patches-6.12/029-04-spi-airoha-remove-unnecessary-switch-to-non-dma-m.patch
View File

@ -17,7 +17,7 @@ Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com
--- a/drivers/spi/spi-airoha-snfi.c
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -812,9 +812,6 @@ static ssize_t airoha_snand_dirmap_write
@@ -815,9 +815,6 @@ static ssize_t airoha_snand_dirmap_write
int err;
as_ctrl = spi_controller_get_devdata(spi->controller);

54
target/linux/airoha/patches-6.12/029-05-spi-airoha-switch-back-to-non-dma-mode-in-the-cas.patch
View File

@ -1,54 +0,0 @@
From 711584484d76448763959ed4e103895d9dcc7438 Mon Sep 17 00:00:00 2001
From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Date: Mon, 11 Aug 2025 20:24:42 +0300
Subject: [PATCH v6 05/13] spi: airoha: switch back to non-dma mode in the case
of error
Current dirmap code does not switch back to non-dma mode in the case of
error. This is wrong.
This patch fixes dirmap read/write error path.
Fixes: a403997c12019 ("spi: airoha: add SPI-NAND Flash controller driver")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/spi/spi-airoha-snfi.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
--- a/drivers/spi/spi-airoha-snfi.c
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -691,13 +691,13 @@ static ssize_t airoha_snand_dirmap_read(
err = airoha_snand_nfi_config(as_ctrl);
if (err)
- return err;
+ goto error_dma_mode_off;
dma_addr = dma_map_single(as_ctrl->dev, txrx_buf, SPI_NAND_CACHE_SIZE,
DMA_FROM_DEVICE);
err = dma_mapping_error(as_ctrl->dev, dma_addr);
if (err)
- return err;
+ goto error_dma_mode_off;
/* set dma addr */
err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_STRADDR,
@@ -797,6 +797,8 @@ static ssize_t airoha_snand_dirmap_read(
error_dma_unmap:
dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
DMA_FROM_DEVICE);
+error_dma_mode_off:
+ airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
return err;
}
@@ -926,6 +928,7 @@ static ssize_t airoha_snand_dirmap_write
error_dma_unmap:
dma_unmap_single(as_ctrl->dev, dma_addr, SPI_NAND_CACHE_SIZE,
DMA_TO_DEVICE);
+ airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
return err;
}

102
target/linux/airoha/patches-6.12/029-06-spi-airoha-fix-reading-writing-of-flashes-with-mo.patch
View File

@ -1,102 +0,0 @@
From d8a0a67bf75c4cf2a760b6fa0002b0baff6e8b20 Mon Sep 17 00:00:00 2001
From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Date: Mon, 11 Aug 2025 20:32:40 +0300
Subject: [PATCH v6 06/13] spi: airoha: fix reading/writing of flashes with
more than one plane per lun
Attaching UBI on the flash with more than one plane per lun will lead to
the following error:
[ 2.980989] spi-nand spi0.0: Micron SPI NAND was found.
[ 2.986309] spi-nand spi0.0: 256 MiB, block size: 128 KiB, page size: 2048, OOB size: 128
[ 2.994978] 2 fixed-partitions partitions found on MTD device spi0.0
[ 3.001350] Creating 2 MTD partitions on "spi0.0":
[ 3.006159] 0x000000000000-0x000000020000 : "bl2"
[ 3.011663] 0x000000020000-0x000010000000 : "ubi"
...
[ 6.391748] ubi0: attaching mtd1
[ 6.412545] ubi0 error: ubi_attach: PEB 0 contains corrupted VID header, and the data does not contain all 0xFF
[ 6.422677] ubi0 error: ubi_attach: this may be a non-UBI PEB or a severe VID header corruption which requires manual inspection
[ 6.434249] Volume identifier header dump:
[ 6.438349] magic 55424923
[ 6.441482] version 1
[ 6.444007] vol_type 0
[ 6.446539] copy_flag 0
[ 6.449068] compat 0
[ 6.451594] vol_id 0
[ 6.454120] lnum 1
[ 6.456651] data_size 4096
[ 6.459442] used_ebs 1061644134
[ 6.462748] data_pad 0
[ 6.465274] sqnum 0
[ 6.467805] hdr_crc 61169820
[ 6.470943] Volume identifier header hexdump:
[ 6.475308] hexdump of PEB 0 offset 4096, length 126976
[ 6.507391] ubi0 warning: ubi_attach: valid VID header but corrupted EC header at PEB 4
[ 6.515415] ubi0 error: ubi_compare_lebs: unsupported on-flash UBI format
[ 6.522222] ubi0 error: ubi_attach_mtd_dev: failed to attach mtd1, error -22
[ 6.529294] UBI error: cannot attach mtd1
Non dirmap reading works good. Looking to spi_mem_no_dirmap_read() code we'll see:
static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, void *buf)
{
struct spi_mem_op op = desc->info.op_tmpl;
int ret;
// --- see here ---
op.addr.val = desc->info.offset + offs;
//-----------------
op.data.buf.in = buf;
op.data.nbytes = len;
ret = spi_mem_adjust_op_size(desc->mem, &op);
if (ret)
return ret;
ret = spi_mem_exec_op(desc->mem, &op);
if (ret)
return ret;
return op.data.nbytes;
}
The similar happens for spi_mem_no_dirmap_write(). Thus the address
passed to the flash should take in the account the value of
desc->info.offset.
This patch fix dirmap reading/writing of flashes with more than one
plane per lun.
Fixes: a403997c12019 ("spi: airoha: add SPI-NAND Flash controller driver")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/spi/spi-airoha-snfi.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
--- a/drivers/spi/spi-airoha-snfi.c
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -726,8 +726,9 @@ static ssize_t airoha_snand_dirmap_read(
if (err)
goto error_dma_unmap;
- /* set read addr */
- err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3, 0x0);
+ /* set read addr: zero page offset + descriptor read offset */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_RD_CTL3,
+ desc->info.offset);
if (err)
goto error_dma_unmap;
@@ -860,7 +861,9 @@ static ssize_t airoha_snand_dirmap_write
if (err)
goto error_dma_unmap;
- err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2, 0x0);
+ /* set write addr: zero page offset + descriptor write offset */
+ err = regmap_write(as_ctrl->regmap_nfi, REG_SPI_NFI_PG_CTL2,
+ desc->info.offset);
if (err)
goto error_dma_unmap;

578
target/linux/airoha/patches-6.12/108-pwm-airoha-Add-support-for-EN7581-SoC.patch → target/linux/airoha/patches-6.12/107-v6.19-pwm-airoha-Add-support-for-EN7581-SoC.patch
View File

@ -1,155 +1,47 @@
From: Christian Marangi <ansuelsmth@gmail.com>
To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,
linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org
Cc: Benjamin Larsson <benjamin.larsson@genexis.eu>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
Lorenzo Bianconi <lorenzo@kernel.org>,
Christian Marangi <ansuelsmth@gmail.com>
Subject: [PATCH v13] pwm: airoha: Add support for EN7581 SoC
Date: Sat, 10 May 2025 00:36:52 +0200
Message-ID: <20250509223653.8800-1-ansuelsmth@gmail.com>
X-Mailer: git-send-email 2.48.1
Precedence: bulk
X-Mailing-List: linux-pwm@vger.kernel.org
List-Id: <linux-pwm.vger.kernel.org>
List-Subscribe: <mailto:linux-pwm+subscribe@vger.kernel.org>
List-Unsubscribe: <mailto:linux-pwm+unsubscribe@vger.kernel.org>
MIME-Version: 1.0
From 61d7c2f94d391594de08d8a52a7c2630d2f3d263 Mon Sep 17 00:00:00 2001
From: Benjamin Larsson <benjamin.larsson@genexis.eu>
Date: Mon, 13 Oct 2025 12:34:03 +0200
Subject: [PATCH] pwm: airoha: Add support for EN7581 SoC
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
Introduce driver for PWM module available on EN7581 SoC.
Limitations:
- Only 8 concurrent waveform generators are available for 8 combinations of
duty_cycle and period. Waveform generators are shared between 16 GPIO
pins and 17 SIPO GPIO pins.
- Supports only normal polarity.
- On configuration the currently running period is completed.
- Minimum supported period is 4 ms
- Maximum supported period is 1s
Signed-off-by: Benjamin Larsson <benjamin.larsson@genexis.eu>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://patch.msgid.link/20251013103408.14724-1-ansuelsmth@gmail.com
Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org>
---
Changes v13:
- Reorder include
- Split ticks_from_ns function
- Add additional comments for shift register chip clock
- Address suggested minor optimization (Uwe)
Changes v12:
- Make shift function more readable
- Use unsigned int where possible
- Better comment some SIPO strangeness
- Move SIPO init after flash map config
- Retrun real values in get_state instead of the
one saved in bucket
- Improve period_ns parsing so we can better share generators
Changes v11:
- Fix wrong calculation of period and duty
- Use AIROHA_PWM prefix for each define
- Drop set/get special define in favour of BITS and GENMASK
- Correctly use dev_err_probe
- Init bucket with initial values
- Rework define to make use of FIELD_PREP and FIELD_GET
Changes in v10:
- repost just patch 6/6 (pwm driver) since patches {1/6-5/6} have been
already applied in linux-pinctrl tree
- pwm: introduce AIROHA_PWM_FIELD_GET and AIROHA_PWM_FIELD_SET macros to
get/set field with non-const mask
- pwm: simplify airoha_pwm_get_generator() to report unused generator
and remove double lookup
- pwm: remove device_node pointer in airoha_pwm struct since this is
write-only field
- pwm: cosmetics
- Link to v9: https://lore.kernel.org/r/20241023-en7581-pinctrl-v9-0-afb0cbcab0ec@kernel.org
Changes in v9:
- pwm: remove unused properties
- Link to v8: https://lore.kernel.org/r/20241018-en7581-pinctrl-v8-0-b676b966a1d1@kernel.org
Changes in v8:
- pwm: add missing properties documentation
- Link to v7: https://lore.kernel.org/r/20241016-en7581-pinctrl-v7-0-4ff611f263a7@kernel.org
Changes in v7:
- pinctrl: cosmetics
- pinctrl: fix compilation warning
- Link to v6: https://lore.kernel.org/r/20241013-en7581-pinctrl-v6-0-2048e2d099c2@kernel.org
Changes in v6:
- pwm: rely on regmap APIs
- pwm: introduce compatible string
- pinctrl: introduce compatible string
- remove airoha-mfd driver
- add airoha,en7581-pinctrl binding
- add airoha,en7581-pwm binding
- update airoha,en7581-gpio-sysctl binding
- Link to v5: https://lore.kernel.org/r/20241001-en7581-pinctrl-v5-0-dc1ce542b6c6@kernel.org
Changes in v5:
- use spin_lock in airoha_pinctrl_rmw instead of a mutex since it can run
in interrupt context
- remove unused includes in pinctrl driver
- since the irq_chip is immutable, allocate the gpio_irq_chip struct
statically in pinctrl driver
- rely on regmap APIs in pinctrl driver but keep the spin_lock local to the
driver
- rely on guard/guard_scope APIs in pinctrl driver
- improve naming convention pinctrl driver
- introduce airoha_pinconf_set_pin_value utility routine
- Link to v4: https://lore.kernel.org/r/20240911-en7581-pinctrl-v4-0-60ac93d760bb@kernel.org
Changes in v4:
- add 'Limitation' description in pwm driver
- fix comments in pwm driver
- rely on mfd->base __iomem pointer in pwm driver, modify register
offsets according to it and get rid of sgpio_cfg, flash_cfg and
cycle_cfg pointers
- simplify register utility routines in pwm driver
- use 'generator' instead of 'waveform' suffix for pwm routines
- fix possible overflow calculating duty cycle in pwm driver
- do not modify pwm state in free callback in pwm driver
- cap the maximum period in pwm driver
- do not allow inverse polarity in pwm driver
- do not set of_xlate callback in the pwm driver and allow the stack to
do it
- fix MAINTAINERS file for airoha pinctrl driver
- fix undefined reference to __ffsdi2 in pinctrl driver
- simplify airoha,en7581-gpio-sysctl.yam binding
- Link to v3: https://lore.kernel.org/r/20240831-en7581-pinctrl-v3-0-98eebfb4da66@kernel.org
Changes in v3:
- introduce airoha-mfd driver
- add pwm driver to the same series
- model pinctrl and pwm drivers as childs of a parent mfd driver.
- access chip-scu memory region in pinctrl driver via syscon
- introduce a single airoha,en7581-gpio-sysctl.yaml binding and get rid
of dedicated bindings for pinctrl and pwm
- add airoha,en7581-chip-scu.yaml binding do the series
- Link to v2: https://lore.kernel.org/r/20240822-en7581-pinctrl-v2-0-ba1559173a7f@kernel.org
Changes in v2:
- Fix compilation errors
- Collapse some register mappings for gpio and irq controllers
- update dt-bindings according to new register mapping
- fix some dt-bindings errors
- Link to v1: https://lore.kernel.org/all/cover.1723392444.git.lorenzo@kernel.org/
drivers/pwm/Kconfig | 11 +
drivers/pwm/Kconfig | 10 +
drivers/pwm/Makefile | 1 +
drivers/pwm/pwm-airoha.c | 536 +++++++++++++++++++++++++++++++++++++++
3 files changed, 548 insertions(+)
drivers/pwm/pwm-airoha.c | 622 +++++++++++++++++++++++++++++++++++++++
3 files changed, 633 insertions(+)
create mode 100644 drivers/pwm/pwm-airoha.c
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -54,6 +54,17 @@ config PWM_ADP5585
@@ -54,6 +54,16 @@ config PWM_ADP5585
This option enables support for the PWM function found in the Analog
Devices ADP5585.
+config PWM_AIROHA
+ tristate "Airoha PWM support"
+ depends on ARCH_AIROHA || COMPILE_TEST
+ depends on OF
+ select REGMAP_MMIO
+ help
+ Generic PWM framework driver for Airoha SoC.
@ -172,10 +64,11 @@ Changes in v2:
obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o
--- /dev/null
+++ b/drivers/pwm/pwm-airoha.c
@@ -0,0 +1,536 @@
@@ -0,0 +1,622 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Markus Gothe <markus.gothe@genexis.eu>
+ * Copyright 2025 Christian Marangi <ansuelsmth@gmail.com>
+ *
+ * Limitations:
+ * - Only 8 concurrent waveform generators are available for 8 combinations of
@ -183,23 +76,24 @@ Changes in v2:
+ * pins and 17 SIPO GPIO pins.
+ * - Supports only normal polarity.
+ * - On configuration the currently running period is completed.
+ * - Minimum supported period is 4ms
+ * - Minimum supported period is 4 ms
+ * - Maximum supported period is 1s
+ */
+
+#include <linux/array_size.h>
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/bitmap.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/math64.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#define AIROHA_PWM_REG_SGPIO_LED_DATA 0x0024
+#define AIROHA_PWM_SGPIO_LED_DATA_SHIFT_FLAG BIT(31)
@ -207,10 +101,10 @@ Changes in v2:
+
+#define AIROHA_PWM_REG_SGPIO_CLK_DIVR 0x0028
+#define AIROHA_PWM_SGPIO_CLK_DIVR GENMASK(1, 0)
+#define AIROHA_PWM_SGPIO_CLK_DIVR_32 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0x3)
+#define AIROHA_PWM_SGPIO_CLK_DIVR_16 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0x2)
+#define AIROHA_PWM_SGPIO_CLK_DIVR_8 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0x1)
+#define AIROHA_PWM_SGPIO_CLK_DIVR_4 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0x0)
+#define AIROHA_PWM_SGPIO_CLK_DIVR_32 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 3)
+#define AIROHA_PWM_SGPIO_CLK_DIVR_16 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 2)
+#define AIROHA_PWM_SGPIO_CLK_DIVR_8 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 1)
+#define AIROHA_PWM_SGPIO_CLK_DIVR_4 FIELD_PREP_CONST(AIROHA_PWM_SGPIO_CLK_DIVR, 0)
+
+#define AIROHA_PWM_REG_SGPIO_CLK_DLY 0x002c
+
@ -237,9 +131,9 @@ Changes in v2:
+
+/* GPIO/SIPO flash map handles 8 pins in one register */
+#define AIROHA_PWM_PINS_PER_FLASH_MAP 8
+/* Cycle cfg handles 4 generators in one register */
+/* Cycle(Period) registers handles 4 generators in one 32-bit register */
+#define AIROHA_PWM_BUCKET_PER_CYCLE_CFG 4
+/* Flash producer handles 2 generators in one register */
+/* Flash(Duty) producer handles 2 generators in one 32-bit register */
+#define AIROHA_PWM_BUCKET_PER_FLASH_PROD 2
+
+#define AIROHA_PWM_NUM_BUCKETS 8
@ -254,16 +148,16 @@ Changes in v2:
+#define AIROHA_PWM_MAX_CHANNELS (AIROHA_PWM_NUM_GPIO + AIROHA_PWM_NUM_SIPO)
+
+struct airoha_pwm_bucket {
+ /* Bitmask of PWM channels using this bucket */
+ u64 used;
+ u64 period_ns;
+ u64 duty_ns;
+ /* Concurrent access protected by PWM core */
+ int used;
+ u32 period_ticks;
+ u32 duty_ticks;
+};
+
+struct airoha_pwm {
+ struct regmap *regmap;
+
+ u64 initialized;
+ DECLARE_BITMAP(initialized, AIROHA_PWM_MAX_CHANNELS);
+
+ struct airoha_pwm_bucket buckets[AIROHA_PWM_NUM_BUCKETS];
+
@ -304,93 +198,138 @@ Changes in v2:
+ }
+}
+
+static u32 airoha_pwm_get_period_ticks_from_ns(u64 period_ns)
+static u32 airoha_pwm_get_period_ticks_from_ns(u32 period_ns)
+{
+ return div_u64(period_ns, AIROHA_PWM_PERIOD_TICK_NS);
+ return period_ns / AIROHA_PWM_PERIOD_TICK_NS;
+}
+
+static u32 airoha_pwm_get_duty_ticks_from_ns(u64 period_ns, u64 duty_ns)
+static u32 airoha_pwm_get_duty_ticks_from_ns(u32 period_ns, u32 duty_ns)
+{
+ return mul_u64_u64_div_u64(duty_ns, AIROHA_PWM_DUTY_FULL,
+ period_ns);
+ return mul_u64_u32_div(duty_ns, AIROHA_PWM_DUTY_FULL, period_ns);
+}
+
+static void airoha_pwm_get_bucket(struct airoha_pwm *pc, int bucket,
+ u64 *period_ns, u64 *duty_ns)
+static u32 airoha_pwm_get_period_ns_from_ticks(u32 period_tick)
+{
+ u32 period_tick, duty_tick;
+ unsigned int offset;
+ u32 shift, val;
+ return period_tick * AIROHA_PWM_PERIOD_TICK_NS;
+}
+
+ offset = bucket / AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
+ shift = bucket % AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
+ shift = AIROHA_PWM_REG_CYCLE_CFG_SHIFT(shift);
+static u32 airoha_pwm_get_duty_ns_from_ticks(u32 period_tick, u32 duty_tick)
+{
+ u32 period_ns = period_tick * AIROHA_PWM_PERIOD_TICK_NS;
+
+ regmap_read(pc->regmap, AIROHA_PWM_REG_CYCLE_CFG_VALUE(offset), &val);
+
+ period_tick = FIELD_GET(AIROHA_PWM_WAVE_GEN_CYCLE, val >> shift);
+ *period_ns = period_tick * AIROHA_PWM_PERIOD_TICK_NS;
+
+ offset = bucket / AIROHA_PWM_BUCKET_PER_FLASH_PROD;
+ shift = bucket % AIROHA_PWM_BUCKET_PER_FLASH_PROD;
+ shift = AIROHA_PWM_REG_GPIO_FLASH_PRD_SHIFT(shift);
+
+ regmap_read(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
+ &val);
+
+ duty_tick = FIELD_GET(AIROHA_PWM_GPIO_FLASH_PRD_HIGH, val >> shift);
+ /*
+ * Overflow can't occur in multiplication as duty_tick is just 8 bit
+ * and period_ns is clamped to AIROHA_PWM_PERIOD_MAX_NS and fit in a
+ * u64.
+ */
+ *duty_ns = DIV_U64_ROUND_UP(duty_tick * *period_ns, AIROHA_PWM_DUTY_FULL);
+ return DIV_U64_ROUND_UP(duty_tick * period_ns, AIROHA_PWM_DUTY_FULL);
+}
+
+static int airoha_pwm_get_generator(struct airoha_pwm *pc, u64 duty_ns,
+ u64 period_ns)
+static int airoha_pwm_get_bucket(struct airoha_pwm *pc, int bucket,
+ u64 *period_ns, u64 *duty_ns)
+{
+ int i, best = -ENOENT, unused = -ENOENT;
+ struct regmap *map = pc->regmap;
+ u32 period_tick, duty_tick;
+ unsigned int offset;
+ u32 shift, val;
+ int ret;
+
+ offset = bucket / AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
+ shift = bucket % AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
+ shift = AIROHA_PWM_REG_CYCLE_CFG_SHIFT(shift);
+
+ ret = regmap_read(map, AIROHA_PWM_REG_CYCLE_CFG_VALUE(offset), &val);
+ if (ret)
+ return ret;
+
+ period_tick = FIELD_GET(AIROHA_PWM_WAVE_GEN_CYCLE, val >> shift);
+ *period_ns = airoha_pwm_get_period_ns_from_ticks(period_tick);
+
+ offset = bucket / AIROHA_PWM_BUCKET_PER_FLASH_PROD;
+ shift = bucket % AIROHA_PWM_BUCKET_PER_FLASH_PROD;
+ shift = AIROHA_PWM_REG_GPIO_FLASH_PRD_SHIFT(shift);
+
+ ret = regmap_read(map, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
+ &val);
+ if (ret)
+ return ret;
+
+ duty_tick = FIELD_GET(AIROHA_PWM_GPIO_FLASH_PRD_HIGH, val >> shift);
+ *duty_ns = airoha_pwm_get_duty_ns_from_ticks(period_tick, duty_tick);
+
+ return 0;
+}
+
+static int airoha_pwm_get_generator(struct airoha_pwm *pc, u32 duty_ticks,
+ u32 period_ticks)
+{
+ int best = -ENOENT, unused = -ENOENT;
+ u32 duty_ns, best_duty_ns = 0;
+ u32 best_period_ticks = 0;
+ unsigned int i;
+
+ duty_ns = airoha_pwm_get_duty_ns_from_ticks(period_ticks, duty_ticks);
+
+ for (i = 0; i < ARRAY_SIZE(pc->buckets); i++) {
+ struct airoha_pwm_bucket *bucket = &pc->buckets[i];
+ u32 duty_ticks, duty_ticks_bucket;
+ u32 bucket_period_ticks = bucket->period_ticks;
+ u32 bucket_duty_ticks = bucket->duty_ticks;
+
+ /* If found, save an unused bucket to return it later */
+ if (!bucket->used && unused == -ENOENT) {
+ if (!bucket->used) {
+ unused = i;
+ continue;
+ }
+
+ if (duty_ns == bucket->duty_ns) {
+ /* We found a matching bucket */
+ if (period_ns == bucket->period_ns)
+ /* We found a matching bucket, exit early */
+ if (duty_ticks == bucket_duty_ticks &&
+ period_ticks == bucket_period_ticks)
+ return i;
+
+ /*
+ * Save a bucket for later that is not bigger than the
+ * requested period_ns (to be used if we don't have
+ * any unused bucket)
+ */
+ if (bucket->period_ns <= period_ns)
+ best = i;
+ }
+
+ /*
+ * Unlike duty cycle zero, which can be handled by
+ * disabling PWM, a generator is needed for full duty
+ * cycle but it can be reused regardless of period
+ */
+ duty_ticks = airoha_pwm_get_duty_ticks_from_ns(period_ns, duty_ns);
+ duty_ticks_bucket = airoha_pwm_get_duty_ticks_from_ns(bucket->period_ns,
+ bucket->duty_ns);
+ if (duty_ticks == AIROHA_PWM_DUTY_FULL &&
+ duty_ticks_bucket == AIROHA_PWM_DUTY_FULL)
+ bucket_duty_ticks == AIROHA_PWM_DUTY_FULL)
+ return i;
+
+ /*
+ * With an unused bucket available, skip searching for
+ * a bucket to recycle (closer to the requested period/duty)
+ */
+ if (unused >= 0)
+ continue;
+
+ /* Ignore bucket with invalid period */
+ if (bucket_period_ticks > period_ticks)
+ continue;
+
+ /*
+ * Search for a bucket closer to the requested period
+ * that has the maximal possible period that isn't bigger
+ * than the requested period. For that period pick the maximal
+ * duty cycle that isn't bigger than the requested duty_cycle.
+ */
+ if (bucket_period_ticks >= best_period_ticks) {
+ u32 bucket_duty_ns = airoha_pwm_get_duty_ns_from_ticks(bucket_period_ticks,
+ bucket_duty_ticks);
+
+ /* Skip bucket that goes over the requested duty */
+ if (bucket_duty_ns > duty_ns)
+ continue;
+
+ if (bucket_duty_ns > best_duty_ns) {
+ best_period_ticks = bucket_period_ticks;
+ best_duty_ns = bucket_duty_ns;
+ best = i;
+ }
+ }
+ }
+
+ /* With no unused bucket, return the best one found (if ever) */
+ return unused == -ENOENT ? best : unused;
+ /* Return an unused bucket or the best one found (if ever) */
+ return unused >= 0 ? unused : best;
+}
+
+static void airoha_pwm_release_bucket_config(struct airoha_pwm *pc,
@ -399,32 +338,85 @@ Changes in v2:
+ int bucket;
+
+ /* Nothing to clear, PWM channel never used */
+ if (!(pc->initialized & BIT_ULL(hwpwm)))
+ if (!test_bit(hwpwm, pc->initialized))
+ return;
+
+ bucket = pc->channel_bucket[hwpwm];
+ pc->buckets[bucket].used &= ~BIT_ULL(hwpwm);
+ pc->buckets[bucket].used--;
+}
+
+static int airoha_pwm_apply_bucket_config(struct airoha_pwm *pc, unsigned int bucket,
+ u32 duty_ticks, u32 period_ticks)
+{
+ u32 mask, shift, val;
+ u32 offset;
+ int ret;
+
+ offset = bucket / AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
+ shift = bucket % AIROHA_PWM_BUCKET_PER_CYCLE_CFG;
+ shift = AIROHA_PWM_REG_CYCLE_CFG_SHIFT(shift);
+
+ /* Configure frequency divisor */
+ mask = AIROHA_PWM_WAVE_GEN_CYCLE << shift;
+ val = FIELD_PREP(AIROHA_PWM_WAVE_GEN_CYCLE, period_ticks) << shift;
+ ret = regmap_update_bits(pc->regmap, AIROHA_PWM_REG_CYCLE_CFG_VALUE(offset),
+ mask, val);
+ if (ret)
+ return ret;
+
+ offset = bucket / AIROHA_PWM_BUCKET_PER_FLASH_PROD;
+ shift = bucket % AIROHA_PWM_BUCKET_PER_FLASH_PROD;
+ shift = AIROHA_PWM_REG_GPIO_FLASH_PRD_SHIFT(shift);
+
+ /* Configure duty cycle */
+ mask = AIROHA_PWM_GPIO_FLASH_PRD_HIGH << shift;
+ val = FIELD_PREP(AIROHA_PWM_GPIO_FLASH_PRD_HIGH, duty_ticks) << shift;
+ ret = regmap_update_bits(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
+ mask, val);
+ if (ret)
+ return ret;
+
+ mask = AIROHA_PWM_GPIO_FLASH_PRD_LOW << shift;
+ val = FIELD_PREP(AIROHA_PWM_GPIO_FLASH_PRD_LOW,
+ AIROHA_PWM_DUTY_FULL - duty_ticks) << shift;
+ return regmap_update_bits(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
+ mask, val);
+}
+
+static int airoha_pwm_consume_generator(struct airoha_pwm *pc,
+ u64 duty_ns, u64 period_ns,
+ u32 duty_ticks, u32 period_ticks,
+ unsigned int hwpwm)
+{
+ int bucket;
+ bool config_bucket = false;
+ int bucket, ret;
+
+ /*
+ * Search for a bucket that already satisfy duty and period
+ * Search for a bucket that already satisfies duty and period
+ * or an unused one.
+ * If not found, -ENOENT is returned.
+ */
+ bucket = airoha_pwm_get_generator(pc, duty_ns, period_ns);
+ bucket = airoha_pwm_get_generator(pc, duty_ticks, period_ticks);
+ if (bucket < 0)
+ return bucket;
+
+ /* Release previous used bucket (if any) */
+ airoha_pwm_release_bucket_config(pc, hwpwm);
+ pc->buckets[bucket].used |= BIT_ULL(hwpwm);
+ pc->buckets[bucket].period_ns = period_ns;
+ pc->buckets[bucket].duty_ns = duty_ns;
+
+ if (!pc->buckets[bucket].used)
+ config_bucket = true;
+ pc->buckets[bucket].used++;
+
+ if (config_bucket) {
+ pc->buckets[bucket].period_ticks = period_ticks;
+ pc->buckets[bucket].duty_ticks = duty_ticks;
+ ret = airoha_pwm_apply_bucket_config(pc, bucket,
+ duty_ticks,
+ period_ticks);
+ if (ret) {
+ pc->buckets[bucket].used--;
+ return ret;
+ }
+ }
+
+ return bucket;
+}
@ -432,16 +424,18 @@ Changes in v2:
+static int airoha_pwm_sipo_init(struct airoha_pwm *pc)
+{
+ u32 val;
+ int ret;
+
+ if (!(pc->initialized >> AIROHA_PWM_NUM_GPIO))
+ return 0;
+
+ regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
+ ret = regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
+ AIROHA_PWM_SERIAL_GPIO_MODE_74HC164);
+ if (ret)
+ return ret;
+
+ /* Configure shift register chip clock timings, use 32x divisor */
+ regmap_write(pc->regmap, AIROHA_PWM_REG_SGPIO_CLK_DIVR,
+ ret = regmap_write(pc->regmap, AIROHA_PWM_REG_SGPIO_CLK_DIVR,
+ AIROHA_PWM_SGPIO_CLK_DIVR_32);
+ if (ret)
+ return ret;
+
+ /*
+ * Configure the shift register chip clock delay. This needs
@ -458,7 +452,9 @@ Changes in v2:
+ * From documentation is specified that clock delay should not be
+ * greater than (AIROHA_PWM_REG_SGPIO_CLK_DIVR / 2) - 1.
+ */
+ regmap_write(pc->regmap, AIROHA_PWM_REG_SGPIO_CLK_DLY, 0x0);
+ ret = regmap_write(pc->regmap, AIROHA_PWM_REG_SGPIO_CLK_DLY, 0);
+ if (ret)
+ return ret;
+
+ /*
+ * It is necessary to explicitly shift out all zeros after muxing
@ -466,103 +462,75 @@ Changes in v2:
+ * mode because in PWM mode SIPO will not start shifting until
+ * it needs to output a non-zero value (bit 31 of led_data
+ * indicates shifting in progress and it must return to zero
+ * before led_data can be written or PWM mode can be set)
+ * before led_data can be written or PWM mode can be set).
+ */
+ if (regmap_read_poll_timeout(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA, val,
+ ret = regmap_read_poll_timeout(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA, val,
+ !(val & AIROHA_PWM_SGPIO_LED_DATA_SHIFT_FLAG),
+ 10, 200 * USEC_PER_MSEC))
+ return -ETIMEDOUT;
+ 10, 200 * USEC_PER_MSEC);
+ if (ret)
+ return ret;
+
+ regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA,
+ ret = regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA,
+ AIROHA_PWM_SGPIO_LED_DATA_DATA);
+ if (regmap_read_poll_timeout(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA, val,
+ if (ret)
+ return ret;
+ ret = regmap_read_poll_timeout(pc->regmap, AIROHA_PWM_REG_SGPIO_LED_DATA, val,
+ !(val & AIROHA_PWM_SGPIO_LED_DATA_SHIFT_FLAG),
+ 10, 200 * USEC_PER_MSEC))
+ return -ETIMEDOUT;
+ 10, 200 * USEC_PER_MSEC);
+ if (ret)
+ return ret;
+
+ /* Set SIPO in PWM mode */
+ regmap_set_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
+ return regmap_set_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
+ AIROHA_PWM_SERIAL_GPIO_FLASH_MODE);
+
+ return 0;
+}
+
+static void airoha_pwm_calc_bucket_config(struct airoha_pwm *pc, int bucket,
+ u64 duty_ns, u64 period_ns)
+{
+ u32 period_ticks, duty_ticks;
+ u32 mask, shift, val;
+ u64 offset;
+
+ period_ticks = airoha_pwm_get_period_ticks_from_ns(period_ns);
+ duty_ticks = airoha_pwm_get_duty_ticks_from_ns(period_ns, duty_ns);
+
+ offset = bucket;
+ shift = do_div(offset, AIROHA_PWM_BUCKET_PER_CYCLE_CFG);
+ shift = AIROHA_PWM_REG_CYCLE_CFG_SHIFT(shift);
+
+ /* Configure frequency divisor */
+ mask = AIROHA_PWM_WAVE_GEN_CYCLE << shift;
+ val = FIELD_PREP(AIROHA_PWM_WAVE_GEN_CYCLE, period_ticks) << shift;
+ regmap_update_bits(pc->regmap, AIROHA_PWM_REG_CYCLE_CFG_VALUE(offset), mask, val);
+
+ offset = bucket;
+ shift = do_div(offset, AIROHA_PWM_BUCKET_PER_FLASH_PROD);
+ shift = AIROHA_PWM_REG_GPIO_FLASH_PRD_SHIFT(shift);
+
+ /* Configure duty cycle */
+ mask = AIROHA_PWM_GPIO_FLASH_PRD_HIGH << shift;
+ val = FIELD_PREP(AIROHA_PWM_GPIO_FLASH_PRD_HIGH, duty_ticks) << shift;
+ regmap_update_bits(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
+ mask, val);
+
+ mask = AIROHA_PWM_GPIO_FLASH_PRD_LOW << shift;
+ val = FIELD_PREP(AIROHA_PWM_GPIO_FLASH_PRD_LOW,
+ AIROHA_PWM_DUTY_FULL - duty_ticks) << shift;
+ regmap_update_bits(pc->regmap, AIROHA_PWM_REG_GPIO_FLASH_PRD_SET(offset),
+ mask, val);
+}
+
+static void airoha_pwm_config_flash_map(struct airoha_pwm *pc,
+static int airoha_pwm_config_flash_map(struct airoha_pwm *pc,
+ unsigned int hwpwm, int index)
+{
+ unsigned int addr;
+ u32 shift;
+ int ret;
+
+ airoha_pwm_get_flash_map_addr_and_shift(hwpwm, &addr, &shift);
+
+ /* index -1 means disable PWM channel */
+ /* negative index means disable PWM channel */
+ if (index < 0) {
+ /*
+ * If we need to disable the PWM, we just put low the
+ * GPIO. No need to setup buckets.
+ */
+ regmap_clear_bits(pc->regmap, addr,
+ return regmap_clear_bits(pc->regmap, addr,
+ AIROHA_PWM_GPIO_FLASH_EN << shift);
+ return;
+ }
+
+ regmap_update_bits(pc->regmap, addr,
+ ret = regmap_update_bits(pc->regmap, addr,
+ AIROHA_PWM_GPIO_FLASH_SET_ID << shift,
+ FIELD_PREP(AIROHA_PWM_GPIO_FLASH_SET_ID, index) << shift);
+ regmap_set_bits(pc->regmap, addr, AIROHA_PWM_GPIO_FLASH_EN << shift);
+ if (ret)
+ return ret;
+
+ return regmap_set_bits(pc->regmap, addr, AIROHA_PWM_GPIO_FLASH_EN << shift);
+}
+
+static int airoha_pwm_config(struct airoha_pwm *pc, struct pwm_device *pwm,
+ u64 duty_ns, u64 period_ns)
+ u32 period_ticks, u32 duty_ticks)
+{
+ unsigned int hwpwm = pwm->hwpwm;
+ int bucket;
+ int bucket, ret;
+
+ bucket = airoha_pwm_consume_generator(pc, duty_ns, period_ns,
+ bucket = airoha_pwm_consume_generator(pc, duty_ticks, period_ticks,
+ hwpwm);
+ if (bucket < 0)
+ return -EBUSY;
+ return bucket;
+
+ airoha_pwm_calc_bucket_config(pc, bucket, duty_ns, period_ns);
+ airoha_pwm_config_flash_map(pc, hwpwm, bucket);
+ ret = airoha_pwm_config_flash_map(pc, hwpwm, bucket);
+ if (ret) {
+ pc->buckets[bucket].used--;
+ return ret;
+ }
+
+ pc->initialized |= BIT_ULL(hwpwm);
+ __set_bit(hwpwm, pc->initialized);
+ pc->channel_bucket[hwpwm] = bucket;
+
+ /*
@ -570,13 +538,18 @@ Changes in v2:
+ * of this chip is internal to the SoC that takes care of applying the
+ * values based on the flash map. To apply a new flash map, it's needed
+ * to trigger a refresh on the shift register chip.
+ * If we are configuring a SIPO, always reinit the shift register chip
+ * to make sure the correct flash map is applied.
+ * We skip reconfiguring the shift register if we related hwpwm
+ * If a SIPO is getting configuring , always reinit the shift register
+ * chip to make sure the correct flash map is applied.
+ * Skip reconfiguring the shift register if the related hwpwm
+ * is disabled (as it doesn't need to be mapped).
+ */
+ if (!(pc->initialized & BIT_ULL(hwpwm)) && hwpwm >= AIROHA_PWM_NUM_GPIO)
+ airoha_pwm_sipo_init(pc);
+ if (hwpwm >= AIROHA_PWM_NUM_GPIO) {
+ ret = airoha_pwm_sipo_init(pc);
+ if (ret) {
+ airoha_pwm_release_bucket_config(pc, hwpwm);
+ return ret;
+ }
+ }
+
+ return 0;
+}
@ -587,10 +560,11 @@ Changes in v2:
+ airoha_pwm_config_flash_map(pc, pwm->hwpwm, -1);
+ airoha_pwm_release_bucket_config(pc, pwm->hwpwm);
+
+ pc->initialized &= ~BIT_ULL(pwm->hwpwm);
+ __clear_bit(pwm->hwpwm, pc->initialized);
+
+ /* If no SIPO is used, disable the shift register chip */
+ if (!(pc->initialized >> AIROHA_PWM_NUM_GPIO))
+ if (!bitmap_read(pc->initialized,
+ AIROHA_PWM_NUM_GPIO, AIROHA_PWM_NUM_SIPO))
+ regmap_clear_bits(pc->regmap, AIROHA_PWM_REG_SIPO_FLASH_MODE_CFG,
+ AIROHA_PWM_SERIAL_GPIO_FLASH_MODE);
+}
@ -599,37 +573,41 @@ Changes in v2:
+ const struct pwm_state *state)
+{
+ struct airoha_pwm *pc = pwmchip_get_drvdata(chip);
+ u64 duty_ns = state->duty_cycle;
+ u64 period_ns = state->period;
+
+ /* Only normal polarity is supported */
+ if (state->polarity == PWM_POLARITY_INVERSED)
+ return -EINVAL;
+ u32 period_ticks, duty_ticks;
+ u32 period_ns, duty_ns;
+
+ if (!state->enabled) {
+ airoha_pwm_disable(pc, pwm);
+ return 0;
+ }
+
+ /* Exit early if period is less than minimum supported */
+ if (period_ns < AIROHA_PWM_PERIOD_TICK_NS)
+ /* Only normal polarity is supported */
+ if (state->polarity == PWM_POLARITY_INVERSED)
+ return -EINVAL;
+
+ /*
+ * Period goes at 4ns step, normalize it to check if we can
+ * share a generator.
+ */
+ period_ns = rounddown(period_ns, AIROHA_PWM_PERIOD_TICK_NS);
+ /* Exit early if period is less than minimum supported */
+ if (state->period < AIROHA_PWM_PERIOD_TICK_NS)
+ return -EINVAL;
+
+ /* Clamp period to MAX supported value */
+ if (period_ns > AIROHA_PWM_PERIOD_MAX_NS) {
+ if (state->period > AIROHA_PWM_PERIOD_MAX_NS)
+ period_ns = AIROHA_PWM_PERIOD_MAX_NS;
+ else
+ period_ns = state->period;
+
+ if (duty_ns > period_ns)
+ /* Validate duty to configured period */
+ if (state->duty_cycle > period_ns)
+ duty_ns = period_ns;
+ }
+ else
+ duty_ns = state->duty_cycle;
+
+ return airoha_pwm_config(pc, pwm, duty_ns, period_ns);
+ /* Convert period ns to ticks */
+ period_ticks = airoha_pwm_get_period_ticks_from_ns(period_ns);
+ /* Convert period ticks to ns again for cosistent duty tick calculation */
+ period_ns = airoha_pwm_get_period_ns_from_ticks(period_ticks);
+ duty_ticks = airoha_pwm_get_duty_ticks_from_ns(period_ns, duty_ns);
+
+ return airoha_pwm_config(pc, pwm, period_ticks, duty_ticks);
+}
+
+static int airoha_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
@ -653,10 +631,8 @@ Changes in v2:
+ state->polarity = PWM_POLARITY_NORMAL;
+
+ bucket = FIELD_GET(AIROHA_PWM_GPIO_FLASH_SET_ID, val >> shift);
+ airoha_pwm_get_bucket(pc, bucket, &state->period,
+ return airoha_pwm_get_bucket(pc, bucket, &state->period,
+ &state->duty_cycle);
+
+ return 0;
+}
+
+static const struct pwm_ops airoha_pwm_ops = {
@ -678,11 +654,11 @@ Changes in v2:
+ chip->ops = &airoha_pwm_ops;
+ pc = pwmchip_get_drvdata(chip);
+
+ pc->regmap = device_node_to_regmap(dev->parent->of_node);
+ pc->regmap = device_node_to_regmap(dev_of_node(dev->parent));
+ if (IS_ERR(pc->regmap))
+ return dev_err_probe(dev, PTR_ERR(pc->regmap), "Failed to get PWM regmap\n");
+
+ ret = devm_pwmchip_add(&pdev->dev, chip);
+ ret = devm_pwmchip_add(dev, chip);
+ if (ret)
+ return dev_err_probe(dev, ret, "Failed to add PWM chip\n");
+
@ -698,6 +674,7 @@ Changes in v2:
+static struct platform_driver airoha_pwm_driver = {
+ .driver = {
+ .name = "pwm-airoha",
+ .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ .of_match_table = airoha_pwm_of_match,
+ },
+ .probe = airoha_pwm_probe,
@ -707,5 +684,6 @@ Changes in v2:
+MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Airoha EN7581 PWM driver");
+MODULE_LICENSE("GPL");

20
target/linux/bcm27xx/modules/video.mk
View File

@ -93,6 +93,26 @@ endef
$(eval $(call KernelPackage,codec-bcm2835))
define KernelPackage/drm-v3d
SUBMENU:=$(VIDEO_MENU)
TITLE:=Broadcom V3D Graphics
DEPENDS:= \
@TARGET_bcm27xx_bcm2711||TARGET_bcm27xx_bcm2712 +kmod-drm \
+kmod-drm-shmem-helper +kmod-drm-sched
KCONFIG:=CONFIG_DRM_V3D
FILES:= \
$(LINUX_DIR)/drivers/gpu/drm/v3d/v3d.ko
AUTOLOAD:=$(call AutoProbe,v3d)
endef
define KernelPackage/drm-v3d/description
Broadcom V3D 3.x or newer GPUs. SoCs supported include the BCM2711,
BCM7268 and BCM7278.
endef
$(eval $(call KernelPackage,drm-v3d))
define KernelPackage/drm-vc4
SUBMENU:=$(VIDEO_MENU)
TITLE:=Broadcom VC4 Graphics

2
target/linux/bcm27xx/patches-6.12/950-0312-hwmon-sht3x-Add-DT-compatible-string.patch
View File

@ -10,7 +10,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
--- a/drivers/hwmon/sht3x.c
+++ b/drivers/hwmon/sht3x.c
@@ -954,19 +954,19 @@ static int sht3x_probe(struct i2c_client
@@ -961,19 +961,19 @@ static int sht3x_probe(struct i2c_client
return PTR_ERR_OR_ZERO(hwmon_dev);
}

2
target/linux/bcm27xx/patches-6.12/950-0331-serial-sc16is7xx-Read-modem-line-state-at-startup.patch
View File

@ -16,7 +16,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
--- a/drivers/tty/serial/sc16is7xx.c
+++ b/drivers/tty/serial/sc16is7xx.c
@@ -1196,6 +1196,9 @@ static int sc16is7xx_startup(struct uart
@@ -1189,6 +1189,9 @@ static int sc16is7xx_startup(struct uart
SC16IS7XX_IER_MSI_BIT;
sc16is7xx_port_write(port, SC16IS7XX_IER_REG, val);

2
target/linux/bcm27xx/patches-6.12/950-0416-serial-sc16is7xx-Don-t-spin-if-no-data-received.patch
View File

@ -15,7 +15,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
--- a/drivers/tty/serial/sc16is7xx.c
+++ b/drivers/tty/serial/sc16is7xx.c
@@ -821,6 +821,8 @@ static bool sc16is7xx_port_irq(struct sc
@@ -814,6 +814,8 @@ static bool sc16is7xx_port_irq(struct sc
if (rxlen)
sc16is7xx_handle_rx(port, rxlen, iir);

6
target/linux/bcm27xx/patches-6.12/950-0623-arm64-dts-broadcom-Add-display-pipeline-support-to-B.patch
View File

@ -36,8 +36,8 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
};
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -265,6 +265,172 @@
interrupt-controller;
@@ -268,6 +268,172 @@
IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
};
+
@ -209,7 +209,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
};
timer {
@@ -280,4 +446,27 @@
@@ -283,4 +449,27 @@
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) |
IRQ_TYPE_LEVEL_LOW)>;
};

2
target/linux/bcm27xx/patches-6.12/950-0628-arm64-dts-broadcom-Fixup-HVS-address-for-downstream-.patch
View File

@ -14,7 +14,7 @@ Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -463,10 +463,10 @@
@@ -466,10 +466,10 @@
hvs: hvs@107c580000 {
compatible = "brcm,bcm2712-hvs";

2
target/linux/bcm27xx/patches-6.12/950-0702-serial-sc16is7xx-announce-support-for-SER_RS485_RTS_.patch
View File

@ -31,7 +31,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
--- a/drivers/tty/serial/sc16is7xx.c
+++ b/drivers/tty/serial/sc16is7xx.c
@@ -1468,7 +1468,7 @@ static int sc16is7xx_setup_mctrl_ports(s
@@ -1461,7 +1461,7 @@ static int sc16is7xx_setup_mctrl_ports(s
}
static const struct serial_rs485 sc16is7xx_rs485_supported = {

2
target/linux/bcm27xx/patches-6.12/950-0794-arm64-dts-Prepare-for-size-cells-2.patch
View File

@ -72,7 +72,7 @@ Signed-off-by: Phil Elwell <phil@raspberrypi.com>
};
--- a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi
@@ -463,7 +463,11 @@
@@ -466,7 +466,11 @@
hvs: hvs@107c580000 {
compatible = "brcm,bcm2712-hvs";

2
target/linux/bcm27xx/patches-6.12/950-0900-arm64-dts-broadcom-bcm2712-Add-PCIe-DT-nodes.patch
View File

@ -39,7 +39,7 @@ Signed-off-by: Stanimir Varbanov <svarbanov@suse.de>
system_timer: timer@7c003000 {
compatible = "brcm,bcm2835-system-timer";
reg = <0x7c003000 0x1000>;
@@ -431,6 +443,141 @@
@@ -434,6 +446,141 @@
vc4: gpu {
compatible = "brcm,bcm2712-vc6";
};

22
target/linux/bcm47xx/patches-6.6/980-no-previous-protoype-fixes.patch Normal file
View File

@ -0,0 +1,22 @@
--- a/drivers/bcma/driver_chipcommon_sflash.c
+++ b/drivers/bcma/driver_chipcommon_sflash.c
@@ -93,7 +93,7 @@ static void bcma_sflash_cmd(struct bcma_
bcma_err(cc->core->bus, "SFLASH control command failed (timeout)!\n");
}
-const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id)
+static const struct bcma_sflash_tbl_e *bcma_sflash_shrink_flash(u32 id)
{
enum bcm47xx_board board = bcm47xx_board_get();
const struct bcma_sflash_tbl_e *e;
--- a/drivers/firmware/broadcom/cfe_env.c
+++ b/drivers/firmware/broadcom/cfe_env.c
@@ -21,6 +21,8 @@
static char _nvdata[NVRAM_SIZE];
static char _valuestr[256];
+char *cfe_env_get(unsigned char *nv_buf, const char *name);
+
/*
* TLV types. These codes are used in the "type-length-value"
* encoding of the items stored in the NVRAM device (flash or EEPROM)

2
target/linux/generic/backport-6.12/810-v6.14-gpio-regmap-Use-generic-request-free-ops.patch
View File

@ -19,7 +19,7 @@ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
--- a/drivers/gpio/gpio-regmap.c
+++ b/drivers/gpio/gpio-regmap.c
@@ -262,6 +262,8 @@ struct gpio_regmap *gpio_regmap_register
@@ -276,6 +276,8 @@ struct gpio_regmap *gpio_regmap_register
chip->label = config->label ?: dev_name(config->parent);
chip->can_sleep = regmap_might_sleep(config->regmap);

2
target/linux/generic/backport-6.6/880-v6.14-gpio-regmap-Use-generic-request-free-ops.patch
View File

@ -19,7 +19,7 @@ Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
--- a/drivers/gpio/gpio-regmap.c
+++ b/drivers/gpio/gpio-regmap.c
@@ -262,6 +262,8 @@ struct gpio_regmap *gpio_regmap_register
@@ -276,6 +276,8 @@ struct gpio_regmap *gpio_regmap_register
chip->label = config->label ?: dev_name(config->parent);
chip->can_sleep = regmap_might_sleep(config->regmap);

2
target/linux/generic/files/drivers/mtd/mtdsplit/mtdsplit_fit.c
View File

@ -258,7 +258,7 @@ mtdsplit_fit_parse(struct mtd_info *mtd,
* hence we need to parse FDT structure to find the end of the
* last external data refernced.
*/
if (fit_size > 0x1000) {
if (fit_size > 0x80000) {
enum mtdsplit_part_type type;
/* Search for the rootfs partition after the FIT image */

2
target/linux/generic/files/drivers/net/phy/b53/b53_common.c
View File

@ -227,7 +227,7 @@ static void b53_set_vlan_entry(struct b53_device *dev, u16 vid, u16 members,
}
}
void b53_set_forwarding(struct b53_device *dev, int enable)
static void b53_set_forwarding(struct b53_device *dev, int enable)
{
u8 mgmt;

4
target/linux/generic/files/drivers/net/phy/b53/b53_mdio.c
View File

@ -400,7 +400,7 @@ static struct phy_driver b53_phy_driver_id3 = {
.read_status = b53_phy_read_status,
};
int __init b53_phy_driver_register(void)
static int __init b53_phy_driver_register(void)
{
int ret;
@ -422,7 +422,7 @@ err1:
return ret;
}
void __exit b53_phy_driver_unregister(void)
static void __exit b53_phy_driver_unregister(void)
{
phy_driver_unregister(&b53_phy_driver_id3);
phy_driver_unregister(&b53_phy_driver_id2);

2
target/linux/generic/files/drivers/net/phy/b53/b53_phy_fixup.c
View File

@ -47,7 +47,7 @@ static int b53_phy_fixup(struct phy_device *dev)
return 0;
}
int __init b53_phy_fixup_register(void)
static int __init b53_phy_fixup_register(void)
{
return phy_register_fixup_for_id(PHY_ANY_ID, b53_phy_fixup);
}

4
target/linux/generic/hack-6.12/780-usb-net-MeigLink_modem_support.patch
View File

@ -44,7 +44,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
#define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */
@@ -1154,6 +1159,11 @@ static const struct usb_device_id option
@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
.driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
@ -56,7 +56,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
/* Quectel products using Qualcomm vendor ID */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
@@ -1195,6 +1205,11 @@ static const struct usb_device_id option
@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
.driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) },

4
target/linux/generic/hack-6.6/780-usb-net-MeigLink_modem_support.patch
View File

@ -44,7 +44,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
#define QUECTEL_VENDOR_ID 0x2c7c
/* These Quectel products use Quectel's vendor ID */
@@ -1154,6 +1159,11 @@ static const struct usb_device_id option
@@ -1156,6 +1161,11 @@ static const struct usb_device_id option
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
.driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
@ -56,7 +56,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
/* Quectel products using Qualcomm vendor ID */
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
@@ -1195,6 +1205,11 @@ static const struct usb_device_id option
@@ -1197,6 +1207,11 @@ static const struct usb_device_id option
.driver_info = ZLP },
{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
.driver_info = RSVD(4) },

4
target/linux/generic/kernel-6.12
View File

@ -1,2 +1,2 @@
LINUX_VERSION-6.12 = .55
LINUX_KERNEL_HASH-6.12.55 = 328f8f4608a653063a5fd82d29b17163faab2825fa419fa85b961740a342fb9f
LINUX_VERSION-6.12 = .57
LINUX_KERNEL_HASH-6.12.57 = 165ca1c37c4607b90e731996b7c1e3311285167d13deeedf08f3f1f0b9d2541a

4
target/linux/generic/kernel-6.6
View File

@ -1,2 +1,2 @@
LINUX_VERSION-6.6 = .114
LINUX_KERNEL_HASH-6.6.114 = ca4175a03ce2943ae192d77ad91e37ee292f1f1bb7b2954b062b0ef7eb0cb97c
LINUX_VERSION-6.6 = .116
LINUX_KERNEL_HASH-6.6.116 = a9a59742c29be284c205dc87cbe9b065f9688488132c8f5a6057a5539230a51d

2
target/linux/generic/pending-6.12/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
View File

@ -161,7 +161,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
struct rtnl_link {
rtnl_doit_func doit;
@@ -5012,7 +5012,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu
@@ -5009,7 +5009,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu
brport_nla_put_flag(skb, flags, mask,
IFLA_BRPORT_MCAST_FLOOD, BR_MCAST_FLOOD) ||
brport_nla_put_flag(skb, flags, mask,

2
target/linux/generic/pending-6.12/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
View File

@ -544,7 +544,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+ }
+
+ if (mtk_is_netsys_v3_or_greater(eth) && (mac->sgmii_pcs || mac->usxgmii_pcs)) {
+ mac->pextp = devm_of_phy_get(eth->dev, mac->of_node, NULL);
+ mac->pextp = devm_of_phy_optional_get(eth->dev, mac->of_node, NULL);
+ if (IS_ERR(mac->pextp)) {
+ if (PTR_ERR(mac->pextp) != -EPROBE_DEFER)
+ dev_err(eth->dev, "cannot get PHY, error %ld\n",

2
target/linux/generic/pending-6.6/710-bridge-add-knob-for-filtering-rx-tx-BPDU-pack.patch
View File

@ -161,7 +161,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
struct rtnl_link {
rtnl_doit_func doit;
@@ -4981,7 +4981,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu
@@ -4978,7 +4978,9 @@ int ndo_dflt_bridge_getlink(struct sk_bu
brport_nla_put_flag(skb, flags, mask,
IFLA_BRPORT_MCAST_FLOOD, BR_MCAST_FLOOD) ||
brport_nla_put_flag(skb, flags, mask,

3
target/linux/ipq806x/Makefile
View File

@ -10,8 +10,7 @@ CPU_TYPE:=cortex-a15
CPU_SUBTYPE:=neon-vfpv4
SUBTARGETS:=generic chromium
KERNEL_PATCHVER:=6.6
KERNEL_TESTING_PATCHVER:=6.12
KERNEL_PATCHVER:=6.12
KERNELNAME:=zImage Image dtbs

534
target/linux/ipq806x/config-6.6
View File

@ -1,534 +0,0 @@
CONFIG_ALIGNMENT_TRAP=y
# CONFIG_APQ_GCC_8084 is not set
# CONFIG_APQ_MMCC_8084 is not set
CONFIG_ARCH_32BIT_OFF_T=y
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
# CONFIG_ARCH_IPQ40XX is not set
CONFIG_ARCH_KEEP_MEMBLOCK=y
# CONFIG_ARCH_MDM9615 is not set
CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y
# CONFIG_ARCH_MSM8909 is not set
# CONFIG_ARCH_MSM8916 is not set
CONFIG_ARCH_MSM8960=y
CONFIG_ARCH_MSM8974=y
CONFIG_ARCH_MSM8X60=y
CONFIG_ARCH_MULTIPLATFORM=y
CONFIG_ARCH_MULTI_V6_V7=y
CONFIG_ARCH_MULTI_V7=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y
CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y
CONFIG_ARCH_QCOM=y
CONFIG_ARCH_SELECT_MEMORY_MODEL=y
CONFIG_ARCH_SPARSEMEM_ENABLE=y
CONFIG_ARCH_STACKWALK=y
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_ARM=y
CONFIG_ARM_AMBA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ARCH_TIMER=y
CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
# CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER is not set
CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_MANGLE=y
CONFIG_ARM_ATAG_DTB_COMPAT_IGNORE_MEM=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_ARM_CPU_TOPOLOGY is not set
CONFIG_ARM_GIC=y
CONFIG_ARM_HAS_GROUP_RELOCS=y
CONFIG_ARM_IPQ806X_FAB_DEVFREQ=y
CONFIG_ARM_KRAIT_CACHE_DEVFREQ=y
CONFIG_ARM_L1_CACHE_SHIFT=6
CONFIG_ARM_L1_CACHE_SHIFT_6=y
CONFIG_ARM_PATCH_IDIV=y
CONFIG_ARM_PATCH_PHYS_VIRT=y
# CONFIG_ARM_QCOM_CPUFREQ_HW is not set
CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y
CONFIG_ARM_QCOM_SPM_CPUIDLE=y
# CONFIG_ARM_SMMU is not set
CONFIG_ARM_THUMB=y
CONFIG_ARM_UNWIND=y
CONFIG_ARM_VIRT_EXT=y
CONFIG_AT803X_PHY=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_MQ_PCI=y
CONFIG_BOUNCE=y
# CONFIG_CACHE_L2X0 is not set
CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y
CONFIG_CLKSRC_QCOM=y
CONFIG_CLONE_BACKWARDS=y
CONFIG_CMDLINE_OVERRIDE=y
CONFIG_COMMON_CLK=y
CONFIG_COMMON_CLK_QCOM=y
CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_CONTEXT_TRACKING=y
CONFIG_CONTEXT_TRACKING_IDLE=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPUFREQ_DT_PLATDEV=y
CONFIG_CPU_32v6K=y
CONFIG_CPU_32v7=y
CONFIG_CPU_ABRT_EV7=y
CONFIG_CPU_CACHE_V7=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
CONFIG_CPU_FREQ_GOV_ATTR_SET=y
CONFIG_CPU_FREQ_GOV_COMMON=y
# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
CONFIG_CPU_FREQ_STAT=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_IDLE=y
CONFIG_CPU_IDLE_GOV_LADDER=y
CONFIG_CPU_IDLE_GOV_MENU=y
CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
CONFIG_CPU_LITTLE_ENDIAN=y
CONFIG_CPU_MITIGATIONS=y
CONFIG_CPU_PABRT_V7=y
CONFIG_CPU_PM=y
CONFIG_CPU_RMAP=y
CONFIG_CPU_SPECTRE=y
CONFIG_CPU_THERMAL=y
CONFIG_CPU_THUMB_CAPABLE=y
CONFIG_CPU_TLB_V7=y
CONFIG_CPU_V7=y
CONFIG_CRC16=y
CONFIG_CRC8=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_DEV_QCOM_RNG=y
CONFIG_CRYPTO_DRBG=y
CONFIG_CRYPTO_DRBG_HMAC=y
CONFIG_CRYPTO_DRBG_MENU=y
CONFIG_CRYPTO_HASH_INFO=y
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_HW=y
CONFIG_CRYPTO_JITTERENTROPY=y
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKS=64
CONFIG_CRYPTO_JITTERENTROPY_MEMORY_BLOCKSIZE=32
CONFIG_CRYPTO_JITTERENTROPY_OSR=1
CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
CONFIG_CRYPTO_LIB_GF128MUL=y
CONFIG_CRYPTO_LIB_SHA1=y
CONFIG_CRYPTO_LIB_SHA256=y
CONFIG_CRYPTO_LIB_UTILS=y
CONFIG_CRYPTO_LZO=y
CONFIG_CRYPTO_RNG=y
CONFIG_CRYPTO_RNG2=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_ZSTD=y
CONFIG_CURRENT_POINTER_IN_TPIDRURO=y
CONFIG_DCACHE_WORD_ACCESS=y
CONFIG_DEBUG_GPIO=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
CONFIG_DEVFREQ_GOV_PASSIVE=y
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
# CONFIG_DEVFREQ_GOV_USERSPACE is not set
# CONFIG_DEVFREQ_THERMAL is not set
CONFIG_DMADEVICES=y
CONFIG_DMA_ENGINE=y
CONFIG_DMA_OF=y
CONFIG_DMA_OPS=y
CONFIG_DMA_VIRTUAL_CHANNELS=y
CONFIG_DTC=y
CONFIG_DT_IDLE_STATES=y
# CONFIG_DWMAC_GENERIC is not set
CONFIG_DWMAC_IPQ806X=y
# CONFIG_DWMAC_QCOM_ETHQOS is not set
CONFIG_EDAC_ATOMIC_SCRUB=y
CONFIG_EDAC_SUPPORT=y
CONFIG_EXCLUSIVE_SYSTEM_RAM=y
CONFIG_FIXED_PHY=y
CONFIG_FIX_EARLYCON_MEM=y
CONFIG_FS_IOMAP=y
CONFIG_FUNCTION_ALIGNMENT=0
CONFIG_FWNODE_MDIO=y
CONFIG_FW_LOADER_PAGED_BUF=y
CONFIG_FW_LOADER_SYSFS=y
CONFIG_GENERIC_ALLOCATOR=y
CONFIG_GENERIC_BUG=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
CONFIG_GENERIC_CPU_AUTOPROBE=y
CONFIG_GENERIC_CPU_VULNERABILITIES=y
CONFIG_GENERIC_EARLY_IOREMAP=y
CONFIG_GENERIC_GETTIMEOFDAY=y
CONFIG_GENERIC_IDLE_POLL_SETUP=y
CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y
CONFIG_GENERIC_IRQ_MIGRATION=y
CONFIG_GENERIC_IRQ_MULTI_HANDLER=y
CONFIG_GENERIC_IRQ_SHOW=y
CONFIG_GENERIC_IRQ_SHOW_LEVEL=y
CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y
CONFIG_GENERIC_MSI_IRQ=y
CONFIG_GENERIC_PCI_IOMAP=y
CONFIG_GENERIC_PHY=y
CONFIG_GENERIC_PINCONF=y
CONFIG_GENERIC_PINCTRL_GROUPS=y
CONFIG_GENERIC_PINMUX_FUNCTIONS=y
CONFIG_GENERIC_SCHED_CLOCK=y
CONFIG_GENERIC_SMP_IDLE_THREAD=y
CONFIG_GENERIC_STRNCPY_FROM_USER=y
CONFIG_GENERIC_STRNLEN_USER=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_VDSO_32=y
CONFIG_GLOB=y
CONFIG_GPIOLIB_IRQCHIP=y
CONFIG_GPIO_CDEV=y
CONFIG_GRO_CELLS=y
CONFIG_HARDEN_BRANCH_PREDICTOR=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_HAS_DMA=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_IOPORT_MAP=y
CONFIG_HAVE_SMP=y
CONFIG_HIGHMEM=y
# CONFIG_HIGHPTE is not set
CONFIG_HOTPLUG_CORE_SYNC=y
CONFIG_HOTPLUG_CORE_SYNC_DEAD=y
CONFIG_HOTPLUG_CPU=y
CONFIG_HWMON=y
CONFIG_HWSPINLOCK=y
CONFIG_HWSPINLOCK_QCOM=y
CONFIG_HW_RANDOM=y
CONFIG_HZ_FIXED=0
CONFIG_I2C=y
CONFIG_I2C_BOARDINFO=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_HELPER_AUTO=y
# CONFIG_I2C_QCOM_CCI is not set
CONFIG_I2C_QUP=y
CONFIG_INITRAMFS_SOURCE=""
# CONFIG_IOMMUFD is not set
# CONFIG_IOMMU_DEBUGFS is not set
# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set
# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
CONFIG_IOMMU_SUPPORT=y
# CONFIG_IPQ_APSS_PLL is not set
# CONFIG_IPQ_GCC_4019 is not set
# CONFIG_IPQ_GCC_5018 is not set
# CONFIG_IPQ_GCC_6018 is not set
CONFIG_IPQ_GCC_806X=y
# CONFIG_IPQ_GCC_8074 is not set
# CONFIG_IPQ_GCC_9574 is not set
# CONFIG_IPQ_LCC_806X is not set
CONFIG_IRQCHIP=y
CONFIG_IRQSTACKS=y
CONFIG_IRQ_DOMAIN=y
CONFIG_IRQ_DOMAIN_HIERARCHY=y
CONFIG_IRQ_FASTEOI_HIERARCHY_HANDLERS=y
CONFIG_IRQ_FORCED_THREADING=y
CONFIG_IRQ_WORK=y
CONFIG_KMAP_LOCAL=y
CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y
CONFIG_KPSS_XCC=y
CONFIG_KRAITCC=y
CONFIG_KRAIT_CLOCKS=y
CONFIG_KRAIT_L2_ACCESSORS=y
CONFIG_LIBFDT=y
CONFIG_LOCK_DEBUGGING_SUPPORT=y
CONFIG_LOCK_SPIN_ON_OWNER=y
CONFIG_LZO_COMPRESS=y
CONFIG_LZO_DECOMPRESS=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_BUS=y
CONFIG_MDIO_DEVICE=y
CONFIG_MDIO_DEVRES=y
CONFIG_MDIO_GPIO=y
CONFIG_MDIO_IPQ8064=y
# CONFIG_MDM_GCC_9615 is not set
# CONFIG_MFD_HI6421_SPMI is not set
CONFIG_MFD_QCOM_RPM=y
# CONFIG_MFD_SPMI_PMIC is not set
CONFIG_MFD_SYSCON=y
CONFIG_MIGHT_HAVE_CACHE_L2X0=y
CONFIG_MIGRATION=y
CONFIG_MMC=y
CONFIG_MMC_ARMMMCI=y
CONFIG_MMC_BLOCK=y
CONFIG_MMC_BLOCK_MINORS=16
CONFIG_MMC_CQHCI=y
CONFIG_MMC_QCOM_DML=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_IO_ACCESSORS=y
CONFIG_MMC_SDHCI_MSM=y
# CONFIG_MMC_SDHCI_PCI is not set
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMU_LAZY_TLB_REFCOUNT=y
CONFIG_MODULES_USE_ELF_REL=y
CONFIG_MSM_GCC_8660=y
# CONFIG_MSM_GCC_8909 is not set
# CONFIG_MSM_GCC_8916 is not set
# CONFIG_MSM_GCC_8939 is not set
# CONFIG_MSM_GCC_8960 is not set
# CONFIG_MSM_GCC_8974 is not set
# CONFIG_MSM_GCC_8976 is not set
# CONFIG_MSM_GCC_8994 is not set
# CONFIG_MSM_GCC_8996 is not set
# CONFIG_MSM_GCC_8998 is not set
# CONFIG_MSM_GPUCC_8998 is not set
# CONFIG_MSM_IOMMU is not set
# CONFIG_MSM_LCC_8960 is not set
# CONFIG_MSM_MMCC_8960 is not set
# CONFIG_MSM_MMCC_8974 is not set
# CONFIG_MSM_MMCC_8996 is not set
# CONFIG_MSM_MMCC_8998 is not set
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_NAND_CORE=y
CONFIG_MTD_NAND_ECC=y
CONFIG_MTD_NAND_ECC_SW_HAMMING=y
CONFIG_MTD_NAND_QCOM=y
CONFIG_MTD_QCOMSMEM_PARTS=y
CONFIG_MTD_RAW_NAND=y
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPLIT_FIRMWARE=y
CONFIG_MTD_SPLIT_FIT_FW=y
CONFIG_MTD_SPLIT_UIMAGE_FW=y
CONFIG_MTD_UBI=y
CONFIG_MTD_UBI_BEB_LIMIT=20
CONFIG_MTD_UBI_BLOCK=y
CONFIG_MTD_UBI_WL_THRESHOLD=4096
CONFIG_MUTEX_SPIN_ON_OWNER=y
CONFIG_NEED_DMA_MAP_STATE=y
CONFIG_NEED_SRCU_NMI_SAFE=y
CONFIG_NEON=y
CONFIG_NET_DEVLINK=y
CONFIG_NET_DSA=y
CONFIG_NET_DSA_QCA8K=y
CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y
CONFIG_NET_DSA_TAG_QCA=y
CONFIG_NET_EGRESS=y
CONFIG_NET_FLOW_LIMIT=y
CONFIG_NET_INGRESS=y
CONFIG_NET_PTP_CLASSIFY=y
CONFIG_NET_SELFTESTS=y
CONFIG_NET_XGRESS=y
CONFIG_NLS=y
CONFIG_NO_HZ=y
CONFIG_NO_HZ_COMMON=y
CONFIG_NO_HZ_IDLE=y
CONFIG_NR_CPUS=2
CONFIG_NVMEM=y
CONFIG_NVMEM_LAYOUTS=y
CONFIG_NVMEM_LAYOUT_ASCII_ENV=y
CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=y
CONFIG_NVMEM_QCOM_QFPROM=y
# CONFIG_NVMEM_QCOM_SEC_QFPROM is not set
# CONFIG_NVMEM_SPMI_SDAM is not set
CONFIG_NVMEM_SYSFS=y
CONFIG_NVMEM_U_BOOT_ENV=y
CONFIG_OF=y
CONFIG_OF_ADDRESS=y
CONFIG_OF_EARLY_FLATTREE=y
CONFIG_OF_FLATTREE=y
CONFIG_OF_GPIO=y
CONFIG_OF_IRQ=y
CONFIG_OF_KOBJ=y
CONFIG_OF_MDIO=y
CONFIG_OLD_SIGACTION=y
CONFIG_OLD_SIGSUSPEND3=y
CONFIG_PADATA=y
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_PAGE_POOL=y
CONFIG_PAGE_SIZE_LESS_THAN_256KB=y
CONFIG_PAGE_SIZE_LESS_THAN_64KB=y
CONFIG_PCI=y
CONFIG_PCIEAER=y
CONFIG_PCIEPORTBUS=y
CONFIG_PCIE_DW=y
CONFIG_PCIE_DW_HOST=y
CONFIG_PCIE_QCOM=y
CONFIG_PCI_DEBUG=y
CONFIG_PCI_DISABLE_COMMON_QUIRKS=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_DOMAINS_GENERIC=y
CONFIG_PCI_MSI=y
CONFIG_PCS_XPCS=y
CONFIG_PERF_USE_VMALLOC=y
CONFIG_PGTABLE_LEVELS=2
CONFIG_PHYLIB=y
CONFIG_PHYLIB_LEDS=y
CONFIG_PHYLINK=y
# CONFIG_PHY_QCOM_APQ8064_SATA is not set
# CONFIG_PHY_QCOM_EDP is not set
# CONFIG_PHY_QCOM_EUSB2_REPEATER is not set
# CONFIG_PHY_QCOM_IPQ4019_USB is not set
CONFIG_PHY_QCOM_IPQ806X_SATA=y
# CONFIG_PHY_QCOM_IPQ806X_USB is not set
# CONFIG_PHY_QCOM_M31_USB is not set
# CONFIG_PHY_QCOM_PCIE2 is not set
# CONFIG_PHY_QCOM_QMP is not set
# CONFIG_PHY_QCOM_QUSB2 is not set
# CONFIG_PHY_QCOM_SGMII_ETH is not set
# CONFIG_PHY_QCOM_SNPS_EUSB2 is not set
# CONFIG_PHY_QCOM_USB_HS_28NM is not set
# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set
# CONFIG_PHY_QCOM_USB_SS is not set
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_APQ8064 is not set
# CONFIG_PINCTRL_APQ8084 is not set
# CONFIG_PINCTRL_IPQ4019 is not set
CONFIG_PINCTRL_IPQ8064=y
# CONFIG_PINCTRL_MDM9615 is not set
CONFIG_PINCTRL_MSM=y
# CONFIG_PINCTRL_MSM8226 is not set
# CONFIG_PINCTRL_MSM8660 is not set
# CONFIG_PINCTRL_MSM8909 is not set
# CONFIG_PINCTRL_MSM8916 is not set
# CONFIG_PINCTRL_MSM8960 is not set
# CONFIG_PINCTRL_QCOM_SPMI_PMIC is not set
# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set
# CONFIG_PINCTRL_SDX65 is not set
CONFIG_PM_DEVFREQ=y
# CONFIG_PM_DEVFREQ_EVENT is not set
CONFIG_PM_OPP=y
CONFIG_POWER_RESET=y
CONFIG_POWER_RESET_MSM=y
CONFIG_POWER_SUPPLY=y
CONFIG_PPS=y
CONFIG_PREEMPT_NONE_BUILD=y
CONFIG_PRINTK_TIME=y
CONFIG_PTP_1588_CLOCK=y
CONFIG_PTP_1588_CLOCK_OPTIONAL=y
CONFIG_QCA83XX_PHY=y
# CONFIG_QCM_DISPCC_2290 is not set
# CONFIG_QCM_GCC_2290 is not set
# CONFIG_QCOM_A53PLL is not set
CONFIG_QCOM_ADM=y
CONFIG_QCOM_BAM_DMA=y
CONFIG_QCOM_CLK_RPM=y
# CONFIG_QCOM_COMMAND_DB is not set
# CONFIG_QCOM_CPR is not set
# CONFIG_QCOM_EBI2 is not set
# CONFIG_QCOM_GENI_SE is not set
CONFIG_QCOM_GSBI=y
CONFIG_QCOM_HFPLL=y
# CONFIG_QCOM_ICC_BWMON is not set
# CONFIG_QCOM_IOMMU is not set
# CONFIG_QCOM_LLCC is not set
CONFIG_QCOM_NET_PHYLIB=y
# CONFIG_QCOM_OCMEM is not set
# CONFIG_QCOM_PDC is not set
# CONFIG_QCOM_RAMP_CTRL is not set
# CONFIG_QCOM_RMTFS_MEM is not set
CONFIG_QCOM_RPMCC=y
# CONFIG_QCOM_RPMH is not set
CONFIG_QCOM_RPM_MASTER_STATS=y
CONFIG_QCOM_SCM=y
# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set
CONFIG_QCOM_SMEM=y
# CONFIG_QCOM_SMSM is not set
CONFIG_QCOM_SOCINFO=y
CONFIG_QCOM_SPM=y
# CONFIG_QCOM_STATS is not set
CONFIG_QCOM_TCSR=y
CONFIG_QCOM_TSENS=y
CONFIG_QCOM_WDT=y
# CONFIG_QCS_GCC_404 is not set
# CONFIG_QCS_Q6SSTOP_404 is not set
# CONFIG_QCS_TURING_404 is not set
# CONFIG_QDU_GCC_1000 is not set
CONFIG_RANDSTRUCT_NONE=y
CONFIG_RAS=y
CONFIG_RATIONAL=y
CONFIG_RCU_CPU_STALL_TIMEOUT=21
CONFIG_REGMAP=y
CONFIG_REGMAP_MMIO=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_REGULATOR_QCOM_LABIBB is not set
CONFIG_REGULATOR_QCOM_RPM=y
# CONFIG_REGULATOR_QCOM_SPMI is not set
# CONFIG_REGULATOR_QCOM_USB_VBUS is not set
# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set
CONFIG_RESET_CONTROLLER=y
# CONFIG_RESET_QCOM_AOSS is not set
# CONFIG_RESET_QCOM_PDC is not set
CONFIG_RFS_ACCEL=y
CONFIG_RPS=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_I2C_AND_SPI=y
CONFIG_RTC_MC146818_LIB=y
CONFIG_RWSEM_SPIN_ON_OWNER=y
# CONFIG_SA_GCC_8775P is not set
# CONFIG_SA_GPUCC_8775P is not set
# CONFIG_SDX_GCC_65 is not set
# CONFIG_SDX_GCC_75 is not set
CONFIG_SERIAL_8250_FSL=y
CONFIG_SERIAL_MCTRL_GPIO=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
CONFIG_SGL_ALLOC=y
CONFIG_SMP=y
CONFIG_SMP_ON_UP=y
# CONFIG_SM_GCC_7150 is not set
CONFIG_SOCK_RX_QUEUE_MAPPING=y
CONFIG_SOC_BUS=y
CONFIG_SOFTIRQ_ON_OWN_STACK=y
CONFIG_SPARSE_IRQ=y
CONFIG_SPI=y
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_QPIC_SNAND is not set
CONFIG_SPI_QUP=y
CONFIG_SPMI=y
# CONFIG_SPMI_HISI3670 is not set
CONFIG_SPMI_MSM_PMIC_ARB=y
# CONFIG_SPMI_PMIC_CLKDIV is not set
CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
CONFIG_STMMAC_ETH=y
CONFIG_STMMAC_PLATFORM=y
CONFIG_SWPHY=y
CONFIG_SWP_EMULATE=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_THERMAL=y
CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0
CONFIG_THERMAL_GOV_STEP_WISE=y
CONFIG_THERMAL_HWMON=y
CONFIG_THERMAL_OF=y
CONFIG_THREAD_INFO_IN_TASK=y
CONFIG_TICK_CPU_ACCOUNTING=y
CONFIG_TIMER_OF=y
CONFIG_TIMER_PROBE=y
CONFIG_TREE_RCU=y
CONFIG_TREE_SRCU=y
CONFIG_UBIFS_FS=y
CONFIG_UBIFS_FS_ADVANCED_COMPR=y
# CONFIG_UCLAMP_TASK is not set
CONFIG_UEVENT_HELPER_PATH=""
CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
CONFIG_UNWINDER_ARM=y
CONFIG_USB=y
CONFIG_USB_COMMON=y
CONFIG_USB_SUPPORT=y
CONFIG_USE_OF=y
CONFIG_VFP=y
CONFIG_VFPv3=y
CONFIG_WATCHDOG_CORE=y
CONFIG_XPS=y
CONFIG_XXHASH=y
CONFIG_XZ_DEC_ARM=y
CONFIG_XZ_DEC_BCJ=y
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZSTD_COMMON=y
CONFIG_ZSTD_COMPRESS=y
CONFIG_ZSTD_DECOMPRESS=y

743
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8062-wg2600hp3.dts
View File

@ -1,743 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8062-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "NEC Platforms Aterm WG2600HP3";
compatible = "nec,wg2600hp3", "qcom,ipq8062", "qcom,ipq8064";
memory {
device_type = "memory";
reg = <0x42000000 0x1e000000>;
};
aliases {
label-mac-device = &gmac2;
led-boot = &led_power_green;
led-failsafe = &led_power_red;
led-running = &led_power_green;
led-upgrade = &led_power_red;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&buttons_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
mode0 {
label = "mode0";
gpios = <&qcom_pinmux 40 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
debounce-interval = <60>;
wakeup-source;
};
mode1 {
label = "mode1";
gpios = <&qcom_pinmux 41 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&leds_pins>;
pinctrl-names = "default";
led_power_green: power_green {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
};
led_power_red: power_red {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&qcom_pinmux 35 GPIO_ACTIVE_HIGH>;
};
active_green {
label = "green:active";
gpios = <&qcom_pinmux 42 GPIO_ACTIVE_HIGH>;
};
active_red {
label = "red:active";
gpios = <&qcom_pinmux 38 GPIO_ACTIVE_HIGH>;
};
wlan2g_green {
label = "green:wlan2g";
gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy1tpt";
};
wlan2g_red {
label = "red:wlan2g";
gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
};
wlan5g_green {
label = "green:wlan5g";
gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "phy0tpt";
};
wlan5g_red {
label = "red:wlan5g";
gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
};
tv_green {
label = "green:tv";
gpios = <&qcom_pinmux 46 GPIO_ACTIVE_HIGH>;
};
tv_red {
label = "red:tv";
gpios = <&qcom_pinmux 36 GPIO_ACTIVE_HIGH>;
};
converter_green {
label = "green:converter";
gpios = <&qcom_pinmux 43 GPIO_ACTIVE_HIGH>;
};
converter_red {
label = "red:converter";
gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
};
};
};
/* nand_pins are used for leds_pins, empty the node
* from ipq8064.dtsi
*/
&nand_pins {
/delete-property/ disable;
/delete-property/ pullups;
/delete-property/ hold;
};
&qcom_pinmux {
pinctrl-0 = <&akro_pins>;
pinctrl-names = "default";
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs {
pins = "gpio20";
drive-strength = <10>;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
buttons_pins: buttons_pins {
mux {
pins = "gpio22", "gpio24", "gpio40",
"gpio41";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
leds_pins: leds_pins {
mux {
pins = "gpio14", "gpio15", "gpio35",
"gpio36", "gpio38", "gpio42",
"gpio43", "gpio46", "gpio55",
"gpio56", "gpio57", "gpio58";
function = "gpio";
bias-pull-down;
};
akro2 {
pins = "gpio15", "gpio35", "gpio38",
"gpio42", "gpio43", "gpio46",
"gpio55", "gpio56", "gpio57",
"gpio58";
drive-strength = <2>;
};
akro4 {
pins = "gpio14", "gpio36";
drive-strength = <4>;
};
};
/*
* Stock firmware has the following settings, so let's do the same.
* I don't sure why these are required.
*/
akro_pins: akro_pinmux {
akro {
pins = "gpio17", "gpio26", "gpio47";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
reset {
pins = "gpio45";
function = "gpio";
drive-strength = <2>;
bias-disable;
output-low;
};
gmac0_rgmii {
pins = "gpio25";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
};
};
&gsbi5 {
status = "okay";
qcom,mode = <GSBI_PROT_SPI>;
spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0000000 0x0020000>;
read-only;
};
partition@20000 {
label = "MIBIB";
reg = <0x0020000 0x0020000>;
read-only;
};
partition@40000 {
label = "SBL2";
reg = <0x0040000 0x0040000>;
read-only;
};
partition@80000 {
label = "SBL3";
reg = <0x0080000 0x0080000>;
read-only;
};
partition@100000 {
label = "DDRCONFIG";
reg = <0x0100000 0x0010000>;
read-only;
};
partition@110000 {
label = "SSD";
reg = <0x0110000 0x0010000>;
read-only;
};
partition@120000 {
label = "TZ";
reg = <0x0120000 0x0080000>;
read-only;
};
partition@1a0000 {
label = "RPM";
reg = <0x01a0000 0x0080000>;
read-only;
};
partition@220000 {
label = "APPSBL";
reg = <0x0220000 0x0080000>;
read-only;
};
partition@2a0000 {
label = "APPSBLENV";
reg = <0x02a0000 0x0010000>;
read-only;
};
factory: partition@2b0000 {
label = "PRODUCTDATA";
reg = <0x02b0000 0x0030000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_factory_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_factory_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_PRODUCTDATA_c: macaddr@c {
reg = <0xc 0x6>;
};
macaddr_PRODUCTDATA_12: macaddr@12 {
reg = <0x12 0x6>;
};
};
};
partition@2e0000 {
label = "ART";
reg = <0x02e0000 0x0040000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
partition@320000 {
label = "TP";
reg = <0x0320000 0x0040000>;
read-only;
};
partition@360000 {
label = "TINY";
reg = <0x0360000 0x0500000>;
read-only;
};
partition@860000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x0860000 0x17a0000>;
};
};
};
};
};
&adm_dma {
status = "okay";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
force_gen1 = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
ieee80211-freq-limit = <2400000 2483000>;
qcom,ath10k-calibration-variant = "NEC-Platforms-WG2600HP3";
nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port1>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
function-enumerator = <1>;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
function-enumerator = <2>;
default-state = "keep";
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_WAN;
function-enumerator = <3>;
default-state = "keep";
};
};
};
port@2 {
reg = <2>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port2>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
default-state = "keep";
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <3>;
default-state = "keep";
};
};
};
port@3 {
reg = <3>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port3>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
default-state = "keep";
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <3>;
default-state = "keep";
};
};
};
port@4 {
reg = <4>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port4>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
default-state = "keep";
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <3>;
default-state = "keep";
};
};
};
port@5 {
reg = <5>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port5>;
leds {
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <1>;
default-state = "keep";
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <2>;
default-state = "keep";
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_GREEN>;
function = LED_FUNCTION_LAN;
function-enumerator = <3>;
default-state = "keep";
};
};
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
qca,sgmii-rxclk-falling-edge;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
phy-mode = "rgmii";
qcom,id = <1>;
mdiobus = <&mdio0>;
nvmem-cells = <&macaddr_factory_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
mdiobus = <&mdio0>;
nvmem-cells = <&macaddr_factory_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};

487
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ad7200-c2600.dtsi
View File

@ -1,487 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
/ {
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
reserved-memory {
ramoops@42100000 {
compatible = "ramoops";
reg = <0x42100000 0x40000>;
record-size = <0x4000>;
console-size = <0x4000>;
ftrace-size = <0x4000>;
pmsg-size = <0x4000>;
};
};
aliases {
mdio-gpio0 = &mdio0;
label-mac-device = &gmac2;
};
};
&qcom_pinmux {
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs {
pins = "gpio20";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
usb0_pwr_en_pin: usb0_pwr_en_pin {
mux {
pins = "gpio25";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
output-high;
};
};
usb1_pwr_en_pin: usb1_pwr_en_pin {
mux {
pins = "gpio23";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
output-high;
};
};
};
&gsbi5 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
label = "MIBIB";
reg = <0x20000 0x20000>;
read-only;
};
partition@40000 {
label = "SBL2";
reg = <0x40000 0x20000>;
read-only;
};
partition@60000 {
label = "SBL3";
reg = <0x60000 0x30000>;
read-only;
};
partition@90000 {
label = "DDRCONFIG";
reg = <0x90000 0x10000>;
read-only;
};
partition@a0000 {
label = "SSD";
reg = <0xa0000 0x10000>;
read-only;
};
partition@b0000 {
label = "TZ";
reg = <0xb0000 0x30000>;
read-only;
};
partition@e0000 {
label = "RPM";
reg = <0xe0000 0x20000>;
read-only;
};
partition@100000 {
label = "fs-uboot";
reg = <0x100000 0x70000>;
read-only;
};
partition@170000 {
label = "uboot-env";
reg = <0x170000 0x40000>;
read-only;
};
partition@1b0000 {
label = "radio";
reg = <0x1b0000 0x40000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
precal_radio_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_radio_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
partition@1f0000 {
label = "os-image";
reg = <0x1f0000 0x400000>;
};
partition@5f0000 {
label = "rootfs";
reg = <0x5f0000 0x1900000>;
};
defaultmac: partition@1ef0000 {
label = "default-mac";
reg = <0x1ef0000 0x00200>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_defaultmac_8: macaddr@8 {
compatible = "mac-base";
reg = <0x8 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@1ef0200 {
label = "pin";
reg = <0x1ef0200 0x00200>;
read-only;
};
partition@1ef0400 {
label = "product-info";
reg = <0x1ef0400 0x0fc00>;
read-only;
};
partition@1f00000 {
label = "partition-table";
reg = <0x1f00000 0x10000>;
read-only;
};
partition@1f10000 {
label = "soft-version";
reg = <0x1f10000 0x10000>;
read-only;
};
partition@1f20000 {
label = "support-list";
reg = <0x1f20000 0x10000>;
read-only;
};
partition@1f30000 {
label = "profile";
reg = <0x1f30000 0x10000>;
read-only;
};
partition@1f40000 {
label = "default-config";
reg = <0x1f40000 0x10000>;
read-only;
};
partition@1f50000 {
label = "user-config";
reg = <0x1f50000 0x40000>;
read-only;
};
partition@1f90000 {
label = "qos-db";
reg = <0x1f90000 0x40000>;
read-only;
};
partition@1fd0000 {
label = "usb-config";
reg = <0x1fd0000 0x10000>;
read-only;
};
partition@1fe0000 {
label = "log";
reg = <0x1fe0000 0x20000>;
read-only;
};
};
};
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb0_pwr_en_pin>;
pinctrl-names = "default";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb1_pwr_en_pin>;
pinctrl-names = "default";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_defaultmac_8 (-1)>, <&precal_radio_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_defaultmac_8 0>, <&precal_radio_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_defaultmac_8 1>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_defaultmac_8 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};

168
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ad7200.dts
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@ -1,168 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/leds/common.h>
#include "qcom-ipq8064-ad7200-c2600.dtsi"
/ {
model = "TP-Link Talon AD7200";
compatible = "tplink,ad7200", "qcom,ipq8064";
aliases {
led-boot = &led_status;
led-failsafe = &led_status;
led-running = &led_status;
led-upgrade = &led_status;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
led_enable {
label = "led-enable";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
linux,code = <KEY_LIGHTS_TOGGLE>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
lan {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_BLUE>;
gpios = <&qcom_pinmux 2 GPIO_ACTIVE_HIGH>;
};
usb1 {
label = "blue:usb1";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
wlan5g {
label = "blue:wlan5g";
gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
};
usb3 {
label = "blue:usb3";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
};
wlan2g {
label = "blue:wlan2g";
gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
};
wan_orange {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_ORANGE>;
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
};
wan_blue {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_BLUE>;
gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
};
wps {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
};
wlan60g {
label = "blue:wlan60g";
gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
};
led_status: status {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio53", "gpio54", "gpio67";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio2", "gpio8", "gpio15", "gpio16", "gpio17", "gpio26",
"gpio33", "gpio55", "gpio56", "gpio66";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&mdio0 {
switch@10 {
ports {
port@1 {
label = "wan";
};
port@2 {
label = "lan1";
};
port@3 {
label = "lan2";
};
port@4 {
label = "lan3";
};
port@5 {
label = "lan4";
};
};
};
};
&pcie2 {
status = "okay";
max-link-speed = <1>;
};

219
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ap148.dts
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@ -1,219 +0,0 @@
#include "qcom-ipq8064-v1.0.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
aliases {
mdio-gpio0 = &mdio0;
};
};
&adm_dma {
status = "okay";
};
&flash {
partitions {
compatible = "qcom,smem-part";
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
/*
port@6 {
reg = <0>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
asym-pause;
};
};
*/
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};

254
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ap161.dts
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@ -1,254 +0,0 @@
#include "qcom-ipq8064-v1.0.dtsi"
/ {
model = "Qualcomm IPQ8064/AP161";
compatible = "qcom,ipq8064-ap161", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
aliases {
mdio-gpio0 = &mdio0;
};
};
&qcom_pinmux {
rgmii2_pins: rgmii2-pins {
mux {
pins = "gpio27", "gpio28", "gpio29",
"gpio30", "gpio31", "gpio32",
"gpio51", "gpio52", "gpio59",
"gpio60", "gpio61", "gpio62",
"gpio2", "gpio66";
};
};
};
&flash {
partitions {
compatible = "qcom,smem-part";
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
};
&pcie2 {
status = "okay";
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
/*
port@6 {
reg = <0>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
asym-pause;
};
};
*/
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
phy3: ethernet-phy@3 {
device_type = "ethernet-phy";
reg = <3>;
};
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mdiobus = <&mdio0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
mdiobus = <&mdio0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
mdiobus = <&mdio0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};

92
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-asus-onhub.dts
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@ -1,92 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2014 The ChromiumOS Authors
*/
#include "qcom-ipq8064-onhub.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/qcom,gsbi.h>
/ {
model = "ASUS OnHub";
compatible = "asus,onhub", "google,arkham", "qcom,ipq8064";
};
&qcom_pinmux {
ap3223_pins: ap3223_pinmux {
pins = "gpio22";
function = "gpio";
bias-none;
};
i2c7_pins: i2c7_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "gsbi7";
};
data {
pins = "gpio8";
bias-disable;
};
clk {
pins = "gpio9";
bias-disable;
};
};
};
&gsbi7 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C_UART>;
};
&gsbi7_i2c {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c7_pins>;
pinctrl-names = "default";
ap3223@1c {
compatible = "dynaimage,ap3223";
reg = <0x1c>;
pinctrl-0 = <&ap3223_pins>;
pinctrl-names = "default";
int-gpio = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
};
led-controller@32 {
compatible = "national,lp5523";
reg = <0x32>;
clock-mode = /bits/ 8 <1>;
#address-cells = <1>;
#size-cells = <0>;
led@4 {
reg = <4>;
color = <LED_COLOR_ID_GREEN>;
chan-name = "green:status";
linux,default-trigger = "default-on";
led-cur = /bits/ 8 <0xfa>;
max-cur = /bits/ 8 <0xff>;
};
led@5 {
reg = <5>;
color = <LED_COLOR_ID_BLUE>;
chan-name = "blue:status";
led-cur = /bits/ 8 <0xfa>;
max-cur = /bits/ 8 <0xff>;
};
led@8 {
reg = <8>;
color = <LED_COLOR_ID_RED>;
chan-name = "red:status";
led-cur = /bits/ 8 <0xfa>;
max-cur = /bits/ 8 <0xff>;
};
};
};

126
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-c2600.dts
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@ -1,126 +0,0 @@
#include <dt-bindings/leds/common.h>
#include "qcom-ipq8064-ad7200-c2600.dtsi"
/ {
model = "TP-Link Archer C2600";
compatible = "tplink,c2600", "qcom,ipq8064";
aliases {
led-boot = &power;
led-failsafe = &general;
led-running = &power;
led-upgrade = &general;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 49 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
ledswitch {
label = "ledswitch";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_LIGHTS_TOGGLE>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
lan {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
};
usb4 {
label = "white:usb_4";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
usb2 {
label = "white:usb_2";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
wps {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
wan_amber {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_AMBER>;
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
};
wan_white {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 33 GPIO_ACTIVE_LOW>;
};
power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
general: general {
label = "white:general";
gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio16", "gpio54", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio26", "gpio33",
"gpio53", "gpio66";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};

485
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-d7800.dts
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@ -1,485 +0,0 @@
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Netgear Nighthawk X4 D7800";
compatible = "netgear,d7800", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
reserved-memory {
rsvd@5fe00000 {
reg = <0x5fe00000 0x200000>;
reusable;
};
};
aliases {
mdio-gpio0 = &mdio0;
led-boot = &power_white;
led-failsafe = &power_amber;
led-running = &power_white;
led-upgrade = &power_amber;
};
chosen {
bootargs = "rootfstype=squashfs noinitrd";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
usb1 {
label = "white:usb1";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
usb2 {
label = "white:usb2";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
power_amber: power_amber {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_AMBER>;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
wan_white {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
wan_amber {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_AMBER>;
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
wps {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
esata {
label = "white:esata";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
power_white: power_white {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
wifi {
label = "white:wifi";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio6", "gpio54", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
"gpio24","gpio26", "gpio53", "gpio64";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
usb0_pwr_en_pins: usb0_pwr_en_pins {
mux {
pins = "gpio15";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
};
usb1_pwr_en_pins: usb1_pwr_en_pins {
mux {
pins = "gpio16", "gpio68";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
};
};
&sata_phy {
status = "okay";
};
&sata {
status = "okay";
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
&pcie0 {
status = "okay";
reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie2 {
status = "okay";
reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie2_pins>;
pinctrl-names = "default";
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot-partitions = <0x0 0x1180000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qcadata@0 {
label = "qcadata";
reg = <0x0000000 0x0c80000>;
read-only;
};
APPSBL@c80000 {
label = "APPSBL";
reg = <0x0c80000 0x0500000>;
read-only;
};
APPSBLENV@1180000 {
label = "APPSBLENV";
reg = <0x1180000 0x0080000>;
read-only;
};
art@1200000 {
label = "art";
reg = <0x1200000 0x0140000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
compatible = "mac-base";
reg = <0x6 0x6>;
#nvmem-cell-cells = <1>;
};
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
artbak: art@1340000 {
label = "artbak";
reg = <0x1340000 0x0140000>;
read-only;
};
kernel@1480000 {
label = "kernel";
reg = <0x1480000 0x0400000>;
};
ubi@1880000 {
label = "ubi";
reg = <0x1880000 0x6080000>;
};
reserve@7900000 {
label = "reserve";
reg = <0x7900000 0x0700000>;
read-only;
};
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_art_6 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};

263
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-db149.dts
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@ -1,263 +0,0 @@
#include "qcom-ipq8064-v1.0.dtsi"
/ {
model = "Qualcomm IPQ8064/DB149";
compatible = "qcom,ipq8064-db149", "qcom,ipq8064";
aliases {
serial0 = &gsbi2_serial;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
};
&qcom_pinmux {
rgmii0_pins: rgmii0_pins {
mux {
pins = "gpio2", "gpio66";
drive-strength = <8>;
bias-disable;
};
};
};
&gsbi2 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
gsbi2_serial: serial@12490000 {
status = "okay";
};
};
&gsbi4 {
status = "disabled";
};
&gsbi4_serial {
status = "disabled";
};
&flash {
m25p,fast-read;
partition@0 {
label = "lowlevel_init";
reg = <0x0 0x1b0000>;
};
partition@1 {
label = "u-boot";
reg = <0x1b0000 0x80000>;
};
partition@2 {
label = "u-boot-env";
reg = <0x230000 0x40000>;
};
partition@3 {
label = "caldata";
reg = <0x270000 0x40000>;
};
partition@4 {
label = "firmware";
reg = <0x2b0000 0x1d50000>;
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&pcie2 {
status = "okay";
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
/*
port@6 {
reg = <0>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
pause;
asym-pause;
};
};
*/
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
phy6: ethernet-phy@6 {
reg = <6>;
};
phy7: ethernet-phy@7 {
reg = <7>;
};
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <0>;
pinctrl-0 = <&rgmii0_pins>;
pinctrl-names = "default";
};
&gmac1 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
phy-handle = <&phy6>;
};
&gmac3 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <3>;
phy-handle = <&phy7>;
};

427
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-e8350-v1.dts
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@ -1,427 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Linksys E8350 V1 WiFi Router";
compatible = "linksys,e8350-v1", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
aliases {
serial0 = &gsbi4_serial;
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
wifi {
label = "wifi";
gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_power: power {
label = "green:power";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
wps {
label = "green:wps";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
};
wifi {
label = "green:wifi";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
};
};
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
nand-ecc-strength = <4>;
nand-bus-width = <8>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "ubi";
reg = <0 0x4000000>;
};
partition@4000000 {
label = "extra";
reg = <0x4000000 0x4000000>;
};
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio68","gpio65", "gpio67";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio26","gpio53", "gpio54";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
switch_reset: switch_reset_pins {
mux {
pins = "gpio63";
function = "gpio";
drive-strength = <12>;
bias-pull-up;
};
};
};
&gsbi5 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi5: spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
m25p80@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <51200000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:sbl1";
reg = <0x0000000 0x0010000>;
read-only;
};
partition@10000 {
label = "0:mibib";
reg = <0x0010000 0x0020000>;
read-only;
};
partition@30000 {
label = "0:sbl2";
reg = <0x0030000 0x0020000>;
read-only;
};
partition@50000 {
label = "0:sbl3";
reg = <0x0050000 0x0030000>;
read-only;
};
partition@80000 {
label = "0:ddrconfig";
reg = <0x0080000 0x0010000>;
read-only;
};
partition@90000 {
label = "0:ssd";
reg = <0x0090000 0x0010000>;
read-only;
};
partition@a0000 {
label = "0:tz";
reg = <0x00a0000 0x0030000>;
read-only;
};
partition@d0000 {
label = "0:rpm";
reg = <0x00d0000 0x0020000>;
read-only;
};
partition@f0000 {
label = "0:oldappsbl";
reg = <0x00f0000 0x0040000>;
read-only;
};
partition@130000 {
label = "0:appsblenv";
reg = <0x0130000 0x0040000>;
read-only;
};
art: partition@170000 {
label = "0:ART";
reg = <0x0170000 0x0020000>;
read-only;
};
partition@190000 {
label = "0:uboot";
reg = <0x0190000 0x0050000>;
read-only;
};
partition@1e0000 {
label = "0:oldnss1";
reg = <0x01e0000 0x0020000>;
read-only;
};
partition@200000 {
label = "0:nvram";
reg = <0x0200000 0x0020000>;
read-only;
};
partition@220000 {
label = "0:oldkernel";
reg = <0x0220000 0x01e0000>;
read-only;
};
};
};
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
max-link-speed = <1>;
};
&pcie1 {
status = "okay";
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
/* Switch from documentation require at least 12ms for reset */
reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
reset-post-delay-us = <12000>;
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&tcsr {
qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
compatible = "qcom,tcsr", "syscon";
};
&adm_dma {
status = "okay";
};

120
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ea7500-v1.dts
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@ -1,120 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include <dt-bindings/leds/common.h>
#include "qcom-ipq8064-eax500.dtsi"
/ {
model = "Linksys EA7500 V1 WiFi Router";
compatible = "linksys,ea7500-v1", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0xe000000>;
device_type = "memory";
};
aliases {
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
chosen {
/* look for root deviceblock nbr in this bootarg */
find-rootblock = "ubi.mtd=";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio65", "gpio68";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio6";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&partitions {
partition@5f80000 {
label = "sysdiag";
reg = <0x5f80000 0x100000>;
};
partition@6080000 {
label = "syscfg";
reg = <0x6080000 0x1f80000>;
};
};
&mdio0 {
switch@10 {
ports {
port@1 {
label = "wan";
};
port@2 {
label = "lan1";
};
port@3 {
label = "lan2";
};
port@4 {
label = "lan3";
};
port@5 {
label = "lan4";
};
};
};
};

126
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-ea8500.dts
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@ -1,126 +0,0 @@
#include <dt-bindings/leds/common.h>
#include "qcom-ipq8064-eax500.dtsi"
/ {
model = "Linksys EA8500 WiFi Router";
compatible = "linksys,ea8500", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
aliases {
mdio-gpio0 = &mdio0;
led-boot = &led_power;
led-failsafe = &led_power;
led-running = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
wps {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
};
led_power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
default-state = "keep";
};
wifi {
label = "green:wifi";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio65", "gpio67", "gpio68";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio6", "gpio53", "gpio54";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&sata_phy {
status = "okay";
};
&sata {
status = "okay";
};
&partitions {
partition@5f80000 {
label = "syscfg";
reg = <0x5f80000 0x2080000>;
};
};
&gmac1 {
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <1>;
qcom,rgmii_delay = <0>;
qcom,emulation = <0>;
};
/* LAN */
&gmac2 {
qcom,phy_mdio_addr = <0>; /* none */
qcom,poll_required = <0>; /* no polling */
qcom,rgmii_delay = <0>;
qcom,emulation = <0>;
};

377
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-eax500.dtsi
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@ -1,377 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
/ {
chosen {
bootargs = "console=ttyMSM0,115200n8";
/* append to bootargs adding the root deviceblock nbr from bootloader */
append-rootblock = "ubi.mtd=";
};
};
&qcom_pinmux {
/* eax500 routers reuse the pcie2 reset pin for switch reset pin */
switch_reset: switch_reset_pins {
mux {
pins = "gpio63";
function = "gpio";
drive-strength = <12>;
bias-pull-up;
};
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&precal_art_1000>;
nvmem-cell-names = "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&precal_art_5000>;
nvmem-cell-names = "pre-calibration";
};
};
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot-partitions = <0x0 0x0c80000>;
partitions: partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0000000 0x0040000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x0040000 0x0140000>;
read-only;
};
partition@180000 {
label = "SBL2";
reg = <0x0180000 0x0140000>;
read-only;
};
partition@2c0000 {
label = "SBL3";
reg = <0x02c0000 0x0280000>;
read-only;
};
partition@540000 {
label = "DDRCONFIG";
reg = <0x0540000 0x0120000>;
read-only;
};
partition@660000 {
label = "SSD";
reg = <0x0660000 0x0120000>;
read-only;
};
partition@780000 {
label = "TZ";
reg = <0x0780000 0x0280000>;
read-only;
};
partition@a00000 {
label = "RPM";
reg = <0x0a00000 0x0280000>;
read-only;
};
art: partition@c80000 {
label = "art";
reg = <0x0c80000 0x0140000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
precal_art_1000: pre-calibration@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: pre-calibration@5000 {
reg = <0x5000 0x2f20>;
};
};
};
partition@dc0000 {
label = "APPSBL";
reg = <0x0dc0000 0x0100000>;
read-only;
};
partition@ec0000 {
label = "u_env";
reg = <0x0ec0000 0x0040000>;
};
partition@f00000 {
label = "s_env";
reg = <0x0f00000 0x0040000>;
};
partition@f40000 {
label = "devinfo";
reg = <0x0f40000 0x0040000>;
nvmem-layout {
compatible = "ascii-eq-delim-env";
#address-cells = <1>;
#size-cells = <1>;
hw_mac_addr: hw_mac_addr {
compatible = "mac-base";
#nvmem-cell-cells = <1>;
};
};
};
partition@f80000 {
label = "kernel1";
reg = <0x0f80000 0x2800000>; /* 4 MB, spill to rootfs */
};
partition@1380000 {
label = "rootfs1";
reg = <0x1380000 0x2400000>;
};
partition@3780000 {
label = "kernel2";
reg = <0x3780000 0x2800000>;
};
partition@3b80000 {
label = "rootfs2";
reg = <0x3b80000 0x2400000>;
};
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
/* Switch from documentation require at least 10ms for reset */
reset-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_HIGH>;
reset-post-delay-us = <12000>;
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&hw_mac_addr 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&hw_mac_addr 1>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};

413
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-fap-421e.dts
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@ -1,413 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Fortinet FAP-421E";
compatible = "fortinet,fap-421e", "qcom,ipq8064";
memory@42000000 {
device_type = "memory";
reg = <0x42000000 0xe000000>;
};
reserved-memory {
rsvd@41200000 {
no-map;
reg = <0x41200000 0x300000>;
};
wifi_dump@44000000 {
no-map;
reg = <0x44000000 0x600000>;
};
};
aliases {
led-boot = &led_power_yellow;
led-failsafe = &led_power_yellow;
led-running = &led_power_yellow;
led-upgrade = &led_power_yellow;
label-mac-device = &gmac0;
};
chosen {
bootargs-override = "console=ttyMSM0,9600n8";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
eth1-amber {
label = "amber:eth1";
gpios = <&qcom_pinmux 27 GPIO_ACTIVE_LOW>;
};
eth1-yellow {
label = "yellow:eth1";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
};
eth2-amber {
label = "amber:eth2";
gpios = <&qcom_pinmux 29 GPIO_ACTIVE_LOW>;
};
eth2-yellow {
label = "yellow:eth2";
gpios = <&qcom_pinmux 28 GPIO_ACTIVE_LOW>;
};
power-amber {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_AMBER>;
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
};
led_power_yellow: power-yellow {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_YELLOW>;
gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
};
2g-yellow {
label = "yellow:2g";
gpios = <&qcom_pinmux 30 GPIO_ACTIVE_LOW>;
};
5g-yellow {
label = "yellow:5g";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
bias-pull-up;
drive-strength = <2>;
pins = "gpio56";
};
};
led_pins: led_pins {
mux {
bias-pull-down;
drive-strength = <2>;
function = "gpio";
output-low;
pins = "gpio23";
};
};
rgmii2_pins: rgmii2-pins {
mux {
bias-disable;
drive-strength = <16>;
function = "rgmii2";
pins = "gpio66";
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs {
pins = "gpio20";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
uart0_pins: uart0_pins {
mux {
bias-disable;
drive-strength = <12>;
function = "gsbi7";
pins = "gpio6", "gpio7";
};
};
usb_pwr_en_pins: usb_pwr_en_pins {
mux {
pins = "gpio22";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-low;
};
};
};
&gsbi7 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
};
&gsbi7_serial{
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
status = "okay";
};
&gsbi5 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
m25p,fast-read;
partition@0 {
label = "SBL1";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
label = "MIBIB";
reg = <0x20000 0x20000>;
read-only;
};
partition@40000 {
label = "SBL2";
reg = <0x40000 0x40000>;
read-only;
};
partition@80000 {
label = "SBL3";
reg = <0x80000 0x80000>;
read-only;
};
partition@100000 {
label = "DDRCONFIG";
reg = <0x100000 0x10000>;
read-only;
};
partition@110000 {
label = "SSD";
reg = <0x110000 0x10000>;
read-only;
};
partition@120000 {
label = "TZ";
reg = <0x120000 0x80000>;
read-only;
};
partition@1a0000 {
label = "RPM";
reg = <0x1a0000 0x80000>;
read-only;
};
partition@220000 {
label = "APPSBL";
reg = <0x220000 0x80000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_appsbl_7ff80: mac-address@7ff80 {
compatible = "mac-base";
reg = <0x7ff80 0xc>;
#nvmem-cell-cells = <1>;
};
};
};
partition@2a0000 {
label = "APPSBLENV";
reg = <0x2a0000 0x40000>;
};
partition@2e0000 {
label = "ART";
reg = <0x2e0000 0x40000>;
read-only;
};
partition@320000 {
label = "kernel";
reg = <0x320000 0x600000>;
};
partition@920000 {
label = "ubi";
reg = <0x920000 0x1400000>;
};
partition@1d20000 {
label = "reserved";
reg = <0x1d20000 0x260000>;
read-only;
};
partition@1f80000 {
label = "config";
reg = <0x1f80000 0x80000>;
read-only;
};
};
};
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb_pwr_en_pins>;
pinctrl-names = "default";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_appsbl_7ff80 8>;
nvmem-cell-names = "mac-address";
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_appsbl_7ff80 16>;
nvmem-cell-names = "mac-address";
};
};
};
&adm_dma {
status = "okay";
};
&mdio0 {
status = "okay";
#address-cells = <0x1>;
#size-cells = <0x0>;
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy1: ethernet-phy@1 {
reg = <1>;
};
phy2: ethernet-phy@2 {
reg = <2>;
};
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_appsbl_7ff80 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_appsbl_7ff80 1>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};

383
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-g10.dts
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@ -1,383 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
compatible = "asrock,g10", "qcom,ipq8064";
model = "ASRock G10";
aliases {
ethernet0 = &gmac1;
ethernet1 = &gmac0;
led-boot = &led_status_blue;
led-failsafe = &led_status_amber;
led-running = &led_status_blue;
led-upgrade = &led_status_amber;
};
chosen {
bootargs-override = "console=ttyMSM0,115200n8";
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
/*
* this is a bit misleading. Because there are about seven
* multicolor LEDs connected all wired together in parallel.
*/
status_yellow {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
led_status_amber: status_amber {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_AMBER>;
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
led_status_blue: status_blue {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
/*
* LED is declared in vendors boardfile but it's not
* working and the manual doesn't mention anything
* about the LED being white.
status_white {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
*/
};
i2c-gpio {
#address-cells = <1>;
#size-cells = <0>;
compatible = "i2c-gpio";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>, /* sda */
<&qcom_pinmux 54 GPIO_ACTIVE_HIGH>; /* scl */
i2c-gpio,delay-us = <5>;
i2c-gpio,scl-output-only;
mcu@50 {
reg = <0x50>;
compatible = "sonix,sn8f25e21";
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
ir-remote {
label = "ir-remote";
gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps5g {
label = "wps5g";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
wps2g {
label = "wps2g";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
};
&adm_dma {
status = "okay";
};
&gmac1 {
status = "okay";
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
phy-mode = "rgmii";
qcom,id = <1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gsbi4_serial {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot-partitions = <0x0 0x1200000>;
partitions {
compatible = "qcom,smem-part";
};
};
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi5g: wifi@1,0 {
reg = <0x00010000 0 0 0 0>;
compatible = "qcom,ath10k";
qcom,ath10k-calibration-variant = "ASRock-G10";
};
};
};
&pcie1 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi2g: wifi@1,0 {
reg = <0x00010000 0 0 0 0>;
compatible = "qcom,ath10k";
qcom,ath10k-calibration-variant = "ASRock-G10";
};
};
};
&qcom_pinmux {
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio26";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
button_pins: button_pins {
mux {
pins = "gpio15", "gpio16", "gpio64", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
uart0_pins: uart0_pins {
mux {
pins = "gpio10", "gpio11";
function = "gsbi4";
drive-strength = <10>;
bias-disable;
};
};
};
&rpm {
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&tcsr {
qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
};
/delete-node/ &pcie2_pins;
/delete-node/ &pcie2;

559
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-mi-router-hd.dts
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@ -1,559 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Xiaomi Mi Router HD";
compatible = "xiaomi,mi-router-hd", "qcom,ipq8064";
memory@0 {
device_type = "memory";
reg = <0x42000000 0x1e000000>;
};
reserved-memory {
rsvd@44600000 {
reg = <0x44600000 0x200000>; /* IPQ_TZ_APPS_ADDR */
no-map;
};
};
aliases {
label-mac-device = &gmac1;
mdio-gpio0 = &mdio0;
led-boot = &led_status_yellow;
led-failsafe = &led_status_red;
led-running = &led_status_blue;
led-upgrade = &led_status_yellow;
};
chosen {
bootargs = "rootfstype=squashfs noinitrd";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
power {
label = "power"; /* Labeled POWER on the device, but using for sleep mode */
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_status_red: led_status_red {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
led_status_blue: led_status_blue {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_BLUE>;
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
led_status_yellow: led_status_yellow {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_YELLOW>;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
};
i2c_gpio_0 { // GSBI1
compatible = "i2c-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
sda-gpios = <&qcom_pinmux 53 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&qcom_pinmux 54 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
fan@2f {
compatible = "microchip,emc2305";
reg = <0x2f>;
emc2305,pwm-channel = <0>;
emc2305,pwm-min = <0>;
emc2305,pwm-max = <255>;
};
};
i2c_gpio_1 { // GSBI2
compatible = "i2c-gpio";
#address-cells = <1>;
#size-cells = <0>;
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
sda-gpios = <&qcom_pinmux 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&qcom_pinmux 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-gpio,delay-us = <5>;
tmp75@48 {
compatible = "ti,tmp75";
reg = <0x48>;
#address-cells = <1>;
#size-cells = <0>;
#thermal-sensor-cells = <0>;
status = "okay";
};
};
};
// https://github.com/openwrt/openwrt/commit/622ce713ca246aa465bf28d2a743f96999085ea2
// https://github.com/openwrt/openwrt/commit/2336c2dbb1929837f7e42d4315c8073342a5b46b
// https://forum.openwrt.org/t/failed-to-startup-an-ipq806x-router-on-kernel-5-4/60775/41
&CPU_SPC {
status = "disabled";
};
&adm_dma {
status = "okay";
};
&qcom_pinmux {
i2c1_pins: i2c1_pins { // GSBI1 - EMC2301
mux {
pins = "gpio53", "gpio54";
function = "gsbi1";
drive-strength = <12>;
bias-none;
input;
};
};
i2c2_pins: i2c2_pins { // GSBI2 - TMP75
mux {
pins = "gpio24", "gpio25";
function = "gsbi2";
drive-strength = <12>;
bias-none;
input;
};
};
button_pins: button_pins {
mux {
pins = "gpio16", "gpio68";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
usb_pwr_en_pins: usb_pwr_en_pins {
mux {
pins = "gpio56";
function = "gpio";
drive-strength = <12>;
bias-pull-up;
output-high;
};
};
};
&sata_phy {
status = "okay";
};
&sata {
status = "okay";
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb_pwr_en_pins>;
pinctrl-names = "default";
};
&pcie0 {
status = "okay";
reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_1006 0>, <&precal_art_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_5006 0>, <&precal_art_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-bus-width = <8>;
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot-partitions = <0x0 0xf0000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x40000>;
read-only;
};
partition@40000 {
label = "MIBIB";
reg = <0x40000 0x80000>;
read-only;
};
partition@c0000 {
label = "SBL2";
reg = <0xc0000 0x80000>;
read-only;
};
partition@140000 {
label = "SBL3";
reg = <0x140000 0x80000>;
read-only;
};
partition@1c0000 {
label = "DDRCONFIG";
reg = <0x1c0000 0x80000>;
read-only;
};
partition@240000 {
label = "SSD";
reg = <0x240000 0x80000>;
read-only;
};
partition@2c0000 {
label = "TZ";
reg = <0x2c0000 0x80000>;
read-only;
};
partition@340000 {
label = "RPM";
reg = <0x340000 0x80000>;
read-only;
};
partition@3c0000 {
label = "APPSBL";
reg = <0x3c0000 0x100000>;
read-only;
};
partition@4c0000 {
label = "APPSBLENV";
reg = <0x4c0000 0x80000>;
};
art: partition@540000 {
label = "ART";
reg = <0x540000 0x80000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_art_6: macaddr@6 {
compatible = "mac-base";
reg = <0x6 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_art_1006: macaddr@1006 {
compatible = "mac-base";
reg = <0x1006 0x6>;
#nvmem-cell-cells = <1>;
};
macaddr_art_5006: macaddr@5006 {
compatible = "mac-base";
reg = <0x5006 0x6>;
#nvmem-cell-cells = <1>;
};
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
partition@5c0000 {
label = "BOOTCONFIG";
reg = <0x5c0000 0x40000>;
read-only;
};
partition@600000 {
label = "bdata";
reg = <0x600000 0x80000>;
};
partition@680000 {
label = "crash";
reg = <0x680000 0x80000>;
read-only;
};
partition@700000 {
label = "crash_syslog";
reg = <0x700000 0x80000>;
read-only;
};
partition@780000 {
label = "rsvd";
reg = <0x780000 0x80000>;
read-only;
};
/* Stock U-Boot support Dual Boot */
partition@800000 {
label = "kernel_dup";
reg = <0x800000 0x400000>;
};
partition@c00000 {
label = "kernel";
reg = <0xc00000 0x400000>;
};
partition@1000000 {
label = "ubi";
reg = <0x1000000 0xf000000>;
};
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_art_0 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_art_6 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};

545
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-onhub.dtsi
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@ -1,545 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2014 The ChromiumOS Authors
*/
#include "qcom-ipq8064-smb208.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
aliases {
ethernet0 = &gmac0;
ethernet1 = &gmac2;
mdio-gpio0 = &mdio;
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
dev {
label = "dev";
gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_CONFIG>;
debounce-interval = <60>;
wakeup-source;
};
};
mdio: mdio {
compatible = "virtual,mdio-gpio";
#address-cells = <1>;
#size-cells = <0>;
gpios = <&qcom_pinmux 1 GPIO_ACTIVE_HIGH>,
<&qcom_pinmux 0 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&mdio_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac0>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
};
};
};
soc {
rng@1a500000 {
status = "disabled";
};
sound {
compatible = "google,storm-audio";
qcom,model = "ipq806x-storm";
cpu = <&lpass>;
codec = <&max98357a>;
};
lpass: lpass@28100000 {
status = "okay";
pinctrl-names = "default", "idle";
pinctrl-0 = <&mi2s_default>;
pinctrl-1 = <&mi2s_idle>;
};
max98357a: max98357a {
compatible = "maxim,max98357a";
#sound-dai-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&sdmode_pins>;
sdmode-gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
rgmii0_pins: rgmii0_pins {
mux {
pins = "gpio2", "gpio66";
drive-strength = <8>;
bias-disable;
};
};
mi2s_pins {
mi2s_default: mi2s_default {
dout {
pins = "gpio32";
function = "mi2s";
drive-strength = <16>;
bias-disable;
};
sync {
pins = "gpio27";
function = "mi2s";
drive-strength = <16>;
bias-disable;
};
clk {
pins = "gpio28";
function = "mi2s";
drive-strength = <16>;
bias-disable;
};
};
mi2s_idle: mi2s_idle {
dout {
pins = "gpio32";
function = "mi2s";
drive-strength = <2>;
bias-pull-down;
};
sync {
pins = "gpio27";
function = "mi2s";
drive-strength = <2>;
bias-pull-down;
};
clk {
pins = "gpio28";
function = "mi2s";
drive-strength = <2>;
bias-pull-down;
};
};
};
mdio_pins: mdio_pins {
mux {
pins = "gpio0", "gpio1";
function = "gpio";
drive-strength = <8>;
bias-disable;
};
rst {
pins = "gpio26";
output-low;
};
};
sdmode_pins: sdmode_pinmux {
pins = "gpio25";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
sdcc1_pins: sdcc1_pinmux {
mux {
pins = "gpio38", "gpio39", "gpio40",
"gpio41", "gpio42", "gpio43",
"gpio44", "gpio45", "gpio46",
"gpio47";
function = "sdc1";
};
cmd {
pins = "gpio45";
drive-strength = <10>;
bias-pull-up;
};
data {
pins = "gpio38", "gpio39", "gpio40",
"gpio41", "gpio43", "gpio44",
"gpio46", "gpio47";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio42";
drive-strength = <16>;
bias-pull-down;
};
};
i2c1_pins: i2c1_pinmux {
pins = "gpio53", "gpio54";
function = "gsbi1";
bias-disable;
};
rpm_i2c_pinmux: rpm_i2c_pinmux {
mux {
pins = "gpio12", "gpio13";
function = "gsbi4";
drive-strength = <12>;
bias-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
/delete-property/ bias-none;
/delete-property/ drive-strength;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs {
pins = "gpio20";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
fw_pinmux {
wp {
pins = "gpio17";
output-low;
};
};
button_pins: button_pins {
recovery {
pins = "gpio16";
function = "gpio";
bias-none;
};
developer {
pins = "gpio15";
function = "gpio";
bias-none;
};
};
spi6_pins: spi6_pins {
mux {
pins = "gpio55", "gpio56", "gpio58";
function = "gsbi6";
bias-pull-down;
};
data {
pins = "gpio55", "gpio56";
drive-strength = <10>;
};
cs {
pins = "gpio57";
drive-strength = <10>;
bias-pull-up;
output-high;
};
clk {
pins = "gpio58";
drive-strength = <12>;
};
};
};
&adm_dma {
status = "okay";
};
&gmac0 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <0>;
pinctrl-0 = <&rgmii0_pins>;
pinctrl-names = "default";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gsbi1 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C_UART>;
};
&gsbi1_i2c {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
tpm@20 {
compatible = "infineon,slb9645tt";
reg = <0x20>;
powered-while-suspended;
};
};
&gsbi4 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C_UART>;
};
&gsbi4_serial {
status = "okay";
};
&gsbi5 {
status = "okay";
qcom,mode = <GSBI_PROT_SPI>;
spi4: spi@1a280000 {
status = "okay";
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
flash: flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
};
&gsbi6 {
status = "okay";
qcom,mode = <GSBI_PROT_SPI>;
};
&gsbi6_spi {
status = "okay";
spi-max-frequency = <25000000>;
pinctrl-0 = <&spi6_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>;
dmas = <&adm_dma 8 0xb>,
<&adm_dma 7 0x14>;
dma-names = "rx", "tx";
/*
* This "spidev" was included in the manufacturer device tree. I suspect
* it's the (unused) Zigbee radio -- SiliconLabs EM3581 Zigbee? There's
* no driver or binding for this at the moment.
*/
spidev@0 {
compatible = "spidev";
reg = <0>;
spi-max-frequency = <25000000>;
};
};
&pcie0 {
status = "okay";
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupt-controller;
ath10k@0,0 {
reg = <0 0 0 0 0>;
device_type = "pci";
qcom,ath10k-sa-gpio = <2 3 4 0>;
qcom,ath10k-sa-gpio-func = <5 5 5 0>;
};
};
};
&pcie1 {
status = "okay";
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupt-controller;
ath10k@0,0 {
reg = <0 0 0 0 0>;
device_type = "pci";
qcom,ath10k-sa-gpio = <2 3 4 0>;
qcom,ath10k-sa-gpio-func = <5 5 5 0>;
};
};
};
&pcie2 {
status = "okay";
pcie@0 {
reg = <0 0 0 0 0>;
#interrupt-cells = <1>;
#size-cells = <2>;
#address-cells = <3>;
device_type = "pci";
interrupt-controller;
ath10k@0,0 {
reg = <0 0 0 0 0>;
device_type = "pci";
};
};
};
&rpm {
pinctrl-0 = <&rpm_i2c_pinmux>;
pinctrl-names = "default";
};
&sdcc1 {
status = "okay";
pinctrl-0 = <&sdcc1_pins>;
pinctrl-names = "default";
/delete-property/ mmc-ddr-1_8v;
};
&tcsr {
compatible = "qcom,tcsr-ipq8064", "qcom,tcsr", "syscon";
qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};

415
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-r7500.dts
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@ -1,415 +0,0 @@
#include "qcom-ipq8064-v1.0.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
model = "Netgear Nighthawk X4 R7500";
compatible = "netgear,r7500", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0xe000000>;
device_type = "memory";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
aliases {
mdio-gpio0 = &mdio0;
led-boot = &power_white;
led-failsafe = &power_amber;
led-running = &power_white;
led-upgrade = &power_amber;
};
chosen {
bootargs = "rootfstype=squashfs noinitrd";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
usb1 {
label = "white:usb1";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
usb2 {
label = "white:usb2";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
power_amber: power_amber {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_AMBER>;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
wan_white {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
wan_amber {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_AMBER>;
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
wps {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
esata {
label = "white:esata";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
power_white: power_white {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
wifi {
label = "white:wifi";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio6", "gpio54", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
"gpio24","gpio26", "gpio53", "gpio64";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&gsbi5 {
status = "disabled";
spi@1a280000 {
status = "disabled";
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot-partitions = <0x0 0x1180000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qcadata@0 {
label = "qcadata";
reg = <0x0000000 0x0c80000>;
read-only;
};
APPSBL@c80000 {
label = "APPSBL";
reg = <0x0c80000 0x0500000>;
read-only;
};
APPSBLENV@1180000 {
label = "APPSBLENV";
reg = <0x1180000 0x0080000>;
read-only;
};
art: art@1200000 {
label = "art";
reg = <0x1200000 0x0140000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
reg = <0x6 0x6>;
};
};
};
kernel@1340000 {
label = "kernel";
reg = <0x1340000 0x0400000>;
};
ubi@1740000 {
label = "ubi";
reg = <0x1740000 0x1600000>;
};
netgear@2d40000 {
label = "netgear";
reg = <0x2d40000 0x0c00000>;
read-only;
};
reserve@3940000 {
label = "reserve";
reg = <0x3940000 0x46c0000>;
read-only;
};
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_art_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&tcsr {
qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
compatible = "qcom,tcsr";
};
&adm_dma {
status = "okay";
};

477
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-r7500v2.dts
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@ -1,477 +0,0 @@
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Netgear Nighthawk X4 R7500v2";
compatible = "netgear,r7500v2", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
reserved-memory {
rsvd@5fe00000 {
reg = <0x5fe00000 0x200000>;
reusable;
};
};
aliases {
mdio-gpio0 = &mdio0;
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
chosen {
bootargs = "rootfstype=squashfs noinitrd";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
usb1 {
label = "amber:usb1";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
usb3 {
label = "amber:usb3";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
status {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_AMBER>;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
internet {
label = "white:internet";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
wan {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
wps {
function = LED_FUNCTION_WPS;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
esata {
label = "white:esata";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
wifi {
label = "white:wifi";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
};
};
};
&adm_dma {
status = "okay";
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio6", "gpio54", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio22", "gpio23",
"gpio24","gpio26", "gpio53", "gpio64";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
usb0_pwr_en_pins: usb0_pwr_en_pins {
mux {
pins = "gpio15";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
};
usb1_pwr_en_pins: usb1_pwr_en_pins {
mux {
pins = "gpio16", "gpio68";
function = "gpio";
drive-strength = <12>;
bias-pull-down;
output-high;
};
};
};
&sata_phy {
status = "okay";
};
&sata {
status = "okay";
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
&pcie0 {
status = "okay";
reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_6 1>, <&precal_art_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_art_6 2>, <&precal_art_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&nand {
status = "okay";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot-partitions = <0x0 0x1180000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
qcadata@0 {
label = "qcadata";
reg = <0x0000000 0x0c80000>;
read-only;
};
APPSBL@c80000 {
label = "APPSBL";
reg = <0x0c80000 0x0500000>;
read-only;
};
APPSBLENV@1180000 {
label = "APPSBLENV";
reg = <0x1180000 0x0080000>;
read-only;
};
art@1200000 {
label = "art";
reg = <0x1200000 0x0140000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_art_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_art_6: macaddr@6 {
compatible = "mac-base";
reg = <0x6 0x6>;
#nvmem-cell-cells = <1>;
};
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
artbak: art@1340000 {
label = "artbak";
reg = <0x1340000 0x0140000>;
read-only;
};
kernel@1480000 {
label = "kernel";
reg = <0x1480000 0x0400000>;
};
ubi@1880000 {
label = "ubi";
reg = <0x1880000 0x6080000>;
};
reserve@7900000 {
label = "reserve";
reg = <0x7900000 0x0700000>;
read-only;
};
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_art_6 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_art_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};

375
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-rg-mtfi-m520.dts
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@ -1,375 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Ruijie RG-MTFi-M520";
compatible = "ruijie,rg-mtfi-m520", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x7e000000>;
device_type = "memory";
};
aliases {
mdio-gpio0 = &mdio0;
sdcc1 = &sdcc1;
led-boot = &led_sys;
led-failsafe = &led_sys;
led-running = &led_sys;
led-upgrade = &led_sys;
};
chosen {
bootargs = "root=/dev/mmcblk0p3 rootfstype=squashfs,ext4 rootwait noinitrd";
};
leds {
compatible = "gpio-leds";
led_sys: sys {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio_ext 15 GPIO_ACTIVE_LOW>;
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio54";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
mdio0_pins: mdio0-pins {
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2-pins {
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
input-disable;
};
};
sdcc1_pins: sdcc1_pinmux {
mux {
pins = "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
"gpio43", "gpio44", "gpio45", "gpio46", "gpio47";
function = "sdc1";
};
cmd {
pins = "gpio45";
drive-strength = <10>;
bias-pull-up;
};
data {
pins = "gpio38", "gpio39", "gpio40", "gpio41",
"gpio43", "gpio44", "gpio46", "gpio47";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio42";
drive-strength = <16>;
bias-disable;
};
};
spi_pins: spi_pins {
cs {
pins = "gpio20";
drive-strength = <12>;
};
};
};
&gsbi2 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "okay";
i2c@124a0000 {
status = "okay";
lm75@48 {
compatible = "lm75";
reg = <0x48>;
};
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
gpio_ext: tca9539@74 {
compatible = "ti,tca9539";
reg = <0x74>;
gpio-controller;
#gpio-cells = <2>;
};
};
};
&gsbi5 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi4: spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
m25p80@0 {
compatible = "s25fl256s1";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
SBL1@0 {
label = "SBL1";
reg = <0x0 0x10000>;
read-only;
};
MIBIB@10000 {
label = "MIBIB";
reg = <0x10000 0x10000>;
read-only;
};
SBL2@20000 {
label = "SBL2";
reg = <0x20000 0x20000>;
read-only;
};
SBL3@40000 {
label = "SBL3";
reg = <0x40000 0x30000>;
read-only;
};
DDRCONFIG@70000 {
label = "DDRCONFIG";
reg = <0x70000 0x10000>;
read-only;
};
PRODUCTINFO@80000 {
label = "PRODUCTINFO";
reg = <0x80000 0x10000>;
read-only;
};
TZ@90000 {
label = "TZ";
reg = <0x90000 0x30000>;
read-only;
};
RPM@c0000 {
label = "RPM";
reg = <0xc0000 0x20000>;
read-only;
};
APPSBL@e0000 {
label = "APPSBL";
reg = <0xe0000 0x80000>;
read-only;
};
APPSBLENV@160000 {
label = "APPSBLENV";
reg = <0x160000 0x10000>;
read-only;
};
BOOTCONFIG@170000 {
label = "BOOTCONFIG";
reg = <0x170000 0x10000>;
read-only;
};
ART@180000 {
label = "ART";
reg = <0x180000 0x40000>;
read-only;
};
};
};
};
&sata_phy {
status = "okay";
};
&sata {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
&pcie1 {
status = "okay";
reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&sdcc1 {
status = "okay";
pinctrl-0 = <&sdcc1_pins>;
pinctrl-names = "default";
};
&adm_dma {
status = "okay";
};
&CPU_SPC {
status = "disabled";
};

230
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-tplink-onhub.dts
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@ -1,230 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2014 The ChromiumOS Authors
*/
#include "qcom-ipq8064-onhub.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/qcom,gsbi.h>
/ {
model = "TP-Link OnHub";
compatible = "tplink,onhub", "google,whirlwind-sp5", "qcom,ipq8064";
};
&qcom_pinmux {
gpio-line-names = "",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
"",
/* RECOVERY_SW_L is crossystem ABI. */
"RECOVERY_SW_L", /* 16 */
/* AP_FLASH_WP_L is crossystem ABI. */
"AP_FLASH_WP_L" /* 17 */;
i2c7_pins: i2c7_pinmux {
mux {
pins = "gpio8", "gpio9";
function = "gsbi7";
};
data {
pins = "gpio8";
bias-disable;
};
clk {
pins = "gpio9";
bias-disable;
};
};
};
&gsbi7 {
status = "okay";
qcom,mode = <GSBI_PROT_I2C_UART>;
};
&gsbi7_i2c {
status = "okay";
clock-frequency = <100000>;
pinctrl-0 = <&i2c7_pins>;
pinctrl-names = "default";
led-controller@32 {
compatible = "national,lp5523";
reg = <0x32>;
clock-mode = /bits/ 8 <1>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
chan-name = "red:status-0";
linux,default-trigger = "default-on";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
chan-name = "green:status-0";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
chan-name = "blue:status-0";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@3 {
reg = <3>;
color = <LED_COLOR_ID_RED>;
chan-name = "red:status-1";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@4 {
reg = <4>;
color = <LED_COLOR_ID_GREEN>;
chan-name = "green:status-1";
linux,default-trigger = "default-on";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@5 {
reg = <5>;
color = <LED_COLOR_ID_BLUE>;
chan-name = "blue:status-1";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@6 {
reg = <6>;
color = <LED_COLOR_ID_RED>;
chan-name = "red:status-2";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@7 {
reg = <7>;
color = <LED_COLOR_ID_GREEN>;
chan-name = "green:status-2";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@8 {
reg = <8>;
color = <LED_COLOR_ID_BLUE>;
chan-name = "blue:status-2";
linux,default-trigger = "default-on";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
};
led-controller@33 {
compatible = "national,lp5523";
reg = <0x33>;
clock-mode = /bits/ 8 <1>;
#address-cells = <1>;
#size-cells = <0>;
led@0 {
reg = <0>;
color = <LED_COLOR_ID_RED>;
chan-name = "red:status-3";
linux,default-trigger = "default-on";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@1 {
reg = <1>;
color = <LED_COLOR_ID_GREEN>;
chan-name = "green:status-3";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@2 {
reg = <2>;
color = <LED_COLOR_ID_BLUE>;
chan-name = "blue:status-3";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@3 {
reg = <3>;
color = <LED_COLOR_ID_RED>;
chan-name = "red:status-4";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@4 {
reg = <4>;
color = <LED_COLOR_ID_GREEN>;
chan-name = "green:status-4";
linux,default-trigger = "default-on";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@5 {
reg = <5>;
color = <LED_COLOR_ID_BLUE>;
chan-name = "blue:status-4";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@6 {
reg = <6>;
color = <LED_COLOR_ID_RED>;
chan-name = "red:status-5";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@7 {
reg = <7>;
color = <LED_COLOR_ID_GREEN>;
chan-name = "green:status-5";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
led@8 {
reg = <8>;
color = <LED_COLOR_ID_BLUE>;
chan-name = "blue:status-5";
linux,default-trigger = "default-on";
led-cur = /bits/ 8 <0x64>;
max-cur = /bits/ 8 <0x78>;
};
};
};

347
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-unifi-ac-hd.dts
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@ -1,347 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Ubiquiti UniFi AC HD";
compatible = "ubnt,unifi-ac-hd", "qcom,ipq8064";
aliases {
label-mac-device = &gmac2;
led-boot = &led_dome_white;
led-failsafe = &led_dome_white;
led-running = &led_dome_blue;
led-upgrade = &led_dome_blue;
mdio-gpio0 = &mdio0;
ethernet0 = &gmac2;
ethernet1 = &gmac1;
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
led_dome_blue: dome_blue {
label = "blue:dome";
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
led_dome_white: dome_white {
label = "white:dome";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio68";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio9", "gpio53";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
output-low;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
drive-strength = <10>;
bias-none;
};
cs {
pins = "gpio20";
drive-strength = <12>;
};
};
};
&CPU_SPC {
status = "disabled";
};
&gsbi5 {
status = "okay";
qcom,mode = <GSBI_PROT_SPI>;
spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
flash@0 {
compatible = "mx25u25635f", "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
m25p,fast-read;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
label = "MIBIB";
reg = <0x20000 0x10000>;
read-only;
};
partition@30000 {
label = "SBL2";
reg = <0x30000 0x20000>;
read-only;
};
partition@50000 {
label = "SBL3";
reg = <0x50000 0x30000>;
read-only;
};
partition@80000 {
label = "DDRCONFIG";
reg = <0x80000 0x10000>;
read-only;
};
partition@90000 {
label = "SSD";
reg = <0x90000 0x10000>;
read-only;
};
partition@a0000 {
label = "TZ";
reg = <0xa0000 0x30000>;
read-only;
};
partition@d0000 {
label = "RPM";
reg = <0xd0000 0x20000>;
read-only;
};
partition@f0000 {
label = "APPSBL";
reg = <0xf0000 0xc0000>;
read-only;
};
partition@1b0000 {
label = "APPSBLENV";
reg = <0x1b0000 0x10000>;
read-only;
};
eeprom: partition@1c0000 {
label = "EEPROM";
reg = <0x1c0000 0x10000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_eeprom_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_eeprom_6: macaddr@6 {
compatible = "mac-base";
reg = <0x6 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@1d0000 {
label = "bootselect";
reg = <0x1d0000 0x10000>;
};
partition@1e0000 {
compatible = "denx,fit";
label = "firmware";
reg = <0x1e0000 0xe70000>;
};
partition@1050000 {
label = "kernel1";
reg = <0x1050000 0xe70000>;
read-only;
};
partition@1ec0000 {
label = "debug";
reg = <0x1ec0000 0x100000>;
read-only;
};
partition@1fc0000 {
label = "cfg";
reg = <0x1fc0000 0x40000>;
read-only;
};
};
};
};
};
&adm_dma {
status = "okay";
};
&nand {
status = "okay";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy4: ethernet-phy@4 {
reg = <4>;
};
phy5: ethernet-phy@5 {
reg = <5>;
};
};
&gmac1 {
status = "okay";
mdiobus = <&mdio0>;
phy-handle = <&phy5>;
phy-mode = "sgmii";
qcom,id = <1>;
nvmem-cells = <&macaddr_eeprom_6 0>;
nvmem-cell-names = "mac-address";
};
&gmac2 {
status = "okay";
mdiobus = <&mdio0>;
phy-handle = <&phy4>;
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_eeprom_0>;
nvmem-cell-names = "mac-address";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_eeprom_6 1>;
nvmem-cell-names = "mac-address";
};
};
};
&pcie1 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_eeprom_6 2>;
nvmem-cell-names = "mac-address";
};
};
};
&tcsr {
status = "okay";
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};

515
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-vr2600v.dts
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@ -1,515 +0,0 @@
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "TP-Link Archer VR2600v";
compatible = "tplink,vr2600v", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
aliases {
mdio-gpio0 = &mdio0;
led-boot = &power;
led-failsafe = &general;
led-running = &power;
led-upgrade = &general;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
dect {
label = "dect";
gpios = <&qcom_pinmux 67 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PHONE>;
debounce-interval = <60>;
wakeup-source;
};
ledswitch {
label = "ledswitch";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
linux,code = <KEY_LIGHTS_TOGGLE>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
dsl {
label = "white:dsl";
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
usb {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
lan {
function = LED_FUNCTION_LAN;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
wlan2g {
label = "white:wlan2g";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
};
wlan5g {
label = "white:wlan5g";
gpios = <&qcom_pinmux 17 GPIO_ACTIVE_HIGH>;
};
power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
phone {
label = "white:phone";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
};
wan {
function = LED_FUNCTION_WAN;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
};
general: general {
label = "white:general";
gpios = <&qcom_pinmux 66 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio17",
"gpio26", "gpio53", "gpio56", "gpio66";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
button_pins: button_pins {
mux {
pins = "gpio54", "gpio64", "gpio65", "gpio67", "gpio68";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs {
pins = "gpio20";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
};
&gsbi5 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi4: spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
flash@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "SBL1";
reg = <0x0 0x20000>;
read-only;
};
partition@20000 {
label = "MIBIB";
reg = <0x20000 0x20000>;
read-only;
};
partition@40000 {
label = "SBL2";
reg = <0x40000 0x40000>;
read-only;
};
partition@80000 {
label = "SBL3";
reg = <0x80000 0x80000>;
read-only;
};
partition@100000 {
label = "DDRCONFIG";
reg = <0x100000 0x10000>;
read-only;
};
partition@110000 {
label = "SSD";
reg = <0x110000 0x10000>;
read-only;
};
partition@120000 {
label = "TZ";
reg = <0x120000 0x80000>;
read-only;
};
partition@1a0000 {
label = "RPM";
reg = <0x1a0000 0x80000>;
read-only;
};
partition@220000 {
label = "APPSBL";
reg = <0x220000 0x80000>;
read-only;
};
partition@2a0000 {
label = "APPSBLENV";
reg = <0x2a0000 0x40000>;
read-only;
};
partition@2e0000 {
label = "OLDART";
reg = <0x2e0000 0x40000>;
read-only;
};
partition@320000 {
label = "firmware";
reg = <0x320000 0xc60000>;
compatible = "openwrt,uimage";
openwrt,offset = <512>; /* account for pad-extra 512 */
};
/* hole 0xf80000 - 0xfaf100 */
partition@faf100 {
label = "default-mac";
reg = <0xfaf100 0x00200>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_defaultmac_0: macaddr@0 {
compatible = "mac-base";
reg = <0x0 0x6>;
#nvmem-cell-cells = <1>;
};
};
};
partition@fc0000 {
label = "ART";
reg = <0xfc0000 0x40000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
};
};
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_defaultmac_0 (-1)>, <&precal_ART_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_defaultmac_0 0>, <&precal_ART_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_defaultmac_0 1>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_defaultmac_0 0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&adm_dma {
status = "okay";
};

552
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wg2600hp.dts
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@ -1,552 +0,0 @@
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "NEC Aterm WG2600HP";
compatible = "nec,wg2600hp", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
aliases {
mdio-gpio0 = &mdio0;
led-boot = &power_green;
led-failsafe = &power_red;
led-running = &power_green;
led-upgrade = &power_green;
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wps {
label = "wps";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
bridge {
label = "bridge";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
debounce-interval = <60>;
wakeup-source;
};
converter {
label = "converter";
gpios = <&qcom_pinmux 25 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
linux,input-type = <EV_SW>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
converter_green {
label = "green:converter";
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_HIGH>;
};
power_red: power_red {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_RED>;
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
active_green {
label = "green:active";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
active_red {
label = "red:active";
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
power_green: power_green {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_GREEN>;
gpios = <&qcom_pinmux 14 GPIO_ACTIVE_HIGH>;
};
converter_red {
label = "red:converter";
gpios = <&qcom_pinmux 15 GPIO_ACTIVE_HIGH>;
};
wlan2g_green {
label = "green:wlan2g";
gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
};
wlan2g_red {
label = "red:wlan2g";
gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
};
wlan5g_green {
label = "green:wlan5g";
gpios = <&qcom_pinmux 57 GPIO_ACTIVE_HIGH>;
};
wlan5g_red {
label = "red:wlan5g";
gpios = <&qcom_pinmux 58 GPIO_ACTIVE_HIGH>;
};
tv_green {
label = "green:tv";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
};
tv_red {
label = "red:tv";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;
};
};
};
&CPU_SPC {
status = "disabled";
};
&adm_dma {
status = "okay";
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
qca,sgmii-rxclk-falling-edge;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_PRODUCTDATA_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_PRODUCTDATA_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gsbi5 {
status = "okay";
qcom,mode = <GSBI_PROT_SPI>;
spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
SBL1@0 {
label = "SBL1";
reg = <0x0 0x20000>;
read-only;
};
MIBIB@20000 {
label = "MIBIB";
reg = <0x20000 0x20000>;
read-only;
};
SBL2@40000 {
label = "SBL2";
reg = <0x40000 0x40000>;
read-only;
};
SBL3@80000 {
label = "SBL3";
reg = <0x80000 0x80000>;
read-only;
};
DDRCONFIG@100000 {
label = "DDRCONFIG";
reg = <0x100000 0x10000>;
read-only;
};
SSD@110000 {
label = "SSD";
reg = <0x110000 0x10000>;
read-only;
};
TZ@120000 {
label = "TZ";
reg = <0x120000 0x80000>;
read-only;
};
RPM@1a0000 {
label = "RPM";
reg = <0x1a0000 0x80000>;
read-only;
};
APPSBL@220000 {
label = "APPSBL";
reg = <0x220000 0x80000>;
read-only;
};
APPSBLENV@2a0000 {
label = "APPSBLENV";
reg = <0x2a0000 0x10000>;
};
PRODUCTDATA: PRODUCTDATA@2b0000 {
label = "PRODUCTDATA";
reg = <0x2b0000 0x30000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_PRODUCTDATA_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_PRODUCTDATA_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_PRODUCTDATA_c: macaddr@c {
reg = <0xc 0x6>;
};
macaddr_PRODUCTDATA_12: macaddr@12 {
reg = <0x12 0x6>;
};
};
};
ART@2e0000 {
label = "ART";
reg = <0x2e0000 0x40000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
TP@320000 {
label = "TP";
reg = <0x320000 0x40000>;
read-only;
};
TINY@360000 {
label = "TINY";
reg = <0x360000 0x500000>;
read-only;
};
firmware@860000 {
compatible = "denx,uimage";
label = "firmware";
reg = <0x860000 0x17a0000>;
};
};
};
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb_pwr_en_pins>;
pinctrl-names = "default";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_PRODUCTDATA_12>, <&precal_ART_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_PRODUCTDATA_c>, <&precal_ART_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio16", "gpio54", "gpio24", "gpio25";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio6", "gpio7", "gpio8", "gpio9", "gpio14",
"gpio15", "gpio55", "gpio56", "gpio57", "gpio58",
"gpio64", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs {
pins = "gpio20";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
usb_pwr_en_pins: usb_pwr_en_pins {
mux {
pins = "gpio22";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
output-high;
};
};
};

557
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wpq864.dts
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@ -1,557 +0,0 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (C) 2017 Christian Mehlis <christian@m3hlis.de>
* Copyright (C) 2018 Mathias Kresin <dev@kresin.me>
* All rights reserved.
*/
#include "qcom-ipq8064-v1.0.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/soc/qcom,tcsr.h>
/ {
compatible = "compex,wpq864", "qcom,ipq8064";
model = "Compex WPQ864";
aliases {
mdio-gpio0 = &mdio0;
ethernet0 = &gmac1;
ethernet1 = &gmac0;
led-boot = &led_pass;
led-failsafe = &led_fail;
led-running = &led_pass;
led-upgrade = &led_pass;
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
rss4 {
label = "green:rss4";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
rss3 {
label = "green:rss3";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
rss2 {
label = "orange:rss2";
gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
};
rss1 {
label = "red:rss1";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
led_pass: pass {
label = "green:pass";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
};
led_fail: fail {
label = "green:fail";
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
usb {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_GREEN>;
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
};
usb-pcie {
label = "green:usb-pcie";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
};
beeper {
compatible = "gpio-beeper";
pinctrl-0 = <&beeper_pins>;
pinctrl-names = "default";
gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
};
};
&rpm {
pinctrl-0 = <&rpm_pins>;
pinctrl-names = "default";
};
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
mt29f2g08abbeah4@0 {
compatible = "qcom,nandcs";
reg = <0>;
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
nand-is-boot-medium;
qcom,boot-partitions = <0x0 0x1180000 0x5340000 0x10c0000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "0:SBL1";
reg = <0x0000000 0x0040000>;
read-only;
};
partition@40000 {
label = "0:MIBIB";
reg = <0x0040000 0x0140000>;
read-only;
};
partition@180000 {
label = "0:SBL2";
reg = <0x0180000 0x0140000>;
read-only;
};
partition@2c0000 {
label = "0:SBL3";
reg = <0x02c0000 0x0280000>;
read-only;
};
partition@540000 {
label = "0:DDRCONFIG";
reg = <0x0540000 0x0120000>;
read-only;
};
partition@660000 {
label = "0:SSD";
reg = <0x0660000 0x0120000>;
read-only;
};
partition@780000 {
label = "0:TZ";
reg = <0x0780000 0x0280000>;
read-only;
};
partition@a00000 {
label = "0:RPM";
reg = <0x0a00000 0x0280000>;
read-only;
};
partition@c80000 {
label = "0:APPSBL";
reg = <0x0c80000 0x0500000>;
read-only;
};
partition@1180000 {
label = "0:APPSBLENV";
reg = <0x1180000 0x0080000>;
};
partition@1200000 {
label = "0:ART";
reg = <0x1200000 0x0140000>;
};
partition@1340000 {
label = "ubi";
reg = <0x1340000 0x4000000>;
};
partition@5340000 {
label = "0:BOOTCONFIG";
reg = <0x5340000 0x0060000>;
};
partition@53a0000 {
label = "0:SBL2_1";
reg = <0x53a0000 0x0140000>;
read-only;
};
partition@54e0000 {
label = "0:SBL3_1";
reg = <0x54e0000 0x0280000>;
read-only;
};
partition@5760000 {
label = "0:DDRCONFIG_1";
reg = <0x5760000 0x0120000>;
read-only;
};
partition@5880000 {
label = "0:SSD_1";
reg = <0x5880000 0x0120000>;
read-only;
};
partition@59a0000 {
label = "0:TZ_1";
reg = <0x59a0000 0x0280000>;
read-only;
};
partition@5c20000 {
label = "0:RPM_1";
reg = <0x5c20000 0x0280000>;
read-only;
};
partition@5ea0000 {
label = "0:BOOTCONFIG1";
reg = <0x5ea0000 0x0060000>;
};
partition@5f00000 {
label = "0:APPSBL_1";
reg = <0x5f00000 0x0500000>;
read-only;
};
partition@6400000 {
label = "ubi_1";
reg = <0x6400000 0x4000000>;
};
partition@a400000 {
label = "unused";
reg = <0xa400000 0x5c00000>;
};
};
};
};
&adm_dma {
status = "okay";
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
phy-mode = "rgmii";
qcom,id = <1>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gsbi4_serial {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
&flash {
compatible = "jedec,spi-nor";
};
&sata_phy {
status = "disabled";
};
&sata {
status = "disabled";
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
rx_eq = <2>;
tx_deamp_3_5db = <32>;
mpll = <160>;
};
&usb3_0 {
status = "okay";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
rx_eq = <2>;
tx_deamp_3_5db = <32>;
mpll = <160>;
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
/delete-property/ perst-gpios;
};
&pcie1 {
status = "okay";
};
&pcie2 {
status = "okay";
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
/delete-property/ perst-gpios;
};
&qcom_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
state_default: pinctrl0 {
pcie0_pcie2_perst {
pins = "gpio3";
function = "gpio";
drive-strength = <2>;
bias-disable;
output-high;
};
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio22",
"gpio23", "gpio24", "gpio25", "gpio53";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
button_pins: button_pins {
mux {
pins = "gpio54";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
beeper_pins: beeper_pins {
mux {
pins = "gpio55";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
rpm_pins: rpm_pins {
mux {
pins = "gpio12", "gpio13";
function = "gsbi4";
drive-strength = <10>;
bias-disable;
};
};
uart0_pins: uart0_pins {
mux {
pins = "gpio10", "gpio11";
function = "gsbi4";
drive-strength = <10>;
bias-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19";
function = "gsbi5";
drive-strength = <10>;
bias-pull-down;
};
clk {
pins = "gpio21";
function = "gsbi5";
drive-strength = <12>;
bias-pull-down;
};
cs {
pins = "gpio20";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
};
};
&tcsr {
qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
};

622
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8064-wxr-2533dhp.dts
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@ -1,622 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8064-v2.0-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Buffalo WXR-2533DHP";
compatible = "buffalo,wxr-2533dhp", "qcom,ipq8064";
memory@42000000 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
aliases {
led-boot = &power;
led-failsafe = &diag;
led-running = &power;
led-upgrade = &power;
};
chosen {
/* use "ubi_rootfs" volume in "ubi" partition as rootfs */
bootargs = "ubi.block=0,1 root=/dev/ubiblock0_1 rootfstype=squashfs";
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
usb {
function = LED_FUNCTION_USB;
color = <LED_COLOR_ID_GREEN>;
gpios = <&qcom_pinmux 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "usbport";
trigger-sources = <&hub_port0 &hub_port1>;
};
guestport {
label = "green:guestport";
gpios = <&qcom_pinmux 8 GPIO_ACTIVE_HIGH>;
};
diag: diag {
label = "orange:diag";
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
};
internet_orange {
label = "orange:internet";
gpios = <&qcom_pinmux 16 GPIO_ACTIVE_HIGH>;
};
internet_white {
label = "white:internet";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
};
wireless_orange {
label = "orange:wireless";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
};
wireless_white {
label = "white:wireless";
gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
};
router_orange {
label = "orange:router";
gpios = <&qcom_pinmux 25 GPIO_ACTIVE_HIGH>;
};
router_white {
label = "white:router";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_LOW>;
};
power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
};
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
power {
label = "power";
gpios = <&qcom_pinmux 58 GPIO_ACTIVE_LOW>;
linux,code = <KEY_POWER>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
eject {
label = "eject";
gpios = <&qcom_pinmux 6 GPIO_ACTIVE_LOW>;
linux,code = <KEY_EJECTCD>;
debounce-interval = <60>;
wakeup-source;
};
guest {
label = "guest";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
debounce-interval = <60>;
wakeup-source;
};
ap {
label = "ap";
gpios = <&qcom_pinmux 55 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
debounce-interval = <60>;
wakeup-source;
};
router {
label = "router";
gpios = <&qcom_pinmux 56 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
debounce-interval = <60>;
wakeup-source;
};
auto {
label = "auto";
gpios = <&qcom_pinmux 57 GPIO_ACTIVE_LOW>;
linux,code = <BTN_1>;
linux,input-type = <EV_SW>;
debounce-interval = <60>;
wakeup-source;
};
};
};
&nand {
status = "okay";
cs@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
ubi@0 {
label = "ubi";
reg = <0x0000000 0x4000000>;
};
rootfs_1@4000000 {
label = "rootfs_1";
reg = <0x4000000 0x4000000>;
};
};
};
};
&adm_dma {
status = "okay";
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
nvmem-cells = <&macaddr_ART_6>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
nvmem-cells = <&macaddr_ART_0>;
nvmem-cell-names = "mac-address";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gsbi4_serial {
pinctrl-0 = <&uart0_pins>;
pinctrl-names = "default";
};
&gsbi5 {
status = "okay";
qcom,mode = <GSBI_PROT_SPI>;
spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
flash@0 {
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
SBL1@0 {
label = "SBL1";
reg = <0x0 0x10000>;
read-only;
};
MIBIB@10000 {
label = "MIBIB";
reg = <0x10000 0x20000>;
read-only;
};
SBL2@30000 {
label = "SBL2";
reg = <0x30000 0x30000>;
read-only;
};
SBL3@60000 {
label = "SBL3";
reg = <0x60000 0x30000>;
read-only;
};
DDRCONFIG@90000 {
label = "DDRCONFIG";
reg = <0x90000 0x10000>;
read-only;
};
SSD@a0000 {
label = "SSD";
reg = <0xa0000 0x10000>;
read-only;
};
TZ@b0000 {
label = "TZ";
reg = <0xb0000 0x30000>;
read-only;
};
RPM@e0000 {
label = "RPM";
reg = <0xe0000 0x20000>;
read-only;
};
APPSBL@100000 {
label = "APPSBL";
reg = <0x100000 0x70000>;
read-only;
};
APPSBLENV@170000 {
label = "APPSBLENV";
reg = <0x170000 0x10000>;
read-only;
};
ART@180000 {
label = "ART";
reg = <0x180000 0x40000>;
read-only;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
macaddr_ART_0: macaddr@0 {
reg = <0x0 0x6>;
};
macaddr_ART_6: macaddr@6 {
reg = <0x6 0x6>;
};
macaddr_ART_18: macaddr@18 {
reg = <0x18 0x6>;
};
macaddr_ART_1e: macaddr@1e {
reg = <0x1e 0x6>;
};
precal_ART_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_ART_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};
BOOTCONFIG@1c0000 {
label = "BOOTCONFIG";
reg = <0x1c0000 0x10000>;
read-only;
};
APPSBL_1@1d0000 {
label = "APPSBL_1";
reg = <0x1d0000 0x70000>;
read-only;
};
};
};
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb_pwr_en_pins>;
pinctrl-names = "default";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&dwc3_0 {
#address-cells = <1>;
#size-cells = <0>;
hub_port0: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&dwc3_1 {
#address-cells = <1>;
#size-cells = <0>;
hub_port1: port@1 {
reg = <1>;
#trigger-source-cells = <0>;
};
};
&pcie0 {
status = "okay";
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_ART_1e>, <&precal_ART_1000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&pcie1 {
status = "okay";
max-link-speed = <1>;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
reg = <0x00010000 0 0 0 0>;
nvmem-cells = <&macaddr_ART_18>, <&precal_ART_5000>;
nvmem-cell-names = "mac-address", "pre-calibration";
};
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio6", "gpio54", "gpio55", "gpio56", "gpio57",
"gpio58", "gpio64", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio7", "gpio8", "gpio9", "gpio16", "gpio22",
"gpio23", "gpio24", "gpio25", "gpio26", "gpio53";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
uart0_pins: uart0_pins {
mux {
pins = "gpio10", "gpio11";
function = "gsbi4";
drive-strength = <12>;
bias-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
bias-pull-down;
};
data {
pins = "gpio18", "gpio19";
drive-strength = <10>;
};
cs{
pins = "gpio20";
drive-strength = <10>;
bias-pull-up;
};
clk {
pins = "gpio21";
drive-strength = <12>;
};
};
usb_pwr_en_pins: usb_pwr_en_pins {
mux{
pins = "gpio68";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
output-high;
};
};
};

318
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-ac400i.dts
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@ -1,318 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
/ {
model = "Nokia AC400i";
compatible = "nokia,ac400i", "qcom,ipq8065", "qcom,ipq8064";
aliases {
mdio-gpio0 = &mdio0;
ethernet0 = &gmac0;
ethernet1 = &gmac1;
led-boot = &pwr_red;
led-failsafe = &pwr_red;
led-running = &pwr_green;
led-upgrade = &pwr_green;
};
chosen {
bootargs-override = " console=ttyMSM0,115200n8 ubi.mtd=ubi root=/dev/ubiblock0_2";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
reset {
label = "reset";
gpios = <&qcom_pinmux 15 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
5g_red {
label = "red:5g";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_HIGH>;
};
5g_green {
label = "green:5g";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
};
2g_red {
label = "red:2g";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_HIGH>;
};
2g_green {
label = "green:2g";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_HIGH>;
};
eth1_red {
label = "red:eth1";
gpios = <&qcom_pinmux 68 GPIO_ACTIVE_HIGH>;
};
eth1_green {
label = "green:eth1";
gpios = <&qcom_pinmux 22 GPIO_ACTIVE_LOW>;
};
eth2_red {
label = "red:eth2";
gpios = <&qcom_pinmux 67 GPIO_ACTIVE_HIGH>;
};
eth2_green {
label = "green:eth2";
gpios = <&qcom_pinmux 23 GPIO_ACTIVE_LOW>;
};
ctrl_red {
label = "red:ctrl";
gpios = <&qcom_pinmux 55 GPIO_ACTIVE_HIGH>;
};
ctrl_green {
label = "green:ctrl";
gpios = <&qcom_pinmux 56 GPIO_ACTIVE_HIGH>;
};
pwr_red: pwr_red {
label = "red:pwr";
gpios = <&qcom_pinmux 2 GPIO_ACTIVE_LOW>;
};
pwr_green: pwr_green {
label = "green:pwr";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
};
};
&qcom_pinmux {
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19";
function = "gsbi5";
drive-strength = <10>;
bias-pull-down;
};
clk {
pins = "gpio21";
function = "gsbi5";
drive-strength = <12>;
bias-pull-down;
};
cs {
pins = "gpio20";
function = "gpio";
drive-strength = <10>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio65", "gpio64",
"gpio53", "gpio54",
"gpio68", "gpio22",
"gpio67", "gpio23",
"gpio55", "gpio56",
"gpio2", "gpio26";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
button_pins: button_pins {
mux {
pins = "gpio15";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
};
&gsbi5 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi4: spi@1a280000 {
status = "okay";
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
m25p80@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
partitions {
compatible = "qcom,smem-part";
};
};
};
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&pcie0 {
status = "okay";
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
/delete-property/ perst-gpios;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "Nokia-AC400i";
};
};
};
&pcie1 {
status = "okay";
/delete-property/ pinctrl-0;
/delete-property/ pinctrl-names;
/delete-property/ perst-gpios;
bridge@0,0 {
reg = <0x00000000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
wifi@1,0 {
compatible = "qcom,ath10k";
status = "okay";
reg = <0x00010000 0 0 0 0>;
qcom,ath10k-calibration-variant = "Nokia-AC400i";
};
};
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
phy0: ethernet-phy@0 {
reg = <0>;
};
phy1: ethernet-phy@1 {
reg = <1>;
};
};
//POE
&gmac0 {
status = "okay";
qcom,id = <0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
mdiobus = <&mdio0>;
phy-handle = <&phy0>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
//LAN1
&gmac1 {
status = "okay";
qcom,id = <1>;
mdiobus = <&mdio0>;
phy-handle = <&phy1>;
phy-mode = "rgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&nand {
status = "okay";
pinctrl-0 = <&nand_pins>;
pinctrl-names = "default";
nand@0 {
reg = <0>;
compatible = "qcom,nandcs";
nand-ecc-strength = <4>;
nand-bus-width = <8>;
nand-ecc-step-size = <512>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
rootfs@0 {
label = "rootfs";
reg = <0x0000000 0x4000000>;
};
rootfs_1@4000000 {
label = "rootfs_1";
reg = <0x4000000 0x4000000>;
};
cfg@8000000 {
label = "cfg";
reg = <0x8000000 0x8000000>;
};
};
};
};
&adm_dma {
status = "okay";
};

395
target/linux/ipq806x/files-6.6/arch/arm/boot/dts/qcom/qcom-ipq8065-nbg6817.dts
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@ -1,395 +0,0 @@
#include "qcom-ipq8065-smb208.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
/ {
model = "Zyxel NBG6817";
compatible = "zyxel,nbg6817", "qcom,ipq8065", "qcom,ipq8064";
memory@0 {
reg = <0x42000000 0x1e000000>;
device_type = "memory";
};
aliases {
mdio-gpio0 = &mdio0;
sdcc1 = &sdcc1;
led-boot = &power;
led-failsafe = &power;
led-running = &power;
led-upgrade = &power;
};
chosen {
bootargs = "rootfstype=squashfs,ext4 rootwait noinitrd fstools_ignore_partname=1";
append-rootblock = "root=/dev/mmcblk0p";
};
keys {
compatible = "gpio-keys";
pinctrl-0 = <&button_pins>;
pinctrl-names = "default";
wifi {
label = "wifi";
gpios = <&qcom_pinmux 53 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RFKILL>;
linux,input-type = <EV_SW>;
debounce-interval = <60>;
wakeup-source;
};
reset {
label = "reset";
gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
linux,code = <KEY_RESTART>;
debounce-interval = <60>;
wakeup-source;
};
wps {
label = "wps";
gpios = <&qcom_pinmux 65 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WPS_BUTTON>;
debounce-interval = <60>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-0 = <&led_pins>;
pinctrl-names = "default";
internet {
label = "white:internet";
gpios = <&qcom_pinmux 64 GPIO_ACTIVE_HIGH>;
};
power: power {
function = LED_FUNCTION_POWER;
color = <LED_COLOR_ID_WHITE>;
gpios = <&qcom_pinmux 9 GPIO_ACTIVE_HIGH>;
default-state = "keep";
};
wifi2g {
label = "amber:wifi2g";
gpios = <&qcom_pinmux 33 GPIO_ACTIVE_HIGH>;
};
/* wifi2g amber from the manual is missing */
wifi5g {
label = "amber:wifi5g";
gpios = <&qcom_pinmux 26 GPIO_ACTIVE_HIGH>;
};
/* wifi5g amber from the manual is missing */
};
};
&qcom_pinmux {
button_pins: button_pins {
mux {
pins = "gpio53", "gpio54", "gpio65";
function = "gpio";
drive-strength = <2>;
bias-pull-up;
};
};
led_pins: led_pins {
mux {
pins = "gpio9", "gpio26", "gpio33", "gpio64";
function = "gpio";
drive-strength = <2>;
bias-pull-down;
};
};
mdio0_pins: mdio0-pins {
clk {
pins = "gpio1";
input-disable;
};
};
rgmii2_pins: rgmii2-pins {
tx {
pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32" ;
input-disable;
};
};
spi_pins: spi_pins {
cs {
pins = "gpio20";
drive-strength = <12>;
};
};
usb0_pwr_en_pins: usb0_pwr_en_pins {
mux {
pins = "gpio16", "gpio17";
function = "gpio";
drive-strength = <12>;
};
pwr {
pins = "gpio17";
bias-pull-down;
output-high;
};
ovc {
pins = "gpio16";
bias-pull-up;
};
};
usb1_pwr_en_pins: usb1_pwr_en_pins {
mux {
pins = "gpio14", "gpio15";
function = "gpio";
drive-strength = <12>;
};
pwr {
pins = "gpio14";
bias-pull-down;
output-high;
};
ovc {
pins = "gpio15";
bias-pull-up;
};
};
};
&gsbi5 {
qcom,mode = <GSBI_PROT_SPI>;
status = "okay";
spi4: spi@1a280000 {
status = "okay";
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 GPIO_ACTIVE_LOW>;
m25p80@0 {
compatible = "jedec,spi-nor";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <51200000>;
reg = <0>;
partitions {
compatible = "qcom,smem-part";
};
};
};
};
&hs_phy_0 {
status = "okay";
};
&ss_phy_0 {
status = "okay";
};
&usb3_0 {
status = "okay";
pinctrl-0 = <&usb0_pwr_en_pins>;
pinctrl-names = "default";
};
&hs_phy_1 {
status = "okay";
};
&ss_phy_1 {
status = "okay";
};
&usb3_1 {
status = "okay";
pinctrl-0 = <&usb1_pwr_en_pins>;
pinctrl-names = "default";
};
&pcie0 {
status = "okay";
reset-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie0_pins>;
pinctrl-names = "default";
};
&pcie1 {
status = "okay";
reset-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
max-link-speed = <1>;
};
&mdio0 {
status = "okay";
pinctrl-0 = <&mdio0_pins>;
pinctrl-names = "default";
switch@10 {
compatible = "qca,qca8337";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
label = "cpu";
ethernet = <&gmac1>;
phy-mode = "rgmii";
tx-internal-delay-ps = <1000>;
rx-internal-delay-ps = <1000>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
port@1 {
reg = <1>;
label = "lan1";
phy-mode = "internal";
phy-handle = <&phy_port1>;
};
port@2 {
reg = <2>;
label = "lan2";
phy-mode = "internal";
phy-handle = <&phy_port2>;
};
port@3 {
reg = <3>;
label = "lan3";
phy-mode = "internal";
phy-handle = <&phy_port3>;
};
port@4 {
reg = <4>;
label = "lan4";
phy-mode = "internal";
phy-handle = <&phy_port4>;
};
port@5 {
reg = <5>;
label = "wan";
phy-mode = "internal";
phy-handle = <&phy_port5>;
};
port@6 {
reg = <6>;
label = "cpu";
ethernet = <&gmac2>;
phy-mode = "sgmii";
qca,sgmii-enable-pll;
fixed-link {
speed = <1000>;
full-duplex;
};
};
};
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy_port1: phy@0 {
reg = <0>;
};
phy_port2: phy@1 {
reg = <1>;
};
phy_port3: phy@2 {
reg = <2>;
};
phy_port4: phy@3 {
reg = <3>;
};
phy_port5: phy@4 {
reg = <4>;
};
};
};
};
&gmac1 {
status = "okay";
phy-mode = "rgmii";
qcom,id = <1>;
qcom,phy_mdio_addr = <4>;
qcom,poll_required = <0>;
qcom,rgmii_delay = <1>;
qcom,phy_mii_type = <0>;
qcom,emulation = <0>;
qcom,irq = <255>;
mdiobus = <&mdio0>;
pinctrl-0 = <&rgmii2_pins>;
pinctrl-names = "default";
fixed-link {
speed = <1000>;
full-duplex;
};
};
&gmac2 {
status = "okay";
phy-mode = "sgmii";
qcom,id = <2>;
qcom,phy_mdio_addr = <0>; /* none */
qcom,poll_required = <0>; /* no polling */
qcom,rgmii_delay = <0>;
qcom,phy_mii_type = <1>;
qcom,emulation = <0>;
qcom,irq = <258>;
mdiobus = <&mdio0>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&sdcc1 {
status = "okay";
};
&adm_dma {
status = "okay";
};

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